| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vshl.i64 q0,q0,#0' |
| [^:]*:11: Error: immediate out of range for shift -- `vshl.i8 q0,q1,#8' |
| [^:]*:12: Error: immediate out of range for shift -- `vshl.i16 q0,q1,#16' |
| [^:]*:13: Error: immediate out of range for shift -- `vshl.i32 q0,q1,#32' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vshl.s64 q0,r1' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vshl.i16 q0,r1' |
| [^:]*:16: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:18: Error: bad type in SIMD instruction -- `vshl.s64 q0,q1,q2' |
| [^:]*:19: Error: bad type in SIMD instruction -- `vshl.i32 q0,q1,q2' |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Error: syntax error -- `vshleq.i16 q0,q1,#0' |
| [^:]*:25: Error: syntax error -- `vshleq.i16 q0,q1,#0' |
| [^:]*:27: Error: syntax error -- `vshleq.i16 q0,q1,#0' |
| [^:]*:28: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.i16 q0,q1,#0' |
| [^:]*:30: Error: instruction missing MVE vector predication code -- `vshl.i16 q0,q1,#0' |
| [^:]*:32: Error: syntax error -- `vshleq.s16 q0,r1' |
| [^:]*:33: Error: syntax error -- `vshleq.s16 q0,r1' |
| [^:]*:35: Error: syntax error -- `vshleq.s16 q0,r1' |
| [^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.s16 q0,r1' |
| [^:]*:38: Error: instruction missing MVE vector predication code -- `vshl.s16 q0,r1' |
| [^:]*:40: Error: syntax error -- `vshleq.s16 q0,q1,q2' |
| [^:]*:41: Error: syntax error -- `vshleq.s16 q0,q1,q2' |
| [^:]*:43: Error: syntax error -- `vshleq.s16 q0,q1,q2' |
| [^:]*:44: Error: vector predicated instruction should be in VPT/VPST block -- `vshlt.s16 q0,q1,q2' |
| [^:]*:46: Error: instruction missing MVE vector predication code -- `vshl.s16 q0,q1,q2' |