blob: bde2a6d23b4df3b1ed05e83c6caea4ea0f067154 [file] [log] [blame]
[^:]*: Assembler messages:
[^:]*:10: Error: bad type in SIMD instruction -- `vsli.64 q0,q1,#1'
[^:]*:11: Error: immediate out of range for insert -- `vsli.8 q0,q1,#8'
[^:]*:12: Error: immediate out of range for insert -- `vsli.16 q0,q1,#16'
[^:]*:13: Error: immediate out of range for insert -- `vsli.32 q0,q1,#32'
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:16: Error: syntax error -- `vslieq.8 q0,q1,#2'
[^:]*:17: Error: syntax error -- `vslieq.8 q0,q1,#2'
[^:]*:19: Error: syntax error -- `vslieq.8 q0,q1,#2'
[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vslit.8 q0,q1,#2'
[^:]*:22: Error: instruction missing MVE vector predication code -- `vsli.8 q0,q1,#2'