| [^:]*: Assembler messages: |
| [^:]*:3: Error: register stride must be 1 -- `vst20.8 {q0,q2},\[r0\]' |
| [^:]*:4: Error: syntax error -- `vst20.8 {q0,q1,q2},\[r0\]' |
| [^:]*:5: Error: syntax error -- `vst20.8 {q0},\[r0\]' |
| [^:]*:6: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:7: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:8: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:9: Error: register stride must be 1 -- `vst20.8 {q3,q2},\[r0\]' |
| [^:]*:10: Error: bad element type for instruction -- `vst20.64 {q0,q1},\[r0\]' |
| [^:]*:11: Error: register stride must be 1 -- `vst21.8 {q0,q2},\[r0\]' |
| [^:]*:12: Error: syntax error -- `vst21.8 {q0,q1,q2},\[r0\]' |
| [^:]*:13: Error: syntax error -- `vst21.8 {q0},\[r0\]' |
| [^:]*:14: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:15: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:16: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:17: Error: register stride must be 1 -- `vst21.8 {q3,q2},\[r0\]' |
| [^:]*:18: Error: bad element type for instruction -- `vst21.64 {q0,q1},\[r0\]' |
| [^:]*:19: Error: register stride must be 1 -- `vst40.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:20: Error: register stride must be 1 -- `vst40.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:21: Error: register stride must be 1 -- `vst40.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:22: Error: register stride must be 1 -- `vst40.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:23: Error: syntax error -- `vst40.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:24: Error: syntax error -- `vst40.8 {q0,q1,q2},\[r0\]' |
| [^:]*:25: Error: syntax error -- `vst40.8 {q0,q1},\[r0\]' |
| [^:]*:26: Error: syntax error -- `vst40.8 {q0},\[r0\]' |
| [^:]*:27: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:28: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:30: Error: bad element type for instruction -- `vst40.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:31: Error: register stride must be 1 -- `vst41.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:32: Error: register stride must be 1 -- `vst41.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:33: Error: register stride must be 1 -- `vst41.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:34: Error: register stride must be 1 -- `vst41.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:35: Error: syntax error -- `vst41.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:36: Error: syntax error -- `vst41.8 {q0,q1,q2},\[r0\]' |
| [^:]*:37: Error: syntax error -- `vst41.8 {q0,q1},\[r0\]' |
| [^:]*:38: Error: syntax error -- `vst41.8 {q0},\[r0\]' |
| [^:]*:39: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:40: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:41: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:42: Error: bad element type for instruction -- `vst41.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:43: Error: register stride must be 1 -- `vst42.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:44: Error: register stride must be 1 -- `vst42.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:45: Error: register stride must be 1 -- `vst42.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:46: Error: register stride must be 1 -- `vst42.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:47: Error: syntax error -- `vst42.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:48: Error: syntax error -- `vst42.8 {q0,q1,q2},\[r0\]' |
| [^:]*:49: Error: syntax error -- `vst42.8 {q0,q1},\[r0\]' |
| [^:]*:50: Error: syntax error -- `vst42.8 {q0},\[r0\]' |
| [^:]*:51: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:52: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:53: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:54: Error: bad element type for instruction -- `vst42.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:55: Error: register stride must be 1 -- `vst43.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:56: Error: register stride must be 1 -- `vst43.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:57: Error: register stride must be 1 -- `vst43.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:58: Error: register stride must be 1 -- `vst43.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:59: Error: syntax error -- `vst43.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:60: Error: syntax error -- `vst43.8 {q0,q1,q2},\[r0\]' |
| [^:]*:61: Error: syntax error -- `vst43.8 {q0,q1},\[r0\]' |
| [^:]*:62: Error: syntax error -- `vst43.8 {q0},\[r0\]' |
| [^:]*:63: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:64: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:65: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:66: Error: bad element type for instruction -- `vst43.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:67: Error: selected processor does not support `vst1.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:68: Error: selected processor does not support `vst2.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:69: Error: selected processor does not support `vst3.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:70: Error: selected processor does not support `vst4.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:71: Error: bad instruction `vst23.32 {q0,q1},\[r0\]' |
| [^:]*:72: Error: bad instruction `vst44.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:73: Error: register stride must be 1 -- `vld20.8 {q0,q2},\[r0\]' |
| [^:]*:74: Error: syntax error -- `vld20.8 {q0,q1,q2},\[r0\]' |
| [^:]*:75: Error: syntax error -- `vld20.8 {q0},\[r0\]' |
| [^:]*:76: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:77: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:78: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:79: Error: register stride must be 1 -- `vld20.8 {q3,q2},\[r0\]' |
| [^:]*:80: Error: bad element type for instruction -- `vld20.64 {q0,q1},\[r0\]' |
| [^:]*:81: Error: register stride must be 1 -- `vld21.8 {q0,q2},\[r0\]' |
| [^:]*:82: Error: syntax error -- `vld21.8 {q0,q1,q2},\[r0\]' |
| [^:]*:83: Error: syntax error -- `vld21.8 {q0},\[r0\]' |
| [^:]*:84: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:85: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:86: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:87: Error: register stride must be 1 -- `vld21.8 {q3,q2},\[r0\]' |
| [^:]*:88: Error: bad element type for instruction -- `vld21.64 {q0,q1},\[r0\]' |
| [^:]*:89: Error: register stride must be 1 -- `vld40.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:90: Error: register stride must be 1 -- `vld40.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:91: Error: register stride must be 1 -- `vld40.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:92: Error: register stride must be 1 -- `vld40.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:93: Error: syntax error -- `vld40.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:94: Error: syntax error -- `vld40.8 {q0,q1,q2},\[r0\]' |
| [^:]*:95: Error: syntax error -- `vld40.8 {q0,q1},\[r0\]' |
| [^:]*:96: Error: syntax error -- `vld40.8 {q0},\[r0\]' |
| [^:]*:97: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:98: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:99: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:100: Error: bad element type for instruction -- `vld40.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:101: Error: register stride must be 1 -- `vld41.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:102: Error: register stride must be 1 -- `vld41.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:103: Error: register stride must be 1 -- `vld41.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:104: Error: register stride must be 1 -- `vld41.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:105: Error: syntax error -- `vld41.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:106: Error: syntax error -- `vld41.8 {q0,q1,q2},\[r0\]' |
| [^:]*:107: Error: syntax error -- `vld41.8 {q0,q1},\[r0\]' |
| [^:]*:108: Error: syntax error -- `vld41.8 {q0},\[r0\]' |
| [^:]*:109: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:110: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:111: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:112: Error: bad element type for instruction -- `vld41.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:113: Error: register stride must be 1 -- `vld42.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:114: Error: register stride must be 1 -- `vld42.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:115: Error: register stride must be 1 -- `vld42.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:116: Error: register stride must be 1 -- `vld42.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:117: Error: syntax error -- `vld42.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:118: Error: syntax error -- `vld42.8 {q0,q1,q2},\[r0\]' |
| [^:]*:119: Error: syntax error -- `vld42.8 {q0,q1},\[r0\]' |
| [^:]*:120: Error: syntax error -- `vld42.8 {q0},\[r0\]' |
| [^:]*:121: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:122: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:123: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:124: Error: bad element type for instruction -- `vld42.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:125: Error: register stride must be 1 -- `vld43.8 {q0,q2,q3,q4},\[r0\]' |
| [^:]*:126: Error: register stride must be 1 -- `vld43.8 {q0,q1,q3,q4},\[r0\]' |
| [^:]*:127: Error: register stride must be 1 -- `vld43.8 {q0,q1,q2,q4},\[r0\]' |
| [^:]*:128: Error: register stride must be 1 -- `vld43.8 {q3,q1,q2,q3},\[r0\]' |
| [^:]*:129: Error: syntax error -- `vld43.8 {q0,q1,q2,q3,q4},\[r0\]' |
| [^:]*:130: Error: syntax error -- `vld43.8 {q0,q1,q2},\[r0\]' |
| [^:]*:131: Error: syntax error -- `vld43.8 {q0,q1},\[r0\]' |
| [^:]*:132: Error: syntax error -- `vld43.8 {q0},\[r0\]' |
| [^:]*:133: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:134: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:135: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:136: Error: bad element type for instruction -- `vld43.64 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:137: Error: selected processor does not support `vld1.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:138: Error: selected processor does not support `vld2.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:139: Error: selected processor does not support `vld3.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:140: Error: selected processor does not support `vld4.8 {q0,q1},\[r0\]' in Thumb mode |
| [^:]*:141: Error: bad instruction `vld23.32 {q0,q1},\[r0\]' |
| [^:]*:142: Error: bad instruction `vld44.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:167: Error: syntax error -- `vst20t.32 {q0,q1},\[r0\]' |
| [^:]*:168: Error: syntax error -- `vst20e.32 {q0,q1},\[r0\]' |
| [^:]*:170: Error: syntax error -- `vst21t.32 {q0,q1},\[r0\]' |
| [^:]*:171: Error: syntax error -- `vst21e.32 {q0,q1},\[r0\]' |
| [^:]*:173: Error: syntax error -- `vst40t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:174: Error: syntax error -- `vst40e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:176: Error: syntax error -- `vst41t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:177: Error: syntax error -- `vst41e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:179: Error: syntax error -- `vst42t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:180: Error: syntax error -- `vst42e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:182: Error: syntax error -- `vst43t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:183: Error: syntax error -- `vst43e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:186: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:188: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:190: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:192: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:194: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:196: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:205: Error: syntax error -- `vld20t.32 {q0,q1},\[r0\]' |
| [^:]*:206: Error: syntax error -- `vld20e.32 {q0,q1},\[r0\]' |
| [^:]*:208: Error: syntax error -- `vld21t.32 {q0,q1},\[r0\]' |
| [^:]*:209: Error: syntax error -- `vld21e.32 {q0,q1},\[r0\]' |
| [^:]*:211: Error: syntax error -- `vld40t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:212: Error: syntax error -- `vld40e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:214: Error: syntax error -- `vld41t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:215: Error: syntax error -- `vld41e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:217: Error: syntax error -- `vld42t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:218: Error: syntax error -- `vld42e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:220: Error: syntax error -- `vld43t.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:221: Error: syntax error -- `vld43e.32 {q0,q1,q2,q3},\[r0\]' |
| [^:]*:224: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:226: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:228: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:230: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:232: Warning: instruction is UNPREDICTABLE in a VPT block |
| [^:]*:234: Warning: instruction is UNPREDICTABLE in a VPT block |