gas/testsuite/gas/aarch64/rcpc3-fail.l

.*: Assembler messages:
.*: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp w0,w1,\[x3,#8\]'
.*: Error: operand 3 must be an address with post-incrementing by ammount of loaded bytes -- `ldiapp x0,x1,\[x3,#16\]'
.*: Error: invalid addressing mode at operand 3 -- `ldiapp w0,w1,\[x3,#-8\]!'
.*: Error: invalid addressing mode at operand 3 -- `ldiapp x0,x1,\[x3,#-16\]!'
.*: Error: expected an integer or zero register at operand 1 -- `ldiapp sp,x1,\[x3\],#16'
.*: Error: expected an integer or zero register at operand 1 -- `ldiapp wsp,w1,\[x3\],#8'
.*: Error: expected an integer or zero register at operand 2 -- `ldiapp x0,sp,\[x3\],#16'
.*: Error: expected an integer or zero register at operand 2 -- `ldiapp w0,wsp,\[x3\],#8'
.*: Error: invalid base register at operand 3 -- `ldiapp x0,x1,\[xzr\],#16'
.*: Error: invalid base register at operand 3 -- `ldiapp x0,x1,\[wzr\],#16'
.*: Error: expected a 64-bit base register at operand 3 -- `ldiapp w0,w1,\[w3\],#8'
.*: Error: invalid increment amount at operand 3 -- `ldiapp x0,x1,\[x3\],#8'
.*: Error: invalid increment amount at operand 3 -- `ldiapp w0,w1,\[x3\],#16'
.*: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp w0,w1,\[x3,#8\]'
.*: Error: operand 3 must be an address with pre-incrementing with write-back by ammount of stored bytes -- `stilp x0,x1,\[x3,#16\]'
.*: Error: invalid addressing mode at operand 3 -- `stilp w0,w1,\[x3\],#8'
.*: Error: invalid addressing mode at operand 3 -- `stilp x0,x1,\[x3\],#16'
.*: Error: expected an integer or zero register at operand 1 -- `stilp sp,x1,\[x3,#-16\]!'
.*: Error: expected an integer or zero register at operand 1 -- `stilp wsp,w1,\[x3,#-8\]!'
.*: Error: expected an integer or zero register at operand 2 -- `stilp x0,sp,\[x3,#-16\]!'
.*: Error: expected an integer or zero register at operand 2 -- `stilp w0,wsp,\[x3,#-8\]!'
.*: Error: invalid base register at operand 3 -- `stilp x0,x1,\[xzr,#-16\]!'
.*: Error: invalid base register at operand 3 -- `stilp x0,x1,\[wzr,#-16\]!'
.*: Error: expected a 64-bit base register at operand 3 -- `stilp w0,w1,\[w3,#-8\]!'
.*: Error: invalid increment amount at operand 3 -- `stilp w0,w1,\[x3,#-16\]!'
.*: Error: invalid increment amount at operand 3 -- `stilp x0,x1,\[x3,#-8\]!'
.*: Error: invalid increment amount at operand 3 -- `stilp w0,w1,\[x3,#16\]!'
.*: Error: invalid increment amount at operand 3 -- `stilp x0,x1,\[x3,#8\]!'
.*: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w0,\[x1,#4\]'
.*: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]'
.*: Error: unexpected address writeback at operand 2 -- `ldapr w0,\[x1,#-4\]!'
.*: Error: unexpected address writeback at operand 2 -- `ldapr x0,\[x1,#-8\]!'
.*: Error: expected an integer or zero register at operand 1 -- `ldapr wsp,\[x0\],#4'
.*: Error: expected an integer or zero register at operand 1 -- `ldapr sp,\[x0\],#8'
.*: Error: invalid base register at operand 2 -- `ldapr x0,\[wzr\],#8'
.*: Error: invalid base register at operand 2 -- `ldapr x0,\[xzr\],#8'
.*: Error: expected a 64-bit base register at operand 2 -- `ldapr x0,\[w1\],#8'
.*: Error: invalid increment amount at operand 2 -- `ldapr w0,\[x1\],#8'
.*: Error: invalid increment amount at operand 2 -- `ldapr x0,\[x1\],#4'
.*: Error: unexpected address writeback at operand 2 -- `stlr w0,\[x1\],#4'
.*: Error: unexpected address writeback at operand 2 -- `stlr x0,\[x1\],#8'
.*: Error: expected an integer or zero register at operand 1 -- `stlr wsp,\[x0,#-4\]!'
.*: Error: expected an integer or zero register at operand 1 -- `stlr sp,\[x0,#-8\]!'
.*: Error: invalid base register at operand 2 -- `stlr x0,\[xzr,#-8\]!'
.*: Error: invalid base register at operand 2 -- `stlr x0,\[wzr,#-8\]!'
.*: Error: expected a 64-bit base register at operand 2 -- `stlr x0,\[w1,#-8\]!'
.*: Error: the optional immediate offset can only be 0 at operand 2 -- `stlr w0,\[x1,#4\]'
.*: Error: the optional immediate offset can only be 0 at operand 2 -- `stlr x0,\[x1,#8\]'
.*: Error: invalid increment amount at operand 2 -- `stlr w0,\[x1,#-8\]!'
.*: Error: invalid increment amount at operand 2 -- `stlr x0,\[x1,#-4\]!'
.*: Error: invalid increment amount at operand 2 -- `stlr w0,\[x1,#4\]!'
.*: Error: invalid increment amount at operand 2 -- `stlr x0,\[x1,#8\]!'
.*: Warning: unpredictable load pair transfer with register overlap -- `ldiapp w0,w0,\[x1\]'
.*: Warning: unpredictable load pair transfer with register overlap -- `ldiapp x0,x0,\[x1\]'
.*: Warning: unpredictable load pair transfer with register overlap -- `ldiapp w0,w0,\[x1\],#8'
.*: Warning: unpredictable load pair transfer with register overlap -- `ldiapp x0,x0,\[x1\],#16'
.*: Warning: unpredictable load pair transfer with register overlap -- `stilp w0,w0,\[x1\]'
.*: Warning: unpredictable load pair transfer with register overlap -- `stilp x0,x0,\[x1\]'
.*: Warning: unpredictable load pair transfer with register overlap -- `stilp w0,w0,\[x1,#-8\]!'
.*: Warning: unpredictable load pair transfer with register overlap -- `stilp x0,x0,\[x1,#-16\]!'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldiapp x0,x1,\[x0\],#16'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldiapp x0,x1,\[x1\],#16'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldiapp w0,w1,\[x0\],#8'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldiapp w0,w1,\[x1\],#8'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldapr x0,\[x0\],#8'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldapr w0,\[x0\],#4'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldapr x1,\[x1\],#8'
.*: Warning: unpredictable transfer with writeback \(load\) -- `ldapr x30,\[x30\],#8'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stilp x0,x1,\[x1,#-16\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stilp w0,w1,\[x1,#-8\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stilp x0,x1,\[x0,#-16\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stilp w0,w1,\[x0,#-8\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stlr x0,\[x0,#-8\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stlr w0,\[x0,#-4\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stlr x1,\[x1,#-8\]!'
.*: Warning: unpredictable transfer with writeback \(store\) -- `stlr x30,\[x30,#-8\]!'