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gnu / binutils-gdb / 2786ef85faf16c13029548832c4e4b025bf2624c / . / gdb / aarch64-tdep.c
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/* Common target dependent code for GDB on AArch64 systems.
Copyright (C) 2009-2021 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h"
#include "regcache.h"
#include "reggroups.h"
#include "value.h"
#include "arch-utils.h"
#include "osabi.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "objfiles.h"
#include "dwarf2.h"
#include "dwarf2/frame.h"
#include "gdbtypes.h"
#include "prologue-value.h"
#include "target-descriptions.h"
#include "user-regs.h"
#include "ax-gdb.h"
#include "gdbsupport/selftest.h"
#include "aarch64-tdep.h"
#include "aarch64-ravenscar-thread.h"
#include "record.h"
#include "record-full.h"
#include "arch/aarch64-insn.h"
#include "gdbarch.h"
#include "opcode/aarch64.h"
#include <algorithm>
/* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
four members. */
#define HA_MAX_NUM_FLDS 4
/* All possible aarch64 target descriptors. */
static target_desc *tdesc_aarch64_list[AARCH64_MAX_SVE_VQ + 1][2/*pauth*/][2 /* mte */];
/* The standard register names, and all the valid aliases for them. */
static const struct
{
const char *const name;
int regnum;
} aarch64_register_aliases[] =
{
/* 64-bit register names. */
{"fp", AARCH64_FP_REGNUM},
{"lr", AARCH64_LR_REGNUM},
{"sp", AARCH64_SP_REGNUM},
/* 32-bit register names. */
{"w0", AARCH64_X0_REGNUM + 0},
{"w1", AARCH64_X0_REGNUM + 1},
{"w2", AARCH64_X0_REGNUM + 2},
{"w3", AARCH64_X0_REGNUM + 3},
{"w4", AARCH64_X0_REGNUM + 4},
{"w5", AARCH64_X0_REGNUM + 5},
{"w6", AARCH64_X0_REGNUM + 6},
{"w7", AARCH64_X0_REGNUM + 7},
{"w8", AARCH64_X0_REGNUM + 8},
{"w9", AARCH64_X0_REGNUM + 9},
{"w10", AARCH64_X0_REGNUM + 10},
{"w11", AARCH64_X0_REGNUM + 11},
{"w12", AARCH64_X0_REGNUM + 12},
{"w13", AARCH64_X0_REGNUM + 13},
{"w14", AARCH64_X0_REGNUM + 14},
{"w15", AARCH64_X0_REGNUM + 15},
{"w16", AARCH64_X0_REGNUM + 16},
{"w17", AARCH64_X0_REGNUM + 17},
{"w18", AARCH64_X0_REGNUM + 18},
{"w19", AARCH64_X0_REGNUM + 19},
{"w20", AARCH64_X0_REGNUM + 20},
{"w21", AARCH64_X0_REGNUM + 21},
{"w22", AARCH64_X0_REGNUM + 22},
{"w23", AARCH64_X0_REGNUM + 23},
{"w24", AARCH64_X0_REGNUM + 24},
{"w25", AARCH64_X0_REGNUM + 25},
{"w26", AARCH64_X0_REGNUM + 26},
{"w27", AARCH64_X0_REGNUM + 27},
{"w28", AARCH64_X0_REGNUM + 28},
{"w29", AARCH64_X0_REGNUM + 29},
{"w30", AARCH64_X0_REGNUM + 30},
/* specials */
{"ip0", AARCH64_X0_REGNUM + 16},
{"ip1", AARCH64_X0_REGNUM + 17}
};
/* The required core 'R' registers. */
static const char *const aarch64_r_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_X0_REGNUM! */
"x0", "x1", "x2", "x3",
"x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11",
"x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19",
"x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27",
"x28", "x29", "x30", "sp",
"pc", "cpsr"
};
/* The FP/SIMD 'V' registers. */
static const char *const aarch64_v_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_V0_REGNUM! */
"v0", "v1", "v2", "v3",
"v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19",
"v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27",
"v28", "v29", "v30", "v31",
"fpsr",
"fpcr"
};
/* The SVE 'Z' and 'P' registers. */
static const char *const aarch64_sve_register_names[] =
{
/* These registers must appear in consecutive RAW register number
order and they must begin with AARCH64_SVE_Z0_REGNUM! */
"z0", "z1", "z2", "z3",
"z4", "z5", "z6", "z7",
"z8", "z9", "z10", "z11",
"z12", "z13", "z14", "z15",
"z16", "z17", "z18", "z19",
"z20", "z21", "z22", "z23",
"z24", "z25", "z26", "z27",
"z28", "z29", "z30", "z31",
"fpsr", "fpcr",
"p0", "p1", "p2", "p3",
"p4", "p5", "p6", "p7",
"p8", "p9", "p10", "p11",
"p12", "p13", "p14", "p15",
"ffr", "vg"
};
static const char *const aarch64_pauth_register_names[] =
{
/* Authentication mask for data pointer. */
"pauth_dmask",
/* Authentication mask for code pointer. */
"pauth_cmask"
};
static const char *const aarch64_mte_register_names[] =
{
/* Tag Control Register. */
"tag_ctl"
};
/* AArch64 prologue cache structure. */
struct aarch64_prologue_cache
{
/* The program counter at the start of the function. It is used to
identify this frame as a prologue frame. */
CORE_ADDR func;
/* The program counter at the time this frame was created; i.e. where
this function was called from. It is used to identify this frame as a
stub frame. */
CORE_ADDR prev_pc;
/* The stack pointer at the time this frame was created; i.e. the
caller's stack pointer when this function was called. It is used
to identify this frame. */
CORE_ADDR prev_sp;
/* Is the target available to read from? */
int available_p;
/* The frame base for this frame is just prev_sp - frame size.
FRAMESIZE is the distance from the frame pointer to the
initial stack pointer. */
int framesize;
/* The register used to hold the frame pointer for this frame. */
int framereg;
/* Saved register offsets. */
trad_frame_saved_reg *saved_regs;
};
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
{
fprintf_filtered (file, _("AArch64 debugging is %s.\n"), value);
}
namespace {
/* Abstract instruction reader. */
class abstract_instruction_reader
{
public:
/* Read in one instruction. */
virtual ULONGEST read (CORE_ADDR memaddr, int len,
enum bfd_endian byte_order) = 0;
};
/* Instruction reader from real target. */
class instruction_reader : public abstract_instruction_reader
{
public:
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
override
{
return read_code_unsigned_integer (memaddr, len, byte_order);
}
};
} // namespace
/* If address signing is enabled, mask off the signature bits from the link
register, which is passed by value in ADDR, using the register values in
THIS_FRAME. */
static CORE_ADDR
aarch64_frame_unmask_lr (struct gdbarch_tdep *tdep,
struct frame_info *this_frame, CORE_ADDR addr)
{
if (tdep->has_pauth ()
&& frame_unwind_register_unsigned (this_frame,
tdep->pauth_ra_state_regnum))
{
int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base);
CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num);
addr = addr & ~cmask;
/* Record in the frame that the link register required unmasking. */
set_frame_previous_pc_masked (this_frame);
}
return addr;
}
/* Implement the "get_pc_address_flags" gdbarch method. */
static std::string
aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc)
{
if (pc != 0 && get_frame_pc_masked (frame))
return "PAC";
return "";
}
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
static CORE_ADDR
aarch64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start, CORE_ADDR limit,
struct aarch64_prologue_cache *cache,
abstract_instruction_reader& reader)
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
/* Whether the stack has been set. This should be true when we notice a SP
to FP move or if we are using the SP as the base register for storing
data, in case the FP is ommitted. */
bool seen_stack_set = false;
/* Track X registers and D registers in prologue. */
pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
regs[i] = pv_register (i, 0);
pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
for (; start < limit; start += 4)
{
uint32_t insn;
aarch64_inst inst;
insn = reader.read (start, 4, byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
break;
if (inst.opcode->iclass == addsub_imm
&& (inst.opcode->op == OP_ADD
|| strcmp ("sub", inst.opcode->name) == 0))
{
unsigned rd = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].reg.regno;
gdb_assert (aarch64_num_of_operands (inst.opcode) == 3);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP);
gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM);
if (inst.opcode->op == OP_ADD)
{
regs[rd] = pv_add_constant (regs[rn],
inst.operands[2].imm.value);
}
else
{
regs[rd] = pv_add_constant (regs[rn],
-inst.operands[2].imm.value);
}
/* Did we move SP to FP? */
if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM)
seen_stack_set = true;
}
else if (inst.opcode->iclass == pcreladdr
&& inst.operands[1].type == AARCH64_OPND_ADDR_ADRP)
{
gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
regs[inst.operands[0].reg.regno] = pv_unknown ();
}
else if (inst.opcode->iclass == branch_imm)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == condbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == branch_reg)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == compbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->op == OP_MOVZ)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
/* If this shows up before we set the stack, keep going. Otherwise
stop the analysis. */
if (seen_stack_set)
break;
regs[inst.operands[0].reg.regno] = pv_unknown ();
}
else if (inst.opcode->iclass == log_shift
&& strcmp (inst.opcode->name, "orr") == 0)
{
unsigned rd = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].reg.regno;
unsigned rm = inst.operands[2].reg.regno;
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn);
gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT);
if (inst.operands[2].shifter.amount == 0
&& rn == AARCH64_SP_REGNUM)
regs[rd] = regs[rm];
else
{
aarch64_debug_printf ("prologue analysis gave up "
"addr=%s opcode=0x%x (orr x register)",
core_addr_to_string_nz (start), insn);
break;
}
}
else if (inst.opcode->op == OP_STUR)
{
unsigned rt = inst.operands[0].reg.regno;
unsigned rn = inst.operands[1].addr.base_regno;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
gdb_assert (!inst.operands[1].addr.offset.is_reg);
stack.store
(pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
size, regs[rt]);
/* Are we storing with SP as a base? */
if (rn == AARCH64_SP_REGNUM)
seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldstpair_off
|| (inst.opcode->iclass == ldstpair_indexed
&& inst.operands[2].addr.preind))
&& strcmp ("stp", inst.opcode->name) == 0)
{
/* STP with addressing mode Pre-indexed and Base register. */
unsigned rt1;
unsigned rt2;
unsigned rn = inst.operands[2].addr.base_regno;
int32_t imm = inst.operands[2].addr.offset.imm;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
|| inst.operands[1].type == AARCH64_OPND_Ft2);
gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
gdb_assert (!inst.operands[2].addr.offset.is_reg);
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
further prologue analysis. */
if (stack.store_would_trash (pv_add_constant (regs[rn], imm)))
break;
if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8)))
break;
rt1 = inst.operands[0].reg.regno;
rt2 = inst.operands[1].reg.regno;
if (inst.operands[0].type == AARCH64_OPND_Ft)
{
rt1 += AARCH64_X_REGISTER_COUNT;
rt2 += AARCH64_X_REGISTER_COUNT;
}
stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
if (inst.operands[2].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
/* Ignore the instruction that allocates stack space and sets
the SP. */
if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback)
seen_stack_set = true;
}
else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */
|| (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */
&& (inst.opcode->op == OP_STR_POS
|| inst.opcode->op == OP_STRF_POS)))
&& inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM
&& strcmp ("str", inst.opcode->name) == 0)
{
/* STR (immediate) */
unsigned int rt = inst.operands[0].reg.regno;
int32_t imm = inst.operands[1].addr.offset.imm;
unsigned int rn = inst.operands[1].addr.base_regno;
int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
|| inst.operands[0].type == AARCH64_OPND_Ft);
if (inst.operands[0].type == AARCH64_OPND_Ft)
rt += AARCH64_X_REGISTER_COUNT;
stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
if (inst.operands[1].addr.writeback)
regs[rn] = pv_add_constant (regs[rn], imm);
/* Are we storing with SP as a base? */
if (rn == AARCH64_SP_REGNUM)
seen_stack_set = true;
}
else if (inst.opcode->iclass == testbranch)
{
/* Stop analysis on branch. */
break;
}
else if (inst.opcode->iclass == ic_system)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int ra_state_val = 0;
if (insn == 0xd503233f /* paciasp. */
|| insn == 0xd503237f /* pacibsp. */)
{
/* Return addresses are mangled. */
ra_state_val = 1;
}
else if (insn == 0xd50323bf /* autiasp. */
|| insn == 0xd50323ff /* autibsp. */)
{
/* Return addresses are not mangled. */
ra_state_val = 0;
}
else
{
aarch64_debug_printf ("prologue analysis gave up addr=%s"
" opcode=0x%x (iclass)",
core_addr_to_string_nz (start), insn);
break;
}
if (tdep->has_pauth () && cache != nullptr)
{
int regnum = tdep->pauth_ra_state_regnum;
cache->saved_regs[regnum].set_value (ra_state_val);
}
}
else
{
aarch64_debug_printf ("prologue analysis gave up addr=%s"
" opcode=0x%x",
core_addr_to_string_nz (start), insn);
break;
}
}
if (cache == NULL)
return start;
if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM))
{
/* Frame pointer is fp. Frame size is constant. */
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = -regs[AARCH64_FP_REGNUM].k;
}
else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM))
{
/* Try the stack pointer. */
cache->framesize = -regs[AARCH64_SP_REGNUM].k;
cache->framereg = AARCH64_SP_REGNUM;
}
else
{
/* We're just out of luck. We don't know where the frame is. */
cache->framereg = -1;
cache->framesize = 0;
}
for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i, &offset))
cache->saved_regs[i].set_addr (offset);
}
for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int regnum = gdbarch_num_regs (gdbarch);
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT,
&offset))
cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].set_addr (offset);
}
return start;
}
static CORE_ADDR
aarch64_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR start, CORE_ADDR limit,
struct aarch64_prologue_cache *cache)
{
instruction_reader reader;
return aarch64_analyze_prologue (gdbarch, start, limit, cache,
reader);
}
#if GDB_SELF_TEST
namespace selftests {
/* Instruction reader from manually cooked instruction sequences. */
class instruction_reader_test : public abstract_instruction_reader
{
public:
template<size_t SIZE>
explicit instruction_reader_test (const uint32_t (&insns)[SIZE])
: m_insns (insns), m_insns_size (SIZE)
{}
ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order)
override
{
SELF_CHECK (len == 4);
SELF_CHECK (memaddr % 4 == 0);
SELF_CHECK (memaddr / 4 < m_insns_size);
return m_insns[memaddr / 4];
}
private:
const uint32_t *m_insns;
size_t m_insns_size;
};
static void
aarch64_analyze_prologue_test (void)
{
struct gdbarch_info info;
info.bfd_arch_info = bfd_scan_arch ("aarch64");
struct gdbarch *gdbarch = gdbarch_find_by_info (info);
SELF_CHECK (gdbarch != NULL);
struct aarch64_prologue_cache cache;
cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* Test the simple prologue in which frame pointer is used. */
{
static const uint32_t insns[] = {
0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
0x910003fd, /* mov x29, sp */
0x97ffffe6, /* bl 0x400580 */
};
instruction_reader_test reader (insns);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
SELF_CHECK (end == 4 * 2);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 272);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == AARCH64_FP_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -272);
else if (i == AARCH64_LR_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -264);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int num_regs = gdbarch_num_regs (gdbarch);
int regnum = i + num_regs + AARCH64_D0_REGNUM;
SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
&& cache.saved_regs[regnum].realreg () == regnum);
}
}
/* Test a prologue in which STR is used and frame pointer is not
used. */
{
static const uint32_t insns[] = {
0xf81d0ff3, /* str x19, [sp, #-48]! */
0xb9002fe0, /* str w0, [sp, #44] */
0xf90013e1, /* str x1, [sp, #32]*/
0xfd000fe0, /* str d0, [sp, #24] */
0xaa0203f3, /* mov x19, x2 */
0xf94013e0, /* ldr x0, [sp, #32] */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
SELF_CHECK (end == 4 * 5);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 48);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == 1)
SELF_CHECK (cache.saved_regs[i].addr () == -16);
else if (i == 19)
SELF_CHECK (cache.saved_regs[i].addr () == -48);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
{
int num_regs = gdbarch_num_regs (gdbarch);
int regnum = i + num_regs + AARCH64_D0_REGNUM;
if (i == 0)
SELF_CHECK (cache.saved_regs[regnum].addr () == -24);
else
SELF_CHECK (cache.saved_regs[regnum].is_realreg ()
&& cache.saved_regs[regnum].realreg () == regnum);
}
}
/* Test handling of movz before setting the frame pointer. */
{
static const uint32_t insns[] = {
0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
0x52800020, /* mov w0, #0x1 */
0x910003fd, /* mov x29, sp */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 4th instruction. */
SELF_CHECK (end == (4 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 16);
}
/* Test handling of movz/stp when using the stack pointer as frame
pointer. */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0x290207e0, /* stp w0, w1, [sp, #16] */
0xa9018fe2, /* stp x2, x3, [sp, #24] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz/str when using the stack pointer as frame
pointer */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0xb9002be4, /* str w4, [sp, #40] */
0xf9001be5, /* str x5, [sp, #48] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz/stur when using the stack pointer as frame
pointer. */
{
static const uint32_t insns[] = {
0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
0x52800020, /* mov w0, #0x1 */
0xb80343e6, /* stur w6, [sp, #52] */
0xf80383e7, /* stur x7, [sp, #56] */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 5th instruction. */
SELF_CHECK (end == (5 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 64);
}
/* Test handling of movz when there is no frame pointer set or no stack
pointer used. */
{
static const uint32_t insns[] = {
0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
0x52800020, /* mov w0, #0x1 */
0x528000a2, /* mov w2, #0x5 */
0x97fffff8, /* bl 6e4 */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader);
/* We should stop at the 4th instruction. */
SELF_CHECK (end == (4 - 1) * 4);
SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM);
SELF_CHECK (cache.framesize == 16);
}
/* Test a prologue in which there is a return address signing instruction. */
if (tdep->has_pauth ())
{
static const uint32_t insns[] = {
0xd503233f, /* paciasp */
0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
0x910003fd, /* mov x29, sp */
0xf801c3f3, /* str x19, [sp, #28] */
0xb9401fa0, /* ldr x19, [x29, #28] */
};
instruction_reader_test reader (insns);
trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
reader);
SELF_CHECK (end == 4 * 4);
SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
SELF_CHECK (cache.framesize == 48);
for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
{
if (i == 19)
SELF_CHECK (cache.saved_regs[i].addr () == -20);
else if (i == AARCH64_FP_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -48);
else if (i == AARCH64_LR_REGNUM)
SELF_CHECK (cache.saved_regs[i].addr () == -40);
else
SELF_CHECK (cache.saved_regs[i].is_realreg ()
&& cache.saved_regs[i].realreg () == i);
}
if (tdep->has_pauth ())
{
int regnum = tdep->pauth_ra_state_regnum;
SELF_CHECK (cache.saved_regs[regnum].is_value ());
}
}
}
} // namespace selftests
#endif /* GDB_SELF_TEST */
/* Implement the "skip_prologue" gdbarch method. */
static CORE_ADDR
aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr, limit_pc;
/* See if we can determine the end of the prologue via the symbol
table. If so, then return either PC, or the PC after the
prologue, whichever is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return std::max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. */
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to
provide that bound, then use an arbitrary large number as the
upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
limit_pc = pc + 128; /* Magic. */
/* Try disassembling prologue. */
return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL);
}
/* Scan the function prologue for THIS_FRAME and populate the prologue
cache CACHE. */
static void
aarch64_scan_prologue (struct frame_info *this_frame,
struct aarch64_prologue_cache *cache)
{
CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR prev_pc = get_frame_pc (this_frame);
struct gdbarch *gdbarch = get_frame_arch (this_frame);
cache->prev_pc = prev_pc;
/* Assume we do not find a frame. */
cache->framereg = -1;
cache->framesize = 0;
if (find_pc_partial_function (block_addr, NULL, &prologue_start,
&prologue_end))
{
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0)
{
/* No line info so use the current PC. */
prologue_end = prev_pc;
}
else if (sal.end < prologue_end)
{
/* The next line begins after the function end. */
prologue_end = sal.end;
}
prologue_end = std::min (prologue_end, prev_pc);
aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
}
else
{
CORE_ADDR frame_loc;
frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM);
if (frame_loc == 0)
return;
cache->framereg = AARCH64_FP_REGNUM;
cache->framesize = 16;
cache->saved_regs[29].set_addr (0);
cache->saved_regs[30].set_addr (8);
}
}
/* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
function may throw an exception if the inferior's registers or memory is
not available. */
static void
aarch64_make_prologue_cache_1 (struct frame_info *this_frame,
struct aarch64_prologue_cache *cache)
{
CORE_ADDR unwound_fp;
int reg;
aarch64_scan_prologue (this_frame, cache);
if (cache->framereg == -1)
return;
unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
if (unwound_fp == 0)
return;
cache->prev_sp = unwound_fp + cache->framesize;
/* Calculate actual addresses of saved registers using offsets
determined by aarch64_analyze_prologue. */
for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
if (cache->saved_regs[reg].is_addr ())
cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr ()
+ cache->prev_sp);
cache->func = get_frame_func (this_frame);
cache->available_p = 1;
}
/* Allocate and fill in *THIS_CACHE with information about the prologue of
*THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
Return a pointer to the current aarch64_prologue_cache in
*THIS_CACHE. */
static struct aarch64_prologue_cache *
aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache)
{
struct aarch64_prologue_cache *cache;
if (*this_cache != NULL)
return (struct aarch64_prologue_cache *) *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
*this_cache = cache;
try
{
aarch64_make_prologue_cache_1 (this_frame, cache);
}
catch (const gdb_exception_error &ex)
{
if (ex.error != NOT_AVAILABLE_ERROR)
throw;
}
return cache;
}
/* Implement the "stop_reason" frame_unwind method. */
static enum unwind_stop_reason
aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame,
void **this_cache)
{
struct aarch64_prologue_cache *cache
= aarch64_make_prologue_cache (this_frame, this_cache);
if (!cache->available_p)
return UNWIND_UNAVAILABLE;
/* Halt the backtrace at "_start". */
if (cache->prev_pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
return UNWIND_OUTERMOST;
/* We've hit a wall, stop. */
if (cache->prev_sp == 0)
return UNWIND_OUTERMOST;
return UNWIND_NO_REASON;
}
/* Our frame ID for a normal frame is the current function's starting
PC and the caller's SP when we were called. */
static void
aarch64_prologue_this_id (struct frame_info *this_frame,
void **this_cache, struct frame_id *this_id)
{
struct aarch64_prologue_cache *cache
= aarch64_make_prologue_cache (this_frame, this_cache);
if (!cache->available_p)
*this_id = frame_id_build_unavailable_stack (cache->func);
else
*this_id = frame_id_build (cache->prev_sp, cache->func);
}
/* Implement the "prev_register" frame_unwind method. */
static struct value *
aarch64_prologue_prev_register (struct frame_info *this_frame,
void **this_cache, int prev_regnum)
{
struct aarch64_prologue_cache *cache
= aarch64_make_prologue_cache (this_frame, this_cache);
/* If we are asked to unwind the PC, then we need to return the LR
instead. The prologue may save PC, but it will point into this
frame's prologue, not the next frame's resume location. */
if (prev_regnum == AARCH64_PC_REGNUM)
{
CORE_ADDR lr;
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
if (tdep->has_pauth ()
&& cache->saved_regs[tdep->pauth_ra_state_regnum].is_value ())
lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
return frame_unwind_got_constant (this_frame, prev_regnum, lr);
}
/* SP is generally not saved to the stack, but this frame is
identified by the next frame's stack pointer at the time of the
call. The value was already reconstructed into PREV_SP. */
/*
+----------+ ^
| saved lr | |
+->| saved fp |--+
| | |
| | | <- Previous SP
| +----------+
| | saved lr |
+--| saved fp |<- FP
| |
| |<- SP
+----------+ */
if (prev_regnum == AARCH64_SP_REGNUM)
return frame_unwind_got_constant (this_frame, prev_regnum,
cache->prev_sp);
return trad_frame_get_prev_register (this_frame, cache->saved_regs,
prev_regnum);
}
/* AArch64 prologue unwinder. */
static frame_unwind aarch64_prologue_unwind =
{
"aarch64 prologue",
NORMAL_FRAME,
aarch64_prologue_frame_unwind_stop_reason,
aarch64_prologue_this_id,
aarch64_prologue_prev_register,
NULL,
default_frame_sniffer
};
/* Allocate and fill in *THIS_CACHE with information about the prologue of
*THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
Return a pointer to the current aarch64_prologue_cache in
*THIS_CACHE. */
static struct aarch64_prologue_cache *
aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache)
{
struct aarch64_prologue_cache *cache;
if (*this_cache != NULL)
return (struct aarch64_prologue_cache *) *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
*this_cache = cache;
try
{
cache->prev_sp = get_frame_register_unsigned (this_frame,
AARCH64_SP_REGNUM);
cache->prev_pc = get_frame_pc (this_frame);
cache->available_p = 1;
}
catch (const gdb_exception_error &ex)
{
if (ex.error != NOT_AVAILABLE_ERROR)
throw;
}
return cache;
}
/* Implement the "stop_reason" frame_unwind method. */
static enum unwind_stop_reason
aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame,
void **this_cache)
{
struct aarch64_prologue_cache *cache
= aarch64_make_stub_cache (this_frame, this_cache);
if (!cache->available_p)
return UNWIND_UNAVAILABLE;
return UNWIND_NO_REASON;
}
/* Our frame ID for a stub frame is the current SP and LR. */
static void
aarch64_stub_this_id (struct frame_info *this_frame,
void **this_cache, struct frame_id *this_id)
{
struct aarch64_prologue_cache *cache
= aarch64_make_stub_cache (this_frame, this_cache);
if (cache->available_p)
*this_id = frame_id_build (cache->prev_sp, cache->prev_pc);
else
*this_id = frame_id_build_unavailable_stack (cache->prev_pc);
}
/* Implement the "sniffer" frame_unwind method. */
static int
aarch64_stub_unwind_sniffer (const struct frame_unwind *self,
struct frame_info *this_frame,
void **this_prologue_cache)
{
CORE_ADDR addr_in_block;
gdb_byte dummy[4];
addr_in_block = get_frame_address_in_block (this_frame);
if (in_plt_section (addr_in_block)
/* We also use the stub winder if the target memory is unreadable
to avoid having the prologue unwinder trying to read it. */
|| target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
return 1;
return 0;
}
/* AArch64 stub unwinder. */
static frame_unwind aarch64_stub_unwind =
{
"aarch64 stub",
NORMAL_FRAME,
aarch64_stub_frame_unwind_stop_reason,
aarch64_stub_this_id,
aarch64_prologue_prev_register,
NULL,
aarch64_stub_unwind_sniffer
};
/* Return the frame base address of *THIS_FRAME. */
static CORE_ADDR
aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache)
{
struct aarch64_prologue_cache *cache
= aarch64_make_prologue_cache (this_frame, this_cache);
return cache->prev_sp - cache->framesize;
}
/* AArch64 default frame base information. */
static frame_base aarch64_normal_base =
{
&aarch64_prologue_unwind,
aarch64_normal_frame_base,
aarch64_normal_frame_base,
aarch64_normal_frame_base
};
/* Return the value of the REGNUM register in the previous frame of
*THIS_FRAME. */
static struct value *
aarch64_dwarf2_prev_register (struct frame_info *this_frame,
void **this_cache, int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame));
CORE_ADDR lr;
switch (regnum)
{
case AARCH64_PC_REGNUM:
lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM);
lr = aarch64_frame_unmask_lr (tdep, this_frame, lr);
return frame_unwind_got_constant (this_frame, regnum, lr);
default:
internal_error (__FILE__, __LINE__,
_("Unexpected register %d"), regnum);
}
}
static const unsigned char op_lit0 = DW_OP_lit0;
static const unsigned char op_lit1 = DW_OP_lit1;
/* Implement the "init_reg" dwarf2_frame_ops method. */
static void
aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
struct dwarf2_frame_state_reg *reg,
struct frame_info *this_frame)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
switch (regnum)
{
case AARCH64_PC_REGNUM:
reg->how = DWARF2_FRAME_REG_FN;
reg->loc.fn = aarch64_dwarf2_prev_register;
return;
case AARCH64_SP_REGNUM:
reg->how = DWARF2_FRAME_REG_CFA;
return;
}
/* Init pauth registers. */
if (tdep->has_pauth ())
{
if (regnum == tdep->pauth_ra_state_regnum)
{
/* Initialize RA_STATE to zero. */
reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
reg->loc.exp.start = &op_lit0;
reg->loc.exp.len = 1;
return;
}
else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
|| regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
{
reg->how = DWARF2_FRAME_REG_SAME_VALUE;
return;
}
}
}
/* Implement the execute_dwarf_cfa_vendor_op method. */
static bool
aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op,
struct dwarf2_frame_state *fs)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
struct dwarf2_frame_state_reg *ra_state;
if (op == DW_CFA_AARCH64_negate_ra_state)
{
/* On systems without pauth, treat as a nop. */
if (!tdep->has_pauth ())
return true;
/* Allocate RA_STATE column if it's not allocated yet. */
fs->regs.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE + 1);
/* Toggle the status of RA_STATE between 0 and 1. */
ra_state = &(fs->regs.reg[AARCH64_DWARF_PAUTH_RA_STATE]);
ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP;
if (ra_state->loc.exp.start == nullptr
|| ra_state->loc.exp.start == &op_lit0)
ra_state->loc.exp.start = &op_lit1;
else
ra_state->loc.exp.start = &op_lit0;
ra_state->loc.exp.len = 1;
return true;
}
return false;
}
/* Used for matching BRK instructions for AArch64. */
static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f;
static constexpr uint32_t BRK_INSN_BASE = 0xd4200000;
/* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
static bool
aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address)
{
const uint32_t insn_len = 4;
gdb_byte target_mem[4];
/* Enable the automatic memory restoration from breakpoints while
we read the memory. Otherwise we may find temporary breakpoints, ones
inserted by GDB, and flag them as permanent breakpoints. */
scoped_restore restore_memory
= make_scoped_restore_show_memory_breakpoints (0);
if (target_read_memory (address, target_mem, insn_len) == 0)
{
uint32_t insn =
(uint32_t) extract_unsigned_integer (target_mem, insn_len,
gdbarch_byte_order_for_code (gdbarch));
/* Check if INSN is a BRK instruction pattern. There are multiple choices
of such instructions with different immediate values. Different OS'
may use a different variation, but they have the same outcome. */
return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE);
}
return false;
}
/* When arguments must be pushed onto the stack, they go on in reverse
order. The code below implements a FILO (stack) to do this. */
struct stack_item_t
{
/* Value to pass on stack. It can be NULL if this item is for stack
padding. */
const gdb_byte *data;
/* Size in bytes of value to pass on stack. */
int len;
};
/* Implement the gdbarch type alignment method, overrides the generic
alignment algorithm for anything that is aarch64 specific. */
static ULONGEST
aarch64_type_align (gdbarch *gdbarch, struct type *t)
{
t = check_typedef (t);
if (t->code () == TYPE_CODE_ARRAY && t->is_vector ())
{
/* Use the natural alignment for vector types (the same for
scalar type), but the maximum alignment is 128-bit. */
if (TYPE_LENGTH (t) > 16)
return 16;
else
return TYPE_LENGTH (t);
}
/* Allow the common code to calculate the alignment. */
return 0;
}
/* Worker function for aapcs_is_vfp_call_or_return_candidate.
Return the number of register required, or -1 on failure.
When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
to the element, else fail if the type of this element does not match the
existing value. */
static int
aapcs_is_vfp_call_or_return_candidate_1 (struct type *type,
struct type **fundamental_type)
{
if (type == nullptr)
return -1;
switch (type->code ())
{
case TYPE_CODE_FLT:
if (TYPE_LENGTH (type) > 16)
return -1;
if (*fundamental_type == nullptr)
*fundamental_type = type;
else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
|| type->code () != (*fundamental_type)->code ())
return -1;
return 1;
case TYPE_CODE_COMPLEX:
{
struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type));
if (TYPE_LENGTH (target_type) > 16)
return -1;
if (*fundamental_type == nullptr)
*fundamental_type = target_type;
else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type)
|| target_type->code () != (*fundamental_type)->code ())
return -1;
return 2;
}
case TYPE_CODE_ARRAY:
{
if (type->is_vector ())
{
if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16)
return -1;
if (*fundamental_type == nullptr)
*fundamental_type = type;
else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type)
|| type->code () != (*fundamental_type)->code ())
return -1;
return 1;
}
else
{
struct type *target_type = TYPE_TARGET_TYPE (type);
int count = aapcs_is_vfp_call_or_return_candidate_1
(target_type, fundamental_type);
if (count == -1)
return count;
count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type));
return count;
}
}
case TYPE_CODE_STRUCT:
case TYPE_CODE_UNION:
{
int count = 0;
for (int i = 0; i < type->num_fields (); i++)
{
/* Ignore any static fields. */
if (field_is_static (&type->field (i)))
continue;
struct type *member = check_typedef (type->field (i).type ());
int sub_count = aapcs_is_vfp_call_or_return_candidate_1
(member, fundamental_type);
if (sub_count == -1)
return -1;
count += sub_count;
}
/* Ensure there is no padding between the fields (allowing for empty
zero length structs) */
int ftype_length = (*fundamental_type == nullptr)
? 0 : TYPE_LENGTH (*fundamental_type);
if (count * ftype_length != TYPE_LENGTH (type))
return -1;
return count;
}
default:
break;
}
return -1;
}
/* Return true if an argument, whose type is described by TYPE, can be passed or
returned in simd/fp registers, providing enough parameter passing registers
are available. This is as described in the AAPCS64.
Upon successful return, *COUNT returns the number of needed registers,
*FUNDAMENTAL_TYPE contains the type of those registers.
Candidate as per the AAPCS64 5.4.2.C is either a:
- float.
- short-vector.
- HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
all the members are floats and has at most 4 members.
- HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
all the members are short vectors and has at most 4 members.
- Complex (7.1.1)
Note that HFAs and HVAs can include nested structures and arrays. */
static bool
aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count,
struct type **fundamental_type)
{
if (type == nullptr)
return false;
*fundamental_type = nullptr;
int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type,
fundamental_type);
if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS)
{
*count = ag_count;
return true;
}
else
return false;
}
/* AArch64 function call information structure. */
struct aarch64_call_info
{
/* the current argument number. */
unsigned argnum = 0;
/* The next general purpose register number, equivalent to NGRN as
described in the AArch64 Procedure Call Standard. */
unsigned ngrn = 0;
/* The next SIMD and floating point register number, equivalent to
NSRN as described in the AArch64 Procedure Call Standard. */
unsigned nsrn = 0;
/* The next stacked argument address, equivalent to NSAA as
described in the AArch64 Procedure Call Standard. */
unsigned nsaa = 0;
/* Stack item vector. */
std::vector<stack_item_t> si;
};
/* Pass a value in a sequence of consecutive X registers. The caller
is responsible for ensuring sufficient registers are available. */
static void
pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache,
struct aarch64_call_info *info, struct type *type,
struct value *arg)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int len = TYPE_LENGTH (type);
enum type_code typecode = type->code ();
int regnum = AARCH64_X0_REGNUM + info->ngrn;
const bfd_byte *buf = value_contents (arg);
info->argnum++;
while (len > 0)
{
int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE;
CORE_ADDR regval = extract_unsigned_integer (buf, partial_len,
byte_order);
/* Adjust sub-word struct/union args when big-endian. */
if (byte_order == BFD_ENDIAN_BIG
&& partial_len < X_REGISTER_SIZE
&& (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT);
aarch64_debug_printf ("arg %d in %s = 0x%s", info->argnum,
gdbarch_register_name (gdbarch, regnum),
phex (regval, X_REGISTER_SIZE));
regcache_cooked_write_unsigned (regcache, regnum, regval);
len -= partial_len;
buf += partial_len;
regnum++;
}
}
/* Attempt to marshall a value in a V register. Return 1 if
successful, or 0 if insufficient registers are available. This
function, unlike the equivalent pass_in_x() function does not
handle arguments spread across multiple registers. */
static int
pass_in_v (struct gdbarch *gdbarch,
struct regcache *regcache,
struct aarch64_call_info *info,
int len, const bfd_byte *buf)
{
if (info->nsrn < 8)
{
int regnum = AARCH64_V0_REGNUM + info->nsrn;
/* Enough space for a full vector register. */
gdb_byte reg[register_size (gdbarch, regnum)];
gdb_assert (len <= sizeof (reg));
info->argnum++;
info->nsrn++;
memset (reg, 0, sizeof (reg));
/* PCS C.1, the argument is allocated to the least significant
bits of V register. */
memcpy (reg, buf, len);
regcache->cooked_write (regnum, reg);
aarch64_debug_printf ("arg %d in %s", info->argnum,
gdbarch_register_name (gdbarch, regnum));
return 1;
}
info->nsrn = 8;
return 0;
}
/* Marshall an argument onto the stack. */
static void
pass_on_stack (struct aarch64_call_info *info, struct type *type,
struct value *arg)
{
const bfd_byte *buf = value_contents (arg);
int len = TYPE_LENGTH (type);
int align;
stack_item_t item;
info->argnum++;
align = type_align (type);
/* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
Natural alignment of the argument's type. */
align = align_up (align, 8);
/* The AArch64 PCS requires at most doubleword alignment. */
if (align > 16)
align = 16;
aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len,
info->nsaa);
item.len = len;
item.data = buf;
info->si.push_back (item);
info->nsaa += len;
if (info->nsaa & (align - 1))
{
/* Push stack alignment padding. */
int pad = align - (info->nsaa & (align - 1));
item.len = pad;
item.data = NULL;
info->si.push_back (item);
info->nsaa += pad;
}
}
/* Marshall an argument into a sequence of one or more consecutive X
registers or, if insufficient X registers are available then onto
the stack. */
static void
pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache,
struct aarch64_call_info *info, struct type *type,
struct value *arg)
{
int len = TYPE_LENGTH (type);
int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE;
/* PCS C.13 - Pass in registers if we have enough spare */
if (info->ngrn + nregs <= 8)
{
pass_in_x (gdbarch, regcache, info, type, arg);
info->ngrn += nregs;
}
else
{
info->ngrn = 8;
pass_on_stack (info, type, arg);
}
}
/* Pass a value, which is of type arg_type, in a V register. Assumes value is a
aapcs_is_vfp_call_or_return_candidate and there are enough spare V
registers. A return value of false is an error state as the value will have
been partially passed to the stack. */
static bool
pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache,
struct aarch64_call_info *info, struct type *arg_type,
struct value *arg)
{
switch (arg_type->code ())
{
case TYPE_CODE_FLT:
return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
value_contents (arg));
break;
case TYPE_CODE_COMPLEX:
{
const bfd_byte *buf = value_contents (arg);
struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type));
if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
buf))
return false;
return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type),
buf + TYPE_LENGTH (target_type));
}
case TYPE_CODE_ARRAY:
if (arg_type->is_vector ())
return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type),
value_contents (arg));
/* fall through. */
case TYPE_CODE_STRUCT:
case TYPE_CODE_UNION:
for (int i = 0; i < arg_type->num_fields (); i++)
{
/* Don't include static fields. */
if (field_is_static (&arg_type->field (i)))
continue;
struct value *field = value_primitive_field (arg, 0, i, arg_type);
struct type *field_type = check_typedef (value_type (field));
if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type,
field))
return false;
}
return true;
default:
return false;
}
}
/* Implement the "push_dummy_call" gdbarch method. */
static CORE_ADDR
aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs,
struct value **args, CORE_ADDR sp,
function_call_return_method return_method,
CORE_ADDR struct_addr)
{
int argnum;
struct aarch64_call_info info;
/* We need to know what the type of the called function is in order
to determine the number of named/anonymous arguments for the
actual argument placement, and the return type in order to handle
return value correctly.
The generic code above us views the decision of return in memory
or return in registers as a two stage processes. The language
handler is consulted first and may decide to return in memory (eg
class with copy constructor returned by value), this will cause
the generic code to allocate space AND insert an initial leading
argument.
If the language code does not decide to pass in memory then the
target code is consulted.
If the language code decides to pass in memory we want to move
the pointer inserted as the initial argument from the argument
list and into X8, the conventional AArch64 struct return pointer
register. */
/* Set the return address. For the AArch64, the return breakpoint
is always at BP_ADDR. */
regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr);
/* If we were given an initial argument for the return slot, lose it. */
if (return_method == return_method_hidden_param)
{
args++;
nargs--;
}
/* The struct_return pointer occupies X8. */
if (return_method != return_method_normal)
{
aarch64_debug_printf ("struct return in %s = 0x%s",
gdbarch_register_name
(gdbarch, AARCH64_STRUCT_RETURN_REGNUM),
paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM,
struct_addr);
}
for (argnum = 0; argnum < nargs; argnum++)
{
struct value *arg = args[argnum];
struct type *arg_type, *fundamental_type;
int len, elements;
arg_type = check_typedef (value_type (arg));
len = TYPE_LENGTH (arg_type);
/* If arg can be passed in v registers as per the AAPCS64, then do so if
if there are enough spare registers. */
if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements,
&fundamental_type))
{
if (info.nsrn + elements <= 8)
{
/* We know that we have sufficient registers available therefore
this will never need to fallback to the stack. */
if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type,
arg))
gdb_assert_not_reached ("Failed to push args");
}
else
{
info.nsrn = 8;
pass_on_stack (&info, arg_type, arg);
}
continue;
}
switch (arg_type->code ())
{
case TYPE_CODE_INT:
case TYPE_CODE_BOOL:
case TYPE_CODE_CHAR:
case TYPE_CODE_RANGE:
case TYPE_CODE_ENUM:
if (len < 4)
{
/* Promote to 32 bit integer. */
if (arg_type->is_unsigned ())
arg_type = builtin_type (gdbarch)->builtin_uint32;
else
arg_type = builtin_type (gdbarch)->builtin_int32;
arg = value_cast (arg_type, arg);
}
pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
break;
case TYPE_CODE_STRUCT:
case TYPE_CODE_ARRAY:
case TYPE_CODE_UNION:
if (len > 16)
{
/* PCS B.7 Aggregates larger than 16 bytes are passed by
invisible reference. */
/* Allocate aligned storage. */
sp = align_down (sp - len, 16);
/* Write the real data into the stack. */
write_memory (sp, value_contents (arg), len);
/* Construct the indirection. */
arg_type = lookup_pointer_type (arg_type);
arg = value_from_pointer (arg_type, sp);
pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
}
else
/* PCS C.15 / C.18 multiple values pass. */
pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
break;
default:
pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg);
break;
}
}
/* Make sure stack retains 16 byte alignment. */
if (info.nsaa & 15)
sp -= 16 - (info.nsaa & 15);
while (!info.si.empty ())
{
const stack_item_t &si = info.si.back ();
sp -= si.len;
if (si.data != NULL)
write_memory (sp, si.data, si.len);
info.si.pop_back ();
}
/* Finally, update the SP register. */
regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp);
return sp;
}
/* Implement the "frame_align" gdbarch method. */
static CORE_ADDR
aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
/* Align the stack to sixteen bytes. */
return sp & ~(CORE_ADDR) 15;
}
/* Return the type for an AdvSISD Q register. */
static struct type *
aarch64_vnq_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vnq_type == NULL)
{
struct type *t;
struct type *elem;
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
TYPE_CODE_UNION);
elem = builtin_type (gdbarch)->builtin_uint128;
append_composite_type_field (t, "u", elem);
elem = builtin_type (gdbarch)->builtin_int128;
append_composite_type_field (t, "s", elem);
tdep->vnq_type = t;
}
return tdep->vnq_type;
}
/* Return the type for an AdvSISD D register. */
static struct type *
aarch64_vnd_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vnd_type == NULL)
{
struct type *t;
struct type *elem;
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
TYPE_CODE_UNION);
elem = builtin_type (gdbarch)->builtin_double;
append_composite_type_field (t, "f", elem);
elem = builtin_type (gdbarch)->builtin_uint64;
append_composite_type_field (t, "u", elem);
elem = builtin_type (gdbarch)->builtin_int64;
append_composite_type_field (t, "s", elem);
tdep->vnd_type = t;
}
return tdep->vnd_type;
}
/* Return the type for an AdvSISD S register. */
static struct type *
aarch64_vns_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vns_type == NULL)
{
struct type *t;
struct type *elem;
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
TYPE_CODE_UNION);
elem = builtin_type (gdbarch)->builtin_float;
append_composite_type_field (t, "f", elem);
elem = builtin_type (gdbarch)->builtin_uint32;
append_composite_type_field (t, "u", elem);
elem = builtin_type (gdbarch)->builtin_int32;
append_composite_type_field (t, "s", elem);
tdep->vns_type = t;
}
return tdep->vns_type;
}
/* Return the type for an AdvSISD H register. */
static struct type *
aarch64_vnh_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vnh_type == NULL)
{
struct type *t;
struct type *elem;
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
TYPE_CODE_UNION);
elem = builtin_type (gdbarch)->builtin_bfloat16;
append_composite_type_field (t, "bf", elem);
elem = builtin_type (gdbarch)->builtin_half;
append_composite_type_field (t, "f", elem);
elem = builtin_type (gdbarch)->builtin_uint16;
append_composite_type_field (t, "u", elem);
elem = builtin_type (gdbarch)->builtin_int16;
append_composite_type_field (t, "s", elem);
tdep->vnh_type = t;
}
return tdep->vnh_type;
}
/* Return the type for an AdvSISD B register. */
static struct type *
aarch64_vnb_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vnb_type == NULL)
{
struct type *t;
struct type *elem;
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
TYPE_CODE_UNION);
elem = builtin_type (gdbarch)->builtin_uint8;
append_composite_type_field (t, "u", elem);
elem = builtin_type (gdbarch)->builtin_int8;
append_composite_type_field (t, "s", elem);
tdep->vnb_type = t;
}
return tdep->vnb_type;
}
/* Return the type for an AdvSISD V register. */
static struct type *
aarch64_vnv_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->vnv_type == NULL)
{
/* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
slice from the non-pseudo vector registers. However NEON V registers
are always vector registers, and need constructing as such. */
const struct builtin_type *bt = builtin_type (gdbarch);
struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv",
TYPE_CODE_UNION);
struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd",
TYPE_CODE_UNION);
append_composite_type_field (sub, "f",
init_vector_type (bt->builtin_double, 2));
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint64, 2));
append_composite_type_field (sub, "s",
init_vector_type (bt->builtin_int64, 2));
append_composite_type_field (t, "d", sub);
sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns",
TYPE_CODE_UNION);
append_composite_type_field (sub, "f",
init_vector_type (bt->builtin_float, 4));
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint32, 4));
append_composite_type_field (sub, "s",
init_vector_type (bt->builtin_int32, 4));
append_composite_type_field (t, "s", sub);
sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
TYPE_CODE_UNION);
append_composite_type_field (sub, "bf",
init_vector_type (bt->builtin_bfloat16, 8));
append_composite_type_field (sub, "f",
init_vector_type (bt->builtin_half, 8));
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint16, 8));
append_composite_type_field (sub, "s",
init_vector_type (bt->builtin_int16, 8));
append_composite_type_field (t, "h", sub);
sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb",
TYPE_CODE_UNION);
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint8, 16));
append_composite_type_field (sub, "s",
init_vector_type (bt->builtin_int8, 16));
append_composite_type_field (t, "b", sub);
sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq",
TYPE_CODE_UNION);
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint128, 1));
append_composite_type_field (sub, "s",
init_vector_type (bt->builtin_int128, 1));
append_composite_type_field (t, "q", sub);
tdep->vnv_type = t;
}
return tdep->vnv_type;
}
/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
static int
aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30)
return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0;
if (reg == AARCH64_DWARF_SP)
return AARCH64_SP_REGNUM;
if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31)
return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0;
if (reg == AARCH64_DWARF_SVE_VG)
return AARCH64_SVE_VG_REGNUM;
if (reg == AARCH64_DWARF_SVE_FFR)
return AARCH64_SVE_FFR_REGNUM;
if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15)
return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0;
if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15)
return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0;
if (tdep->has_pauth ())
{
if (reg >= AARCH64_DWARF_PAUTH_DMASK && reg <= AARCH64_DWARF_PAUTH_CMASK)
return tdep->pauth_reg_base + reg - AARCH64_DWARF_PAUTH_DMASK;
if (reg == AARCH64_DWARF_PAUTH_RA_STATE)
return tdep->pauth_ra_state_regnum;
}
return -1;
}
/* Implement the "print_insn" gdbarch method. */
static int
aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info)
{
info->symbols = NULL;
return default_print_insn (memaddr, info);
}
/* AArch64 BRK software debug mode instruction.
Note that AArch64 code is always little-endian.
1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4};
typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint;
/* Extract from an array REGS containing the (raw) register state a
function return value of type TYPE, and copy that, in virtual
format, into VALBUF. */
static void
aarch64_extract_return_value (struct type *type, struct regcache *regs,
gdb_byte *valbuf)
{
struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int elements;
struct type *fundamental_type;
if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
&fundamental_type))
{
int len = TYPE_LENGTH (fundamental_type);
for (int i = 0; i < elements; i++)
{
int regno = AARCH64_V0_REGNUM + i;
/* Enough space for a full vector register. */
gdb_byte buf[register_size (gdbarch, regno)];
gdb_assert (len <= sizeof (buf));
aarch64_debug_printf
("read HFA or HVA return value element %d from %s",
i + 1, gdbarch_register_name (gdbarch, regno));
regs->cooked_read (regno, buf);
memcpy (valbuf, buf, len);
valbuf += len;
}
}
else if (type->code () == TYPE_CODE_INT
|| type->code () == TYPE_CODE_CHAR
|| type->code () == TYPE_CODE_BOOL
|| type->code () == TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type)
|| type->code () == TYPE_CODE_ENUM)
{
/* If the type is a plain integer, then the access is
straight-forward. Otherwise we have to play around a bit
more. */
int len = TYPE_LENGTH (type);
int regno = AARCH64_X0_REGNUM;
ULONGEST tmp;
while (len > 0)
{
/* By using store_unsigned_integer we avoid having to do
anything special for small big-endian values. */
regcache_cooked_read_unsigned (regs, regno++, &tmp);
store_unsigned_integer (valbuf,
(len > X_REGISTER_SIZE
? X_REGISTER_SIZE : len), byte_order, tmp);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
}
else
{
/* For a structure or union the behaviour is as if the value had
been stored to word-aligned memory and then loaded into
registers with 64-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = AARCH64_X0_REGNUM;
bfd_byte buf[X_REGISTER_SIZE];
while (len > 0)
{
regs->cooked_read (regno++, buf);
memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
}
}
/* Will a function return an aggregate type in memory or in a
register? Return 0 if an aggregate type can be returned in a
register, 1 if it must be returned in memory. */
static int
aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
{
type = check_typedef (type);
int elements;
struct type *fundamental_type;
if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
&fundamental_type))
{
/* v0-v7 are used to return values and one register is allocated
for one member. However, HFA or HVA has at most four members. */
return 0;
}
if (TYPE_LENGTH (type) > 16)
{
/* PCS B.6 Aggregates larger than 16 bytes are passed by
invisible reference. */
return 1;
}
return 0;
}
/* Write into appropriate registers a function return value of type
TYPE, given in virtual format. */
static void
aarch64_store_return_value (struct type *type, struct regcache *regs,
const gdb_byte *valbuf)
{
struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int elements;
struct type *fundamental_type;
if (aapcs_is_vfp_call_or_return_candidate (type, &elements,
&fundamental_type))
{
int len = TYPE_LENGTH (fundamental_type);
for (int i = 0; i < elements; i++)
{
int regno = AARCH64_V0_REGNUM + i;
/* Enough space for a full vector register. */
gdb_byte tmpbuf[register_size (gdbarch, regno)];
gdb_assert (len <= sizeof (tmpbuf));
aarch64_debug_printf
("write HFA or HVA return value element %d to %s",
i + 1, gdbarch_register_name (gdbarch, regno));
memcpy (tmpbuf, valbuf,
len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len);
regs->cooked_write (regno, tmpbuf);
valbuf += len;
}
}
else if (type->code () == TYPE_CODE_INT
|| type->code () == TYPE_CODE_CHAR
|| type->code () == TYPE_CODE_BOOL
|| type->code () == TYPE_CODE_PTR
|| TYPE_IS_REFERENCE (type)
|| type->code () == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= X_REGISTER_SIZE)
{
/* Values of one word or less are zero/sign-extended and
returned in r0. */
bfd_byte tmpbuf[X_REGISTER_SIZE];
LONGEST val = unpack_long (type, valbuf);
store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val);
regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf);
}
else
{
/* Integral values greater than one word are stored in
consecutive registers starting with r0. This will always
be a multiple of the regiser size. */
int len = TYPE_LENGTH (type);
int regno = AARCH64_X0_REGNUM;
while (len > 0)
{
regs->cooked_write (regno++, valbuf);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
}
}
else
{
/* For a structure or union the behaviour is as if the value had
been stored to word-aligned memory and then loaded into
registers with 64-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = AARCH64_X0_REGNUM;
bfd_byte tmpbuf[X_REGISTER_SIZE];
while (len > 0)
{
memcpy (tmpbuf, valbuf,
len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len);
regs->cooked_write (regno++, tmpbuf);
len -= X_REGISTER_SIZE;
valbuf += X_REGISTER_SIZE;
}
}
}
/* Implement the "return_value" gdbarch method. */
static enum return_value_convention
aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value,
struct type *valtype, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
if (valtype->code () == TYPE_CODE_STRUCT
|| valtype->code () == TYPE_CODE_UNION
|| valtype->code () == TYPE_CODE_ARRAY)
{
if (aarch64_return_in_memory (gdbarch, valtype))
{
aarch64_debug_printf ("return value in memory");
return RETURN_VALUE_STRUCT_CONVENTION;
}
}
if (writebuf)
aarch64_store_return_value (valtype, regcache, writebuf);
if (readbuf)
aarch64_extract_return_value (valtype, regcache, readbuf);
aarch64_debug_printf ("return value in registers");
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Implement the "get_longjmp_target" gdbarch method. */
static int
aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
{
CORE_ADDR jb_addr;
gdb_byte buf[X_REGISTER_SIZE];
struct gdbarch *gdbarch = get_frame_arch (frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM);
if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
X_REGISTER_SIZE))
return 0;
*pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order);
return 1;
}
/* Implement the "gen_return_address" gdbarch method. */
static void
aarch64_gen_return_address (struct gdbarch *gdbarch,
struct agent_expr *ax, struct axs_value *value,
CORE_ADDR scope)
{
value->type = register_type (gdbarch, AARCH64_LR_REGNUM);
value->kind = axs_lvalue_register;
value->u.reg = AARCH64_LR_REGNUM;
}
/* Return the pseudo register name corresponding to register regnum. */
static const char *
aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
static const char *const q_name[] =
{
"q0", "q1", "q2", "q3",
"q4", "q5", "q6", "q7",
"q8", "q9", "q10", "q11",
"q12", "q13", "q14", "q15",
"q16", "q17", "q18", "q19",
"q20", "q21", "q22", "q23",
"q24", "q25", "q26", "q27",
"q28", "q29", "q30", "q31",
};
static const char *const d_name[] =
{
"d0", "d1", "d2", "d3",
"d4", "d5", "d6", "d7",
"d8", "d9", "d10", "d11",
"d12", "d13", "d14", "d15",
"d16", "d17", "d18", "d19",
"d20", "d21", "d22", "d23",
"d24", "d25", "d26", "d27",
"d28", "d29", "d30", "d31",
};
static const char *const s_name[] =
{
"s0", "s1", "s2", "s3",
"s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11",
"s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19",
"s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27",
"s28", "s29", "s30", "s31",
};
static const char *const h_name[] =
{
"h0", "h1", "h2", "h3",
"h4", "h5", "h6", "h7",
"h8", "h9", "h10", "h11",
"h12", "h13", "h14", "h15",
"h16", "h17", "h18", "h19",
"h20", "h21", "h22", "h23",
"h24", "h25", "h26", "h27",
"h28", "h29", "h30", "h31",
};
static const char *const b_name[] =
{
"b0", "b1", "b2", "b3",
"b4", "b5", "b6", "b7",
"b8", "b9", "b10", "b11",
"b12", "b13", "b14", "b15",
"b16", "b17", "b18", "b19",
"b20", "b21", "b22", "b23",
"b24", "b25", "b26", "b27",
"b28", "b29", "b30", "b31",
};
int p_regnum = regnum - gdbarch_num_regs (gdbarch);
if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
return q_name[p_regnum - AARCH64_Q0_REGNUM];
if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
return d_name[p_regnum - AARCH64_D0_REGNUM];
if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
return s_name[p_regnum - AARCH64_S0_REGNUM];
if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
return h_name[p_regnum - AARCH64_H0_REGNUM];
if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
return b_name[p_regnum - AARCH64_B0_REGNUM];
if (tdep->has_sve ())
{
static const char *const sve_v_name[] =
{
"v0", "v1", "v2", "v3",
"v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11",
"v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19",
"v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27",
"v28", "v29", "v30", "v31",
};
if (p_regnum >= AARCH64_SVE_V0_REGNUM
&& p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM];
}
/* RA_STATE is used for unwinding only. Do not assign it a name - this
prevents it from being read by methods such as
mi_cmd_trace_frame_collected. */
if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
return "";
internal_error (__FILE__, __LINE__,
_("aarch64_pseudo_register_name: bad register number %d"),
p_regnum);
}
/* Implement the "pseudo_register_type" tdesc_arch_data method. */
static struct type *
aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int p_regnum = regnum - gdbarch_num_regs (gdbarch);
if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
return aarch64_vnq_type (gdbarch);
if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
return aarch64_vnd_type (gdbarch);
if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
return aarch64_vns_type (gdbarch);
if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
return aarch64_vnh_type (gdbarch);
if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
return aarch64_vnb_type (gdbarch);
if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
&& p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
return aarch64_vnv_type (gdbarch);
if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
return builtin_type (gdbarch)->builtin_uint64;
internal_error (__FILE__, __LINE__,
_("aarch64_pseudo_register_type: bad register number %d"),
p_regnum);
}
/* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
static int
aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int p_regnum = regnum - gdbarch_num_regs (gdbarch);
if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32)
return group == all_reggroup || group == vector_reggroup;
else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32)
return (group == all_reggroup || group == vector_reggroup
|| group == float_reggroup);
else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32)
return (group == all_reggroup || group == vector_reggroup
|| group == float_reggroup);
else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32)
return group == all_reggroup || group == vector_reggroup;
else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32)
return group == all_reggroup || group == vector_reggroup;
else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM
&& p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM)
return group == all_reggroup || group == vector_reggroup;
/* RA_STATE is used for unwinding only. Do not assign it to any groups. */
if (tdep->has_pauth () && regnum == tdep->pauth_ra_state_regnum)
return 0;
return group == all_reggroup;
}
/* Helper for aarch64_pseudo_read_value. */
static struct value *
aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch,
readable_regcache *regcache, int regnum_offset,
int regsize, struct value *result_value)
{
unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
/* Enough space for a full vector register. */
gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID)
mark_value_bytes_unavailable (result_value, 0,
TYPE_LENGTH (value_type (result_value)));
else
memcpy (value_contents_raw (result_value), reg_buf, regsize);
return result_value;
}
/* Implement the "pseudo_register_read_value" gdbarch method. */
static struct value *
aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache,
int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
struct value *result_value = allocate_value (register_type (gdbarch, regnum));
VALUE_LVAL (result_value) = lval_register;
VALUE_REGNUM (result_value) = regnum;
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_Q0_REGNUM,
Q_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_D0_REGNUM,
D_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_S0_REGNUM,
S_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_H0_REGNUM,
H_REGISTER_SIZE, result_value);
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_B0_REGNUM,
B_REGISTER_SIZE, result_value);
if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
&& regnum < AARCH64_SVE_V0_REGNUM + 32)
return aarch64_pseudo_read_value_1 (gdbarch, regcache,
regnum - AARCH64_SVE_V0_REGNUM,
V_REGISTER_SIZE, result_value);
gdb_assert_not_reached ("regnum out of bound");
}
/* Helper for aarch64_pseudo_write. */
static void
aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum_offset, int regsize, const gdb_byte *buf)
{
unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset;
/* Enough space for a full vector register. */
gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)];
gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM);
/* Ensure the register buffer is zero, we want gdb writes of the
various 'scalar' pseudo registers to behavior like architectural
writes, register width bytes are written the remainder are set to
zero. */
memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM));
memcpy (reg_buf, buf, regsize);
regcache->raw_write (v_regnum, reg_buf);
}
/* Implement the "pseudo_register_write" gdbarch method. */
static void
aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
regnum -= gdbarch_num_regs (gdbarch);
if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE,
buf);
if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE,
buf);
if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE,
buf);
if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE,
buf);
if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE,
buf);
if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM
&& regnum < AARCH64_SVE_V0_REGNUM + 32)
return aarch64_pseudo_write_1 (gdbarch, regcache,
regnum - AARCH64_SVE_V0_REGNUM,
V_REGISTER_SIZE, buf);
gdb_assert_not_reached ("regnum out of bound");
}
/* Callback function for user_reg_add. */
static struct value *
value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
{
const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
}
/* Implement the "software_single_step" gdbarch method, needed to
single step through atomic sequences on AArch64. */
static std::vector<CORE_ADDR>
aarch64_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
const int insn_size = 4;
const int atomic_sequence_length = 16; /* Instruction sequence length. */
CORE_ADDR pc = regcache_read_pc (regcache);
CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX };
CORE_ADDR loc = pc;
CORE_ADDR closing_insn = 0;
uint32_t insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code);
int index;
int insn_count;
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return {};
/* Look for a Load Exclusive instruction which begins the sequence. */
if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
return {};
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
loc += insn_size;
insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0)
return {};
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
if (bc_insn_count >= 1)
return {};
/* It is, so we'll try to set a breakpoint at the destination. */
breaks[1] = loc + inst.operands[0].imm.value;
bc_insn_count++;
last_breakpoint++;
}
/* Look for the Store Exclusive which closes the atomic sequence. */
if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
{
closing_insn = loc;
break;
}
}
/* We didn't find a closing Store Exclusive instruction, fall back. */
if (!closing_insn)
return {};
/* Insert breakpoint after the end of the atomic sequence. */
breaks[0] = loc + insn_size;
/* Check for duplicated breakpoints, and also check that the second
breakpoint is not within the atomic sequence. */
if (last_breakpoint
&& (breaks[1] == breaks[0]
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
std::vector<CORE_ADDR> next_pcs;
/* Insert the breakpoint at the end of the sequence, and one at the
destination of the conditional branch, if it exists. */
for (index = 0; index <= last_breakpoint; index++)
next_pcs.push_back (breaks[index]);
return next_pcs;
}
struct aarch64_displaced_step_copy_insn_closure
: public displaced_step_copy_insn_closure
{
/* It is true when condition instruction, such as B.CON, TBZ, etc,
is being displaced stepping. */
bool cond = false;
/* PC adjustment offset after displaced stepping. If 0, then we don't
write the PC back, assuming the PC is already the right address. */
int32_t pc_adjust = 0;
};
/* Data when visiting instructions for displaced stepping. */
struct aarch64_displaced_step_data
{
struct aarch64_insn_data base;
/* The address where the instruction will be executed at. */
CORE_ADDR new_addr;
/* Buffer of instructions to be copied to NEW_ADDR to execute. */
uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
/* Number of instructions in INSN_BUF. */
unsigned insn_count;
/* Registers when doing displaced stepping. */
struct regcache *regs;
aarch64_displaced_step_copy_insn_closure *dsc;
};
/* Implementation of aarch64_insn_visitor method "b". */
static void
aarch64_displaced_step_b (const int is_bl, const int32_t offset,
struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
int64_t new_offset = data->insn_addr - dsd->new_addr + offset;
if (can_encode_int32 (new_offset, 28))
{
/* Emit B rather than BL, because executing BL on a new address
will get the wrong address into LR. In order to avoid this,
we emit B, and update LR if the instruction is BL. */
emit_b (dsd->insn_buf, 0, new_offset);
dsd->insn_count++;
}
else
{
/* Write NOP. */
emit_nop (dsd->insn_buf);
dsd->insn_count++;
dsd->dsc->pc_adjust = offset;
}
if (is_bl)
{
/* Update LR. */
regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
data->insn_addr + 4);
}
}
/* Implementation of aarch64_insn_visitor method "b_cond". */
static void
aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
/* GDB has to fix up PC after displaced step this instruction
differently according to the condition is true or false. Instead
of checking COND against conditional flags, we can use
the following instructions, and GDB can tell how to fix up PC
according to the PC value.
B.COND TAKEN ; If cond is true, then jump to TAKEN.
INSN1 ;
TAKEN:
INSN2
*/
emit_bcond (dsd->insn_buf, cond, 8);
dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
dsd->insn_count = 1;
}
/* Dynamically allocate a new register. If we know the register
statically, we should make it a global as above instead of using this
helper function. */
static struct aarch64_register
aarch64_register (unsigned num, int is64)
{
return (struct aarch64_register) { num, is64 };
}
/* Implementation of aarch64_insn_visitor method "cb". */
static void
aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
const unsigned rn, int is64,
struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
/* The offset is out of range for a compare and branch
instruction. We can use the following instructions instead:
CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
INSN1 ;
TAKEN:
INSN2
*/
emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
dsd->insn_count = 1;
dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
}
/* Implementation of aarch64_insn_visitor method "tb". */
static void
aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
const unsigned rt, unsigned bit,
struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
/* The offset is out of range for a test bit and branch
instruction We can use the following instructions instead:
TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
INSN1 ;
TAKEN:
INSN2
*/
emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
dsd->insn_count = 1;
dsd->dsc->cond = true;
dsd->dsc->pc_adjust = offset;
}
/* Implementation of aarch64_insn_visitor method "adr". */
static void
aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
const int is_adrp, struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
/* We know exactly the address the ADR{P,} instruction will compute.
We can just write it to the destination register. */
CORE_ADDR address = data->insn_addr + offset;
if (is_adrp)
{
/* Clear the lower 12 bits of the offset to get the 4K page. */
regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
address & ~0xfff);
}
else
regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
address);
dsd->dsc->pc_adjust = 4;
emit_nop (dsd->insn_buf);
dsd->insn_count = 1;
}
/* Implementation of aarch64_insn_visitor method "ldr_literal". */
static void
aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
const unsigned rt, const int is64,
struct aarch64_insn_data *data)
{
struct aarch64_displaced_step_data *dsd
= (struct aarch64_displaced_step_data *) data;
CORE_ADDR address = data->insn_addr + offset;
struct aarch64_memory_operand zero =