blob: 446b2bdd39aa182e57f64bd02f58ab66b4c865a6 [file] [log] [blame]
# Copyright 2021 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <>.
# Test to see if gdb is properly single stepping over the
# displaced plxv instruction.
if { ![istarget powerpc*-*] || [skip_power_isa_3_1_tests] } {
verbose "Skipping powerpc ISA 3.1 plxv test."
set retval 0
standard_testfile .s
if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \
{debug quiet}] } {
return -1
gdb_test "set radix 0b10000"
gdb_test "set debug displaced"
if ![runto_main] then {
gdb_test "set debug displaced on"
# Proc to extract the uint128 hex value from the output of
# a print vector statement.
proc get_vector_hexadecimal_valueof { exp default {test ""} } {
set val "0x0000"
global gdb_prompt
if {$test == ""} {
set test "get vector_hexadecimal valueof \"${exp}\""
gdb_test_multiple "print $${exp}.uint128" $test {
-re -wrap "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" {
set val $expect_out(1,string)
pass "$test"
-re -wrap ".*Illegal instruction.* $" {
fail "Illegal instruction on print."
set val 0xffff
return ${val}
# Proc to do a single-step, and ensure we gently handle
# an illegal instruction situation.
proc stepi_over_instruction { xyz } {
global gdb_prompt
gdb_test_multiple "stepi" "${xyz} " {
-re -wrap ".*Illegal instruction.*" {
fail "Illegal instruction on single step."
-re -wrap ".*" {
pass "stepi ${xyz}"
set check_pc [get_hexadecimal_valueof "\$pc" "default0"]
# set some breakpoints on the instructions below main().
gdb_test "disas /r main"
set bp1 *$check_pc+4
set bp2 *$check_pc+0d12
set bp3 *$check_pc+0d20
set bp4 *$check_pc+0d28
gdb_breakpoint $bp1
gdb_breakpoint $bp2
gdb_breakpoint $bp3
gdb_breakpoint $bp4
# single-step through the plxv instructions, and retrieve the
# register values as we proceed.
stepi_over_instruction "stepi over NOP"
stepi_over_instruction "stepi over lnia"
stepi_over_instruction "stepi over addi"
stepi_over_instruction "stepi over vs4 assignment"
set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"]
stepi_over_instruction "stepi over vs5 assignment"
set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"]
stepi_over_instruction "stepi over vs6 assignment"
set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"]
stepi_over_instruction "stepi over vs7 assignment"
set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"]
set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2
set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4
set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6
set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8
if [expr $check_vs4 != $vs4_expected] {
fail "unexpected value vs4; actual:$check_vs4 expected:$vs4_expected"
if [expr $check_vs5 != $vs5_expected ] {
fail "unexpected value vs5; actual:$check_vs5 expected:$vs5_expected"
if [expr $check_vs6 != $vs6_expected ] {
fail "unexpected value vs6; actual:$check_vs6 expected:$vs6_expected"
if [expr $check_vs7 != $vs7_expected ] {
fail "unexpected value vs7; actual:$check_vs7 expected:$vs7_expected"
gdb_test "info break"
gdb_test "info register vs4 vs5 vs6 vs7 "
gdb_test "disas main #2"