| [^:]*: Assembler messages: |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:13: Error: bad type in SIMD instruction -- `vaddv.i32 r0,q0' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vaddv.f32 r0,q0' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vaddv.s64 r0,q0' |
| [^:]*:16: Error: bad type in SIMD instruction -- `vaddv.u64 r0,q0' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vaddva.i32 r0,q0' |
| [^:]*:18: Error: bad type in SIMD instruction -- `vaddva.f32 r0,q0' |
| [^:]*:19: Error: bad type in SIMD instruction -- `vaddva.s64 r0,q0' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vaddva.u64 r0,q0' |
| [^:]*:21: Error: Odd register not allowed here -- `vaddv.s32 r1,q0' |
| [^:]*:23: Error: syntax error -- `vaddveq.s32 r0,q0' |
| [^:]*:24: Error: syntax error -- `vaddveq.s32 r0,q0' |
| [^:]*:26: Error: syntax error -- `vaddveq.s32 r0,q0' |
| [^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvt.s32 r0,q0' |
| [^:]*:29: Error: instruction missing MVE vector predication code -- `vaddv.s32 r0,q0' |
| [^:]*:31: Error: syntax error -- `vaddvaeq.s32 r0,q0' |
| [^:]*:32: Error: syntax error -- `vaddvaeq.s32 r0,q0' |
| [^:]*:34: Error: syntax error -- `vaddvaeq.s32 r0,q0' |
| [^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvat.s32 r0,q0' |
| [^:]*:37: Error: instruction missing MVE vector predication code -- `vaddva.s32 r0,q0' |
