| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad element type for instruction -- `vldrb.16 q0,\[r0,q1\]' |
| [^:]*:11: Error: bad element type for instruction -- `vldrb.p16 q0,\[r0,q1\]' |
| [^:]*:12: Error: bad element type for instruction -- `vldrb.f16 q0,\[r0,q1\]' |
| [^:]*:13: Error: bad element type for instruction -- `vldrb.32 q0,\[r0,q1\]' |
| [^:]*:14: Error: bad element type for instruction -- `vldrb.f32 q0,\[r0,q1\]' |
| [^:]*:15: Error: bad element type for instruction -- `vldrb.64 q0,\[r0,q1\]' |
| [^:]*:16: Error: bad element type for instruction -- `vldrb.u64 q0,\[r0,q1\]' |
| [^:]*:17: Error: bad element type for instruction -- `vldrb.s64 q0,\[r0,q1\]' |
| [^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:19: Error: destination register and offset register may not be the same -- `vldrb.u32 q0,\[r0,q0\]' |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]' |
| [^:]*:23: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]' |
| [^:]*:25: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]' |
| [^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vldrbt.u32 q0,\[r0,q1\]' |
| [^:]*:28: Error: instruction missing MVE vector predication code -- `vldrb.u32 q0,\[r0,q1\]' |
| [^:]*:30: Error: bad element type for instruction -- `vldrh.32 q0,\[r0,q1\]' |
| [^:]*:31: Error: bad element type for instruction -- `vldrh.f32 q0,\[r0,q1\]' |
| [^:]*:32: Error: bad element type for instruction -- `vldrh.64 q0,\[r0,q1\]' |
| [^:]*:33: Error: bad element type for instruction -- `vldrh.u64 q0,\[r0,q1\]' |
| [^:]*:34: Error: bad element type for instruction -- `vldrh.s64 q0,\[r0,q1\]' |
| [^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:36: Error: destination register and offset register may not be the same -- `vldrh.u32 q0,\[r0,q0\]' |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]' |
| [^:]*:40: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]' |
| [^:]*:42: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]' |
| [^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vldrht.u32 q0,\[r0,q1\]' |
| [^:]*:45: Error: instruction missing MVE vector predication code -- `vldrh.u32 q0,\[r0,q1\]' |
| [^:]*:47: Error: bad element type for instruction -- `vldrw.64 q0,\[r0,q1\]' |
| [^:]*:48: Error: bad element type for instruction -- `vldrw.u64 q0,\[r0,q1\]' |
| [^:]*:49: Error: bad element type for instruction -- `vldrw.s64 q0,\[r0,q1\]' |
| [^:]*:50: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:51: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[r0,q0\]' |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:54: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]' |
| [^:]*:55: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]' |
| [^:]*:57: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]' |
| [^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[r0,q1\]' |
| [^:]*:60: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[r0,q1\]' |
| [^:]*:69: Error: bad element type for instruction -- `vldrd.8 q0,\[r0,q1\]' |
| [^:]*:70: Error: bad element type for instruction -- `vldrd.u8 q0,\[r0,q1\]' |
| [^:]*:71: Error: bad element type for instruction -- `vldrd.s8 q0,\[r0,q1\]' |
| [^:]*:72: Error: bad element type for instruction -- `vldrd.p8 q0,\[r0,q1\]' |
| [^:]*:73: Error: bad element type for instruction -- `vldrd.16 q0,\[r0,q1\]' |
| [^:]*:74: Error: bad element type for instruction -- `vldrd.u16 q0,\[r0,q1\]' |
| [^:]*:75: Error: bad element type for instruction -- `vldrd.s16 q0,\[r0,q1\]' |
| [^:]*:76: Error: bad element type for instruction -- `vldrd.p16 q0,\[r0,q1\]' |
| [^:]*:77: Error: bad element type for instruction -- `vldrd.f16 q0,\[r0,q1\]' |
| [^:]*:78: Error: bad element type for instruction -- `vldrd.32 q0,\[r0,q1\]' |
| [^:]*:79: Error: bad element type for instruction -- `vldrd.u32 q0,\[r0,q1\]' |
| [^:]*:80: Error: bad element type for instruction -- `vldrd.s32 q0,\[r0,q1\]' |
| [^:]*:81: Error: bad element type for instruction -- `vldrd.f32 q0,\[r0,q1\]' |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:84: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]' |
| [^:]*:85: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]' |
| [^:]*:87: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]' |
| [^:]*:88: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[r0,q1\]' |
| [^:]*:90: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[r0,q1\]' |
| [^:]*:92: Error: shift expression expected -- `vldrb.u8 q0,\[r0,q1,#0\]' |
| [^:]*:93: Error: can not shift offsets when accessing less than half-word -- `vldrb.u8 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:94: Error: can not shift offsets when accessing less than half-word -- `vldrb.u16 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:95: Error: can not shift offsets when accessing less than half-word -- `vldrb.u32 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:96: Error: shift expression expected -- `vldrh.u16 q0,\[r0,q1,#1\]' |
| [^:]*:97: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#2\]' |
| [^:]*:98: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#2\]' |
| [^:]*:99: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#3\]' |
| [^:]*:100: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#3\]' |
| [^:]*:101: Error: shift expression expected -- `vldrw.u32 q0,\[r0,q1,#2\]' |
| [^:]*:102: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:103: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#3\]' |
| [^:]*:104: Error: shift expression expected -- `vldrd.u64 q0,\[r0,q1,#3\]' |
| [^:]*:105: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:106: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#2\]' |
| [^:]*:107: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#4\]' |
| |
| |
