| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad element type for instruction -- `vldrw.u16 q0,\[q1,#4\]' |
| [^:]*:11: Error: bad element type for instruction -- `vldrw.u64 q0,\[q1,#-4\]' |
| [^:]*:12: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#1\]' |
| [^:]*:13: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#2\]' |
| [^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#231\]' |
| [^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#516\]' |
| [^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#-516\]' |
| [^:]*:17: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[q0,#4\]' |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Error: syntax error -- `vldrweq.u32 q0,\[q1\]' |
| [^:]*:21: Error: syntax error -- `vldrweq.u32 q0,\[q1\]' |
| [^:]*:23: Error: syntax error -- `vldrweq.u32 q0,\[q1\]' |
| [^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[q1\]' |
| [^:]*:26: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[q1\]' |
| [^:]*:27: Error: bad element type for instruction -- `vldrd.u16 q0,\[q1,#8\]' |
| [^:]*:28: Error: bad element type for instruction -- `vldrd.u32 q0,\[q1,#-8\]' |
| [^:]*:29: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1\]' |
| [^:]*:30: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#4\]' |
| [^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#7\]' |
| [^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#228\]' |
| [^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1024\]' |
| [^:]*:34: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#-1024\]' |
| [^:]*:35: Error: destination register and offset register may not be the same -- `vldrd.u64 q0,\[q0,#8\]' |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:38: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]' |
| [^:]*:39: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]' |
| [^:]*:41: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]' |
| [^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[q1\]' |
| [^:]*:44: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[q1\]' |
| |
