gas/testsuite/gas/arm/mve-vmlaldav-bad.l

[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:15: Error: bad type in SIMD instruction -- `vmlaldav.s64 r0,r1,q1,q2'
[^:]*:16: Error: bad type in SIMD instruction -- `vmlaldav.f32 r0,r1,q1,q2'
[^:]*:17: Error: bad type in SIMD instruction -- `vmlaldav.s8 r0,r1,q1,q2'
[^:]*:18: Error: ARM register expected -- `vmlaldav.s16 r0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vmlaldava.s64 r0,r1,q1,q2'
[^:]*:20: Error: bad type in SIMD instruction -- `vmlaldava.f32 r0,r1,q1,q2'
[^:]*:21: Error: bad type in SIMD instruction -- `vmlaldava.s8 r0,r1,q1,q2'
[^:]*:22: Error: ARM register expected -- `vmlaldava.s16 r0,q1,q2'
[^:]*:23: Error: bad type in SIMD instruction -- `vmlaldavx.s64 r0,r1,q1,q2'
[^:]*:24: Error: bad type in SIMD instruction -- `vmlaldavx.f32 r0,r1,q1,q2'
[^:]*:25: Error: bad type in SIMD instruction -- `vmlaldavx.s8 r0,r1,q1,q2'
[^:]*:26: Error: ARM register expected -- `vmlaldavx.s16 r0,q1,q2'
[^:]*:27: Error: bad type in SIMD instruction -- `vmlaldavax.s64 r0,r1,q1,q2'
[^:]*:28: Error: bad type in SIMD instruction -- `vmlaldavax.f32 r0,r1,q1,q2'
[^:]*:29: Error: bad type in SIMD instruction -- `vmlaldavax.s8 r0,r1,q1,q2'
[^:]*:30: Error: ARM register expected -- `vmlaldavax.s16 r0,q1,q2'
[^:]*:32: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:33: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:34: Error: syntax error -- `vmlaldaveq.s16 r0,r1,q1,q2'
[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavt.s16 r0,r1,q1,q2'
[^:]*:37: Error: instruction missing MVE vector predication code -- `vmlaldav.s16 r0,r1,q1,q2'
[^:]*:39: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:40: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:41: Error: syntax error -- `vmlaldavaeq.s16 r0,r1,q1,q2'
[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavat.s16 r0,r1,q1,q2'
[^:]*:44: Error: instruction missing MVE vector predication code -- `vmlaldava.s16 r0,r1,q1,q2'
[^:]*:46: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:47: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:48: Error: syntax error -- `vmlaldavxeq.s16 r0,r1,q1,q2'
[^:]*:49: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavxt.s16 r0,r1,q1,q2'
[^:]*:51: Error: instruction missing MVE vector predication code -- `vmlaldavx.s16 r0,r1,q1,q2'
[^:]*:53: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:54: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:55: Error: syntax error -- `vmlaldavaxeq.s16 r0,r1,q1,q2'
[^:]*:56: Error: vector predicated instruction should be in VPT/VPST block -- `vmlaldavaxt.s16 r0,r1,q1,q2'
[^:]*:58: Error: instruction missing MVE vector predication code -- `vmlaldavax.s16 r0,r1,q1,q2'