| [^:]*: Assembler messages: |
| [^:]*:13: Error: bad type in SIMD instruction -- `vmullb.s64 q0,q1,q2' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vmullb.f16 q0,q1,q2' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vmullb.f32 q0,q1,q2' |
| [^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Error: bad type in SIMD instruction -- `vmullt.s64 q0,q1,q2' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vmullt.f16 q0,q1,q2' |
| [^:]*:21: Error: bad type in SIMD instruction -- `vmullt.f32 q0,q1,q2' |
| [^:]*:22: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:23: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:26: Error: syntax error -- `vmullbeq.s32 q0,q1,q2' |
| [^:]*:27: Error: syntax error -- `vmullbeq.s32 q0,q1,q2' |
| [^:]*:29: Error: syntax error -- `vmullbeq.s32 q0,q1,q2' |
| [^:]*:31: Error: instruction missing MVE vector predication code -- `vmullb.s32 q0,q1,q2' |
| [^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vmullbt.s32 q0,q1,q2' |
| [^:]*:34: Error: syntax error -- `vmullteq.s32 q0,q1,q2' |
| [^:]*:35: Error: syntax error -- `vmullteq.s32 q0,q1,q2' |
| [^:]*:37: Error: syntax error -- `vmullteq.s32 q0,q1,q2' |
| [^:]*:39: Error: instruction missing MVE vector predication code -- `vmullt.s32 q0,q1,q2' |
| [^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vmulltt.s32 q0,q1,q2' |
