| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vqdmulh.s64 q0,q1,q2' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vqdmulh.u8 q0,q1,q2' |
| [^:]*:12: Error: bad type in SIMD instruction -- `vqrdmulh.s64 q0,q1,q2' |
| [^:]*:13: Error: bad type in SIMD instruction -- `vqrdmulh.u8 q0,q1,q2' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vqdmulh.s64 q0,q1,r2' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vqdmulh.u8 q0,q1,r2' |
| [^:]*:16: Error: bad type in SIMD instruction -- `vqrdmulh.s64 q0,q1,r2' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vqrdmulh.u8 q0,q1,r2' |
| [^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:27: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2' |
| [^:]*:28: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2' |
| [^:]*:30: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2' |
| [^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulht.s8 q0,q1,q2' |
| [^:]*:33: Error: instruction missing MVE vector predication code -- `vqdmulh.s8 q0,q1,q2' |
| [^:]*:35: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2' |
| [^:]*:36: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2' |
| [^:]*:38: Error: syntax error -- `vqrdmulheq.s8 q0,q1,q2' |
| [^:]*:39: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmulht.s8 q0,q1,q2' |
| [^:]*:41: Error: instruction missing MVE vector predication code -- `vqrdmulh.s8 q0,q1,q2' |
| [^:]*:43: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2' |
| [^:]*:44: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2' |
| [^:]*:46: Error: syntax error -- `vqdmulheq.s8 q0,q1,r2' |
| [^:]*:47: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulht.s8 q0,q1,r2' |
| [^:]*:49: Error: instruction missing MVE vector predication code -- `vqdmulh.s8 q0,q1,r2' |
| [^:]*:51: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2' |
| [^:]*:52: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2' |
| [^:]*:54: Error: syntax error -- `vqrdmulheq.s8 q0,q1,r2' |
| [^:]*:55: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmulht.s8 q0,q1,r2' |
| [^:]*:57: Error: instruction missing MVE vector predication code -- `vqrdmulh.s8 q0,q1,r2' |