| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,q1,q2' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,q1,q2' |
| [^:]*:12: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,q1,q2' |
| [^:]*:13: Error: bad type in SIMD instruction -- `vqrshl.s64 q0,r2' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vqrshl.u64 q0,r2' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vqrshl.i32 q0,r2' |
| [^:]*:16: Error: invalid instruction shape -- `vqrshl.s32 q0,q1,r2' |
| [^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:18: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Error: syntax error -- `vqrshleq.s32 q0,q1,q2' |
| [^:]*:23: Error: syntax error -- `vqrshleq.s32 q0,q1,q2' |
| [^:]*:25: Error: syntax error -- `vqrshleq.s32 q0,q1,q2' |
| [^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,q1,q2' |
| [^:]*:28: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,q1,q2' |
| [^:]*:30: Error: syntax error -- `vqrshleq.s32 q0,r2' |
| [^:]*:31: Error: syntax error -- `vqrshleq.s32 q0,r2' |
| [^:]*:33: Error: syntax error -- `vqrshleq.s32 q0,r2' |
| [^:]*:34: Error: vector predicated instruction should be in VPT/VPST block -- `vqrshlt.s32 q0,r2' |
| [^:]*:36: Error: instruction missing MVE vector predication code -- `vqrshl.s32 q0,r2' |
