| [^:]*: Assembler messages: |
| [^:]*:10: Error: elements must be smaller than reversal region -- `vrev16.16 q0,q1' |
| [^:]*:11: Error: elements must be smaller than reversal region -- `vrev32.32 q0,q1' |
| [^:]*:12: Error: elements must be smaller than reversal region -- `vrev64.64 q0,q1' |
| [^:]*:13: Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:18: Error: syntax error -- `vrev16eq.8 q0,q1' |
| [^:]*:19: Error: syntax error -- `vrev16eq.8 q0,q1' |
| [^:]*:21: Error: syntax error -- `vrev16eq.8 q0,q1' |
| [^:]*:22: Error: vector predicated instruction should be in VPT/VPST block -- `vrev16t.8 q0,q1' |
| [^:]*:24: Error: instruction missing MVE vector predication code -- `vrev16.8 q0,q1' |
| [^:]*:26: Error: syntax error -- `vrev32eq.8 q0,q1' |
| [^:]*:27: Error: syntax error -- `vrev32eq.8 q0,q1' |
| [^:]*:29: Error: syntax error -- `vrev32eq.8 q0,q1' |
| [^:]*:30: Error: vector predicated instruction should be in VPT/VPST block -- `vrev32t.8 q0,q1' |
| [^:]*:32: Error: instruction missing MVE vector predication code -- `vrev32.8 q0,q1' |
| [^:]*:34: Error: syntax error -- `vrev64eq.8 q0,q1' |
| [^:]*:35: Error: syntax error -- `vrev64eq.8 q0,q1' |
| [^:]*:37: Error: syntax error -- `vrev64eq.8 q0,q1' |
| [^:]*:38: Error: vector predicated instruction should be in VPT/VPST block -- `vrev64t.8 q0,q1' |
| [^:]*:40: Error: instruction missing MVE vector predication code -- `vrev64.8 q0,q1' |
