| .syntax unified |
| .thumb |
| vst20.8 {q0, q2}, [r0] |
| vst20.8 {q0, q1, q2}, [r0] |
| vst20.8 {q0}, [r0] |
| vst20.8 {q0, q1}, [pc] |
| vst20.8 {q0, q1}, [pc]! |
| vst20.8 {q0, q1}, [sp]! |
| vst20.8 {q3, q2}, [r0] |
| vst20.64 {q0, q1}, [r0] |
| vst21.8 {q0, q2}, [r0] |
| vst21.8 {q0, q1, q2}, [r0] |
| vst21.8 {q0}, [r0] |
| vst21.8 {q0, q1}, [pc] |
| vst21.8 {q0, q1}, [pc]! |
| vst21.8 {q0, q1}, [sp]! |
| vst21.8 {q3, q2}, [r0] |
| vst21.64 {q0, q1}, [r0] |
| vst40.8 {q0, q2, q3, q4}, [r0] |
| vst40.8 {q0, q1, q3, q4}, [r0] |
| vst40.8 {q0, q1, q2, q4}, [r0] |
| vst40.8 {q3, q1, q2, q3}, [r0] |
| vst40.8 {q0, q1, q2, q3, q4}, [r0] |
| vst40.8 {q0, q1, q2}, [r0] |
| vst40.8 {q0, q1}, [r0] |
| vst40.8 {q0}, [r0] |
| vst40.8 {q0, q1, q2, q3}, [pc] |
| vst40.8 {q0, q1, q2, q3}, [pc]! |
| vst40.8 {q0, q1, q2, q3}, [sp]! |
| vst40.64 {q0, q1, q2, q3}, [r0] |
| vst41.8 {q0, q2, q3, q4}, [r0] |
| vst41.8 {q0, q1, q3, q4}, [r0] |
| vst41.8 {q0, q1, q2, q4}, [r0] |
| vst41.8 {q3, q1, q2, q3}, [r0] |
| vst41.8 {q0, q1, q2, q3, q4}, [r0] |
| vst41.8 {q0, q1, q2}, [r0] |
| vst41.8 {q0, q1}, [r0] |
| vst41.8 {q0}, [r0] |
| vst41.8 {q0, q1, q2, q3}, [pc] |
| vst41.8 {q0, q1, q2, q3}, [pc]! |
| vst41.8 {q0, q1, q2, q3}, [sp]! |
| vst41.64 {q0, q1, q2, q3}, [r0] |
| vst42.8 {q0, q2, q3, q4}, [r0] |
| vst42.8 {q0, q1, q3, q4}, [r0] |
| vst42.8 {q0, q1, q2, q4}, [r0] |
| vst42.8 {q3, q1, q2, q3}, [r0] |
| vst42.8 {q0, q1, q2, q3, q4}, [r0] |
| vst42.8 {q0, q1, q2}, [r0] |
| vst42.8 {q0, q1}, [r0] |
| vst42.8 {q0}, [r0] |
| vst42.8 {q0, q1, q2, q3}, [pc] |
| vst42.8 {q0, q1, q2, q3}, [pc]! |
| vst42.8 {q0, q1, q2, q3}, [sp]! |
| vst42.64 {q0, q1, q2, q3}, [r0] |
| vst43.8 {q0, q2, q3, q4}, [r0] |
| vst43.8 {q0, q1, q3, q4}, [r0] |
| vst43.8 {q0, q1, q2, q4}, [r0] |
| vst43.8 {q3, q1, q2, q3}, [r0] |
| vst43.8 {q0, q1, q2, q3, q4}, [r0] |
| vst43.8 {q0, q1, q2}, [r0] |
| vst43.8 {q0, q1}, [r0] |
| vst43.8 {q0}, [r0] |
| vst43.8 {q0, q1, q2, q3}, [pc] |
| vst43.8 {q0, q1, q2, q3}, [pc]! |
| vst43.8 {q0, q1, q2, q3}, [sp]! |
| vst43.64 {q0, q1, q2, q3}, [r0] |
| vst1.8 {q0, q1}, [r0] |
| vst2.8 {q0, q1}, [r0] |
| vst3.8 {q0, q1}, [r0] |
| vst4.8 {q0, q1}, [r0] |
| vst23.32 {q0, q1}, [r0] |
| vst44.32 {q0, q1, q2, q3}, [r0] |
| vld20.8 {q0, q2}, [r0] |
| vld20.8 {q0, q1, q2}, [r0] |
| vld20.8 {q0}, [r0] |
| vld20.8 {q0, q1}, [pc] |
| vld20.8 {q0, q1}, [pc]! |
| vld20.8 {q0, q1}, [sp]! |
| vld20.8 {q3, q2}, [r0] |
| vld20.64 {q0, q1}, [r0] |
| vld21.8 {q0, q2}, [r0] |
| vld21.8 {q0, q1, q2}, [r0] |
| vld21.8 {q0}, [r0] |
| vld21.8 {q0, q1}, [pc] |
| vld21.8 {q0, q1}, [pc]! |
| vld21.8 {q0, q1}, [sp]! |
| vld21.8 {q3, q2}, [r0] |
| vld21.64 {q0, q1}, [r0] |
| vld40.8 {q0, q2, q3, q4}, [r0] |
| vld40.8 {q0, q1, q3, q4}, [r0] |
| vld40.8 {q0, q1, q2, q4}, [r0] |
| vld40.8 {q3, q1, q2, q3}, [r0] |
| vld40.8 {q0, q1, q2, q3, q4}, [r0] |
| vld40.8 {q0, q1, q2}, [r0] |
| vld40.8 {q0, q1}, [r0] |
| vld40.8 {q0}, [r0] |
| vld40.8 {q0, q1, q2, q3}, [pc] |
| vld40.8 {q0, q1, q2, q3}, [pc]! |
| vld40.8 {q0, q1, q2, q3}, [sp]! |
| vld40.64 {q0, q1, q2, q3}, [r0] |
| vld41.8 {q0, q2, q3, q4}, [r0] |
| vld41.8 {q0, q1, q3, q4}, [r0] |
| vld41.8 {q0, q1, q2, q4}, [r0] |
| vld41.8 {q3, q1, q2, q3}, [r0] |
| vld41.8 {q0, q1, q2, q3, q4}, [r0] |
| vld41.8 {q0, q1, q2}, [r0] |
| vld41.8 {q0, q1}, [r0] |
| vld41.8 {q0}, [r0] |
| vld41.8 {q0, q1, q2, q3}, [pc] |
| vld41.8 {q0, q1, q2, q3}, [pc]! |
| vld41.8 {q0, q1, q2, q3}, [sp]! |
| vld41.64 {q0, q1, q2, q3}, [r0] |
| vld42.8 {q0, q2, q3, q4}, [r0] |
| vld42.8 {q0, q1, q3, q4}, [r0] |
| vld42.8 {q0, q1, q2, q4}, [r0] |
| vld42.8 {q3, q1, q2, q3}, [r0] |
| vld42.8 {q0, q1, q2, q3, q4}, [r0] |
| vld42.8 {q0, q1, q2}, [r0] |
| vld42.8 {q0, q1}, [r0] |
| vld42.8 {q0}, [r0] |
| vld42.8 {q0, q1, q2, q3}, [pc] |
| vld42.8 {q0, q1, q2, q3}, [pc]! |
| vld42.8 {q0, q1, q2, q3}, [sp]! |
| vld42.64 {q0, q1, q2, q3}, [r0] |
| vld43.8 {q0, q2, q3, q4}, [r0] |
| vld43.8 {q0, q1, q3, q4}, [r0] |
| vld43.8 {q0, q1, q2, q4}, [r0] |
| vld43.8 {q3, q1, q2, q3}, [r0] |
| vld43.8 {q0, q1, q2, q3, q4}, [r0] |
| vld43.8 {q0, q1, q2}, [r0] |
| vld43.8 {q0, q1}, [r0] |
| vld43.8 {q0}, [r0] |
| vld43.8 {q0, q1, q2, q3}, [pc] |
| vld43.8 {q0, q1, q2, q3}, [pc]! |
| vld43.8 {q0, q1, q2, q3}, [sp]! |
| vld43.64 {q0, q1, q2, q3}, [r0] |
| vld1.8 {q0, q1}, [r0] |
| vld2.8 {q0, q1}, [r0] |
| vld3.8 {q0, q1}, [r0] |
| vld4.8 {q0, q1}, [r0] |
| vld23.32 {q0, q1}, [r0] |
| vld44.32 {q0, q1, q2, q3}, [r0] |
| |
| .macro cond2 op |
| .irp cond, eq, ne, gt, ge, lt, le |
| it \cond |
| \op\().32 {q0, q1}, [r0] |
| .endr |
| .endm |
| |
| |
| |
| .macro cond4 op |
| .irp cond, eq, ne, gt, ge, lt, le |
| it \cond |
| \op\().32 {q0, q1, q2, q3}, [r0] |
| .endr |
| .endm |
| |
| cond2 vst20 |
| cond2 vst21 |
| cond4 vst40 |
| cond4 vst41 |
| cond4 vst42 |
| cond4 vst43 |
| vpste |
| vst20t.32 {q0, q1}, [r0] |
| vst20e.32 {q0, q1}, [r0] |
| vpste |
| vst21t.32 {q0, q1}, [r0] |
| vst21e.32 {q0, q1}, [r0] |
| vpste |
| vst40t.32 {q0, q1, q2, q3}, [r0] |
| vst40e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vst41t.32 {q0, q1, q2, q3}, [r0] |
| vst41e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vst42t.32 {q0, q1, q2, q3}, [r0] |
| vst42e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vst43t.32 {q0, q1, q2, q3}, [r0] |
| vst43e.32 {q0, q1, q2, q3}, [r0] |
| |
| vpst |
| vst20.32 {q0, q1}, [r0] |
| vpst |
| vst21.32 {q0, q1}, [r0] |
| vpst |
| vst40.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vst41.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vst42.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vst43.32 {q0, q1, q2, q3}, [r0] |
| |
| cond2 vld20 |
| cond2 vld21 |
| cond4 vld40 |
| cond4 vld41 |
| cond4 vld42 |
| cond4 vld43 |
| vpste |
| vld20t.32 {q0, q1}, [r0] |
| vld20e.32 {q0, q1}, [r0] |
| vpste |
| vld21t.32 {q0, q1}, [r0] |
| vld21e.32 {q0, q1}, [r0] |
| vpste |
| vld40t.32 {q0, q1, q2, q3}, [r0] |
| vld40e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vld41t.32 {q0, q1, q2, q3}, [r0] |
| vld41e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vld42t.32 {q0, q1, q2, q3}, [r0] |
| vld42e.32 {q0, q1, q2, q3}, [r0] |
| vpste |
| vld43t.32 {q0, q1, q2, q3}, [r0] |
| vld43e.32 {q0, q1, q2, q3}, [r0] |
| |
| vpst |
| vld20.32 {q0, q1}, [r0] |
| vpst |
| vld21.32 {q0, q1}, [r0] |
| vpst |
| vld40.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vld41.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vld42.32 {q0, q1, q2, q3}, [r0] |
| vpst |
| vld43.32 {q0, q1, q2, q3}, [r0] |
