| [^:]*: Assembler messages: |
| [^:]*:12: Error: bad element type for instruction -- `vstrb.s8 q0,\[r0,q1\]' |
| [^:]*:13: Error: bad element type for instruction -- `vstrb.u8 q0,\[r0,q1\]' |
| [^:]*:14: Error: bad element type for instruction -- `vstrb.s16 q0,\[r0,q1\]' |
| [^:]*:15: Error: bad element type for instruction -- `vstrb.u16 q0,\[r0,q1\]' |
| [^:]*:16: Error: bad element type for instruction -- `vstrb.f16 q0,\[r0,q1\]' |
| [^:]*:17: Error: bad element type for instruction -- `vstrb.u32 q0,\[r0,q1\]' |
| [^:]*:18: Error: bad element type for instruction -- `vstrb.s32 q0,\[r0,q1\]' |
| [^:]*:19: Error: bad element type for instruction -- `vstrb.f32 q0,\[r0,q1\]' |
| [^:]*:20: Error: bad element type for instruction -- `vstrb.64 q0,\[r0,q1\]' |
| [^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:25: Error: bad element type for instruction -- `vstrh.8 q0,\[r0,q1\]' |
| [^:]*:26: Error: bad element type for instruction -- `vstrh.s8 q0,\[r0,q1\]' |
| [^:]*:27: Error: bad element type for instruction -- `vstrh.u8 q0,\[r0,q1\]' |
| [^:]*:28: Error: bad element type for instruction -- `vstrh.s16 q0,\[r0,q1\]' |
| [^:]*:29: Error: bad element type for instruction -- `vstrh.u16 q0,\[r0,q1\]' |
| [^:]*:30: Error: bad element type for instruction -- `vstrh.f16 q0,\[r0,q1\]' |
| [^:]*:31: Error: bad element type for instruction -- `vstrh.u32 q0,\[r0,q1\]' |
| [^:]*:32: Error: bad element type for instruction -- `vstrh.s32 q0,\[r0,q1\]' |
| [^:]*:33: Error: bad element type for instruction -- `vstrh.f32 q0,\[r0,q1\]' |
| [^:]*:34: Error: bad element type for instruction -- `vstrh.64 q0,\[r0,q1\]' |
| [^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:39: Error: shift expression expected -- `vstrh.16 q0,\[r0,q1,#1\]' |
| [^:]*:40: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrh.16 q0,\[r0,q1,UXTW#2\]' |
| [^:]*:41: Error: bad element type for instruction -- `vstrw.8 q0,\[r0,q1\]' |
| [^:]*:42: Error: bad element type for instruction -- `vstrw.u8 q0,\[r0,q1\]' |
| [^:]*:43: Error: bad element type for instruction -- `vstrw.s8 q0,\[r0,q1\]' |
| [^:]*:44: Error: bad element type for instruction -- `vstrw.16 q0,\[r0,q1\]' |
| [^:]*:45: Error: bad element type for instruction -- `vstrw.f16 q0,\[r0,q1\]' |
| [^:]*:46: Error: bad element type for instruction -- `vstrw.u16 q0,\[r0,q1\]' |
| [^:]*:47: Error: bad element type for instruction -- `vstrw.s16 q0,\[r0,q1\]' |
| [^:]*:48: Error: bad element type for instruction -- `vstrw.u32 q0,\[r0,q1\]' |
| [^:]*:49: Error: bad element type for instruction -- `vstrw.s32 q0,\[r0,q1\]' |
| [^:]*:50: Error: bad element type for instruction -- `vstrw.f32 q0,\[r0,q1\]' |
| [^:]*:51: Error: bad element type for instruction -- `vstrw.64 q0,\[r0,q1\]' |
| [^:]*:52: Warning: instruction is UNPREDICTABLE with PC operand |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:56: Error: shift expression expected -- `vstrw.32 q0,\[r0,q1,#2\]' |
| [^:]*:57: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:58: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#3\]' |
| [^:]*:59: Error: bad element type for instruction -- `vstrd.8 q0,\[r0,q1\]' |
| [^:]*:60: Error: bad element type for instruction -- `vstrd.u8 q0,\[r0,q1\]' |
| [^:]*:61: Error: bad element type for instruction -- `vstrd.s8 q0,\[r0,q1\]' |
| [^:]*:62: Error: bad element type for instruction -- `vstrd.16 q0,\[r0,q1\]' |
| [^:]*:63: Error: bad element type for instruction -- `vstrd.u16 q0,\[r0,q1\]' |
| [^:]*:64: Error: bad element type for instruction -- `vstrd.s16 q0,\[r0,q1\]' |
| [^:]*:65: Error: bad element type for instruction -- `vstrd.f16 q0,\[r0,q1\]' |
| [^:]*:66: Error: bad element type for instruction -- `vstrd.32 q0,\[r0,q1\]' |
| [^:]*:67: Error: bad element type for instruction -- `vstrd.u32 q0,\[r0,q1\]' |
| [^:]*:68: Error: bad element type for instruction -- `vstrd.s32 q0,\[r0,q1\]' |
| [^:]*:69: Error: bad element type for instruction -- `vstrd.f32 q0,\[r0,q1\]' |
| [^:]*:70: Error: bad element type for instruction -- `vstrd.f64 q0,\[r0,q1\]' |
| [^:]*:71: Error: bad element type for instruction -- `vstrd.u64 q0,\[r0,q1\]' |
| [^:]*:72: Error: bad element type for instruction -- `vstrd.s64 q0,\[r0,q1\]' |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:84: Error: shift expression expected -- `vstrd.64 q0,\[r0,q1,#3\]' |
| [^:]*:85: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#1\]' |
| [^:]*:86: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#2\]' |
| [^:]*:87: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#4\]' |
| [^:]*:90: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' |
| [^:]*:91: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' |
| [^:]*:93: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]' |
| [^:]*:95: Error: instruction missing MVE vector predication code -- `vstrb.32 q0,\[r0,q1\]' |
| [^:]*:96: Error: vector predicated instruction should be in VPT/VPST block -- `vstrbt.32 q0,\[r0,q1\]' |
| [^:]*:97: Error: vector predicated instruction should be in VPT/VPST block -- `vstrbe.32 q0,\[r0,q1\]' |
| [^:]*:99: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]' |
| [^:]*:100: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]' |
| [^:]*:102: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]' |
| [^:]*:104: Error: instruction missing MVE vector predication code -- `vstrh.32 q0,\[r0,q1\]' |
| [^:]*:105: Error: vector predicated instruction should be in VPT/VPST block -- `vstrht.32 q0,\[r0,q1\]' |
| [^:]*:106: Error: vector predicated instruction should be in VPT/VPST block -- `vstrhe.32 q0,\[r0,q1\]' |
| [^:]*:108: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]' |
| [^:]*:109: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]' |
| [^:]*:111: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]' |
| [^:]*:113: Error: instruction missing MVE vector predication code -- `vstrw.32 q0,\[r0,q1\]' |
| [^:]*:114: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwt.32 q0,\[r0,q1\]' |
| [^:]*:115: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwe.32 q0,\[r0,q1\]' |
| [^:]*:117: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]' |
| [^:]*:118: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]' |
| [^:]*:120: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]' |
| [^:]*:122: Error: instruction missing MVE vector predication code -- `vstrd.64 q0,\[r0,q1\]' |
| [^:]*:123: Error: vector predicated instruction should be in VPT/VPST block -- `vstrdt.64 q0,\[r0,q1\]' |
| [^:]*:124: Error: vector predicated instruction should be in VPT/VPST block -- `vstrde.64 q0,\[r0,q1\]' |