| /* Instruction printing code for the ARM |
| Copyright (C) 1994-2024 Free Software Foundation, Inc. |
| Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) |
| Modification by James G. Smith (jsmith@cygnus.co.uk) |
| |
| This file is part of libopcodes. |
| |
| This library is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3 of the License, or |
| (at your option) any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with this program; if not, write to the Free Software |
| Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| |
| #include "sysdep.h" |
| #include <assert.h> |
| |
| #include "disassemble.h" |
| #include "opcode/arm.h" |
| #include "opintl.h" |
| #include "safe-ctype.h" |
| #include "libiberty.h" |
| #include "floatformat.h" |
| |
| /* FIXME: This shouldn't be done here. */ |
| #include "coff/internal.h" |
| #include "libcoff.h" |
| #include "bfd.h" |
| #include "elf-bfd.h" |
| #include "elf/internal.h" |
| #include "elf/arm.h" |
| #include "mach-o.h" |
| |
| /* Cached mapping symbol state. */ |
| enum map_type |
| { |
| MAP_ARM, |
| MAP_THUMB, |
| MAP_DATA |
| }; |
| |
| struct arm_private_data |
| { |
| /* The features to use when disassembling optional instructions. */ |
| arm_feature_set features; |
| |
| /* Track the last type (although this doesn't seem to be useful) */ |
| enum map_type last_type; |
| |
| /* Tracking symbol table information */ |
| int last_mapping_sym; |
| |
| /* The end range of the current range being disassembled. */ |
| bfd_vma last_stop_offset; |
| bfd_vma last_mapping_addr; |
| }; |
| |
| enum mve_instructions |
| { |
| MVE_VPST, |
| MVE_VPT_FP_T1, |
| MVE_VPT_FP_T2, |
| MVE_VPT_VEC_T1, |
| MVE_VPT_VEC_T2, |
| MVE_VPT_VEC_T3, |
| MVE_VPT_VEC_T4, |
| MVE_VPT_VEC_T5, |
| MVE_VPT_VEC_T6, |
| MVE_VCMP_FP_T1, |
| MVE_VCMP_FP_T2, |
| MVE_VCMP_VEC_T1, |
| MVE_VCMP_VEC_T2, |
| MVE_VCMP_VEC_T3, |
| MVE_VCMP_VEC_T4, |
| MVE_VCMP_VEC_T5, |
| MVE_VCMP_VEC_T6, |
| MVE_VDUP, |
| MVE_VEOR, |
| MVE_VFMAS_FP_SCALAR, |
| MVE_VFMA_FP_SCALAR, |
| MVE_VFMA_FP, |
| MVE_VFMS_FP, |
| MVE_VHADD_T1, |
| MVE_VHADD_T2, |
| MVE_VHSUB_T1, |
| MVE_VHSUB_T2, |
| MVE_VRHADD, |
| MVE_VLD2, |
| MVE_VLD4, |
| MVE_VST2, |
| MVE_VST4, |
| MVE_VLDRB_T1, |
| MVE_VLDRH_T2, |
| MVE_VLDRB_T5, |
| MVE_VLDRH_T6, |
| MVE_VLDRW_T7, |
| MVE_VSTRB_T1, |
| MVE_VSTRH_T2, |
| MVE_VSTRB_T5, |
| MVE_VSTRH_T6, |
| MVE_VSTRW_T7, |
| MVE_VLDRB_GATHER_T1, |
| MVE_VLDRH_GATHER_T2, |
| MVE_VLDRW_GATHER_T3, |
| MVE_VLDRD_GATHER_T4, |
| MVE_VLDRW_GATHER_T5, |
| MVE_VLDRD_GATHER_T6, |
| MVE_VSTRB_SCATTER_T1, |
| MVE_VSTRH_SCATTER_T2, |
| MVE_VSTRW_SCATTER_T3, |
| MVE_VSTRD_SCATTER_T4, |
| MVE_VSTRW_SCATTER_T5, |
| MVE_VSTRD_SCATTER_T6, |
| MVE_VCVT_FP_FIX_VEC, |
| MVE_VCVT_BETWEEN_FP_INT, |
| MVE_VCVT_FP_HALF_FP, |
| MVE_VCVT_FROM_FP_TO_INT, |
| MVE_VRINT_FP, |
| MVE_VMOV_HFP_TO_GP, |
| MVE_VMOV_GP_TO_VEC_LANE, |
| MVE_VMOV_IMM_TO_VEC, |
| MVE_VMOV_VEC_TO_VEC, |
| MVE_VMOV2_VEC_LANE_TO_GP, |
| MVE_VMOV2_GP_TO_VEC_LANE, |
| MVE_VMOV_VEC_LANE_TO_GP, |
| MVE_VMVN_IMM, |
| MVE_VMVN_REG, |
| MVE_VORR_IMM, |
| MVE_VORR_REG, |
| MVE_VORN, |
| MVE_VBIC_IMM, |
| MVE_VBIC_REG, |
| MVE_VMOVX, |
| MVE_VMOVL, |
| MVE_VMOVN, |
| MVE_VMULL_INT, |
| MVE_VMULL_POLY, |
| MVE_VQDMULL_T1, |
| MVE_VQDMULL_T2, |
| MVE_VQMOVN, |
| MVE_VQMOVUN, |
| MVE_VADDV, |
| MVE_VMLADAV_T1, |
| MVE_VMLADAV_T2, |
| MVE_VMLALDAV, |
| MVE_VMLAS, |
| MVE_VADDLV, |
| MVE_VMLSDAV_T1, |
| MVE_VMLSDAV_T2, |
| MVE_VMLSLDAV, |
| MVE_VRMLALDAVH, |
| MVE_VRMLSLDAVH, |
| MVE_VQDMLADH, |
| MVE_VQRDMLADH, |
| MVE_VQDMLAH, |
| MVE_VQRDMLAH, |
| MVE_VQDMLASH, |
| MVE_VQRDMLASH, |
| MVE_VQDMLSDH, |
| MVE_VQRDMLSDH, |
| MVE_VQDMULH_T1, |
| MVE_VQRDMULH_T2, |
| MVE_VQDMULH_T3, |
| MVE_VQRDMULH_T4, |
| MVE_VDDUP, |
| MVE_VDWDUP, |
| MVE_VIWDUP, |
| MVE_VIDUP, |
| MVE_VCADD_FP, |
| MVE_VCADD_VEC, |
| MVE_VHCADD, |
| MVE_VCMLA_FP, |
| MVE_VCMUL_FP, |
| MVE_VQRSHL_T1, |
| MVE_VQRSHL_T2, |
| MVE_VQRSHRN, |
| MVE_VQRSHRUN, |
| MVE_VQSHL_T1, |
| MVE_VQSHL_T2, |
| MVE_VQSHLU_T3, |
| MVE_VQSHL_T4, |
| MVE_VQSHRN, |
| MVE_VQSHRUN, |
| MVE_VRSHL_T1, |
| MVE_VRSHL_T2, |
| MVE_VRSHR, |
| MVE_VRSHRN, |
| MVE_VSHL_T1, |
| MVE_VSHL_T2, |
| MVE_VSHL_T3, |
| MVE_VSHLC, |
| MVE_VSHLL_T1, |
| MVE_VSHLL_T2, |
| MVE_VSHR, |
| MVE_VSHRN, |
| MVE_VSLI, |
| MVE_VSRI, |
| MVE_VADC, |
| MVE_VABAV, |
| MVE_VABD_FP, |
| MVE_VABD_VEC, |
| MVE_VABS_FP, |
| MVE_VABS_VEC, |
| MVE_VADD_FP_T1, |
| MVE_VADD_FP_T2, |
| MVE_VADD_VEC_T1, |
| MVE_VADD_VEC_T2, |
| MVE_VSBC, |
| MVE_VSUB_FP_T1, |
| MVE_VSUB_FP_T2, |
| MVE_VSUB_VEC_T1, |
| MVE_VSUB_VEC_T2, |
| MVE_VAND, |
| MVE_VBRSR, |
| MVE_VCLS, |
| MVE_VCLZ, |
| MVE_VCTP, |
| MVE_VMAX, |
| MVE_VMAXA, |
| MVE_VMAXNM_FP, |
| MVE_VMAXNMA_FP, |
| MVE_VMAXNMV_FP, |
| MVE_VMAXNMAV_FP, |
| MVE_VMAXV, |
| MVE_VMAXAV, |
| MVE_VMIN, |
| MVE_VMINA, |
| MVE_VMINNM_FP, |
| MVE_VMINNMA_FP, |
| MVE_VMINNMV_FP, |
| MVE_VMINNMAV_FP, |
| MVE_VMINV, |
| MVE_VMINAV, |
| MVE_VMLA, |
| MVE_VMUL_FP_T1, |
| MVE_VMUL_FP_T2, |
| MVE_VMUL_VEC_T1, |
| MVE_VMUL_VEC_T2, |
| MVE_VMULH, |
| MVE_VRMULH, |
| MVE_VNEG_FP, |
| MVE_VNEG_VEC, |
| MVE_VPNOT, |
| MVE_VPSEL, |
| MVE_VQABS, |
| MVE_VQADD_T1, |
| MVE_VQADD_T2, |
| MVE_VQSUB_T1, |
| MVE_VQSUB_T2, |
| MVE_VQNEG, |
| MVE_VREV16, |
| MVE_VREV32, |
| MVE_VREV64, |
| MVE_LSLL, |
| MVE_LSLLI, |
| MVE_LSRL, |
| MVE_ASRL, |
| MVE_ASRLI, |
| MVE_SQRSHRL, |
| MVE_SQRSHR, |
| MVE_UQRSHL, |
| MVE_UQRSHLL, |
| MVE_UQSHL, |
| MVE_UQSHLL, |
| MVE_URSHRL, |
| MVE_URSHR, |
| MVE_SRSHRL, |
| MVE_SRSHR, |
| MVE_SQSHLL, |
| MVE_SQSHL, |
| MVE_CINC, |
| MVE_CINV, |
| MVE_CNEG, |
| MVE_CSINC, |
| MVE_CSINV, |
| MVE_CSET, |
| MVE_CSETM, |
| MVE_CSNEG, |
| MVE_CSEL, |
| MVE_NONE |
| }; |
| |
| enum mve_unpredictable |
| { |
| UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block. |
| */ |
| UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and |
| fcB = 1 (vpt). */ |
| UNPRED_R13, /* Unpredictable because r13 (sp) or |
| r15 (sp) used. */ |
| UNPRED_R15, /* Unpredictable because r15 (pc) is used. */ |
| UNPRED_Q_GT_4, /* Unpredictable because |
| vec reg start > 4 (vld4/st4). */ |
| UNPRED_Q_GT_6, /* Unpredictable because |
| vec reg start > 6 (vld2/st2). */ |
| UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13 |
| and WB bit = 1. */ |
| UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are |
| equal. */ |
| UNPRED_OS, /* Unpredictable because offset scaled == 1. */ |
| UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the |
| same. */ |
| UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and |
| size = 1. */ |
| UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and |
| size = 2. */ |
| UNPRED_NONE /* No unpredictable behavior. */ |
| }; |
| |
| enum mve_undefined |
| { |
| UNDEF_SIZE, /* undefined size. */ |
| UNDEF_SIZE_0, /* undefined because size == 0. */ |
| UNDEF_SIZE_2, /* undefined because size == 2. */ |
| UNDEF_SIZE_3, /* undefined because size == 3. */ |
| UNDEF_SIZE_LE_1, /* undefined because size <= 1. */ |
| UNDEF_SIZE_NOT_0, /* undefined because size != 0. */ |
| UNDEF_SIZE_NOT_2, /* undefined because size != 2. */ |
| UNDEF_SIZE_NOT_3, /* undefined because size != 3. */ |
| UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and |
| size == 0. */ |
| UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and |
| size == 1. */ |
| UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */ |
| UNDEF_VCVT_IMM6, /* imm6 < 32. */ |
| UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */ |
| UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and |
| op1 == (0 or 1). */ |
| UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and |
| op2 == 0 and op1 == (0 or 1). */ |
| UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode |
| in {0xx1, x0x1}. */ |
| UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */ |
| UNDEF_NONE /* no undefined behavior. */ |
| }; |
| |
| struct opcode32 |
| { |
| arm_feature_set arch; /* Architecture defining this insn. */ |
| unsigned long value; /* If arch is 0 then value is a sentinel. */ |
| unsigned long mask; /* Recognise insn if (op & mask) == value. */ |
| const char * assembler; /* How to disassemble this insn. */ |
| }; |
| |
| struct cdeopcode32 |
| { |
| arm_feature_set arch; /* Architecture defining this insn. */ |
| uint8_t coproc_shift; /* coproc is this far into op. */ |
| uint16_t coproc_mask; /* Length of coproc field in op. */ |
| unsigned long value; /* If arch is 0 then value is a sentinel. */ |
| unsigned long mask; /* Recognise insn if (op & mask) == value. */ |
| const char * assembler; /* How to disassemble this insn. */ |
| }; |
| |
| /* MVE opcodes. */ |
| |
| struct mopcode32 |
| { |
| arm_feature_set arch; /* Architecture defining this insn. */ |
| enum mve_instructions mve_op; /* Specific mve instruction for faster |
| decoding. */ |
| unsigned long value; /* If arch is 0 then value is a sentinel. */ |
| unsigned long mask; /* Recognise insn if (op & mask) == value. */ |
| const char * assembler; /* How to disassemble this insn. */ |
| }; |
| |
| enum isa { |
| ANY, |
| T32, |
| ARM |
| }; |
| |
| |
| /* Shared (between Arm and Thumb mode) opcode. */ |
| struct sopcode32 |
| { |
| enum isa isa; /* Execution mode instruction availability. */ |
| arm_feature_set arch; /* Architecture defining this insn. */ |
| unsigned long value; /* If arch is 0 then value is a sentinel. */ |
| unsigned long mask; /* Recognise insn if (op & mask) == value. */ |
| const char * assembler; /* How to disassemble this insn. */ |
| }; |
| |
| struct opcode16 |
| { |
| arm_feature_set arch; /* Architecture defining this insn. */ |
| unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ |
| const char *assembler; /* How to disassemble this insn. */ |
| }; |
| |
| /* print_insn_coprocessor recognizes the following format control codes: |
| |
| %% % |
| |
| %c print condition code (always bits 28-31 in ARM mode) |
| %b print condition code allowing cp_num == 9 |
| %q print shifter argument |
| %u print condition code (unconditional in ARM mode, |
| UNPREDICTABLE if not AL in Thumb) |
| %A print address for ldc/stc instruction |
| %B print vstm/vldm register list |
| %C print vscclrm register list |
| %J print register for VLDR instruction |
| %K print address for VLDR instruction |
| |
| %<bitfield>c print as a condition code (for vsel) |
| %<bitfield>r print as an ARM register |
| %<bitfield>R as %<>r but r15 is UNPREDICTABLE |
| %<bitfield>ru as %<>r but each u register must be unique. |
| %<bitfield>d print the bitfield in decimal |
| %<bitfield>k print immediate for VFPv3 conversion instruction |
| %<bitfield>x print the bitfield in hex |
| %<bitfield>X print the bitfield as 1 hex digit without leading "0x" |
| %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us |
| %<bitfield>g print as an iWMMXt 64-bit register |
| %<bitfield>G print as an iWMMXt general purpose or control register |
| %<bitfield>D print as a NEON D register |
| %<bitfield>Q print as a NEON Q register |
| %<bitfield>V print as a NEON D or Q register |
| %<bitfield>E print a quarter-float immediate value |
| |
| %y<code> print a single precision VFP reg. |
| Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair |
| %z<code> print a double precision VFP reg |
| Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list |
| |
| %<bitfield>'c print specified char iff bitfield is all ones |
| %<bitfield>`c print specified char iff bitfield is all zeroes |
| %<bitfield>?ab... select from array of values in big endian order |
| |
| %L print as an iWMMXt N/M width field. |
| %Z print the Immediate of a WSHUFH instruction. |
| %l like 'A' except use byte offsets for 'B' & 'H' |
| versions. |
| %i print 5-bit immediate in bits 8,3..0 |
| (print "32" when 0) |
| %r print register offset address for wldt/wstr instruction. */ |
| |
| enum opcode_sentinel_enum |
| { |
| SENTINEL_IWMMXT_START = 1, |
| SENTINEL_IWMMXT_END, |
| SENTINEL_GENERIC_START |
| } opcode_sentinels; |
| |
| #define UNDEFINED_INSTRUCTION "\t\t@ <UNDEFINED> instruction: %0-31x" |
| #define UNKNOWN_INSTRUCTION_32BIT "\t\t@ <UNDEFINED> instruction: %08x" |
| #define UNKNOWN_INSTRUCTION_16BIT "\t\t@ <UNDEFINED> instruction: %04x" |
| #define UNPREDICTABLE_INSTRUCTION "\t@ <UNPREDICTABLE>" |
| |
| /* Common coprocessor opcodes shared between Arm and Thumb-2. */ |
| |
| /* print_insn_cde recognizes the following format control codes: |
| |
| %% % |
| |
| %a print 'a' iff bit 28 is 1 |
| %p print bits 8-10 as coprocessor |
| %<bitfield>d print as decimal |
| %<bitfield>r print as an ARM register |
| %<bitfield>n print as an ARM register but r15 is APSR_nzcv |
| %<bitfield>T print as an ARM register + 1 |
| %<bitfield>R as %r but r13 is UNPREDICTABLE |
| %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE |
| %j print immediate taken from bits (16..21,7,0..5) |
| %k print immediate taken from bits (20..21,7,0..5). |
| %l print immediate taken from bits (20..22,7,4..5). */ |
| |
| /* At the moment there is only one valid position for the coprocessor number, |
| and hence that's encoded in the macro below. */ |
| #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \ |
| { ARCH, 8, 7, VALUE, MASK, ASM } |
| static const struct cdeopcode32 cde_opcodes[] = |
| { |
| /* Custom Datapath Extension instructions. */ |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee000000, 0xefc00840, |
| "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee000040, 0xefc00840, |
| "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee400000, 0xefc00840, |
| "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee400040, 0xefc00840, |
| "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee800000, 0xef800840, |
| "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xee800040, 0xef800840, |
| "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec200000, 0xeeb00840, |
| "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec200040, 0xeeb00840, |
| "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec300000, 0xeeb00840, |
| "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec300040, 0xeeb00840, |
| "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec800000, 0xee800840, |
| "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"), |
| CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE), |
| 0xec800040, 0xee800840, |
| "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"), |
| |
| CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0) |
| |
| }; |
| |
| static const struct sopcode32 coprocessor_opcodes[] = |
| { |
| /* XScale instructions. */ |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e200010, 0x0fff0ff0, |
| "mia%c\t%{R:acc0%}, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e280010, 0x0fff0ff0, |
| "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"}, |
| |
| /* Intel Wireless MMX technology instructions. */ |
| {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), |
| 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e800120, 0x0f800ff0, |
| "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e8000a0, 0x0f800ff0, |
| "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), |
| 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, |
| {ANY, ARM_FEATURE_CORE_LOW (0), |
| SENTINEL_IWMMXT_END, 0, "" }, |
| |
| /* Armv8.1-M Mainline instructions. */ |
| {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"}, |
| {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"}, |
| |
| /* ARMv8-M Mainline Security Extensions instructions. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), |
| 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), |
| 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, |
| |
| /* Register load/store. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), |
| 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), |
| 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"}, |
| {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN), |
| 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"}, |
| |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t@ Deprecated"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t@ Deprecated"}, |
| |
| /* Data transfer between ARM and NEON registers. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"}, |
| /* Half-precision conversion instructions. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), |
| 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), |
| 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, |
| |
| /* Floating point coprocessor (VFP) instructions. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"}, |
| {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), |
| 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"}, |
| {ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD), |
| 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), |
| 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), |
| 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), |
| 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), |
| 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), |
| 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), |
| 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), |
| 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), |
| 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), |
| 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), |
| 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), |
| 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), |
| 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, |
| |
| /* VFP Fused multiply add instructions. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), |
| 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, |
| |
| /* FP v5. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), |
| 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, |
| |
| {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, |
| /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"}, |
| |
| /* BFloat16 instructions. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"}, |
| |
| /* Dot Product instructions in the space of coprocessor 13. */ |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), |
| 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, |
| {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), |
| 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"}, |
| |
| /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), |
| 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"}, |
| |
| /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. |
| cp_num: bit <11:8> == 0b1001. |
| cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, |
| |
| /* ARMv8.3 javascript conversion instruction. */ |
| {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), |
| 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, |
| |
| {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} |
| }; |
| |
| /* Generic coprocessor instructions. These are only matched if a more specific |
| SIMD or co-processor instruction does not match first. */ |
| |
| static const struct sopcode32 generic_coprocessor_opcodes[] = |
| { |
| /* Generic coprocessor instructions. */ |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), |
| 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), |
| 0x0c500000, 0x0ff00000, |
| "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0e000000, 0x0f000010, |
| "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0e10f010, 0x0f10f010, |
| "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0e100010, 0x0f100010, |
| "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0e000010, 0x0f100010, |
| "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2), |
| 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, |
| |
| /* V6 coprocessor instructions. */ |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), |
| 0xfc500000, 0xfff00000, |
| "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6), |
| 0xfc400000, 0xfff00000, |
| "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"}, |
| |
| /* V5 coprocessor instructions. */ |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |
| 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |
| 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |
| 0xfe000000, 0xff000010, |
| "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |
| 0xfe000010, 0xff100010, |
| "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |
| 0xfe100010, 0xff100010, |
| "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"}, |
| |
| {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0} |
| }; |
| |
| /* Neon opcode table: This does not encode the top byte -- that is |
| checked by the print_insn_neon routine, as it depends on whether we are |
| doing thumb32 or arm32 disassembly. */ |
| |
| /* print_insn_neon recognizes the following format control codes: |
| |
| %% % |
| |
| %c print condition code |
| %u print condition code (unconditional in ARM mode, |
| UNPREDICTABLE if not AL in Thumb) |
| %A print v{st,ld}[1234] operands |
| %B print v{st,ld}[1234] any one operands |
| %C print v{st,ld}[1234] single->all operands |
| %D print scalar |
| %E print vmov, vmvn, vorr, vbic encoded constant |
| %F print vtbl,vtbx register list |
| |
| %<bitfield>r print as an ARM register |
| %<bitfield>d print the bitfield in decimal |
| %<bitfield>e print the 2^N - bitfield in decimal |
| %<bitfield>D print as a NEON D register |
| %<bitfield>Q print as a NEON Q register |
| %<bitfield>R print as a NEON D or Q register |
| %<bitfield>Sn print byte scaled width limited by n |
| %<bitfield>Tn print short scaled width limited by n |
| %<bitfield>Un print long scaled width limited by n |
| |
| %<bitfield>'c print specified char iff bitfield is all ones |
| %<bitfield>`c print specified char iff bitfield is all zeroes |
| %<bitfield>?ab... select from array of values in big endian order. */ |
| |
| static const struct opcode32 neon_opcodes[] = |
| { |
| /* Extract. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2b00840, 0xffb00850, |
| "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2b00000, 0xffb00810, |
| "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"}, |
| |
| /* Data transfer between ARM and NEON registers. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, |
| |
| /* Move data element to all lanes. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"}, |
| |
| /* Table lookup. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, |
| |
| /* Half-precision conversions. */ |
| {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), |
| 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), |
| 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, |
| |
| /* NEON fused multiply add instructions. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), |
| 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), |
| 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| |
| /* BFloat16 instructions. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16), |
| 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"}, |
| |
| /* Matrix Multiply instructions. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM), |
| 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"}, |
| |
| /* Two registers, miscellaneous. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), |
| 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), |
| 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20300, 0xffb30fd0, |
| "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3bb0600, 0xffbf0e10, |
| "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3b70600, 0xffbf0e10, |
| "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, |
| |
| /* Three registers of the same length. */ |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), |
| 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), |
| 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000b00, 0xff800f10, |
| "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000b10, 0xff800f10, |
| "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3000b00, 0xff800f10, |
| "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000000, 0xfe800f10, |
| "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000010, 0xfe800f10, |
| "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000100, 0xfe800f10, |
| "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000200, 0xfe800f10, |
| "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000210, 0xfe800f10, |
| "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000300, 0xfe800f10, |
| "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000310, 0xfe800f10, |
| "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000400, 0xfe800f10, |
| "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000410, 0xfe800f10, |
| "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000500, 0xfe800f10, |
| "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000510, 0xfe800f10, |
| "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000600, 0xfe800f10, |
| "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000610, 0xfe800f10, |
| "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000700, 0xfe800f10, |
| "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000710, 0xfe800f10, |
| "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000910, 0xfe800f10, |
| "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000a00, 0xfe800f10, |
| "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2000a10, 0xfe800f10, |
| "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf3000b10, 0xff800f10, |
| "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf3000c10, 0xff800f10, |
| "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
| |
| /* One register and an immediate value. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, |
| |
| /* Two registers and a shift amount. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880950, 0xfeb80fd0, |
| "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900950, 0xfeb00fd0, |
| "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00950, 0xfea00fd0, |
| "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2a00e10, 0xfea00e90, |
| "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), |
| 0xf2a00c10, 0xfea00e90, |
| "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"}, |
| |
| /* Three registers of different lengths. */ |
| {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), |
| 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800400, 0xff800f50, |
| "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800600, 0xff800f50, |
| "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800900, 0xff800f50, |
| "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800b00, 0xff800f50, |
| "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800d00, 0xff800f50, |
| "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800400, 0xff800f50, |
| "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800600, 0xff800f50, |
| "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800000, 0xfe800f50, |
| "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800100, 0xfe800f50, |
| "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800200, 0xfe800f50, |
| "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800300, 0xfe800f50, |
| "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800500, 0xfe800f50, |
| "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800700, 0xfe800f50, |
| "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800800, 0xfe800f50, |
| "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800a00, 0xfe800f50, |
| "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800c00, 0xfe800f50, |
| "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
| |
| /* Two registers and a scalar. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), |
| 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800240, 0xfe800f50, |
| "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800640, 0xfe800f50, |
| "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf2800a40, 0xfe800f50, |
| "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf2800e40, 0xff800f50, |
| "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf2800f40, 0xff800f50, |
| "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf3800e40, 0xff800f50, |
| "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), |
| 0xf3800f40, 0xff800f50, |
| "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" |
| }, |
| |
| /* Element and structure load/store. */ |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, |
| {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), |
| 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, |
| |
| {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} |
| }; |
| |
| /* mve opcode table. */ |
| |
| /* print_insn_mve recognizes the following format control codes: |
| |
| %% % |
| |
| %a print '+' or '-' or imm offset in vldr[bhwd] and |
| vstr[bhwd] |
| %c print condition code |
| %d print addr mode of MVE vldr[bhw] and vstr[bhw] |
| %u print 'U' (unsigned) or 'S' for various mve instructions |
| %i print MVE predicate(s) for vpt and vpst |
| %j print a 5-bit immediate from hw2[14:12,7:6] |
| %k print 48 if the 7th position bit is set else print 64. |
| %m print rounding mode for vcvt and vrint |
| %n print vector comparison code for predicated instruction |
| %s print size for various vcvt instructions |
| %v print vector predicate for instruction in predicated |
| block |
| %o print offset scaled for vldr[hwd] and vstr[hwd] |
| %w print writeback mode for MVE v{st,ld}[24] |
| %B print v{st,ld}[24] any one operands |
| %E print vmov, vmvn, vorr, vbic encoded constant |
| %N print generic index for vmov |
| %T print bottom ('b') or top ('t') of source register |
| %X print exchange field in vmla* instructions |
| |
| %<bitfield>r print as an ARM register |
| %<bitfield>d print the bitfield in decimal |
| %<bitfield>A print accumulate or not |
| %<bitfield>c print bitfield as a condition code |
| %<bitfield>C print bitfield as an inverted condition code |
| %<bitfield>Q print as a MVE Q register |
| %<bitfield>F print as a MVE S register |
| %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is |
| UNPREDICTABLE |
| |
| %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE |
| %<bitfield>s print size for vector predicate & non VMOV instructions |
| %<bitfield>I print carry flag or not |
| %<bitfield>i print immediate for vstr/vldr reg +/- imm |
| %<bitfield>h print high half of 64-bit destination reg |
| %<bitfield>k print immediate for vector conversion instruction |
| %<bitfield>l print low half of 64-bit destination reg |
| %<bitfield>o print rotate value for vcmul |
| %<bitfield>u print immediate value for vddup/vdwdup |
| %<bitfield>x print the bitfield in hex. |
| */ |
| |
| static const struct mopcode32 mve_opcodes[] = |
| { |
| /* MVE. */ |
| |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPST, |
| 0xfe310f4d, 0xffbf1fff, |
| "vpst%i" |
| }, |
| |
| /* Floating point VPT T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VPT_FP_T1, |
| 0xee310f00, 0xefb10f50, |
| "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Floating point VPT T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VPT_FP_T2, |
| 0xee310f40, 0xefb10f50, |
| "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"}, |
| |
| /* Vector VPT T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T1, |
| 0xfe010f00, 0xff811f51, |
| "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VPT T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T2, |
| 0xfe010f01, 0xff811f51, |
| "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VPT T3. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T3, |
| 0xfe011f00, 0xff811f50, |
| "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VPT T4. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T4, |
| 0xfe010f40, 0xff811f70, |
| "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"}, |
| /* Vector VPT T5. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T5, |
| 0xfe010f60, 0xff811f70, |
| "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"}, |
| /* Vector VPT T6. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPT_VEC_T6, |
| 0xfe011f40, 0xff811f50, |
| "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"}, |
| |
| /* Vector VBIC immediate. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VBIC_IMM, |
| 0xef800070, 0xefb81070, |
| "vbic%v.i%8-11s\t%13-15,22Q, %E"}, |
| |
| /* Vector VBIC register. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VBIC_REG, |
| 0xef100150, 0xffb11f51, |
| "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VABAV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VABAV, |
| 0xee800f01, 0xefc10f51, |
| "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VABD floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VABD_FP, |
| 0xff200d40, 0xffa11f51, |
| "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VABD. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VABD_VEC, |
| 0xef000740, 0xef811f51, |
| "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VABS floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VABS_FP, |
| 0xFFB10740, 0xFFB31FD1, |
| "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| /* Vector VABS. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VABS_VEC, |
| 0xffb10340, 0xffb31fd1, |
| "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VADD floating point T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VADD_FP_T1, |
| 0xef000d40, 0xffa11f51, |
| "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| /* Vector VADD floating point T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VADD_FP_T2, |
| 0xee300f40, 0xefb11f70, |
| "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| /* Vector VADD T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VADD_VEC_T1, |
| 0xef000840, 0xff811f51, |
| "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| /* Vector VADD T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VADD_VEC_T2, |
| 0xee010f40, 0xff811f70, |
| "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VADDLV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VADDLV, |
| 0xee890f00, 0xef8f1fd1, |
| "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"}, |
| |
| /* Vector VADDV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VADDV, |
| 0xeef10f00, 0xeff31fd1, |
| "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"}, |
| |
| /* Vector VADC. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VADC, |
| 0xee300f00, 0xffb10f51, |
| "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VAND. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VAND, |
| 0xef000150, 0xffb11f51, |
| "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VBRSR register. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VBRSR, |
| 0xfe011e60, 0xff811f70, |
| "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VCADD floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCADD_FP, |
| 0xfc800840, 0xfea11f51, |
| "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"}, |
| |
| /* Vector VCADD. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCADD_VEC, |
| 0xfe000f00, 0xff810f51, |
| "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, |
| |
| /* Vector VCLS. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCLS, |
| 0xffb00440, 0xffb31fd1, |
| "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VCLZ. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCLZ, |
| 0xffb004c0, 0xffb31fd1, |
| "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VCMLA. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCMLA_FP, |
| 0xfc200840, 0xfe211f51, |
| "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"}, |
| |
| /* Vector VCMP floating point T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCMP_FP_T1, |
| 0xee310f00, 0xeff1ef50, |
| "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"}, |
| |
| /* Vector VCMP floating point T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCMP_FP_T2, |
| 0xee310f40, 0xeff1ef50, |
| "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"}, |
| |
| /* Vector VCMP T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T1, |
| 0xfe010f00, 0xffc1ff51, |
| "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VCMP T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T2, |
| 0xfe010f01, 0xffc1ff51, |
| "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VCMP T3. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T3, |
| 0xfe011f00, 0xffc1ff50, |
| "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"}, |
| /* Vector VCMP T4. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T4, |
| 0xfe010f40, 0xffc1ff70, |
| "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"}, |
| /* Vector VCMP T5. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T5, |
| 0xfe010f60, 0xffc1ff70, |
| "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"}, |
| /* Vector VCMP T6. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCMP_VEC_T6, |
| 0xfe011f40, 0xffc1ff50, |
| "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"}, |
| |
| /* Vector VDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VDUP, |
| 0xeea00b10, 0xffb10f5f, |
| "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, |
| |
| /* Vector VEOR. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VEOR, |
| 0xff000150, 0xffd11f51, |
| "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VFMA, vector * scalar. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VFMA_FP_SCALAR, |
| 0xee310e40, 0xefb11f70, |
| "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VFMA floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VFMA_FP, |
| 0xef000c50, 0xffa11f51, |
| "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VFMS floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VFMS_FP, |
| 0xef200c50, 0xffa11f51, |
| "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VFMAS, vector * scalar. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VFMAS_FP_SCALAR, |
| 0xee311e40, 0xefb11f70, |
| "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VHADD T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VHADD_T1, |
| 0xef000040, 0xef811f51, |
| "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VHADD T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VHADD_T2, |
| 0xee000f40, 0xef811f70, |
| "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VHSUB T1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VHSUB_T1, |
| 0xef000240, 0xef811f51, |
| "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VHSUB T2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VHSUB_T2, |
| 0xee001f40, 0xef811f70, |
| "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VCMUL. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCMUL_FP, |
| 0xee300e00, 0xefb10f50, |
| "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"}, |
| |
| /* Vector VCTP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VCTP, |
| 0xf000e801, 0xffc0ffff, |
| "vctp%v.%20-21s\t%16-19r"}, |
| |
| /* Vector VDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VDUP, |
| 0xeea00b10, 0xffb10f5f, |
| "vdup%v.%5,22s\t%17-19,7Q, %12-15r"}, |
| |
| /* Vector VRHADD. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VRHADD, |
| 0xef000140, 0xef811f51, |
| "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VCVT. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCVT_FP_FIX_VEC, |
| 0xef800c50, 0xef801cd1, |
| "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"}, |
| |
| /* Vector VCVT. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCVT_BETWEEN_FP_INT, |
| 0xffb30640, 0xffb31e51, |
| "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VCVT between single and half-precision float, bottom half. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCVT_FP_HALF_FP, |
| 0xee3f0e01, 0xefbf1fd1, |
| "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VCVT between single and half-precision float, top half. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCVT_FP_HALF_FP, |
| 0xee3f1e01, 0xefbf1fd1, |
| "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VCVT. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VCVT_FROM_FP_TO_INT, |
| 0xffb30040, 0xffb31c51, |
| "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VDDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VDDUP, |
| 0xee011f6e, 0xff811f7e, |
| "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, |
| |
| /* Vector VDWDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VDWDUP, |
| 0xee011f60, 0xff811f70, |
| "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, |
| |
| /* Vector VHCADD. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VHCADD, |
| 0xee000f00, 0xff810f51, |
| "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"}, |
| |
| /* Vector VIWDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VIWDUP, |
| 0xee010f60, 0xff811f70, |
| "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"}, |
| |
| /* Vector VIDUP. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VIDUP, |
| 0xee010f6e, 0xff811f7e, |
| "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"}, |
| |
| /* Vector VLD2. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLD2, |
| 0xfc901e00, 0xff901e5f, |
| "vld2%5d.%7-8s\t%B, [%16-19r]%w"}, |
| |
| /* Vector VLD4. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLD4, |
| 0xfc901e01, 0xff901e1f, |
| "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"}, |
| |
| /* Vector VLDRB gather load. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRB_GATHER_T1, |
| 0xec900e00, 0xefb01e50, |
| "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"}, |
| |
| /* Vector VLDRH gather load. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRH_GATHER_T2, |
| 0xec900e10, 0xefb01e50, |
| "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, |
| |
| /* Vector VLDRW gather load. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRW_GATHER_T3, |
| 0xfc900f40, 0xffb01fd0, |
| "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, |
| |
| /* Vector VLDRD gather load. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRD_GATHER_T4, |
| 0xec900fd0, 0xefb01fd0, |
| "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"}, |
| |
| /* Vector VLDRW gather load. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRW_GATHER_T5, |
| 0xfd101e00, 0xff111f00, |
| "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, |
| |
| /* Vector VLDRD gather load, variant T6. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRD_GATHER_T6, |
| 0xfd101f00, 0xff111f00, |
| "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"}, |
| |
| /* Vector VLDRB. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRB_T1, |
| 0xec100e00, 0xee581e00, |
| "vldrb%v.%u%7-8s\t%13-15Q, %d"}, |
| |
| /* Vector VLDRH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRH_T2, |
| 0xec180e00, 0xee581e00, |
| "vldrh%v.%u%7-8s\t%13-15Q, %d"}, |
| |
| /* Vector VLDRB unsigned, variant T5. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRB_T5, |
| 0xec101e00, 0xfe101f80, |
| "vldrb%v.u8\t%13-15,22Q, %d"}, |
| |
| /* Vector VLDRH unsigned, variant T6. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRH_T6, |
| 0xec101e80, 0xfe101f80, |
| "vldrh%v.u16\t%13-15,22Q, %d"}, |
| |
| /* Vector VLDRW unsigned, variant T7. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VLDRW_T7, |
| 0xec101f00, 0xfe101f80, |
| "vldrw%v.u32\t%13-15,22Q, %d"}, |
| |
| /* Vector VMAX. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMAX, |
| 0xef000640, 0xef811f51, |
| "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMAXA. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMAXA, |
| 0xee330e81, 0xffb31fd1, |
| "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VMAXNM floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMAXNM_FP, |
| 0xff000f50, 0xffa11f51, |
| "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMAXNMA floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMAXNMA_FP, |
| 0xee3f0e81, 0xefbf1fd1, |
| "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VMAXNMV floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMAXNMV_FP, |
| 0xeeee0f00, 0xefff0fd1, |
| "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMAXNMAV floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMAXNMAV_FP, |
| 0xeeec0f00, 0xefff0fd1, |
| "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMAXV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMAXV, |
| 0xeee20f00, 0xeff30fd1, |
| "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMAXAV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMAXAV, |
| 0xeee00f00, 0xfff30fd1, |
| "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMIN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMIN, |
| 0xef000650, 0xef811f51, |
| "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMINA. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMINA, |
| 0xee331e81, 0xffb31fd1, |
| "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VMINNM floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMINNM_FP, |
| 0xff200f50, 0xffa11f51, |
| "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMINNMA floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMINNMA_FP, |
| 0xee3f1e81, 0xefbf1fd1, |
| "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VMINNMV floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMINNMV_FP, |
| 0xeeee0f80, 0xefff0fd1, |
| "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMINNMAV floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMINNMAV_FP, |
| 0xeeec0f80, 0xefff0fd1, |
| "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMINV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMINV, |
| 0xeee20f80, 0xeff30fd1, |
| "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMINAV. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMINAV, |
| 0xeee00f80, 0xfff30fd1, |
| "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"}, |
| |
| /* Vector VMLA. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLA, |
| 0xee010e40, 0xef811f70, |
| "vmla%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction |
| opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLALDAV, |
| 0xee801e00, 0xef801f51, |
| "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, |
| |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLALDAV, |
| 0xee800e00, 0xef801f51, |
| "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLADAV_T1, |
| 0xeef00e00, 0xeff01f51, |
| "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLADAV_T2, |
| 0xeef00f00, 0xeff11f51, |
| "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLADAV T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLADAV_T1, |
| 0xeef01e00, 0xeff01f51, |
| "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLADAV T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLADAV_T2, |
| 0xeef01f00, 0xeff11f51, |
| "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLAS. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLAS, |
| 0xee011e40, 0xef811f70, |
| "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction |
| opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VRMLSLDAVH, |
| 0xfe800e01, 0xff810f51, |
| "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction |
| opcdoe aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLSLDAV, |
| 0xee800e01, 0xff800f51, |
| "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLSDAV T1 Variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLSDAV_T1, |
| 0xeef00e01, 0xfff00f51, |
| "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMLSDAV T2 Variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMLSDAV_T2, |
| 0xfef00e01, 0xfff10f51, |
| "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"}, |
| |
| /* Vector VMOV between gpr and half precision register, op == 0. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMOV_HFP_TO_GP, |
| 0xee000910, 0xfff00f7f, |
| "vmov.f16\t%7,16-19F, %12-15r"}, |
| |
| /* Vector VMOV between gpr and half precision register, op == 1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMOV_HFP_TO_GP, |
| 0xee100910, 0xfff00f7f, |
| "vmov.f16\t%12-15r, %7,16-19F"}, |
| |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMOV_GP_TO_VEC_LANE, |
| 0xee000b10, 0xff900f1f, |
| "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"}, |
| |
| /* Vector VORR immediate to vector. |
| NOTE: MVE_VORR_IMM must appear in the table |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VORR_IMM, |
| 0xef800050, 0xefb810f0, |
| "vorr%v.i%8-11s\t%13-15,22Q, %E"}, |
| |
| /* Vector VQSHL T2 Variant. |
| NOTE: MVE_VQSHL_T2 must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHL_T2, |
| 0xef800750, 0xef801fd1, |
| "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VQSHLU T3 Variant |
| NOTE: MVE_VQSHL_T2 must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHLU_T3, |
| 0xff800650, 0xff801fd1, |
| "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VRSHR |
| NOTE: MVE_VRSHR must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VRSHR, |
| 0xef800250, 0xef801fd1, |
| "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VSHL. |
| NOTE: MVE_VSHL must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VSHL_T1, |
| 0xef800550, 0xff801fd1, |
| "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VSHR |
| NOTE: MVE_VSHR must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VSHR, |
| 0xef800050, 0xef801fd1, |
| "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VSLI |
| NOTE: MVE_VSLI must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VSLI, |
| 0xff800550, 0xff801fd1, |
| "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VSRI |
| NOTE: MVE_VSRI must appear in the table before |
| before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VSRI, |
| 0xff800450, 0xff801fd1, |
| "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VMOV immediate to vector, |
| undefinded for cmode == 1111 */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION}, |
| |
| /* Vector VMOV immediate to vector, |
| cmode == 1101 */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0, |
| "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, |
| |
| /* Vector VMOV immediate to vector. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV_IMM_TO_VEC, |
| 0xef800050, 0xefb810d0, |
| "vmov%v.%5,8-11s\t%13-15,22Q, %E"}, |
| |
| /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV2_VEC_LANE_TO_GP, |
| 0xec000f00, 0xffb01ff0, |
| "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"}, |
| |
| /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV2_VEC_LANE_TO_GP, |
| 0xec000f10, 0xffb01ff0, |
| "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"}, |
| |
| /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV2_GP_TO_VEC_LANE, |
| 0xec100f00, 0xffb01ff0, |
| "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"}, |
| |
| /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV2_GP_TO_VEC_LANE, |
| 0xec100f10, 0xffb01ff0, |
| "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"}, |
| |
| /* Vector VMOV Vector lane to gpr. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMOV_VEC_LANE_TO_GP, |
| 0xee100b10, 0xff100f1f, |
| "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"}, |
| |
| /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due |
| to instruction opcode aliasing. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VSHLL_T1, |
| 0xeea00f40, 0xefa00fd1, |
| "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VMOVL long. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOVL, |
| 0xeea00f40, 0xefa70fd1, |
| "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VMOV and narrow. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOVN, |
| 0xfe310e81, 0xffb30fd1, |
| "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Floating point move extract. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMOVX, |
| 0xfeb00a40, 0xffbf0fd0, |
| "vmovx.f16\t%22,12-15F, %5,0-3F"}, |
| |
| /* Vector VMUL floating-point T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMUL_FP_T1, |
| 0xff000d50, 0xffa11f51, |
| "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMUL floating-point T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VMUL_FP_T2, |
| 0xee310e60, 0xefb11f70, |
| "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VMUL T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMUL_VEC_T1, |
| 0xef000950, 0xff811f51, |
| "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMUL T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMUL_VEC_T2, |
| 0xee011e60, 0xff811f70, |
| "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VMULH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMULH, |
| 0xee010e01, 0xef811f51, |
| "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VRMULH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VRMULH, |
| 0xee011e01, 0xef811f51, |
| "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMULL integer. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMULL_INT, |
| 0xee010e00, 0xef810f51, |
| "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMULL polynomial. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMULL_POLY, |
| 0xee310e00, 0xefb10f51, |
| "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMVN immediate to vector. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMVN_IMM, |
| 0xef800070, 0xefb810f0, |
| "vmvn%v.i%8-11s\t%13-15,22Q, %E"}, |
| |
| /* Vector VMVN register. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMVN_REG, |
| 0xffb005c0, 0xffbf1fd1, |
| "vmvn%v\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VNEG floating point. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP), |
| MVE_VNEG_FP, |
| 0xffb107c0, 0xffb31fd1, |
| "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VNEG. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VNEG_VEC, |
| 0xffb103c0, 0xffb31fd1, |
| "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VORN, vector bitwise or not. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VORN, |
| 0xef300150, 0xffb11f51, |
| "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VORR register. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VORR_REG, |
| 0xef200150, 0xffb11f51, |
| "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if |
| "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen |
| MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes |
| array. */ |
| |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VMOV_VEC_TO_VEC, |
| 0xef200150, 0xffb11f51, |
| "vmov%v\t%13-15,22Q, %17-19,7Q"}, |
| |
| /* Vector VQDMULL T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMULL_T1, |
| 0xee300f01, 0xefb10f51, |
| "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VPNOT. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPNOT, |
| 0xfe310f4d, 0xffffffff, |
| "vpnot%v"}, |
| |
| /* Vector VPSEL. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VPSEL, |
| 0xfe310f01, 0xffb11f51, |
| "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQABS. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQABS, |
| 0xffb00740, 0xffb31fd1, |
| "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQADD T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQADD_T1, |
| 0xef000050, 0xef811f51, |
| "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQADD T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQADD_T2, |
| 0xee000f60, 0xef811f70, |
| "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQDMULL T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMULL_T2, |
| 0xee300f60, 0xefb10f70, |
| "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQMOVN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQMOVN, |
| 0xee330e01, 0xefb30fd1, |
| "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VQMOVUN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQMOVUN, |
| 0xee310e81, 0xffb30fd1, |
| "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VQDMLADH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMLADH, |
| 0xee000e00, 0xff810f51, |
| "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQRDMLADH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMLADH, |
| 0xee000e01, 0xff810f51, |
| "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQDMLAH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMLAH, |
| 0xee000e60, 0xff811f70, |
| "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQRDMLAH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMLAH, |
| 0xee000e40, 0xff811f70, |
| "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQDMLASH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMLASH, |
| 0xee001e60, 0xff811f70, |
| "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQRDMLASH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMLASH, |
| 0xee001e40, 0xff811f70, |
| "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQDMLSDH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMLSDH, |
| 0xfe000e00, 0xff810f51, |
| "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQRDMLSDH. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMLSDH, |
| 0xfe000e01, 0xff810f51, |
| "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQDMULH T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMULH_T1, |
| 0xef000b40, 0xff811f51, |
| "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQRDMULH T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMULH_T2, |
| 0xff000b40, 0xff811f51, |
| "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"}, |
| |
| /* Vector VQDMULH T3 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQDMULH_T3, |
| 0xee010e60, 0xff811f70, |
| "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQRDMULH T4 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRDMULH_T4, |
| 0xfe010e60, 0xff811f70, |
| "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"}, |
| |
| /* Vector VQNEG. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQNEG, |
| 0xffb007c0, 0xffb31fd1, |
| "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"}, |
| |
| /* Vector VQRSHL T1 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRSHL_T1, |
| 0xef000550, 0xef811f51, |
| "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, |
| |
| /* Vector VQRSHL T2 variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRSHL_T2, |
| 0xee331ee0, 0xefb31ff0, |
| "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, |
| |
| /* Vector VQRSHRN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRSHRN, |
| 0xee800f41, 0xefa00fd1, |
| "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VQRSHRUN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQRSHRUN, |
| 0xfe800fc0, 0xffa00fd1, |
| "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VQSHL T1 Variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHL_T1, |
| 0xee311ee0, 0xefb31ff0, |
| "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"}, |
| |
| /* Vector VQSHL T4 Variant. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHL_T4, |
| 0xef000450, 0xef811f51, |
| "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"}, |
| |
| /* Vector VQSHRN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHRN, |
| 0xee800f40, 0xefa00fd1, |
| "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
| |
| /* Vector VQSHRUN. */ |
| {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), |
| MVE_VQSHRUN, |
| 0xee800fc0, 0xffa00fd1, |
| "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"}, |
|
