| /* Simulator model support for m32r2f. |
| |
| THIS FILE IS MACHINE GENERATED WITH CGEN. |
| |
| Copyright (C) 1996-2024 Free Software Foundation, Inc. |
| |
| This file is part of the GNU simulators. |
| |
| This file is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License along |
| with this program; if not, write to the Free Software Foundation, Inc., |
| 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| |
| */ |
| |
| #define WANT_CPU m32r2f |
| #define WANT_CPU_M32R2F |
| |
| #include "sim-main.h" |
| |
| /* The profiling data is recorded here, but is accessed via the profiling |
| mechanism. After all, this is information for profiling. */ |
| |
| #if WITH_PROFILE_MODEL_P |
| |
| /* Model handlers for each insn. */ |
| |
| static int |
| model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_addi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 3)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 4)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 4)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 3)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 4)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 4)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| if (insn_referenced & (1 << 1)) referenced |= 1 << 0; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| if (insn_referenced & (1 << 1)) referenced |= 1 << 0; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_sr); |
| out_dr = FLD (out_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_addi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_machi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_mvfachi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_mvfachi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_mvfachi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_mvtachi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_src1); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_mvtachi_a.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_src1); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_rac_dsi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_rac_dsi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| cycles += m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_seth.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_trap.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| cycles += m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r2_sat ( |