[aarch64] - Only use MOV for disassembly when shifter op is LSL #0
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.
2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
opcodes:
PR 23193
PR 19721
* aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
encoding as MOV if the shift operation is a left shift of zero.
gas:
PR 23193
PR 19721
* testsuite/gas/aarch64/pr19721.s: Add new test cases.
* testsuite/gas/aarch64/pr19721.d: Correct existing test
cases and add new ones.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5a1eeea..a7bcfee 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 23193
+ PR 19721
+ * testsuite/gas/aarch64/pr19721.s: Add new test cases.
+ * testsuite/gas/aarch64/pr19721.d: Correct existing test
+ cases and add new ones.
+
2018-12-03 Nick Clifton <nickc@redhat.com>
PR 23941
diff --git a/gas/testsuite/gas/aarch64/pr19721.d b/gas/testsuite/gas/aarch64/pr19721.d
index a621ae5..785d2a2 100644
--- a/gas/testsuite/gas/aarch64/pr19721.d
+++ b/gas/testsuite/gas/aarch64/pr19721.d
@@ -6,5 +6,8 @@
0+000 <.*>:
0: aa1103e7 mov x7, x17
- 4: aa1167e7 mov x7, x17, lsl #25
- 8: aa1167e7 mov x7, x17, lsl #25
+ 4: aa1167e7 orr x7, xzr, x17, lsl #25
+ 8: aa1167e7 orr x7, xzr, x17, lsl #25
+ c: aa4003e0 orr x0, xzr, x0, lsr #0
+ 10: aa0007e0 orr x0, xzr, x0, lsl #1
+ 14: aa0003d0 orr x16, x30, x0
diff --git a/gas/testsuite/gas/aarch64/pr19721.s b/gas/testsuite/gas/aarch64/pr19721.s
index cda068a..be2b508 100644
--- a/gas/testsuite/gas/aarch64/pr19721.s
+++ b/gas/testsuite/gas/aarch64/pr19721.s
@@ -3,3 +3,6 @@
mov x7, x17
mov x7, x17, lsl 25
orr x7, xzr, x17, lsl 25
+ orr x0, xzr, x0, lsr #0 // shift == 01
+ orr x0, xzr, x0, lsl #1 // imm6 == 000001
+ orr x16, x30, x0 // Rn == 11110
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 63560f1..a9bdb2f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 23193
+ PR 19721
+ * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
+ encoding as MOV if the shift operation is a left shift of zero.
+
2018-11-29 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6fb74bf..0ba72cb 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3369,7 +3369,7 @@
CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
- CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
+ CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO),
CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
