| commit | 5eeeafe0a6884eaf1c5a21160e78e53842fa7cba | [log] [tgz] |
|---|---|---|
| author | Jan Beulich <jbeulich@suse.com> | Fri Feb 24 13:57:31 2023 +0100 |
| committer | Jan Beulich <jbeulich@suse.com> | Fri Feb 24 13:57:31 2023 +0100 |
| tree | ccae730941360b00b9870cf3f271701d2e368527 | |
| parent | c34d1cc9200ae24dc7572aaf77d80276c0490e9b [diff] |
x86: have insns acting on segment selector values allow for consistent operands While MOV to/from segment register as well as selector storing insns already permit 32- and 64-bit GPR operands, selector loading insns and ARPL do not. Split templates accordingly.