Fix verilog output when the width is > 1.
PR 25202
bfd * bfd.c (VerilogDataEndianness): New variable.
(verilog_write_record): Use VerilogDataEndianness, if set, to
choose the endianness of the output.
(verilog_write_section): Adjust the address by the data width.
binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
endianness of the input file.
(copy_main): Verifiy the value set by the --verilog-data-width
option.
* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
* testsuite/binutils-all/verilog-I4.hex: New file.
6 files changed
