This commit was manufactured by cvs2svn to create branch 'cagney_writestrings-20030508-branch'. Sprout from jimb-ppc64-linux-20030509-branch 2003-05-09 16:41:43 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'jimb-' Cherrypick from master 2003-05-09 11:35:35 UTC Alan Modra <amodra@gmail.com> ' * cpu-arm.c (arm_check_note): Warning fix.': bfd/ChangeLog bfd/elf32-s390.c bfd/elf64-s390.c Delete: COPYING.LIBGLOSS sim/testsuite/sim/arm/adc.cgs sim/testsuite/sim/arm/add.cgs sim/testsuite/sim/arm/allinsn.exp sim/testsuite/sim/arm/and.cgs sim/testsuite/sim/arm/b.cgs sim/testsuite/sim/arm/bic.cgs sim/testsuite/sim/arm/bl.cgs sim/testsuite/sim/arm/bx.cgs sim/testsuite/sim/arm/cmn.cgs sim/testsuite/sim/arm/cmp.cgs sim/testsuite/sim/arm/eor.cgs sim/testsuite/sim/arm/hello.ms sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp sim/testsuite/sim/arm/iwmmxt/tbcst.cgs sim/testsuite/sim/arm/iwmmxt/testutils.inc sim/testsuite/sim/arm/iwmmxt/textrm.cgs sim/testsuite/sim/arm/iwmmxt/tinsr.cgs sim/testsuite/sim/arm/iwmmxt/tmia.cgs sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs sim/testsuite/sim/arm/iwmmxt/wacc.cgs sim/testsuite/sim/arm/iwmmxt/wadd.cgs sim/testsuite/sim/arm/iwmmxt/waligni.cgs sim/testsuite/sim/arm/iwmmxt/walignr.cgs sim/testsuite/sim/arm/iwmmxt/wand.cgs sim/testsuite/sim/arm/iwmmxt/wandn.cgs sim/testsuite/sim/arm/iwmmxt/wavg2.cgs sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs sim/testsuite/sim/arm/iwmmxt/wmac.cgs sim/testsuite/sim/arm/iwmmxt/wmadd.cgs sim/testsuite/sim/arm/iwmmxt/wmax.cgs sim/testsuite/sim/arm/iwmmxt/wmin.cgs sim/testsuite/sim/arm/iwmmxt/wmov.cgs sim/testsuite/sim/arm/iwmmxt/wmul.cgs sim/testsuite/sim/arm/iwmmxt/wor.cgs sim/testsuite/sim/arm/iwmmxt/wpack.cgs sim/testsuite/sim/arm/iwmmxt/wror.cgs sim/testsuite/sim/arm/iwmmxt/wsad.cgs sim/testsuite/sim/arm/iwmmxt/wshufh.cgs sim/testsuite/sim/arm/iwmmxt/wsll.cgs sim/testsuite/sim/arm/iwmmxt/wsra.cgs sim/testsuite/sim/arm/iwmmxt/wsrl.cgs sim/testsuite/sim/arm/iwmmxt/wsub.cgs sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs sim/testsuite/sim/arm/iwmmxt/wxor.cgs sim/testsuite/sim/arm/iwmmxt/wzero.cgs sim/testsuite/sim/arm/ldm.cgs sim/testsuite/sim/arm/ldr.cgs sim/testsuite/sim/arm/ldrb.cgs sim/testsuite/sim/arm/ldrh.cgs sim/testsuite/sim/arm/ldrsb.cgs sim/testsuite/sim/arm/ldrsh.cgs sim/testsuite/sim/arm/misaligned1.ms sim/testsuite/sim/arm/misaligned2.ms sim/testsuite/sim/arm/misaligned3.ms sim/testsuite/sim/arm/misc.exp sim/testsuite/sim/arm/mla.cgs sim/testsuite/sim/arm/mov.cgs sim/testsuite/sim/arm/mrs.cgs sim/testsuite/sim/arm/msr.cgs sim/testsuite/sim/arm/mul.cgs sim/testsuite/sim/arm/mvn.cgs sim/testsuite/sim/arm/orr.cgs sim/testsuite/sim/arm/rsb.cgs sim/testsuite/sim/arm/rsc.cgs sim/testsuite/sim/arm/sbc.cgs sim/testsuite/sim/arm/smlal.cgs sim/testsuite/sim/arm/smull.cgs sim/testsuite/sim/arm/stm.cgs sim/testsuite/sim/arm/str.cgs sim/testsuite/sim/arm/strb.cgs sim/testsuite/sim/arm/strh.cgs sim/testsuite/sim/arm/sub.cgs sim/testsuite/sim/arm/swi.cgs sim/testsuite/sim/arm/swp.cgs sim/testsuite/sim/arm/swpb.cgs sim/testsuite/sim/arm/teq.cgs sim/testsuite/sim/arm/testutils.inc sim/testsuite/sim/arm/thumb/adc.cgs sim/testsuite/sim/arm/thumb/add-hd-hs.cgs sim/testsuite/sim/arm/thumb/add-hd-rs.cgs sim/testsuite/sim/arm/thumb/add-rd-hs.cgs sim/testsuite/sim/arm/thumb/add-sp.cgs sim/testsuite/sim/arm/thumb/add.cgs sim/testsuite/sim/arm/thumb/addi.cgs sim/testsuite/sim/arm/thumb/addi8.cgs sim/testsuite/sim/arm/thumb/allthumb.exp sim/testsuite/sim/arm/thumb/and.cgs sim/testsuite/sim/arm/thumb/asr.cgs sim/testsuite/sim/arm/thumb/b.cgs sim/testsuite/sim/arm/thumb/bcc.cgs sim/testsuite/sim/arm/thumb/bcs.cgs sim/testsuite/sim/arm/thumb/beq.cgs sim/testsuite/sim/arm/thumb/bge.cgs sim/testsuite/sim/arm/thumb/bgt.cgs sim/testsuite/sim/arm/thumb/bhi.cgs sim/testsuite/sim/arm/thumb/bic.cgs sim/testsuite/sim/arm/thumb/bl-hi.cgs sim/testsuite/sim/arm/thumb/bl-lo.cgs sim/testsuite/sim/arm/thumb/ble.cgs sim/testsuite/sim/arm/thumb/bls.cgs sim/testsuite/sim/arm/thumb/blt.cgs sim/testsuite/sim/arm/thumb/bmi.cgs sim/testsuite/sim/arm/thumb/bne.cgs sim/testsuite/sim/arm/thumb/bpl.cgs sim/testsuite/sim/arm/thumb/bvc.cgs sim/testsuite/sim/arm/thumb/bvs.cgs sim/testsuite/sim/arm/thumb/bx-hs.cgs sim/testsuite/sim/arm/thumb/bx-rs.cgs sim/testsuite/sim/arm/thumb/cmn.cgs sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs sim/testsuite/sim/arm/thumb/cmp.cgs sim/testsuite/sim/arm/thumb/eor.cgs sim/testsuite/sim/arm/thumb/lda-pc.cgs sim/testsuite/sim/arm/thumb/lda-sp.cgs sim/testsuite/sim/arm/thumb/ldmia.cgs sim/testsuite/sim/arm/thumb/ldr-imm.cgs sim/testsuite/sim/arm/thumb/ldr-pc.cgs sim/testsuite/sim/arm/thumb/ldr-sprel.cgs sim/testsuite/sim/arm/thumb/ldr.cgs sim/testsuite/sim/arm/thumb/ldrb-imm.cgs sim/testsuite/sim/arm/thumb/ldrb.cgs sim/testsuite/sim/arm/thumb/ldrh-imm.cgs sim/testsuite/sim/arm/thumb/ldrh.cgs sim/testsuite/sim/arm/thumb/ldsb.cgs sim/testsuite/sim/arm/thumb/ldsh.cgs sim/testsuite/sim/arm/thumb/lsl.cgs sim/testsuite/sim/arm/thumb/lsr.cgs sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs sim/testsuite/sim/arm/thumb/mov.cgs sim/testsuite/sim/arm/thumb/mul.cgs sim/testsuite/sim/arm/thumb/mvn.cgs sim/testsuite/sim/arm/thumb/neg.cgs sim/testsuite/sim/arm/thumb/orr.cgs sim/testsuite/sim/arm/thumb/pop-pc.cgs sim/testsuite/sim/arm/thumb/pop.cgs sim/testsuite/sim/arm/thumb/push-lr.cgs sim/testsuite/sim/arm/thumb/push.cgs sim/testsuite/sim/arm/thumb/ror.cgs sim/testsuite/sim/arm/thumb/sbc.cgs sim/testsuite/sim/arm/thumb/stmia.cgs sim/testsuite/sim/arm/thumb/str-imm.cgs sim/testsuite/sim/arm/thumb/str-sprel.cgs sim/testsuite/sim/arm/thumb/str.cgs sim/testsuite/sim/arm/thumb/strb-imm.cgs sim/testsuite/sim/arm/thumb/strb.cgs sim/testsuite/sim/arm/thumb/strh-imm.cgs sim/testsuite/sim/arm/thumb/strh.cgs sim/testsuite/sim/arm/thumb/sub-sp.cgs sim/testsuite/sim/arm/thumb/sub.cgs sim/testsuite/sim/arm/thumb/subi.cgs sim/testsuite/sim/arm/thumb/subi8.cgs sim/testsuite/sim/arm/thumb/swi.cgs sim/testsuite/sim/arm/thumb/testutils.inc sim/testsuite/sim/arm/thumb/tst.cgs sim/testsuite/sim/arm/tst.cgs sim/testsuite/sim/arm/umlal.cgs sim/testsuite/sim/arm/umull.cgs sim/testsuite/sim/arm/xscale/blx.cgs sim/testsuite/sim/arm/xscale/mia.cgs sim/testsuite/sim/arm/xscale/miaph.cgs sim/testsuite/sim/arm/xscale/miaxy.cgs sim/testsuite/sim/arm/xscale/mra.cgs sim/testsuite/sim/arm/xscale/testutils.inc sim/testsuite/sim/arm/xscale/xscale.exp sim/testsuite/sim/h8300/ChangeLog sim/testsuite/sim/h8300/add.b.s sim/testsuite/sim/h8300/add.l.s sim/testsuite/sim/h8300/add.w.s sim/testsuite/sim/h8300/adds.s sim/testsuite/sim/h8300/addx.s sim/testsuite/sim/h8300/allinsn.exp sim/testsuite/sim/h8300/and.b.s sim/testsuite/sim/h8300/and.l.s sim/testsuite/sim/h8300/and.w.s sim/testsuite/sim/h8300/bfld.s sim/testsuite/sim/h8300/bra.s sim/testsuite/sim/h8300/brabc.s sim/testsuite/sim/h8300/bset.s sim/testsuite/sim/h8300/cmp.b.s sim/testsuite/sim/h8300/cmp.l.s sim/testsuite/sim/h8300/cmp.w.s sim/testsuite/sim/h8300/daa.s sim/testsuite/sim/h8300/das.s sim/testsuite/sim/h8300/dec.s sim/testsuite/sim/h8300/ext.l.s sim/testsuite/sim/h8300/ext.w.s sim/testsuite/sim/h8300/inc.s sim/testsuite/sim/h8300/jmp.s sim/testsuite/sim/h8300/ldc.s sim/testsuite/sim/h8300/mac.s sim/testsuite/sim/h8300/mov.b.s sim/testsuite/sim/h8300/mov.l.s sim/testsuite/sim/h8300/mov.w.s sim/testsuite/sim/h8300/movmd.s sim/testsuite/sim/h8300/movsd.s sim/testsuite/sim/h8300/neg.s sim/testsuite/sim/h8300/nop.s sim/testsuite/sim/h8300/not.s sim/testsuite/sim/h8300/or.b.s sim/testsuite/sim/h8300/or.l.s sim/testsuite/sim/h8300/or.w.s sim/testsuite/sim/h8300/rotl.s sim/testsuite/sim/h8300/rotr.s sim/testsuite/sim/h8300/rotxl.s sim/testsuite/sim/h8300/rotxr.s sim/testsuite/sim/h8300/shal.s sim/testsuite/sim/h8300/shar.s sim/testsuite/sim/h8300/shll.s sim/testsuite/sim/h8300/shlr.s sim/testsuite/sim/h8300/stc.s sim/testsuite/sim/h8300/sub.b.s sim/testsuite/sim/h8300/sub.l.s sim/testsuite/sim/h8300/sub.w.s sim/testsuite/sim/h8300/testutils.inc sim/testsuite/sim/h8300/xor.b.s sim/testsuite/sim/h8300/xor.l.s sim/testsuite/sim/h8300/xor.w.s

diff --git a/COPYING.LIBGLOSS b/COPYING.LIBGLOSS
deleted file mode 100644
index 741bc2f..0000000
--- a/COPYING.LIBGLOSS
+++ /dev/null

@@ -1,297 +0,0 @@
-The libgloss subdirectory is a collection of software from several sources.
-Each have their own copyrights embedded in each file that they concern.
-
-(1) University of California, Berkeley
-
-[1a]
-
-Copyright (c) 1990 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms are permitted
-provided that the above copyright notice and this paragraph are
-duplicated in all such forms and that any documentation,
-and other materials related to such distribution and use 
-acknowledge that the software was developed
-by the University of California, Berkeley.  The name of the
-University may not be used to endorse or promote products derived
-from this software without specific prior written permission.
-THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-
-[1b]
-
-Copyright (c) 1991, 2000 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. All advertising materials mentioning features or use of this software
-   must display the following acknowledgement:
-     This product includes software developed by the University of
-     California, Berkeley and its contributors.
-4. Neither the name of the University nor the names of its contributors
-   may be used to endorse or promote products derived from this software
-   without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
-
-[1c]
-
-Copyright (c) 1991, 1998, 2001 The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. [rescinded 22 July 1999]
-4. Neither the name of the University nor the names of its contributors
-   may be used to endorse or promote products derived from this software
-   without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
-
--------------------------------------------------------------
- Please note that in some of the above alternate licenses, there is a
- statement regarding that acknowledgement must be made in any
- advertising materials for products using the code.  This restriction
- no longer applies due to the following license change:
-
-  ftp://ftp.cs.berkeley.edu/pub/4bsd/README.Impt.License.Change
-
- In some cases the defunct clause has been removed in modified newlib code and
- in some cases, the clause has been left as-is.
--------------------------------------------------------------
-
-(2) DJ Delorie
-
-Copyright (C) 1993 DJ Delorie
-All rights reserved.
-
-Redistribution and use in source and binary forms is permitted
-provided that the above copyright notice and following paragraph are
-duplicated in all such forms.
-
-This file is distributed WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-
-(3) GPL (fr30 directory only)
-
-Copyright (C) 1998 Free Software Foundation, Inc.
-Contributed by Cygnus Solutions.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.
-
-(4) Advanced Micro Devices
-
-Copyright 1989, 1990 Advanced Micro Devices, Inc.
-
-This software is the property of Advanced Micro Devices, Inc  (AMD)  which
-specifically  grants the user the right to modify, use and distribute this
-software provided this notice is not removed or altered.  All other rights
-are reserved by AMD.
-
-AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
-SOFTWARE.  IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
-DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR
-USE OF THIS SOFTWARE.
-
-So that all may benefit from your experience, please report  any  problems
-or  suggestions about this software to the 29K Technical Support Center at
-800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131  in  the  UK,  or
-0031-11-1129 in Japan, toll free.  The direct dial number is 512-462-4118.
-
-Advanced Micro Devices, Inc.
-29K Support Products
-Mail Stop 573
-5900 E. Ben White Blvd.
-Austin, TX 78741
-800-292-9263
-
-(5) Array Technology Corporation and MIPS (mips/lsi33k-stub.h)
- 
-COPYRIGHT (C) 1991, 1992 ARRAY TECHNOLOGY CORPORATION
-              All Rights Reserved
-
-This software is confidential information which is proprietary to and
-a trade secret of ARRAY Technology Corporation.  Use, duplication, or
-disclosure is subject to the terms of a separate license agreement.
-
-Copyright 1985 by MIPS Computer Systems, Inc.
- 
-(6) University of Utah and the Computer Systems Laboratory (CSL)
-    [applies only to hppa*-*-pro* targets] 
-
-Copyright (c) 1990,1994 The University of Utah and
-the Computer Systems Laboratory (CSL).  All rights reserved.
-
-Permission to use, copy, modify and distribute this software is hereby
-granted provided that (1) source code retains these copyright, permission,
-and disclaimer notices, and (2) redistributions including binaries
-reproduce the notices in supporting documentation, and (3) all advertising
-materials mentioning features or use of this software display the following
-acknowledgement: ``This product includes software developed by the
-Computer Systems Laboratory at the University of Utah.''
-
-THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
-IS" CONDITION.  THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
-ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
-
-CSL requests users of this software to return to csl-dist@cs.utah.edu any
-improvements that they make and grant CSL redistribution rights.
-
-(7) Sun Microsystems
-
-Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
-
-Developed at SunPro, a Sun Microsystems, Inc. business.
-Permission to use, copy, modify, and distribute this
-software is freely granted, provided that this notice 
-is preserved.
-
-(8) Hewlett Packard
-
-(c) Copyright 1986 HEWLETT-PACKARD COMPANY
-
-To anyone who acknowledges that this file is provided "AS IS"
-without any express or implied warranty:
-    permission to use, copy, modify, and distribute this file
-for any purpose is hereby granted without fee, provided that
-the above copyright notice and this notice appears in all
-copies, and that the name of Hewlett-Packard Company not be
-used in advertising or publicity pertaining to distribution
-of the software without specific, written prior permission.
-Hewlett-Packard Company makes no representations about the
-suitability of this software for any purpose.
-
-(9) Hans-Peter Nilsson
-
-Copyright (C) 2001 Hans-Peter Nilsson
-
-Permission to use, copy, modify, and distribute this software is
-freely granted, provided that the above copyright notice, this notice
-and the following disclaimer are preserved with no changes.
-
-THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE.
-
-(10) No Copyright
-
-THIS SOFTWARE IS NOT COPYRIGHTED
-
-(11) Cygnus Support / Cygnus Solutions
-
-Copyright (c) 1995, 1996, 1997, 1998, 1999 Cygnus Support
-
-The authors hereby grant permission to use, copy, modify, distribute,
-and license this software and its documentation for any purpose, provided
-that existing copyright notices are retained in all copies and that this
-notice is included verbatim in any distributions. No written agreement,
-license, or royalty fee is required for any of the authorized uses.
-Modifications to this software may be copyrighted by their authors
-and need not follow the licensing terms described here, provided that
-the new terms are clearly indicated on the first page of each file where
-they apply.
-
----------------------------------------------------------------
- Please note that the copyright above may be used with the name
- Cygnus Solutions instead of Cygnus Support.  Both names should
- be considered interchangeable.  These copyrights are now owned
- by Red Hat Incorporated.
----------------------------------------------------------------
-
-(12) Red Hat Incorporated
-
-Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
-The authors hereby grant permission to use, copy, modify, distribute,
-and license this software and its documentation for any purpose, provided
-that existing copyright notices are retained in all copies and that this
-notice is included verbatim in any distributions. No written agreement,
-license, or royalty fee is required for any of the authorized uses.
-Modifications to this software may be copyrighted by their authors
-and need not follow the licensing terms described here, provided that
-the new terms are clearly indicated on the first page of each file where
-they apply.
-
-(13) Default copyright 
-
-Unless otherwise stated in each remaining libgloss file, the remaining
-files in the libgloss subdirectory are governed by the following copyright.
-
-Copyright (c) 1994, 1997, 2001, 2002 Red Hat Incorporated.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without 
-modification, are permitted provided that the following conditions are met: 
-
-    Redistributions of source code must retain the above copyright 
-    notice, this list of conditions and the following disclaimer.
-
-    Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
-
-    The name of Red Hat Incorporated may not be used to endorse 
-    or promote products derived from this software without specific 
-    prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 0cf4ea3..b9fb970 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog

@@ -1,29 +1,3 @@
-2003-05-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
-
-	* elf32-s390.c (allocate_dynrelocs, elf_s390_relocate_section):
-	Fix WILL_CALL_FINISH_DYNAMIC_SYMBOL call.
-	(WILL_CALL_FINISH_DYNAMIC_SYMBOL): Pass SHARED instead of INFO.
-	* elf64-s390.c: Likewise.
-
-2003-05-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
-
-	* elf32-s390.c (ELIMINATE_COPY_RELOCS): Define as one.
-	(elf_s390_adjust_dynamic_symbol): For weak symbols, copy
-	ELF_LINK_NON_GOT_REF from weakdef.
-	(elf_s390_copy_indirect_symbol): Test whether the weakdef sym has
-	already been adjusted before treating it specially.
-	* el64-s390.c: Likwise.
-
-2003-05-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
-
-	* elf32-s390.c (allocate_dynrelocs): For undef weak syms with
-	non-default visibility, a) don't make them dynamic, b) discard
-	space for dynamic relocs.
-	(elf_s390_relocate_section): Initialize the GOT entries and skip
-	R_390_{8,16,32}/R_390_PC{16,16DBL,32DBL,32} for weak undefined
-	symbols with non-default visibility.
-	* elf64-s390.c: Likewise.
-
 2003-05-09  Alan Modra  <amodra@bigpond.net.au>
 
 	* cpu-arm.c (arm_check_note): Warning fix.

diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
index 9475f60..857b7a0 100644
--- a/bfd/elf32-s390.c
+++ b/bfd/elf32-s390.c

@@ -383,12 +383,6 @@
 
 #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
 
-/* If ELIMINATE_COPY_RELOCS is non-zero, the linker will try to avoid
-   copying dynamic variables from a shared lib into an app's dynbss
-   section, and instead use a dynamic relocation to point into the
-   shared lib.  */
-#define ELIMINATE_COPY_RELOCS 1
-
 /* The size in bytes of the first entry in the procedure linkage table.  */
 #define PLT_FIRST_ENTRY_SIZE 32
 /* The size in bytes of an entry in the procedure linkage table.  */
@@ -834,18 +828,7 @@
       eind->tls_type = GOT_UNKNOWN;
     }
 
-  if (ELIMINATE_COPY_RELOCS
-      && ind->root.type != bfd_link_hash_indirect
-      && (dir->elf_link_hash_flags & ELF_LINK_HASH_DYNAMIC_ADJUSTED) != 0)
-    /* If called to transfer flags for a weakdef during processing
-       of elf_adjust_dynamic_symbol, don't copy ELF_LINK_NON_GOT_REF.
-       We clear it ourselves for ELIMINATE_COPY_RELOCS.  */
-    dir->elf_link_hash_flags |=
-      (ind->elf_link_hash_flags & (ELF_LINK_HASH_REF_DYNAMIC
-				   | ELF_LINK_HASH_REF_REGULAR
-				   | ELF_LINK_HASH_REF_REGULAR_NONWEAK));
-  else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
 }
 
 static int
@@ -1166,8 +1149,7 @@
 			   || h->root.type == bfd_link_hash_defweak
 			   || (h->elf_link_hash_flags
 			       & ELF_LINK_HASH_DEF_REGULAR) == 0))))
-	      || (ELIMINATE_COPY_RELOCS
-		  && !info->shared
+	      || (!info->shared
 		  && (sec->flags & SEC_ALLOC) != 0
 		  && h != NULL
 		  && (h->root.type == bfd_link_hash_defweak
@@ -1498,6 +1480,8 @@
      struct elf_link_hash_entry *h;
 {
   struct elf_s390_link_hash_table *htab;
+  struct elf_s390_link_hash_entry * eh;
+  struct elf_s390_dyn_relocs *p;
   asection *s;
   unsigned int power_of_two;
 
@@ -1543,10 +1527,6 @@
 		  || h->weakdef->root.type == bfd_link_hash_defweak);
       h->root.u.def.section = h->weakdef->root.u.def.section;
       h->root.u.def.value = h->weakdef->root.u.def.value;
-      if (ELIMINATE_COPY_RELOCS || info->nocopyreloc)
-	h->elf_link_hash_flags
-	  = ((h->elf_link_hash_flags & ~ELF_LINK_NON_GOT_REF)
-	     | (h->weakdef->elf_link_hash_flags & ELF_LINK_NON_GOT_REF));
       return TRUE;
     }
 
@@ -1572,26 +1552,20 @@
       return TRUE;
     }
 
-  if (ELIMINATE_COPY_RELOCS)
+  eh = (struct elf_s390_link_hash_entry *) h;
+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
     {
-      struct elf_s390_link_hash_entry * eh;
-      struct elf_s390_dyn_relocs *p;
+      s = p->sec->output_section;
+      if (s != NULL && (s->flags & SEC_READONLY) != 0)
+	break;
+    }
 
-      eh = (struct elf_s390_link_hash_entry *) h;
-      for (p = eh->dyn_relocs; p != NULL; p = p->next)
-	{
-	  s = p->sec->output_section;
-	  if (s != NULL && (s->flags & SEC_READONLY) != 0)
-	    break;
-	}
-
-      /* If we didn't find any dynamic relocs in read-only sections, then
-	 we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
-      if (p == NULL)
-	{
-	  h->elf_link_hash_flags &= ~ELF_LINK_NON_GOT_REF;
-	  return TRUE;
-	}
+  /* If we didn't find any dynamic relocs in read-only sections, then
+     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
+  if (p == NULL)
+    {
+      h->elf_link_hash_flags &= ~ELF_LINK_NON_GOT_REF;
+      return TRUE;
     }
 
   /* We must allocate the symbol in our .dynbss section, which will
@@ -1644,9 +1618,9 @@
    will be called from elflink.h.  If elflink.h doesn't call our
    finish_dynamic_symbol routine, we'll need to do something about
    initializing any .plt and .got entries in elf_s390_relocate_section.  */
-#define WILL_CALL_FINISH_DYNAMIC_SYMBOL(DYN, SHARED, H) \
+#define WILL_CALL_FINISH_DYNAMIC_SYMBOL(DYN, INFO, H) \
   ((DYN)								\
-   && ((SHARED)								\
+   && ((INFO)->shared							\
        || ((H)->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL) == 0)	\
    && ((H)->dynindx != -1						\
        || ((H)->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL) != 0))
@@ -1677,9 +1651,7 @@
   htab = elf_s390_hash_table (info);
 
   if (htab->elf.dynamic_sections_created
-      && h->plt.refcount > 0
-      && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-	  || h->root.type != bfd_link_hash_undefweak))
+      && h->plt.refcount > 0)
     {
       /* Make sure this symbol is output as a dynamic symbol.
 	 Undefined weak syms won't yet be marked as dynamic.  */
@@ -1690,8 +1662,7 @@
 	    return FALSE;
 	}
 
-      if (info->shared
-	  || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
+      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info, h))
 	{
 	  asection *s = htab->splt;
 
@@ -1787,10 +1758,7 @@
 	htab->srelgot->_raw_size += sizeof (Elf32_External_Rela);
       else if (tls_type == GOT_TLS_GD)
 	htab->srelgot->_raw_size += 2 * sizeof (Elf32_External_Rela);
-      else if ((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-		|| h->root.type != bfd_link_hash_undefweak)
-	       && (info->shared
-		   || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h)))
+      else if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info, h))
 	htab->srelgot->_raw_size += sizeof (Elf32_External_Rela);
     }
   else
@@ -1824,14 +1792,8 @@
 		pp = &p->next;
 	    }
 	}
-
-      /* Also discard relocs on undefined weak syms with non-default
-	 visibility.  */
-      if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
-	  && h->root.type == bfd_link_hash_undefweak)
-	eh->dyn_relocs = NULL;
     }
-  else if (ELIMINATE_COPY_RELOCS)
+  else
     {
       /* For the non-shared case, discard space for relocs against
 	 symbols which turn out to need copy relocs or are not
@@ -2339,14 +2301,12 @@
 
 	      off = h->got.offset;
 	      dyn = htab->elf.dynamic_sections_created;
-	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
+	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info, h)
 		  || (info->shared
 		      && (info->symbolic
 			  || h->dynindx == -1
 			  || (h->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL))
-		      && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR))
-		  || (ELF_ST_VISIBILITY (h->other)
-		      && h->root.type == bfd_link_hash_undefweak))
+		      && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)))
 		{
 		  /* This is actually a static link, or it is a
 		     -Bsymbolic link and the symbol is defined
@@ -2511,9 +2471,6 @@
 	    break;
 
 	  if ((info->shared
-	       && (h == NULL
-		   || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-		   || h->root.type != bfd_link_hash_undefweak)
 	       && ((r_type != R_390_PC16
 		    && r_type != R_390_PC16DBL
 		    && r_type != R_390_PC32DBL
@@ -2523,8 +2480,7 @@
 		       && (! info->symbolic
 			   || (h->elf_link_hash_flags
 			       & ELF_LINK_HASH_DEF_REGULAR) == 0))))
-	      || (ELIMINATE_COPY_RELOCS
-		  && !info->shared
+	      || (!info->shared
 		  && h != NULL
 		  && h->dynindx != -1
 		  && (h->elf_link_hash_flags & ELF_LINK_NON_GOT_REF) == 0

diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
index 98555f2..37fcf72 100644
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c

@@ -405,12 +405,6 @@
 
 #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
 
-/* If ELIMINATE_COPY_RELOCS is non-zero, the linker will try to avoid
-   copying dynamic variables from a shared lib into an app's dynbss
-   section, and instead use a dynamic relocation to point into the
-   shared lib.  */
-#define ELIMINATE_COPY_RELOCS 1
-
 /* The size in bytes of the first entry in the procedure linkage table.  */
 #define PLT_FIRST_ENTRY_SIZE 32
 /* The size in bytes of an entry in the procedure linkage table.  */
@@ -788,18 +782,7 @@
       eind->tls_type = GOT_UNKNOWN;
     }
 
-  if (ELIMINATE_COPY_RELOCS
-      && ind->root.type != bfd_link_hash_indirect
-      && (dir->elf_link_hash_flags & ELF_LINK_HASH_DYNAMIC_ADJUSTED) != 0)
-    /* If called to transfer flags for a weakdef during processing
-       of elf_adjust_dynamic_symbol, don't copy ELF_LINK_NON_GOT_REF.
-       We clear it ourselves for ELIMINATE_COPY_RELOCS.  */
-    dir->elf_link_hash_flags |=
-      (ind->elf_link_hash_flags & (ELF_LINK_HASH_REF_DYNAMIC
-				   | ELF_LINK_HASH_REF_REGULAR
-				   | ELF_LINK_HASH_REF_REGULAR_NONWEAK));
-  else
-    _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
+  _bfd_elf_link_hash_copy_indirect (bed, dir, ind);
 }
 
 static int
@@ -1131,8 +1114,7 @@
 			   || h->root.type == bfd_link_hash_defweak
 			   || (h->elf_link_hash_flags
 			       & ELF_LINK_HASH_DEF_REGULAR) == 0))))
-	      || (ELIMINATE_COPY_RELOCS
-		  && !info->shared
+	      || (!info->shared
 		  && (sec->flags & SEC_ALLOC) != 0
 		  && h != NULL
 		  && (h->root.type == bfd_link_hash_defweak
@@ -1470,6 +1452,8 @@
      struct elf_link_hash_entry *h;
 {
   struct elf_s390_link_hash_table *htab;
+  struct elf_s390_link_hash_entry * eh;
+  struct elf_s390_dyn_relocs *p;
   asection *s;
   unsigned int power_of_two;
 
@@ -1515,10 +1499,6 @@
 		  || h->weakdef->root.type == bfd_link_hash_defweak);
       h->root.u.def.section = h->weakdef->root.u.def.section;
       h->root.u.def.value = h->weakdef->root.u.def.value;
-      if (ELIMINATE_COPY_RELOCS || info->nocopyreloc)
-	h->elf_link_hash_flags
-	  = ((h->elf_link_hash_flags & ~ELF_LINK_NON_GOT_REF)
-	     | (h->weakdef->elf_link_hash_flags & ELF_LINK_NON_GOT_REF));
       return TRUE;
     }
 
@@ -1544,26 +1524,20 @@
       return TRUE;
     }
 
-  if (ELIMINATE_COPY_RELOCS)
+  eh = (struct elf_s390_link_hash_entry *) h;
+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
     {
-      struct elf_s390_link_hash_entry * eh;
-      struct elf_s390_dyn_relocs *p;
+      s = p->sec->output_section;
+      if (s != NULL && (s->flags & SEC_READONLY) != 0)
+	break;
+    }
 
-      eh = (struct elf_s390_link_hash_entry *) h;
-      for (p = eh->dyn_relocs; p != NULL; p = p->next)
-	{
-	  s = p->sec->output_section;
-	  if (s != NULL && (s->flags & SEC_READONLY) != 0)
-	    break;
-	}
-
-      /* If we didn't find any dynamic relocs in read-only sections, then
-	 we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
-      if (p == NULL)
-	{
-	  h->elf_link_hash_flags &= ~ELF_LINK_NON_GOT_REF;
-	  return TRUE;
-	}
+  /* If we didn't find any dynamic relocs in read-only sections, then
+     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
+  if (p == NULL)
+    {
+      h->elf_link_hash_flags &= ~ELF_LINK_NON_GOT_REF;
+      return TRUE;
     }
 
   /* We must allocate the symbol in our .dynbss section, which will
@@ -1616,9 +1590,9 @@
    will be called from elflink.h.  If elflink.h doesn't call our
    finish_dynamic_symbol routine, we'll need to do something about
    initializing any .plt and .got entries in elf_s390_relocate_section.  */
-#define WILL_CALL_FINISH_DYNAMIC_SYMBOL(DYN, SHARED, H) \
+#define WILL_CALL_FINISH_DYNAMIC_SYMBOL(DYN, INFO, H) \
   ((DYN)								\
-   && ((SHARED)								\
+   && ((INFO)->shared							\
        || ((H)->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL) == 0)	\
    && ((H)->dynindx != -1						\
        || ((H)->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL) != 0))
@@ -1649,9 +1623,7 @@
   htab = elf_s390_hash_table (info);
 
   if (htab->elf.dynamic_sections_created
-      && h->plt.refcount > 0
-      && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-	  || h->root.type != bfd_link_hash_undefweak))
+      && h->plt.refcount > 0)
     {
       /* Make sure this symbol is output as a dynamic symbol.
 	 Undefined weak syms won't yet be marked as dynamic.  */
@@ -1662,8 +1634,7 @@
 	    return FALSE;
 	}
 
-      if (info->shared
-	  || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
+      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info, h))
 	{
 	  asection *s = htab->splt;
 
@@ -1759,10 +1730,7 @@
 	htab->srelgot->_raw_size += sizeof (Elf64_External_Rela);
       else if (tls_type == GOT_TLS_GD)
 	htab->srelgot->_raw_size += 2 * sizeof (Elf64_External_Rela);
-      else if ((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-		|| h->root.type != bfd_link_hash_undefweak)
-	       && (info->shared
-		   || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h)))
+      else if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info, h))
 	htab->srelgot->_raw_size += sizeof (Elf64_External_Rela);
     }
   else
@@ -1796,14 +1764,8 @@
 		pp = &p->next;
 	    }
 	}
-
-      /* Also discard relocs on undefined weak syms with non-default
-	 visibility.  */
-      if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
-	  && h->root.type == bfd_link_hash_undefweak)
-	eh->dyn_relocs = NULL;
     }
-  else if (ELIMINATE_COPY_RELOCS)
+  else
     {
       /* For the non-shared case, discard space for relocs against
 	 symbols which turn out to need copy relocs or are not
@@ -2312,14 +2274,12 @@
 
 	      off = h->got.offset;
 	      dyn = htab->elf.dynamic_sections_created;
-	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, h)
+	      if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info, h)
 		  || (info->shared
 		      && (info->symbolic
 			  || h->dynindx == -1
 			  || (h->elf_link_hash_flags & ELF_LINK_FORCED_LOCAL))
-		      && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR))
-		  || (ELF_ST_VISIBILITY (h->other)
-		      && h->root.type == bfd_link_hash_undefweak))
+		      && (h->elf_link_hash_flags & ELF_LINK_HASH_DEF_REGULAR)))
 		{
 		  /* This is actually a static link, or it is a
 		     -Bsymbolic link and the symbol is defined
@@ -2489,9 +2449,6 @@
 	    break;
 
 	  if ((info->shared
-	       && (h == NULL
-		   || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-		   || h->root.type != bfd_link_hash_undefweak)
 	       && ((r_type != R_390_PC16
 		    && r_type != R_390_PC16DBL
 		    && r_type != R_390_PC32
@@ -2502,8 +2459,7 @@
 		       && (! info->symbolic
 			   || (h->elf_link_hash_flags
 			       & ELF_LINK_HASH_DEF_REGULAR) == 0))))
-	      || (ELIMINATE_COPY_RELOCS
-		  && !info->shared
+	      || (!info->shared
 		  && h != NULL
 		  && h->dynindx != -1
 		  && (h->elf_link_hash_flags & ELF_LINK_NON_GOT_REF) == 0

diff --git a/sim/testsuite/sim/arm/adc.cgs b/sim/testsuite/sim/arm/adc.cgs
deleted file mode 100644
index b6659a1..0000000
--- a/sim/testsuite/sim/arm/adc.cgs
+++ /dev/null

@@ -1,43 +0,0 @@
-# arm testcase for adc
-# mach: all
-
-# ??? Unfinished, more tests needed.
-
-	.include "testutils.inc"
-
-	start
-
-# adc$cond${set-cc?} $rd,$rn,$imm12
-
-	.global adc_imm
-adc_imm:
-	mvi_h_gr r4,1
-	mvi_h_cnvz 0,0,0,0
-	adc r5,r4,#1
-	test_h_cnvz 0,0,0,0
-	test_h_gr r5,2
-
-# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-
-	.global adc_reg_imm_shift
-adc_reg_imm_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_cnvz 0,0,0,0
-	adc r6,r4,r5,lsl #2
-	test_h_cnvz 0,0,0,0
-	test_h_gr r6,5
-
-# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-
-	.global adc_reg_reg_shift
-adc_reg_reg_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_gr r6,2
-	mvi_h_cnvz 0,0,0,0
-	adc r7,r4,r5,lsl r6
-	test_h_cnvz 0,0,0,0
-	test_h_gr r7,5
-
-	pass

diff --git a/sim/testsuite/sim/arm/add.cgs b/sim/testsuite/sim/arm/add.cgs
deleted file mode 100644
index eba32e0..0000000
--- a/sim/testsuite/sim/arm/add.cgs
+++ /dev/null

@@ -1,43 +0,0 @@
-# arm testcase for add
-# mach: all
-
-# ??? Unfinished, more tests needed.
-
-	.include "testutils.inc"
-
-	start
-
-# add$cond${set-cc?} $rd,$rn,$imm12
-
-	.global add_imm
-add_imm:
-	mvi_h_gr r4,1
-	mvi_h_cnvz 0,0,0,0
-	add r5,r4,#1
-	test_h_cnvz 0,0,0,0
-	test_h_gr r5,2
-
-# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-
-	.global add_reg_imm_shift
-add_reg_imm_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_cnvz 0,0,0,0
-	add r6,r4,r5,lsl #2
-	test_h_cnvz 0,0,0,0
-	test_h_gr r6,5
-
-# add$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-
-	.global add_reg_reg_shift
-add_reg_reg_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_gr r6,2
-	mvi_h_cnvz 0,0,0,0
-	add r7,r4,r5,lsl r6
-	test_h_cnvz 0,0,0,0
-	test_h_gr r7,5
-
-	pass

diff --git a/sim/testsuite/sim/arm/allinsn.exp b/sim/testsuite/sim/arm/allinsn.exp
deleted file mode 100644
index ec8402f..0000000
--- a/sim/testsuite/sim/arm/allinsn.exp
+++ /dev/null

@@ -1,28 +0,0 @@
-# ARM simulator testsuite.
-
-if { [istarget arm*-*-*] || [istarget xscale*-*-*] } {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "xscale"
-
-    if [is_remote host] {
-      remote_download host $srcdir/$subdir/testutils.inc
-    }
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-
-	run_sim_test $src $all_machs
-    }
-
-    if [is_remote host] {
-      remote_file host delete testutils.inc
-    }
-}

diff --git a/sim/testsuite/sim/arm/and.cgs b/sim/testsuite/sim/arm/and.cgs
deleted file mode 100644
index cd8f003..0000000
--- a/sim/testsuite/sim/arm/and.cgs
+++ /dev/null

@@ -1,43 +0,0 @@
-# arm testcase for and
-# mach: all
-
-# ??? Unfinished, more tests needed.
-
-	.include "testutils.inc"
-
-	start
-
-# and$cond${set-cc?} $rd,$rn,$imm12
-
-	.global and_imm
-and_imm:
-	mvi_h_gr r4,1
-	mvi_h_cnvz 0,0,0,0
-	and r5,r4,#1
-	test_h_cnvz 0,0,0,0
-	test_h_gr r5,1
-
-# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-
-	.global and_reg_imm_shift
-and_reg_imm_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_cnvz 0,0,0,0
-	and r6,r4,r5,lsl #1
-	test_h_cnvz 0,0,0,0
-	test_h_gr r6,0
-
-# and$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-
-	.global and_reg_reg_shift
-and_reg_reg_shift:
-	mvi_h_gr r4,1
-	mvi_h_gr r5,1
-	mvi_h_gr r6,1
-	mvi_h_cnvz 0,0,0,0
-	and r7,r4,r5,lsl r6
-	test_h_cnvz 0,0,0,0
-	test_h_gr r7,0
-
-	pass

diff --git a/sim/testsuite/sim/arm/b.cgs b/sim/testsuite/sim/arm/b.cgs
deleted file mode 100644
index 414b963..0000000
--- a/sim/testsuite/sim/arm/b.cgs
+++ /dev/null

@@ -1,261 +0,0 @@
-# arm testcase for b$cond $offset24
-# mach: all
-
-# ??? Still need to test edge cases.
-
-	.include "testutils.inc"
-
-	start
-
-	.global b
-b:
-
-# b foo
-
-	b balways1
-	fail
-balways1:
-
-# beq foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,4
-	cmp r4,r5
-	beq beq1
-	fail
-beq1:
-	mvi_h_gr r5,5
-	cmp r4,r5
-	beq beq2
-	b beq3
-beq2:
-	fail
-beq3:
-
-# bne foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,5
-	cmp r4,r5
-	bne bne1
-	fail
-bne1:
-	mvi_h_gr r5,4
-	cmp r4,r5
-	bne bne2
-	b bne3
-bne2:
-	fail
-bne3:
-
-# bcs foo
-
-	mvi_h_cnvz 1,0,0,0
-	bcs bcs1
-	fail
-bcs1:
-	mvi_h_cnvz 0,0,0,0
-	bcs bcs2
-	b bcs3
-bcs2:
-	fail
-bcs3:
-
-# bcc foo
-
-	mvi_h_cnvz 0,0,0,0
-	bcc bcc1
-	fail
-bcc1:
-	mvi_h_cnvz 1,0,0,0
-	bcc bcc2
-	b bcc3
-bcc2:
-	fail
-bcc3:
-
-# bmi foo
-
-	mvi_h_cnvz 0,1,0,0
-	bmi bmi1
-	fail
-bmi1:
-	mvi_h_cnvz 0,0,0,0
-	bmi bmi2
-	b bmi3
-bmi2:
-	fail
-bmi3:
-
-# bpl foo
-
-	mvi_h_cnvz 0,0,0,0
-	bpl bpl1
-	fail
-bpl1:
-	mvi_h_cnvz 0,1,0,0
-	bpl bpl2
-	b bpl3
-bpl2:
-	fail
-bpl3:
-
-# bvs foo
-
-	mvi_h_cnvz 0,0,1,0
-	bvs bvs1
-	fail
-bvs1:
-	mvi_h_cnvz 0,0,0,0
-	bvs bvs2
-	b bvs3
-bvs2:
-	fail
-bvs3:
-
-# bvc foo
-
-	mvi_h_cnvz 0,0,0,0
-	bvc bvc1
-	fail
-bvc1:
-	mvi_h_cnvz 0,0,1,0
-	bvc bvc2
-	b bvc3
-bvc2:
-	fail
-bvc3:
-
-# bhi foo
-
-	mvi_h_gr r4,5
-	mvi_h_gr r5,4
-	cmp r4,r5
-	bhi bhi1
-	fail
-bhi1:
-	mvi_h_gr r5,5
-	cmp r4,r5
-	bhi bhi2
-	b bhi3
-bhi2:
-	fail
-bhi3:
-	mvi_h_gr r5,6
-	cmp r4,r5
-	bhi bhi4
-	b bhi5
-bhi4:
-	fail
-bhi5:
-
-# bls foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,5
-	cmp r4,r5
-	bls bls1
-	fail
-bls1:
-	mvi_h_gr r5,4
-	cmp r4,r5
-	bls bls2
-	fail
-bls2:
-	mvi_h_gr r5,3
-	cmp r4,r5
-	bls bls3
-	b bls4
-bls3:
-	fail
-bls4:
-
-# bge foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,4
-	cmp r4,r5
-	bge bge1
-	fail
-bge1:
-	mvi_h_gr r5,3
-	cmp r4,r5
-	bge bge2
-	fail
-bge2:
-	mvi_h_gr r5,5
-	cmp r4,r5
-	bge bge3
-	b bge4
-bge3:
-	fail
-bge4:
-
-# blt foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,5
-	cmp r4,r5
-	blt blt1
-	fail
-blt1:
-	mvi_h_gr r5,4
-	cmp r4,r5
-	blt blt2
-	b blt3
-blt2:
-	fail
-blt3:
-	mvi_h_gr r5,3
-	cmp r4,r5
-	blt blt4
-	b blt5
-blt4:
-	fail
-blt5:
-
-# bgt foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,3
-	cmp r4,r5
-	bgt bgt1
-	fail
-bgt1:
-	mvi_h_gr r5,4
-	cmp r4,r5
-	bgt bgt2
-	b bgt3
-bgt2:
-	fail
-bgt3:
-	mvi_h_gr r5,5
-	cmp r4,r5
-	bgt bgt4
-	b bgt5
-bgt4:
-	fail
-bgt5:
-
-# ble foo
-
-	mvi_h_gr r4,4
-	mvi_h_gr r5,4
-	cmp r4,r5
-	ble ble1
-	fail
-ble1:
-	mvi_h_gr r5,5
-	cmp r4,r5
-	ble ble2
-	fail
-ble2:
-	mvi_h_gr r5,3
-	cmp r4,r5
-	ble ble3
-	b ble4
-ble3:
-	fail
-ble4:
-
-	pass

diff --git a/sim/testsuite/sim/arm/bic.cgs b/sim/testsuite/sim/arm/bic.cgs
deleted file mode 100644
index 37a9b6c..0000000
--- a/sim/testsuite/sim/arm/bic.cgs
+++ /dev/null

@@ -1,43 +0,0 @@
-# arm testcase for bic
-# mach: all
-
-# ??? Unfinished, more tests needed.
-
-	.include "testutils.inc"
-
-	start
-
-# bic$cond${set-cc?} $rd,$rn,$imm12
-
-	.global bic_imm
-bic_imm:
-	mvi_h_gr r4,1
-	mvi_h_cnvz 0,0,0,0
-	bic r5,r4,#0
-	test_h_cnvz 0,0,0,0
-	test_h_gr r5,1
-
-# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftimm}
-
-	.global bic_reg_imm_shift
-bic_reg_imm_shift:
-	mvi_h_gr r4,7
-	mvi_h_gr r5,1
-	mvi_h_cnvz 0,0,0,0
-	bic r6,r4,r5,lsl #1
-	test_h_cnvz 0,0,0,0
-	test_h_gr r6,5
-
-# bic$cond${set-cc?} $rd,$rn,$rm,${operbic2-shifttype} ${operbic2-shiftreg}
-
-	.global bic_reg_reg_shift
-bic_reg_reg_shift:
-	mvi_h_gr r4,7
-	mvi_h_gr r5,1
-	mvi_h_gr r6,1
-	mvi_h_cnvz 0,0,0,0
-	bic r7,r4,r5,lsl r6
-	test_h_cnvz 0,0,0,0
-	test_h_gr r7,5
-
-	pass

diff --git a/sim/testsuite/sim/arm/bl.cgs b/sim/testsuite/sim/arm/bl.cgs
deleted file mode 100644
index fbc7ef5..0000000
--- a/sim/testsuite/sim/arm/bl.cgs
+++ /dev/null

@@ -1,21 +0,0 @@
-# arm testcase for bl$cond $offset24
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-	.global bl
-bl:
-	mvi_h_gr r14,0
-	bl bl2
-bl1:
-	fail
-bl2:
-	mvaddr_h_gr r4,bl1
-	cmp r14,r4
-	beq bl3
-	fail
-bl3:
-
-	pass

diff --git a/sim/testsuite/sim/arm/bx.cgs b/sim/testsuite/sim/arm/bx.cgs
deleted file mode 100644
index 4c18af4..0000000
--- a/sim/testsuite/sim/arm/bx.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bx$cond $rn
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bx
-bx:
-	bx0 pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/cmn.cgs b/sim/testsuite/sim/arm/cmn.cgs
deleted file mode 100644
index 1829fc7..0000000
--- a/sim/testsuite/sim/arm/cmn.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for cmn${cond}${set-cc?} $rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmn_imm
-cmn_imm:
-	cmn00 pc,0
-
-	pass
-# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmn_reg_imm_shift
-cmn_reg_imm_shift:
-	cmn00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for cmn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmn_reg_reg_shift
-cmn_reg_reg_shift:
-	cmn00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/cmp.cgs b/sim/testsuite/sim/arm/cmp.cgs
deleted file mode 100644
index ab9dd59..0000000
--- a/sim/testsuite/sim/arm/cmp.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for cmp${cond}${set-cc?} $rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_imm
-cmp_imm:
-	cmp00 pc,0
-
-	pass
-# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_reg_imm_shift
-cmp_reg_imm_shift:
-	cmp00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for cmp$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_reg_reg_shift
-cmp_reg_reg_shift:
-	cmp00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/eor.cgs b/sim/testsuite/sim/arm/eor.cgs
deleted file mode 100644
index 5bbb1c6..0000000
--- a/sim/testsuite/sim/arm/eor.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for eor$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global eor_imm
-eor_imm:
-	eor00 pc,pc,0
-
-	pass
-# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global eor_reg_imm_shift
-eor_reg_imm_shift:
-	eor00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for eor$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global eor_reg_reg_shift
-eor_reg_reg_shift:
-	eor00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/hello.ms b/sim/testsuite/sim/arm/hello.ms
deleted file mode 100644
index b063c29..0000000
--- a/sim/testsuite/sim/arm/hello.ms
+++ /dev/null

@@ -1,91 +0,0 @@
-# output(): Hello, world.\n
-# mach(): all
-
-# Emit hello world while switching back and forth between arm/thumb.
-# ??? Unfinished
-
-	.macro invalid
-# This is "undefined" but it's not properly decoded yet.
-	.word 0x07ffffff
-# This is stc which isn't recognized yet.
-	stc 0,cr0,[r0]
-	.endm
-
-	.global _start
-_start:
-# Run some simple insns to confirm the engine is at least working.
-	nop
-
-# Skip over output text.
-
-	bl skip_output
-
-hello_text:
-	.asciz "Hello, world.\n"
-
-	.p2align 2
-skip_output:
-
-# Prime loop.
-
-	mov r4, r14
-
-output_next:
-
-# Switch arm->thumb to output next chacter.
-# At this point r4 must point to the next character to output.
-
-	adr r0, into_thumb + 1
-	bx r0
-
-into_thumb:
-	.thumb
-
-# Output a character.
-
-	mov r0,#3 @ writec angel call
-	mov r1,r4
-	swi 0xab @ ??? Confirm number.
-
-# Switch thumb->arm.
-
-	adr r5, back_to_arm
-	bx r5
-
-	.p2align 2
-back_to_arm:
-	.arm
-
-# Load next character, see if done.
-
-	add r4,r4,#1
-	sub r3,r3,r3
-	ldrb r5,[r4,r3]
-	teq r5,#0
-	beq done
-
-# Output a character (in arm mode).
-
-	mov r0,#3
-	mov r1,r4
-	swi #0x123456
-
-# Load next character, see if done.
-
-	add r4,r4,#1
-	sub r3,r3,r3
-	ldrb r5,[r4,r3]
-	teq r5,#0
-	bne output_next
-
-done:
-	mov r0,#0x18
-	ldr r1,exit_code
-	swi #0x123456
-
-# If that fails, try to die with an invalid insn.
-
-	invalid
-
-exit_code:
-	.word 0x20026

diff --git a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp b/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp
deleted file mode 100644
index f3d0f0a..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp
+++ /dev/null

@@ -1,28 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology simulator testsuite.
-
-if { [istarget xscale*-*-*] } {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "xscale"
-
-    if [is_remote host] {
-      remote_download host $srcdir/$subdir/testutils.inc
-    }
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-
-	run_sim_test $src $all_machs
-    }
-
-    if [is_remote host] {
-      remote_file host delete testutils.inc
-    }
-}

diff --git a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs b/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs
deleted file mode 100644
index b7138df..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tbcst.cgs
+++ /dev/null

@@ -1,65 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TBCST
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tbcst
-tbcst:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte Wide Broadcast
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tbcstb     wr0, r2
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0xffffffff
-	test_h_gr  r1, 0xffffffff
-	test_h_gr  r2, 0x111111ff
-	
-	# Test Half Word Wide Broadcast
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tbcsth     wr0, r2
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x11ff11ff
-	test_h_gr  r1, 0x11ff11ff
-	test_h_gr  r2, 0x111111ff
-	
-	# Test Word Wide Broadcast
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tbcstw     wr0, r2
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x111111ff
-	test_h_gr  r1, 0x111111ff
-	test_h_gr  r2, 0x111111ff
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/testutils.inc b/sim/testsuite/sim/arm/iwmmxt/testutils.inc
deleted file mode 100644
index ae49db8..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/testutils.inc
+++ /dev/null

@@ -1,118 +0,0 @@
-# r0-r3 are used as tmps, consider them call clobbered by these macros.
-# This uses the angel rom monitor calls.
-# ??? How do we use the \@ facility of .macros ???
-# @ is the comment char!
-
-	.macro mvi_h_gr reg, val
-	ldr \reg,[pc]
-	b . + 8
-	.word \val
-	.endm
-
-	.macro mvaddr_h_gr reg, addr
-	ldr \reg,[pc]
-	b . + 8
-	.word \addr
-	.endm
-
-	.macro start
-	.data
-failmsg:
-	.asciz "fail\n"
-passmsg:
-	.asciz "pass\n"
-	.text
-
-do_pass:
-	ldr r1, passmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 0
-passmsg_addr:
-	.word passmsg
-
-do_fail:
-	ldr r1, failmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 1
-failmsg_addr:
-	.word failmsg
-
-	.global _start
-_start:
-	.endm
-
-# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
-
-	.macro pass
-	b do_pass
-	.endm
-
-	.macro fail
-	b do_fail
-	.endm
-
-	.macro exit rc
-	# ??? This works with the ARMulator but maybe not others.
-	#mov r0, #\rc
-	#swi #1
-	# This seems to be portable (though it ignores rc).
-	mov r0,#0x18
-	mvi_h_gr r1, 0x20026
-	swi #0x123456
-	# If that returns, punt with a sigill.
-	stc 0,cr0,[r0]
-	.endm
-
-# Other macros know this only clobbers r0.
-# WARNING: It also clobbers the condition codes (FIXME).
-	.macro test_h_gr reg, val
-	mvaddr_h_gr r0, \val
-	cmp \reg, r0
-	beq . + 8
-	fail
-	.endm
-
-	.macro mvi_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	bic r1, r1, #0xf0000000
-	orr r1, r1, r0
-	msr cpsr, r1
-	# ??? nops needed
-	.endm
-
-# ??? Preserve condition codes?
-	.macro test_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	and r1, r1, #0xf0000000
-	cmp r0, r1
-	beq . + 8
-	fail
-	.endm

diff --git a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs b/sim/testsuite/sim/arm/iwmmxt/textrm.cgs
deleted file mode 100644
index fb3dc94..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/textrm.cgs
+++ /dev/null

@@ -1,113 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TEXTRM
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global textrm
-textrm:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmub   r2, wr0, #3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00000012
-	
-	# Test Signed Byte Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmsb   r2, wr0, #4
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0xfffffff0
-	
-	# Test Unsigned Half Word Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmuh   r2, wr0, #3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00009abc
-	
-	# Test Signed Half Word Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmsh   r2, wr0, #1
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00001234
-	
-	# Test Unsigned Word Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmuw   r2, wr0, #0
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x12345678
-	
-	# Test Signed Word Wide Extraction
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	textrmsw   r2, wr0, #1
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x9abcdef0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs b/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs
deleted file mode 100644
index f457b19..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tinsr.cgs
+++ /dev/null

@@ -1,65 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TINSR
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tinsr
-tinsr:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte Wide Insertion
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tinsrb	   wr0, r2, #3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0xff345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x111111ff
-	
-	# Test Half Word Wide Insertion
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tinsrh	   wr0, r2, #2
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abc11ff
-	test_h_gr  r2, 0x111111ff
-	
-	# Test Word Wide Insertion
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x111111ff
-
-	tmcrr	   wr0, r0, r1
-
-	tinsrw	   wr0, r2, #1
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x111111ff
-	test_h_gr  r2, 0x111111ff
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs b/sim/testsuite/sim/arm/iwmmxt/tmia.cgs
deleted file mode 100644
index 0b0da66..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tmia.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TMIA
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tmia
-tmia:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmia	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x354f53c4
-	test_h_gr  r1, 0x4e330b5e
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs
deleted file mode 100644
index 3778b0a..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tmiaph
-tmiaph:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmiaph	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0xfec3f9f4
-	test_h_gr  r1, 0x55667787
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs b/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs
deleted file mode 100644
index e7a7b73..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs
+++ /dev/null

@@ -1,89 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TMIAxy
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tmiaXY
-tmiaXY:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Bottom Bottom Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmiaBB	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x05f753c4
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Bottom Top Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmiaBT	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0xeeede364
-	test_h_gr  r1, 0x55667787
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Top Bottom Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmiaTB	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x0ec85c04
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Top Top Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	tmiaTT	   wr0, r2, r3
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x09eed974
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs b/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs
deleted file mode 100644
index cfea5b7..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs
+++ /dev/null

@@ -1,65 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for TMOVMSK
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global tmovmsk
-tmovmsk:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte Wide Mask Transfer
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-
-	tmcrr	   wr0, r0, r1
-
-	tmovmskb   r2, wr0
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x000000f0
-
-	# Test Half Word Wide Mask Transfer
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-
-	tmcrr	   wr0, r0, r1
-
-	tmovmskh   r2, wr0
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x0000000c
-
-	# Test Word Wide Mask Transfer
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-
-	tmcrr	   wr0, r0, r1
-
-	tmovmskw   r2, wr0
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00000002
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs b/sim/testsuite/sim/arm/iwmmxt/wacc.cgs
deleted file mode 100644
index b3ffea1..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wacc.cgs
+++ /dev/null

@@ -1,77 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WACC
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wacc
-wacc:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Wide Accumulation
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	waccb	   wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00000438
-	test_h_gr  r3, 0x00000000
-
-	# Test Unsigned Half Word Wide Accumulation
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wacch	   wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x0001e258
-	test_h_gr  r3, 0x00000000
-
-	# Test Unsigned Word Wide Accumulation
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	waccw	   wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0xacf13568
-	test_h_gr  r3, 0x00000000
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wadd.cgs
deleted file mode 100644
index bb4d0ab..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wadd.cgs
+++ /dev/null

@@ -1,251 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WADD
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wadd
-wadd:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test UnSaturated Byte Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddb      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Unsigned Saturated Byte Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddbus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Signed Saturated Byte Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddbss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x2345677f
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test UnSaturated Halfword Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddh      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Unsigned Saturated Halfword Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddhus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Signed Saturated Halfword Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddhss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test UnSaturated Word Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddw      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Unsigned Saturated Word Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddwus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	# Test Signed Saturated Word Addition
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waddwss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456789
-	test_h_gr  r5, 0xabcdef11
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs b/sim/testsuite/sim/arm/iwmmxt/waligni.cgs
deleted file mode 100644
index dc99dae..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/waligni.cgs
+++ /dev/null

@@ -1,43 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WALIGNI
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global waligni
-waligni:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test 2 byte align
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	waligni    wr2, wr0, wr1, #2
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0xdef01234
-	test_h_gr  r5, 0x11119abc
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs b/sim/testsuite/sim/arm/iwmmxt/walignr.cgs
deleted file mode 100644
index 85df51e..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/walignr.cgs
+++ /dev/null

@@ -1,137 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global walignr
-walignr:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test 0 byte align
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-	mvi_h_gr   r6, 3
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-	tmcr	   wcgr0, r6
-
-	walignr0   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	tmrc	   r6, wcgr0
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0xbcdef012
-	test_h_gr  r5, 0x1111119a
-	test_h_gr  r6, 3
-
-	# Test 1 byte align
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-	mvi_h_gr   r6, 4
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-	tmcr	   wcgr1, r6
-
-	walignr1   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	tmrc	   r6, wcgr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x9abcdef0
-	test_h_gr  r5, 0x11111111
-	test_h_gr  r6, 4
-
-	# Test 2 byte align
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-	mvi_h_gr   r6, 2
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-	tmcr	   wcgr2, r6
-
-	walignr2   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	tmrc	   r6, wcgr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0xdef01234
-	test_h_gr  r5, 0x11119abc
-	test_h_gr  r6, 2
-
-	# Test 3 byte align
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-	mvi_h_gr   r6, 5
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-	tmcr	   wcgr3, r6
-
-	walignr3   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	tmrc	   r6, wcgr3
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x119abcde
-	test_h_gr  r5, 0x00111111
-	test_h_gr  r6, 5
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wand.cgs b/sim/testsuite/sim/arm/iwmmxt/wand.cgs
deleted file mode 100644
index 018383f..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wand.cgs
+++ /dev/null

@@ -1,41 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WAND
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wand
-wand:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wand	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x10101010
-	test_h_gr  r5, 0x00000000
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs b/sim/testsuite/sim/arm/iwmmxt/wandn.cgs
deleted file mode 100644
index f2c2305..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wandn.cgs
+++ /dev/null

@@ -1,41 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WANDN
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wandn
-wandn:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wandn	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x02244668
-	test_h_gr  r5, 0x9abcdef0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs b/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs
deleted file mode 100644
index cac2c1a..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wavg2.cgs
+++ /dev/null

@@ -1,121 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WAVG2
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wavg2
-wavg2:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte Wide Averaging
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wavg2b     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x11223344
-	test_h_gr  r5, 0x5e6f8089
-	
-	# Test Byte Wide Averaging with Rounding
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wavg2br    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x12233445
-	test_h_gr  r5, 0x5e6f8089
-	
-	# Test Half Word Wide Averaging
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wavg2h     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x11a233c4
-	test_h_gr  r5, 0x5e6f8089
-	
-	# Test Half Word Wide Averaging with Rounding
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wavg2hr    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x11a333c5
-	test_h_gr  r5, 0x5e6f8089
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs
deleted file mode 100644
index 13ef3dc..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs
+++ /dev/null

@@ -1,95 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WCMPEQ
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wcmpeq
-wcmpeq:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte Wide Compare Equal To
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x9abcde00
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpeqb    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x9abcde00
-	test_h_gr  r4, 0x00000000
-	test_h_gr  r5, 0xffffffff
-	
-	# Test Half Word Wide Compare Equal To
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x9abcde00
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpeqh    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x9abcde00
-	test_h_gr  r4, 0x00000000
-	test_h_gr  r5, 0xffffffff
-	
-	# Test Word Wide Compare Equal To
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x9abcde00
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpeqw    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x9abcde00
-	test_h_gr  r4, 0x00000000
-	test_h_gr  r5, 0xffffffff
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs b/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs
deleted file mode 100644
index 33086c9..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs
+++ /dev/null

@@ -1,173 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WCMPGT
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wcmpgt
-wcmpgt:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtub   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0xffffff00
-	
-	# Test Signed Byte Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtsb   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0x00000000
-	
-	# Test Unsigned Half Word Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtuh   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0xffffffff
-	
-	# Test Signed Half Word Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtsh   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0x00000000
-	
-	# Test Unsigned Word Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtuw   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0xffffffff
-	
-	# Test Signed Word Wide Compare Greater Than
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wcmpgtsw   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xffffffff
-	test_h_gr  r5, 0x00000000
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs b/sim/testsuite/sim/arm/iwmmxt/wmac.cgs
deleted file mode 100644
index 0857ef9..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmac.cgs
+++ /dev/null

@@ -1,121 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMAC
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmac
-wmac:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned, Multiply Accumulate, Non-zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x33333333
-	mvi_h_gr   r5, 0x44444444
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmacu	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x6c889377
-	test_h_gr  r5, 0x44444444
-				
-	# Test Unsigned, Multiply Accumulate, Zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x33333333
-	mvi_h_gr   r5, 0x44444444
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmacuz	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x39556044
-	test_h_gr  r5, 0x00000000
-				
-	# Test Signed, Multiply Accumulate, Non-zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x33333333
-	mvi_h_gr   r5, 0x44444444
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmacs	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x28449377
-	test_h_gr  r5, 0x44444444
-				
-	# Test Signed, Multiply Accumulate, Zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x33333333
-	mvi_h_gr   r5, 0x44444444
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmacsz	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xf5116044
-	test_h_gr  r5, 0xffffffff
-				
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs b/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs
deleted file mode 100644
index 564b3be..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmadd.cgs
+++ /dev/null

@@ -1,69 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMADD
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmadd
-wmadd:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned, Multiply Addition
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaddu	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x06fa5f6c
-	test_h_gr  r5, 0x325b00d8
-		
-	# Test Signed, Multiply Addition
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmadds	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x06fa5f6c
-	test_h_gr  r5, 0xee1700d8
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs b/sim/testsuite/sim/arm/iwmmxt/wmax.cgs
deleted file mode 100644
index 3a684ce..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmax.cgs
+++ /dev/null

@@ -1,173 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMAX
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmax
-wmax:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxub     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x9abcde11
-
-	# Test Signed Byte Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxsb     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x11111111
-
-	# Test Unsigned Halfword Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxuh     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x9abcde00
-
-	# Test Signed Halfword Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxsh     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x11111111
-
-	# Test Unsigned Word Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxuw     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x9abcde00
-
-	# Test Signed Word Maximum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmaxsw     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x11111111
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs b/sim/testsuite/sim/arm/iwmmxt/wmin.cgs
deleted file mode 100644
index 3bc1c08..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmin.cgs
+++ /dev/null

@@ -1,173 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMIN
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmin
-wmin:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminub     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x11111100
-
-	# Test Signed Byte Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminsb     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x9abcde00
-
-	# Test Unsigned Halfword Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminuh     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x11111111
-
-	# Test Signed Halfword Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminsh     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x9abcde00
-
-	# Test Unsigned Word Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminuw     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x11111111
-
-	# Test Signed Word Minimum
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wminsw     wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x11111111
-	test_h_gr  r5, 0x9abcde00
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs b/sim/testsuite/sim/arm/iwmmxt/wmov.cgs
deleted file mode 100644
index e86fed6..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmov.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMOV
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmov
-wmov:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wmov	   wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs b/sim/testsuite/sim/arm/iwmmxt/wmul.cgs
deleted file mode 100644
index 0978b63..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wmul.cgs
+++ /dev/null

@@ -1,121 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WMUL
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wmul
-wmul:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned, Most Significant Multiply
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmulum	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x013605c3
-	test_h_gr  r5, 0x14a11db9
-		
-	# Test Unsigned, Least Significant Multiply
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmulul	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xa974b5f8
-	test_h_gr  r5, 0x84f87be0
-		
-	# Test Signed, Most Significant Multiply
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmulsm	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x013605c3
-	test_h_gr  r5, 0xf27ffb97
-		
-	# Test Signed, Least Significant Multiply
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wmulsl	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0xa974b5f8
-	test_h_gr  r5, 0x84f87be0
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wor.cgs b/sim/testsuite/sim/arm/iwmmxt/wor.cgs
deleted file mode 100644
index 48d5f53..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wor.cgs
+++ /dev/null

@@ -1,41 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WOR
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wor
-wor:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wor	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x13355779
-	test_h_gr  r5, 0x9abcdef0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs b/sim/testsuite/sim/arm/iwmmxt/wpack.cgs
deleted file mode 100644
index 0546bd4..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wpack.cgs
+++ /dev/null

@@ -1,173 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WPACK
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wpack
-wpack:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Halfword, Unsigned Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackhus   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x0000ffff
-	test_h_gr  r5, 0x0000ffff  
-		
-	# Test Halfword, Signed Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackhss   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x80807f7f
-	test_h_gr  r5, 0x00007f7f  
-		
-	# Test Word, Unsigned Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackwus   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x0000ffff
-	test_h_gr  r5, 0x0000ffff  
-		
-	# Test Word, Signed Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackwss   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x80007fff
-	test_h_gr  r5, 0x00007fff  
-		
-	# Test Double Word, Unsigned Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackdus   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x00000000
-	test_h_gr  r5, 0x11111111
-		
-	# Test Double Word, Signed Saturation, Packing
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wpackdss   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x80000000
-	test_h_gr  r5, 0x11111111  
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wror.cgs b/sim/testsuite/sim/arm/iwmmxt/wror.cgs
deleted file mode 100644
index e329916..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wror.cgs
+++ /dev/null

@@ -1,167 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WROR
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wror
-wror:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Halfword wide rotate right by register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wrorh	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x091a2b3c
-	test_h_gr  r5, 0x4d5e6f78
-	
-	# Test Halfword wide rotate right by CG register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcr	   wcgr0, r2
-	tmcrr	   wr1, r2, r3
-
-	wrorhg	   wr1, wr0, wcgr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr0
-	tmrrc	   r3, r4, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x091a2b3c
-	test_h_gr  r4, 0x4d5e6f78
-	
-	# Test Word wide rotate right by register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wrorw	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x2b3c091a
-	test_h_gr  r5, 0x6f784d5e
-	
-	# Test Word wide rotate right by CG register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcr	   wcgr0, r2
-	tmcrr	   wr1, r2, r3
-
-	wrorwg	   wr1, wr0, wcgr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr0
-	tmrrc	   r3, r4, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x2b3c091a
-	test_h_gr  r4, 0x6f784d5e
-	
-	# Test Double Word wide rotate right by register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wrord	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x6f78091a
-	test_h_gr  r5, 0x2b3c4d5e
-	
-	# Test Double Word wide rotate right by CG register
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcr	   wcgr0, r2
-	tmcrr	   wr1, r2, r3
-
-	wrordg	   wr1, wr0, wcgr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr0
-	tmrrc	   r3, r4, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x6f78091a
-	test_h_gr  r4, 0x2b3c4d5e
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs b/sim/testsuite/sim/arm/iwmmxt/wsad.cgs
deleted file mode 100644
index 34a20cc..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wsad.cgs
+++ /dev/null

@@ -1,121 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSAD
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wsad
-wsad:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte wide absolute accumulation
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x22222222
-	mvi_h_gr   r5, 0x22222222
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsadb	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x2222258e
-	test_h_gr  r5, 0x00000000
-	
-	# Test Byte wide absolute accumulation with zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x22222222
-	mvi_h_gr   r5, 0x22222222
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsadbz	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x0000036c
-	test_h_gr  r5, 0x00000000
-	
-	# Test Halfword wide absolute accumulation
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x22222222
-	mvi_h_gr   r5, 0x22222222
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsadh	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x22239e14
-	test_h_gr  r5, 0x00000000
-	
-	# Test Halfword wide absolute accumulation with zeroing
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x22222222
-	mvi_h_gr   r4, 0x22222222
-	mvi_h_gr   r5, 0x22222222
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsadhz	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x22222222
-	test_h_gr  r4, 0x00017bf2
-	test_h_gr  r5, 0x00000000
-
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs b/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs
deleted file mode 100644
index d5cff1e..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wshufh.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wshufh
-wshufh:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wshufh	   wr1, wr0, #0x1b
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0xdef09abc
-	test_h_gr  r3, 0x56781234
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs b/sim/testsuite/sim/arm/iwmmxt/wsll.cgs
deleted file mode 100644
index 17d7893..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wsll.cgs
+++ /dev/null

@@ -1,167 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSLL
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wsll
-wsll:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Halfword Logical Shift Left
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsllh      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23406780
-	test_h_gr  r5, 0xabc0ef00
-		
-	# Test Halfword Aritc Shift Left by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr1, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsllhg     wr1, wr0, wcgr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr1
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x23406780
-	test_h_gr  r4, 0xabc0ef00
-		
-	# Test Word Logical Shift Left
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsllw      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456780
-	test_h_gr  r5, 0xabcdef00
-		
-	# Test Word Logical Shift Left by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr2, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsllwg     wr1, wr0, wcgr2
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr2
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x23456780
-	test_h_gr  r4, 0xabcdef00
-		
-	# Test Double Word Logical Shift Left
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wslld      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x23456780
-	test_h_gr  r5, 0xabcdefc1
-		
-	# Test Double Word Logical Shift Left by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr3, r2
-	tmcrr	   wr1,   r3, r4
-
-	wslldg     wr1, wr0, wcgr3
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr3
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x23456780
-	test_h_gr  r4, 0xabcdefc1
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs b/sim/testsuite/sim/arm/iwmmxt/wsra.cgs
deleted file mode 100644
index db998bb..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wsra.cgs
+++ /dev/null

@@ -1,167 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSRA
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wsra
-wsra:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Halfword Arithmetic Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsrah      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01230567
-	test_h_gr  r5, 0xf9abfdef
-		
-	# Test Halfword Arithmetic Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr1, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsrahg     wr1, wr0, wcgr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr1
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x01230567
-	test_h_gr  r4, 0xf9abfdef
-		
-	# Test Word Arithmetic Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsraw      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0xf9abcdef
-		
-	# Test Word Arithmetic Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr2, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsrawg     wr1, wr0, wcgr2
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr2
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x01234567
-	test_h_gr  r4, 0xf9abcdef
-		
-	# Test Double Word Arithmetic Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsrad      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0xc1234567
-	test_h_gr  r5, 0xf9abcdef
-		
-	# Test Double Word Arithmetic Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr3, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsradg     wr1, wr0, wcgr3
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr3
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0xc1234567
-	test_h_gr  r4, 0xf9abcdef
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs b/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs
deleted file mode 100644
index 416a464..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wsrl.cgs
+++ /dev/null

@@ -1,167 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSRL
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wsrl
-wsrl:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Halfword Logical Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsrlh      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01230567
-	test_h_gr  r5, 0x09ab0def
-		
-	# Test Halfword Logical Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr1, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsrlhg     wr1, wr0, wcgr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr1
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x01230567
-	test_h_gr  r4, 0x09ab0def
-		
-	# Test Word Logical Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsrlw      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x09abcdef
-		
-	# Test Word Logical Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr2, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsrlwg     wr1, wr0, wcgr2
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr2
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x01234567
-	test_h_gr  r4, 0x09abcdef
-		
-	# Test Double Word Logical Shift Right
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsrld      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0xc1234567
-	test_h_gr  r5, 0x09abcdef
-		
-	# Test Double Word Logical Shift Right by CG register
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdefc
-	mvi_h_gr   r2, 0x11111104
-	mvi_h_gr   r3, 0
-	mvi_h_gr   r4, 0
-
-	tmcrr	   wr0,   r0, r1
-	tmcr	   wcgr3, r2
-	tmcrr	   wr1,   r3, r4
-
-	wsrldg     wr1, wr0, wcgr3
-	
-	tmrrc	   r0, r1, wr0
-	tmrc	   r2, wcgr3
-	tmrrc	   r3, r4, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdefc
-	test_h_gr  r2, 0x11111104
-	test_h_gr  r3, 0xc1234567
-	test_h_gr  r4, 0x09abcdef
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs b/sim/testsuite/sim/arm/iwmmxt/wsub.cgs
deleted file mode 100644
index b0e77be..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wsub.cgs
+++ /dev/null

@@ -1,251 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WSUB
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wsub
-wsub:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsaturated Byte subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubb      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abcdef
-		
-	# Test Unsigned saturated Byte subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubbus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abcd00
-		
-	# Test Signed saturated Byte subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubbss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abcdef
-		
-	# Test Unsaturated Halfword subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubh      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	# Test Unsigned saturated Halfword subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubhus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	# Test Signed saturated Halfword subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubhss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	# Test Unsaturated Word subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubw      wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	# Test Unsigned saturated Word subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubwus    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	# Test Signed saturated Word subtraction
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcde00
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x11111111
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wsubwss    wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcde00
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x11111111
-	test_h_gr  r4, 0x01234567
-	test_h_gr  r5, 0x89abccef
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs
deleted file mode 100644
index 32a70f4..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs
+++ /dev/null

@@ -1,137 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEH
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wunpckeh
-wunpckeh:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Unpacking
-		
-	mvi_h_gr   r0, 0x12345687
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehub  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345687
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00de00f0
-	test_h_gr  r3, 0x009a00bc
-		
-	# Test Signed Byte Unpacking
-		
-	mvi_h_gr   r0, 0x12345687
-	mvi_h_gr   r1, 0x7abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehsb  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345687
-	test_h_gr  r1, 0x7abcdef0
-	test_h_gr  r2, 0xffdefff0
-	test_h_gr  r3, 0x007affbc
-		
-	# Test Unsigned Halfword Unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehuh  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x0000def0
-	test_h_gr  r3, 0x00009abc
-		
-	# Test Signed Halfword Unpacking
-		
-	mvi_h_gr   r0, 0x12348678
-	mvi_h_gr   r1, 0x7abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehsh  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12348678
-	test_h_gr  r1, 0x7abcdef0
-	test_h_gr  r2, 0xffffdef0
-	test_h_gr  r3, 0x00007abc
-		
-	# Test Unsigned Word Unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehuw  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x9abcdef0
-	test_h_gr  r3, 0x00000000
-		
-	# Test Signed Word Unpacking
-		
-	mvi_h_gr   r0, 0x82345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckehsw  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x82345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x9abcdef0
-	test_h_gr  r3, 0xffffffff
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs
deleted file mode 100644
index a6ffb4f..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs
+++ /dev/null

@@ -1,137 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKEL
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wunpckel
-wunpckel:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Unsigned Byte Unpacking
-		
-	mvi_h_gr   r0, 0x12345687
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckelub  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345687
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00560087
-	test_h_gr  r3, 0x00120034
-		
-	# Test Signed Byte Unpacking
-		
-	mvi_h_gr   r0, 0x12345687
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckelsb  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345687
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x0056ff87
-	test_h_gr  r3, 0x00120034
-		
-	# Test Unsigned Halfword Unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckeluh  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x00005678
-	test_h_gr  r3, 0x00001234
-		
-	# Test Signed Halfword Unpacking
-		
-	mvi_h_gr   r0, 0x12348678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckelsh  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12348678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0xffff8678
-	test_h_gr  r3, 0x00001234
-		
-	# Test Unsigned Word Unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckeluw  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x00000000
-		
-	# Test Signed Word Unpacking
-		
-	mvi_h_gr   r0, 0x82345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0
-	mvi_h_gr   r3, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-
-	wunpckelsw  wr1, wr0
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	
-	test_h_gr  r0, 0x82345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x82345678
-	test_h_gr  r3, 0xffffffff
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs
deleted file mode 100644
index 41fed0e..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs
+++ /dev/null

@@ -1,95 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIH
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wunpckih
-wunpckih:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckihb  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x00de00f0
-	test_h_gr  r5, 0x009a00bc
-
-	# Test Halfword unpacking
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckihh  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x0000def0
-	test_h_gr  r5, 0x00009abc
-	
-	# Test Word unpacking
-
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckihw  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x9abcdef0
-	test_h_gr  r5, 0x00000000
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs b/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs
deleted file mode 100644
index 7bd7300..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs
+++ /dev/null

@@ -1,95 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WUNPCKIL
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wunpckil
-wunpckil:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Byte unpacking
-		
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckilb  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x11561178
-	test_h_gr  r5, 0x11121134
-
-	# Test Halfword unpacking
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckilh  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x11115678
-	test_h_gr  r5, 0x11111234
-	
-	# Test Word unpacking
-
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wunpckilw  wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x12345678
-	test_h_gr  r5, 0x11111111
-		
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs b/sim/testsuite/sim/arm/iwmmxt/wxor.cgs
deleted file mode 100644
index 95e1fc8..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wxor.cgs
+++ /dev/null

@@ -1,41 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WXOR
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wxor
-wxor:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-	mvi_h_gr   r2, 0x11111111
-	mvi_h_gr   r3, 0x00000000
-	mvi_h_gr   r4, 0
-	mvi_h_gr   r5, 0
-
-	tmcrr	   wr0, r0, r1
-	tmcrr	   wr1, r2, r3
-	tmcrr	   wr2, r4, r5
-
-	wxor	   wr2, wr0, wr1
-	
-	tmrrc	   r0, r1, wr0
-	tmrrc	   r2, r3, wr1
-	tmrrc	   r4, r5, wr2
-	
-	test_h_gr  r0, 0x12345678
-	test_h_gr  r1, 0x9abcdef0
-	test_h_gr  r2, 0x11111111
-	test_h_gr  r3, 0x00000000
-	test_h_gr  r4, 0x03254769
-	test_h_gr  r5, 0x9abcdef0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs b/sim/testsuite/sim/arm/iwmmxt/wzero.cgs
deleted file mode 100644
index 78fa7c5..0000000
--- a/sim/testsuite/sim/arm/iwmmxt/wzero.cgs
+++ /dev/null

@@ -1,29 +0,0 @@
-# Intel(r) Wireless MMX(tm) technology testcase for WZERO
-# mach: xscale
-# as: -mcpu=xscale+iwmmxt
-
-	.include "testutils.inc"
-
-	start
-
-	.global wzero
-wzero:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mvi_h_gr   r0, 0x12345678
-	mvi_h_gr   r1, 0x9abcdef0
-
-	tmcrr	   wr0, r0, r1
-
-	wzero	   wr0
-	
-	tmrrc	   r0, r1, wr0
-	
-	test_h_gr  r0, 0x00000000
-	test_h_gr  r1, 0x00000000
-	
-	pass

diff --git a/sim/testsuite/sim/arm/ldm.cgs b/sim/testsuite/sim/arm/ldm.cgs
deleted file mode 100644
index 6831a83..0000000
--- a/sim/testsuite/sim/arm/ldm.cgs
+++ /dev/null

@@ -1,89 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmda_wb
-ldmda_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmda
-ldmda:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmdb_wb
-ldmdb_wb:
-
-	pass
-# arm testcase for ldm$cond ..
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmdb
-ldmdb:
-	ldm0 ..
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmia_wb
-ldmia_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmia
-ldmia:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmib_wb
-ldmib_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmib
-ldmib:
-
-	pass

diff --git a/sim/testsuite/sim/arm/ldr.cgs b/sim/testsuite/sim/arm/ldr.cgs
deleted file mode 100644
index 437b68c..0000000
--- a/sim/testsuite/sim/arm/ldr.cgs
+++ /dev/null

@@ -1,192 +0,0 @@
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_dec_imm_offset
-ldr_post_dec_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_dec_nonpriv_imm_offset
-ldr_post_dec_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_dec_nonpriv_reg_offset
-ldr_post_dec_nonpriv_reg_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_dec_reg_offset
-ldr_post_dec_reg_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_inc_imm_offset
-ldr_post_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_inc_nonpriv_imm_offset
-ldr_post_inc_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_inc_nonpriv_reg_offset
-ldr_post_inc_nonpriv_reg_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_post_inc_reg_offset
-ldr_post_inc_reg_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_dec_imm_offset
-ldr_pre_dec_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_dec_reg_offset
-ldr_pre_dec_reg_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_dec_wb_imm_offset
-ldr_pre_dec_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_dec_wb_reg_offset
-ldr_pre_dec_wb_reg_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_inc_imm_offset
-ldr_pre_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_inc_reg_offset
-ldr_pre_inc_reg_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_inc_wb_imm_offset
-ldr_pre_inc_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pre_inc_wb_reg_offset
-ldr_pre_inc_wb_reg_offset:
-	ldr0 pc,???
-
-	pass

diff --git a/sim/testsuite/sim/arm/ldrb.cgs b/sim/testsuite/sim/arm/ldrb.cgs
deleted file mode 100644
index b09880c..0000000
--- a/sim/testsuite/sim/arm/ldrb.cgs
+++ /dev/null

@@ -1,192 +0,0 @@
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_dec_imm_offset
-ldrb_post_dec_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}bt $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_dec_nonpriv_imm_offset
-ldrb_post_dec_nonpriv_imm_offset:
-	ldr0bt pc,???
-
-	pass
-# arm testcase for ldr${cond}bt $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_dec_nonpriv_reg_offset
-ldrb_post_dec_nonpriv_reg_offset:
-	ldr0bt pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_dec_reg_offset
-ldrb_post_dec_reg_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_inc_imm_offset
-ldrb_post_inc_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}bt $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_inc_nonpriv_imm_offset
-ldrb_post_inc_nonpriv_imm_offset:
-	ldr0bt pc,???
-
-	pass
-# arm testcase for ldr${cond}bt $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_inc_nonpriv_reg_offset
-ldrb_post_inc_nonpriv_reg_offset:
-	ldr0bt pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_post_inc_reg_offset
-ldrb_post_inc_reg_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_dec_imm_offset
-ldrb_pre_dec_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_dec_reg_offset
-ldrb_pre_dec_reg_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_dec_wb_imm_offset
-ldrb_pre_dec_wb_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_dec_wb_reg_offset
-ldrb_pre_dec_wb_reg_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_inc_imm_offset
-ldrb_pre_inc_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_inc_reg_offset
-ldrb_pre_inc_reg_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_inc_wb_imm_offset
-ldrb_pre_inc_wb_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_pre_inc_wb_reg_offset
-ldrb_pre_inc_wb_reg_offset:
-	ldr0b pc,???
-
-	pass

diff --git a/sim/testsuite/sim/arm/ldrh.cgs b/sim/testsuite/sim/arm/ldrh.cgs
deleted file mode 100644
index 16a4323..0000000
--- a/sim/testsuite/sim/arm/ldrh.cgs
+++ /dev/null

@@ -1,132 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_post_dec_imm_offset
-ldrh_post_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_post_dec_reg_offset
-ldrh_post_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_post_inc_imm_offset
-ldrh_post_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_post_inc_reg_offset
-ldrh_post_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_dec_imm_offset
-ldrh_pre_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_dec_reg_offset
-ldrh_pre_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_dec_wb_imm_offset
-ldrh_pre_dec_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_dec_wb_reg_offset
-ldrh_pre_dec_wb_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_inc_imm_offset
-ldrh_pre_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_inc_reg_offset
-ldrh_pre_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_inc_wb_imm_offset
-ldrh_pre_inc_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_pre_inc_wb_reg_offset
-ldrh_pre_inc_wb_reg_offset:
-
-	pass

diff --git a/sim/testsuite/sim/arm/ldrsb.cgs b/sim/testsuite/sim/arm/ldrsb.cgs
deleted file mode 100644
index 4d08f4c..0000000
--- a/sim/testsuite/sim/arm/ldrsb.cgs
+++ /dev/null

@@ -1,132 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_post_dec_imm_offset
-ldrsb_post_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_post_dec_reg_offset
-ldrsb_post_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_post_inc_imm_offset
-ldrsb_post_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_post_inc_reg_offset
-ldrsb_post_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_dec_imm_offset
-ldrsb_pre_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_dec_reg_offset
-ldrsb_pre_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_dec_wb_imm_offset
-ldrsb_pre_dec_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_dec_wb_reg_offset
-ldrsb_pre_dec_wb_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_inc_imm_offset
-ldrsb_pre_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_inc_reg_offset
-ldrsb_pre_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_inc_wb_imm_offset
-ldrsb_pre_inc_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsb_pre_inc_wb_reg_offset
-ldrsb_pre_inc_wb_reg_offset:
-
-	pass

diff --git a/sim/testsuite/sim/arm/ldrsh.cgs b/sim/testsuite/sim/arm/ldrsh.cgs
deleted file mode 100644
index 5a6e7c7..0000000
--- a/sim/testsuite/sim/arm/ldrsh.cgs
+++ /dev/null

@@ -1,132 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_post_dec_imm_offset
-ldrsh_post_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_post_dec_reg_offset
-ldrsh_post_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_post_inc_imm_offset
-ldrsh_post_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_post_inc_reg_offset
-ldrsh_post_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_dec_imm_offset
-ldrsh_pre_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_dec_reg_offset
-ldrsh_pre_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_dec_wb_imm_offset
-ldrsh_pre_dec_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_dec_wb_reg_offset
-ldrsh_pre_dec_wb_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_inc_imm_offset
-ldrsh_pre_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_inc_reg_offset
-ldrsh_pre_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_inc_wb_imm_offset
-ldrsh_pre_inc_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrsh_pre_inc_wb_reg_offset
-ldrsh_pre_inc_wb_reg_offset:
-
-	pass

diff --git a/sim/testsuite/sim/arm/misaligned1.ms b/sim/testsuite/sim/arm/misaligned1.ms
deleted file mode 100644
index 69fda47..0000000
--- a/sim/testsuite/sim/arm/misaligned1.ms
+++ /dev/null

@@ -1,61 +0,0 @@
-# Test LDR instructions with offsets misaligned by 1 byte.
-# mach(): all
-
-	.macro invalid
-# This is "undefined" but it's not properly decoded yet.
-	.word 0x07ffffff
-# This is stc which isn't recognized yet.
-	stc 0,cr0,[r0]
-	.endm
-
-	.global _start
-_start:
-# Run some simple insns to confirm the engine is at least working.
-	nop
-
-# Skip over output text.
-	bl do_test
-
-pass:
-	.asciz "pass\n"
-	.p2align 2
-
-do_test:
-	mov r4, r14
-	bl continue
-word1:
-	.word 0x5555
-continue:
-	ldr r6, [r14, #1]
-	ldr r7, word2
-	cmp r6, r7
-	# Failed.
-	bne done
-
-output_next:
-# Output a character (in arm mode).
-	mov r0,#3
-	mov r1,r4
-	swi #0x123456
-
-# Load next character, see if done.
-	add r4,r4,#1
-	sub r3,r3,r3
-	ldrb r5,[r4,r3]
-	teq r5,#0
-	bne output_next
-
-done:
-	mov r0,#0x18
-	ldr r1,exit_code
-	swi #0x123456
-
-# If that fails, try to die with an invalid insn.
-	invalid
-
-exit_code:
-	.word 0x20026
-	.word 0xFFFFFFFF
-word2:
-	.word 0x55000055
-	.word 0xFFFFFFFF

diff --git a/sim/testsuite/sim/arm/misaligned2.ms b/sim/testsuite/sim/arm/misaligned2.ms
deleted file mode 100644
index 3a03326..0000000
--- a/sim/testsuite/sim/arm/misaligned2.ms
+++ /dev/null

@@ -1,60 +0,0 @@
-# Test LDR instructions with offsets misaligned by 2 bytes. 
-# mach(): all
-
-	.macro invalid
-# This is "undefined" but it's not properly decoded yet.
-	.word 0x07ffffff
-# This is stc which isn't recognized yet.
-	stc 0,cr0,[r0]
-	.endm
-
-	.global _start
-_start:
-# Run some simple insns to confirm the engine is at least working.
-	nop
-
-# Skip over output text.
-	bl do_test
-
-pass:
-	.asciz "pass\n"
-	.p2align 2
-
-do_test:
-	mov r4, r14
-	bl continue
-word1:
-	.word 0x5555
-continue:
-	ldr r6, [r14, #2]
-	ldr r7, word2
-	cmp r6, r7
-	# Failed.
-	bne done
-
-output_next:
-# Output a character (in arm mode).
-	mov r0,#3
-	mov r1,r4
-	swi #0x123456
-
-# Load next character, see if done.
-	add r4,r4,#1
-	sub r3,r3,r3
-	ldrb r5,[r4,r3]
-	teq r5,#0
-	bne output_next
-
-done:
-	mov r0,#0x18
-	ldr r1,exit_code
-	swi #0x123456
-
-# If that fails, try to die with an invalid insn.
-	invalid
-
-exit_code:
-	.word 0x20026
-
-word2:
-	.word 0x55550000

diff --git a/sim/testsuite/sim/arm/misaligned3.ms b/sim/testsuite/sim/arm/misaligned3.ms
deleted file mode 100644
index bf2d9f1..0000000
--- a/sim/testsuite/sim/arm/misaligned3.ms
+++ /dev/null

@@ -1,62 +0,0 @@
-# Test LDR instructions with offsets misaligned by 3 bytes.
-# mach(): all
-
-	.macro invalid
-# This is "undefined" but it's not properly decoded yet.
-	.word 0x07ffffff
-# This is stc which isn't recognized yet.
-	stc 0,cr0,[r0]
-	.endm
-
-	.global _start
-_start:
-# Run some simple insns to confirm the engine is at least working.
-	nop
-
-# Skip over output text.
-	bl do_test
-
-pass:
-	.asciz "pass\n"
-	.p2align 2
-
-do_test:
-	mov r4, r14
-	bl continue
-word1:
-	.word 0x5555
-continue:
-	ldr r6, [r14, #3]
-	ldr r7, word2
-	cmp r6, r7
-	# Failed.
-	bne done
-
-output_next:
-# Output a character (in arm mode).
-	mov r0,#3
-	mov r1,r4
-	swi #0x123456
-
-# Load next character, see if done.
-	add r4,r4,#1
-	sub r3,r3,r3
-	ldrb r5,[r4,r3]
-	teq r5,#0
-	bne output_next
-
-done:
-	mov r0,#0x18
-	ldr r1,exit_code
-	swi #0x123456
-
-# If that fails, try to die with an invalid insn.
-	invalid
-
-exit_code:
-	.word 0x20026
-
-	.word 0xFFFFFFFF
-word2:
-	.word 0x555500
-	.word 0xFFFFFFFF

diff --git a/sim/testsuite/sim/arm/misc.exp b/sim/testsuite/sim/arm/misc.exp
deleted file mode 100644
index 1e8006f..0000000
--- a/sim/testsuite/sim/arm/misc.exp
+++ /dev/null

@@ -1,20 +0,0 @@
-# Miscellaneous ARM simulator testcases
-
-if { [istarget arm*-*-*] || [istarget thumb*-*-*] || [istarget xscale*-*-*] } {
-    # load support procs
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "arm7tdmi"
-
-    # The .ms suffix is for "miscellaneous .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-
-	run_sim_test $src $all_machs
-    }
-}

diff --git a/sim/testsuite/sim/arm/mla.cgs b/sim/testsuite/sim/arm/mla.cgs
deleted file mode 100644
index c82dd0c..0000000
--- a/sim/testsuite/sim/arm/mla.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mla$cond${set-cc?} ${mul-rd},$rm,$rs,${mul-rn}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mla
-mla:
-	mla00 pc,pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/mov.cgs b/sim/testsuite/sim/arm/mov.cgs
deleted file mode 100644
index d2a83d3..0000000
--- a/sim/testsuite/sim/arm/mov.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for mov$cond${set-cc?} $rd,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_imm
-mov_imm:
-	mov00 pc,0
-
-	pass
-# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_reg_imm_shift
-mov_reg_imm_shift:
-	mov00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_reg_reg_shift
-mov_reg_reg_shift:
-	mov00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/mrs.cgs b/sim/testsuite/sim/arm/mrs.cgs
deleted file mode 100644
index 22c5e95..0000000
--- a/sim/testsuite/sim/arm/mrs.cgs
+++ /dev/null

@@ -1,24 +0,0 @@
-# arm testcase for mrs$cond $rd,cpsr
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrs_c
-mrs_c:
-	mrs0 pc,cpsr
-
-	pass
-# arm testcase for mrs$cond $rd,spsr
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mrs_s
-mrs_s:
-	mrs0 pc,spsr
-
-	pass

diff --git a/sim/testsuite/sim/arm/msr.cgs b/sim/testsuite/sim/arm/msr.cgs
deleted file mode 100644
index c79f0bd..0000000
--- a/sim/testsuite/sim/arm/msr.cgs
+++ /dev/null

@@ -1,24 +0,0 @@
-# arm testcase for msr$cond cpsr,$rm
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global msr_c
-msr_c:
-	msr0 cpsr,pc
-
-	pass
-# arm testcase for msr$cond spsr,$rm
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global msr_s
-msr_s:
-	msr0 spsr,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/mul.cgs b/sim/testsuite/sim/arm/mul.cgs
deleted file mode 100644
index 4f0a926..0000000
--- a/sim/testsuite/sim/arm/mul.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mul$cond${set-cc?} ${mul-rd},$rm,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mul
-mul:
-	mul00 pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/mvn.cgs b/sim/testsuite/sim/arm/mvn.cgs
deleted file mode 100644
index 92fd3a4..0000000
--- a/sim/testsuite/sim/arm/mvn.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for mvn$cond${set-cc?} $rd,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mvn_imm
-mvn_imm:
-	mvn00 pc,0
-
-	pass
-# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mvn_reg_imm_shift
-mvn_reg_imm_shift:
-	mvn00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for mvn$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mvn_reg_reg_shift
-mvn_reg_reg_shift:
-	mvn00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/orr.cgs b/sim/testsuite/sim/arm/orr.cgs
deleted file mode 100644
index 3fc67ad..0000000
--- a/sim/testsuite/sim/arm/orr.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for orr$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global orr_imm
-orr_imm:
-	orr00 pc,pc,0
-
-	pass
-# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global orr_reg_imm_shift
-orr_reg_imm_shift:
-	orr00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for orr$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global orr_reg_reg_shift
-orr_reg_reg_shift:
-	orr00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/rsb.cgs b/sim/testsuite/sim/arm/rsb.cgs
deleted file mode 100644
index 14edc35..0000000
--- a/sim/testsuite/sim/arm/rsb.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for rsb$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsb_imm
-rsb_imm:
-	rsb00 pc,pc,0
-
-	pass
-# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsb_reg_imm_shift
-rsb_reg_imm_shift:
-	rsb00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for rsb$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsb_reg_reg_shift
-rsb_reg_reg_shift:
-	rsb00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/rsc.cgs b/sim/testsuite/sim/arm/rsc.cgs
deleted file mode 100644
index 078fbcc..0000000
--- a/sim/testsuite/sim/arm/rsc.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for rsc$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsc_imm
-rsc_imm:
-	rsc00 pc,pc,0
-
-	pass
-# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsc_reg_imm_shift
-rsc_reg_imm_shift:
-	rsc00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for rsc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global rsc_reg_reg_shift
-rsc_reg_reg_shift:
-	rsc00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/sbc.cgs b/sim/testsuite/sim/arm/sbc.cgs
deleted file mode 100644
index 9462702..0000000
--- a/sim/testsuite/sim/arm/sbc.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for sbc$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sbc_imm
-sbc_imm:
-	sbc00 pc,pc,0
-
-	pass
-# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sbc_reg_imm_shift
-sbc_reg_imm_shift:
-	sbc00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for sbc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sbc_reg_reg_shift
-sbc_reg_reg_shift:
-	sbc00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/smlal.cgs b/sim/testsuite/sim/arm/smlal.cgs
deleted file mode 100644
index 4ad1373..0000000
--- a/sim/testsuite/sim/arm/smlal.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for smlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global smlal
-smlal:
-	smlal00 pc,pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/smull.cgs b/sim/testsuite/sim/arm/smull.cgs
deleted file mode 100644
index 22e3960..0000000
--- a/sim/testsuite/sim/arm/smull.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for smull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global smull
-smull:
-	smull00 pc,pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/stm.cgs b/sim/testsuite/sim/arm/stm.cgs
deleted file mode 100644
index c381216..0000000
--- a/sim/testsuite/sim/arm/stm.cgs
+++ /dev/null

@@ -1,88 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmda_wb
-stmda_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmda
-stmda:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmdb_wb
-stmdb_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmdb
-stmdb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmia_wb
-stmia_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmia
-stmia:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmib_wb
-stmib_wb:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmib
-stmib:
-
-	pass

diff --git a/sim/testsuite/sim/arm/str.cgs b/sim/testsuite/sim/arm/str.cgs
deleted file mode 100644
index 82c683b..0000000
--- a/sim/testsuite/sim/arm/str.cgs
+++ /dev/null

@@ -1,192 +0,0 @@
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_dec_imm_offset
-str_post_dec_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_dec_nonpriv_imm_offset
-str_post_dec_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for str${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_dec_nonpriv_reg_offset
-str_post_dec_nonpriv_reg_offset:
-	str0t pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_dec_reg_offset
-str_post_dec_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_inc_imm_offset
-str_post_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_inc_nonpriv_imm_offset
-str_post_inc_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for str${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_inc_nonpriv_reg_offset
-str_post_inc_nonpriv_reg_offset:
-	str0t pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_post_inc_reg_offset
-str_post_inc_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_dec_imm_offset
-str_pre_dec_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_dec_reg_offset
-str_pre_dec_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_dec_wb_imm_offset
-str_pre_dec_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_dec_wb_reg_offset
-str_pre_dec_wb_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_inc_imm_offset
-str_pre_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_inc_reg_offset
-str_pre_inc_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_inc_wb_imm_offset
-str_pre_inc_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_pre_inc_wb_reg_offset
-str_pre_inc_wb_reg_offset:
-	str0 pc,???
-
-	pass

diff --git a/sim/testsuite/sim/arm/strb.cgs b/sim/testsuite/sim/arm/strb.cgs
deleted file mode 100644
index 875a649..0000000
--- a/sim/testsuite/sim/arm/strb.cgs
+++ /dev/null

@@ -1,192 +0,0 @@
-# arm testcase for ldr${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_dec_imm_offset
-strb_post_dec_imm_offset:
-	ldr0b pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_dec_nonpriv_imm_offset
-strb_post_dec_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for str${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_dec_nonpriv_reg_offset
-strb_post_dec_nonpriv_reg_offset:
-	str0t pc,???
-
-	pass
-# arm testcase for str${cond}b $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_dec_reg_offset
-strb_post_dec_reg_offset:
-	str0b pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_inc_imm_offset
-strb_post_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for ldr${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_inc_nonpriv_imm_offset
-strb_post_inc_nonpriv_imm_offset:
-	ldr0t pc,???
-
-	pass
-# arm testcase for str${cond}t $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_inc_nonpriv_reg_offset
-strb_post_inc_nonpriv_reg_offset:
-	str0t pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_post_inc_reg_offset
-strb_post_inc_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_dec_imm_offset
-strb_pre_dec_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_dec_reg_offset
-strb_pre_dec_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_dec_wb_imm_offset
-strb_pre_dec_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_dec_wb_reg_offset
-strb_pre_dec_wb_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_inc_imm_offset
-strb_pre_inc_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_inc_reg_offset
-strb_pre_inc_reg_offset:
-	str0 pc,???
-
-	pass
-# arm testcase for ldr${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_inc_wb_imm_offset
-strb_pre_inc_wb_imm_offset:
-	ldr0 pc,???
-
-	pass
-# arm testcase for str${cond} $rd,???
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_pre_inc_wb_reg_offset
-strb_pre_inc_wb_reg_offset:
-	str0 pc,???
-
-	pass

diff --git a/sim/testsuite/sim/arm/strh.cgs b/sim/testsuite/sim/arm/strh.cgs
deleted file mode 100644
index e111d48..0000000
--- a/sim/testsuite/sim/arm/strh.cgs
+++ /dev/null

@@ -1,132 +0,0 @@
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_post_dec_imm_offset
-strh_post_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_post_dec_reg_offset
-strh_post_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_post_inc_imm_offset
-strh_post_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_post_inc_reg_offset
-strh_post_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_dec_imm_offset
-strh_pre_dec_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_dec_reg_offset
-strh_pre_dec_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_dec_wb_imm_offset
-strh_pre_dec_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_dec_wb_reg_offset
-strh_pre_dec_wb_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_inc_imm_offset
-strh_pre_inc_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_inc_reg_offset
-strh_pre_inc_reg_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_inc_wb_imm_offset
-strh_pre_inc_wb_imm_offset:
-
-	pass
-# arm testcase for FIXME
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_pre_inc_wb_reg_offset
-strh_pre_inc_wb_reg_offset:
-
-	pass

diff --git a/sim/testsuite/sim/arm/sub.cgs b/sim/testsuite/sim/arm/sub.cgs
deleted file mode 100644
index 50f222c..0000000
--- a/sim/testsuite/sim/arm/sub.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for sub$cond${set-cc?} $rd,$rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub_imm
-sub_imm:
-	sub00 pc,pc,0
-
-	pass
-# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub_reg_imm_shift
-sub_reg_imm_shift:
-	sub00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for sub$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub_reg_reg_shift
-sub_reg_reg_shift:
-	sub00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/swi.cgs b/sim/testsuite/sim/arm/swi.cgs
deleted file mode 100644
index 0c23d43..0000000
--- a/sim/testsuite/sim/arm/swi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for swi$cond ${swi-comment}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global swi
-swi:
-	swi0 0
-
-	pass

diff --git a/sim/testsuite/sim/arm/swp.cgs b/sim/testsuite/sim/arm/swp.cgs
deleted file mode 100644
index f965ef2..0000000
--- a/sim/testsuite/sim/arm/swp.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for swp$cond $rd,$rm,[$rn]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global swp
-swp:
-	swp0 pc,pc,[pc]
-
-	pass

diff --git a/sim/testsuite/sim/arm/swpb.cgs b/sim/testsuite/sim/arm/swpb.cgs
deleted file mode 100644
index 6f8a076..0000000
--- a/sim/testsuite/sim/arm/swpb.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for swpb${cond}b $rd,$rm,[$rn]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global swpb
-swpb:
-	swpb0b pc,pc,[pc]
-
-	pass

diff --git a/sim/testsuite/sim/arm/teq.cgs b/sim/testsuite/sim/arm/teq.cgs
deleted file mode 100644
index 6c69347..0000000
--- a/sim/testsuite/sim/arm/teq.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for teq${cond}${set-cc?} $rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global teq_imm
-teq_imm:
-	teq00 pc,0
-
-	pass
-# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global teq_reg_imm_shift
-teq_reg_imm_shift:
-	teq00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for teq$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global teq_reg_reg_shift
-teq_reg_reg_shift:
-	teq00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/testutils.inc b/sim/testsuite/sim/arm/testutils.inc
deleted file mode 100644
index ae49db8..0000000
--- a/sim/testsuite/sim/arm/testutils.inc
+++ /dev/null

@@ -1,118 +0,0 @@
-# r0-r3 are used as tmps, consider them call clobbered by these macros.
-# This uses the angel rom monitor calls.
-# ??? How do we use the \@ facility of .macros ???
-# @ is the comment char!
-
-	.macro mvi_h_gr reg, val
-	ldr \reg,[pc]
-	b . + 8
-	.word \val
-	.endm
-
-	.macro mvaddr_h_gr reg, addr
-	ldr \reg,[pc]
-	b . + 8
-	.word \addr
-	.endm
-
-	.macro start
-	.data
-failmsg:
-	.asciz "fail\n"
-passmsg:
-	.asciz "pass\n"
-	.text
-
-do_pass:
-	ldr r1, passmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 0
-passmsg_addr:
-	.word passmsg
-
-do_fail:
-	ldr r1, failmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 1
-failmsg_addr:
-	.word failmsg
-
-	.global _start
-_start:
-	.endm
-
-# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
-
-	.macro pass
-	b do_pass
-	.endm
-
-	.macro fail
-	b do_fail
-	.endm
-
-	.macro exit rc
-	# ??? This works with the ARMulator but maybe not others.
-	#mov r0, #\rc
-	#swi #1
-	# This seems to be portable (though it ignores rc).
-	mov r0,#0x18
-	mvi_h_gr r1, 0x20026
-	swi #0x123456
-	# If that returns, punt with a sigill.
-	stc 0,cr0,[r0]
-	.endm
-
-# Other macros know this only clobbers r0.
-# WARNING: It also clobbers the condition codes (FIXME).
-	.macro test_h_gr reg, val
-	mvaddr_h_gr r0, \val
-	cmp \reg, r0
-	beq . + 8
-	fail
-	.endm
-
-	.macro mvi_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	bic r1, r1, #0xf0000000
-	orr r1, r1, r0
-	msr cpsr, r1
-	# ??? nops needed
-	.endm
-
-# ??? Preserve condition codes?
-	.macro test_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	and r1, r1, #0xf0000000
-	cmp r0, r1
-	beq . + 8
-	fail
-	.endm

diff --git a/sim/testsuite/sim/arm/thumb/adc.cgs b/sim/testsuite/sim/arm/thumb/adc.cgs
deleted file mode 100644
index 58d74c1..0000000
--- a/sim/testsuite/sim/arm/thumb/adc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for adc $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_adc
-alu_adc:
-	adc r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs
deleted file mode 100644
index 0307acc..0000000
--- a/sim/testsuite/sim/arm/thumb/add-hd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add $hd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global add_hd_hs
-add_hd_hs:
-	add r8,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs
deleted file mode 100644
index ca080f7..0000000
--- a/sim/testsuite/sim/arm/thumb/add-hd-rs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add $hd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global add_hd_rs
-add_hd_rs:
-	add r8,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs
deleted file mode 100644
index 46373a0..0000000
--- a/sim/testsuite/sim/arm/thumb/add-rd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add $rd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global add_rd_hs
-add_rd_hs:
-	add r0,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/add-sp.cgs b/sim/testsuite/sim/arm/thumb/add-sp.cgs
deleted file mode 100644
index 54efa2a..0000000
--- a/sim/testsuite/sim/arm/thumb/add-sp.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add sp,#$sword7
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global add_sp
-add_sp:
-	add sp,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/add.cgs b/sim/testsuite/sim/arm/thumb/add.cgs
deleted file mode 100644
index 63cc20c..0000000
--- a/sim/testsuite/sim/arm/thumb/add.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add $rd,$rs,$rn
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global add
-add:
-	add r0,r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/addi.cgs b/sim/testsuite/sim/arm/thumb/addi.cgs
deleted file mode 100644
index 00ec76d..0000000
--- a/sim/testsuite/sim/arm/thumb/addi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add $rd,$rs,#$offset3
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global addi
-addi:
-	add r0,r0,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/addi8.cgs b/sim/testsuite/sim/arm/thumb/addi8.cgs
deleted file mode 100644
index d8e9f81..0000000
--- a/sim/testsuite/sim/arm/thumb/addi8.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add ${bit10-rd},#$offset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global addi8
-addi8:
-	add r0,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/allthumb.exp b/sim/testsuite/sim/arm/thumb/allthumb.exp
deleted file mode 100644
index 9674bca..0000000
--- a/sim/testsuite/sim/arm/thumb/allthumb.exp
+++ /dev/null

@@ -1,21 +0,0 @@
-# ARM simulator testsuite.
-
-if { [istarget arm*-*-*]
-     || [istarget thumb*-*-*] } {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "arm7tdmi"
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-
-	run_sim_test $src $all_machs
-    }
-}

diff --git a/sim/testsuite/sim/arm/thumb/and.cgs b/sim/testsuite/sim/arm/thumb/and.cgs
deleted file mode 100644
index d67adf4..0000000
--- a/sim/testsuite/sim/arm/thumb/and.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for and $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_and
-alu_and:
-	and r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/asr.cgs b/sim/testsuite/sim/arm/thumb/asr.cgs
deleted file mode 100644
index 4d21dae..0000000
--- a/sim/testsuite/sim/arm/thumb/asr.cgs
+++ /dev/null

@@ -1,14 +0,0 @@
-# arm testcase for asr $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_asr
-alu_asr:
-	asr r0,r0
-
-# FIXME: Also asr $rd,$rs,#$offset5
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/b.cgs b/sim/testsuite/sim/arm/thumb/b.cgs
deleted file mode 100644
index ecae537..0000000
--- a/sim/testsuite/sim/arm/thumb/b.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for b $offset11
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global b
-b:
-	b footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bcc.cgs b/sim/testsuite/sim/arm/thumb/bcc.cgs
deleted file mode 100644
index 6c84458..0000000
--- a/sim/testsuite/sim/arm/thumb/bcc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bcc $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcc
-bcc:
-	bcc footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bcs.cgs b/sim/testsuite/sim/arm/thumb/bcs.cgs
deleted file mode 100644
index a29a8fb..0000000
--- a/sim/testsuite/sim/arm/thumb/bcs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bcs $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bcs
-bcs:
-	bcs footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/beq.cgs b/sim/testsuite/sim/arm/thumb/beq.cgs
deleted file mode 100644
index 33f3748..0000000
--- a/sim/testsuite/sim/arm/thumb/beq.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for beq $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global beq
-beq:
-	beq footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bge.cgs b/sim/testsuite/sim/arm/thumb/bge.cgs
deleted file mode 100644
index 4eb543d..0000000
--- a/sim/testsuite/sim/arm/thumb/bge.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bge $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bge
-bge:
-	bge footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bgt.cgs b/sim/testsuite/sim/arm/thumb/bgt.cgs
deleted file mode 100644
index 1ffe092..0000000
--- a/sim/testsuite/sim/arm/thumb/bgt.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bgt $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bgt
-bgt:
-	bgt footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bhi.cgs b/sim/testsuite/sim/arm/thumb/bhi.cgs
deleted file mode 100644
index c9811c6..0000000
--- a/sim/testsuite/sim/arm/thumb/bhi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bhi $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bhi
-bhi:
-	bhi footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bic.cgs b/sim/testsuite/sim/arm/thumb/bic.cgs
deleted file mode 100644
index 6dca1ef..0000000
--- a/sim/testsuite/sim/arm/thumb/bic.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bic $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_bic
-alu_bic:
-	bic r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bl-hi.cgs b/sim/testsuite/sim/arm/thumb/bl-hi.cgs
deleted file mode 100644
index c7400c7..0000000
--- a/sim/testsuite/sim/arm/thumb/bl-hi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bl-hi ${lbwl-hi}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bl_hi
-bl_hi:
-	bl-hi 0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bl-lo.cgs b/sim/testsuite/sim/arm/thumb/bl-lo.cgs
deleted file mode 100644
index ed76613..0000000
--- a/sim/testsuite/sim/arm/thumb/bl-lo.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bl-lo ${lbwl-lo}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bl_lo
-bl_lo:
-	bl-lo 0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ble.cgs b/sim/testsuite/sim/arm/thumb/ble.cgs
deleted file mode 100644
index e9c5a8f..0000000
--- a/sim/testsuite/sim/arm/thumb/ble.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ble $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ble
-ble:
-	ble footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bls.cgs b/sim/testsuite/sim/arm/thumb/bls.cgs
deleted file mode 100644
index 483412b..0000000
--- a/sim/testsuite/sim/arm/thumb/bls.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bls $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bls
-bls:
-	bls footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/blt.cgs b/sim/testsuite/sim/arm/thumb/blt.cgs
deleted file mode 100644
index 0fbcbe8..0000000
--- a/sim/testsuite/sim/arm/thumb/blt.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for blt $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global blt
-blt:
-	blt footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bmi.cgs b/sim/testsuite/sim/arm/thumb/bmi.cgs
deleted file mode 100644
index 8f7558a..0000000
--- a/sim/testsuite/sim/arm/thumb/bmi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bmi $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bmi
-bmi:
-	bmi footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bne.cgs b/sim/testsuite/sim/arm/thumb/bne.cgs
deleted file mode 100644
index a5ac348..0000000
--- a/sim/testsuite/sim/arm/thumb/bne.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bne $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bne
-bne:
-	bne footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bpl.cgs b/sim/testsuite/sim/arm/thumb/bpl.cgs
deleted file mode 100644
index 8f64259..0000000
--- a/sim/testsuite/sim/arm/thumb/bpl.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bpl $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bpl
-bpl:
-	bpl footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bvc.cgs b/sim/testsuite/sim/arm/thumb/bvc.cgs
deleted file mode 100644
index bbd3af5..0000000
--- a/sim/testsuite/sim/arm/thumb/bvc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bvc $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bvc
-bvc:
-	bvc footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bvs.cgs b/sim/testsuite/sim/arm/thumb/bvs.cgs
deleted file mode 100644
index 8c9a551..0000000
--- a/sim/testsuite/sim/arm/thumb/bvs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bvs $soffset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bvs
-bvs:
-	bvs footext
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bx-hs.cgs b/sim/testsuite/sim/arm/thumb/bx-hs.cgs
deleted file mode 100644
index d963387..0000000
--- a/sim/testsuite/sim/arm/thumb/bx-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bx $hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bx_hs
-bx_hs:
-	bx r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/bx-rs.cgs b/sim/testsuite/sim/arm/thumb/bx-rs.cgs
deleted file mode 100644
index f6db8c8..0000000
--- a/sim/testsuite/sim/arm/thumb/bx-rs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for bx $rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global bx_rs
-bx_rs:
-	bx r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/cmn.cgs b/sim/testsuite/sim/arm/thumb/cmn.cgs
deleted file mode 100644
index 96d53a1..0000000
--- a/sim/testsuite/sim/arm/thumb/cmn.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for cmn $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_cmn
-alu_cmn:
-	cmn r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs
deleted file mode 100644
index 96a91a2..0000000
--- a/sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for cmp $hd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_hd_hs
-cmp_hd_hs:
-	cmp r8,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs
deleted file mode 100644
index 9fc4875..0000000
--- a/sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for cmp $hd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_hd_rs
-cmp_hd_rs:
-	cmp r8,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs
deleted file mode 100644
index e3f7a4a..0000000
--- a/sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for cmp $rd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp_rd_hs
-cmp_rd_hs:
-	cmp r0,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/cmp.cgs b/sim/testsuite/sim/arm/thumb/cmp.cgs
deleted file mode 100644
index 7564099..0000000
--- a/sim/testsuite/sim/arm/thumb/cmp.cgs
+++ /dev/null

@@ -1,14 +0,0 @@
-# arm testcase for cmp ${bit10-rd},#$offset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global cmp
-cmp:
-	cmp r0,#0
-
-# FIXME: Also: cmp $rd,$rs
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/eor.cgs b/sim/testsuite/sim/arm/thumb/eor.cgs
deleted file mode 100644
index cc6021c..0000000
--- a/sim/testsuite/sim/arm/thumb/eor.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for eor $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_eor
-alu_eor:
-	eor r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/lda-pc.cgs b/sim/testsuite/sim/arm/thumb/lda-pc.cgs
deleted file mode 100644
index 74407e2..0000000
--- a/sim/testsuite/sim/arm/thumb/lda-pc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add ${bit10-rd},pc,$word8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global lda_pc
-lda_pc:
-	add r0,pc,0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/lda-sp.cgs b/sim/testsuite/sim/arm/thumb/lda-sp.cgs
deleted file mode 100644
index ce2b62e..0000000
--- a/sim/testsuite/sim/arm/thumb/lda-sp.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add ${bit10-rd},sp,$word8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global lda_sp
-lda_sp:
-	add r0,sp,0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldmia.cgs b/sim/testsuite/sim/arm/thumb/ldmia.cgs
deleted file mode 100644
index 550031e..0000000
--- a/sim/testsuite/sim/arm/thumb/ldmia.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldmia $rb!,{$rlist}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldmia
-ldmia:
-	ldmia r0!,{0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs b/sim/testsuite/sim/arm/thumb/ldr-imm.cgs
deleted file mode 100644
index a757f33..0000000
--- a/sim/testsuite/sim/arm/thumb/ldr-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldr $rd,[$rb,#${offset5-7}]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_imm
-ldr_imm:
-	ldr r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs b/sim/testsuite/sim/arm/thumb/ldr-pc.cgs
deleted file mode 100644
index 8227562..0000000
--- a/sim/testsuite/sim/arm/thumb/ldr-pc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldr ${bit10-rd},[pc,#$word8]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_pc
-ldr_pc:
-	ldr r0,[pc,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs b/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs
deleted file mode 100644
index 11eee26..0000000
--- a/sim/testsuite/sim/arm/thumb/ldr-sprel.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldr ${bit10-rd},[sp,#$word8]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr_sprel
-ldr_sprel:
-	ldr r0,[sp,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldr.cgs b/sim/testsuite/sim/arm/thumb/ldr.cgs
deleted file mode 100644
index 03af925..0000000
--- a/sim/testsuite/sim/arm/thumb/ldr.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldr $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldr
-ldr:
-	ldr r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs
deleted file mode 100644
index c1eeafe..0000000
--- a/sim/testsuite/sim/arm/thumb/ldrb-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldrb $rd,[$rb,#$offset5]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb_imm
-ldrb_imm:
-	ldrb r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldrb.cgs b/sim/testsuite/sim/arm/thumb/ldrb.cgs
deleted file mode 100644
index 316a10f..0000000
--- a/sim/testsuite/sim/arm/thumb/ldrb.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldrb $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrb
-ldrb:
-	ldrb r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs b/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs
deleted file mode 100644
index 81ea1e0..0000000
--- a/sim/testsuite/sim/arm/thumb/ldrh-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldrh $rd,[$rb,#${offset5-6}]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh_imm
-ldrh_imm:
-	ldrh r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldrh.cgs b/sim/testsuite/sim/arm/thumb/ldrh.cgs
deleted file mode 100644
index 3ff8f4e..0000000
--- a/sim/testsuite/sim/arm/thumb/ldrh.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldrh $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldrh
-ldrh:
-	ldrh r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldsb.cgs b/sim/testsuite/sim/arm/thumb/ldsb.cgs
deleted file mode 100644
index e1612c9..0000000
--- a/sim/testsuite/sim/arm/thumb/ldsb.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldsb $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsb
-ldsb:
-	ldsb r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ldsh.cgs b/sim/testsuite/sim/arm/thumb/ldsh.cgs
deleted file mode 100644
index 46d49ac..0000000
--- a/sim/testsuite/sim/arm/thumb/ldsh.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ldsh $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global ldsh
-ldsh:
-	ldsh r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/lsl.cgs b/sim/testsuite/sim/arm/thumb/lsl.cgs
deleted file mode 100644
index 05222e7..0000000
--- a/sim/testsuite/sim/arm/thumb/lsl.cgs
+++ /dev/null

@@ -1,14 +0,0 @@
-# arm testcase for lsl $rd,$rs,#$offset5
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global lsl
-lsl:
-	lsl r0,r0,#0
-
-# FIXME: Also lsl $rd,$rs
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/lsr.cgs b/sim/testsuite/sim/arm/thumb/lsr.cgs
deleted file mode 100644
index fe38fe0..0000000
--- a/sim/testsuite/sim/arm/thumb/lsr.cgs
+++ /dev/null

@@ -1,14 +0,0 @@
-# arm testcase for lsr $rd,$rs,#$offset5
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global lsr
-lsr:
-	lsr r0,r0,#0
-
-# FIXME: Also lsr $rd,$rs
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs
deleted file mode 100644
index 2050908..0000000
--- a/sim/testsuite/sim/arm/thumb/mov-hd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mov $hd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_hd_hs
-mov_hd_hs:
-	mov r8,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs b/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs
deleted file mode 100644
index 3d229c3..0000000
--- a/sim/testsuite/sim/arm/thumb/mov-hd-rs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mov $hd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_hd_rs
-mov_hd_rs:
-	mov r8,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs b/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs
deleted file mode 100644
index 0661dfa..0000000
--- a/sim/testsuite/sim/arm/thumb/mov-rd-hs.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mov $rd,$hs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov_rd_hs
-mov_rd_hs:
-	mov r0,r8
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mov.cgs b/sim/testsuite/sim/arm/thumb/mov.cgs
deleted file mode 100644
index b497b0f..0000000
--- a/sim/testsuite/sim/arm/thumb/mov.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mov ${bit10-rd},#$offset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global mov
-mov:
-	mov r0,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mul.cgs b/sim/testsuite/sim/arm/thumb/mul.cgs
deleted file mode 100644
index d160c56..0000000
--- a/sim/testsuite/sim/arm/thumb/mul.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mul $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_mul
-alu_mul:
-	mul r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/mvn.cgs b/sim/testsuite/sim/arm/thumb/mvn.cgs
deleted file mode 100644
index 606ce85..0000000
--- a/sim/testsuite/sim/arm/thumb/mvn.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for mvn $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_mvn
-alu_mvn:
-	mvn r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/neg.cgs b/sim/testsuite/sim/arm/thumb/neg.cgs
deleted file mode 100644
index 09f0c81..0000000
--- a/sim/testsuite/sim/arm/thumb/neg.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for neg $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_neg
-alu_neg:
-	neg r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/orr.cgs b/sim/testsuite/sim/arm/thumb/orr.cgs
deleted file mode 100644
index de6f688..0000000
--- a/sim/testsuite/sim/arm/thumb/orr.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for orr $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_orr
-alu_orr:
-	orr r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/pop-pc.cgs b/sim/testsuite/sim/arm/thumb/pop-pc.cgs
deleted file mode 100644
index 4579cad..0000000
--- a/sim/testsuite/sim/arm/thumb/pop-pc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for pop {${rlist-pc}}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global pop_pc
-pop_pc:
-	pop {0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/pop.cgs b/sim/testsuite/sim/arm/thumb/pop.cgs
deleted file mode 100644
index b156e1d..0000000
--- a/sim/testsuite/sim/arm/thumb/pop.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for pop {$rlist}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global pop
-pop:
-	pop {0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/push-lr.cgs b/sim/testsuite/sim/arm/thumb/push-lr.cgs
deleted file mode 100644
index ee700a4..0000000
--- a/sim/testsuite/sim/arm/thumb/push-lr.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for push {${rlist-lr}}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global push_lr
-push_lr:
-	push {0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/push.cgs b/sim/testsuite/sim/arm/thumb/push.cgs
deleted file mode 100644
index ff94ca5..0000000
--- a/sim/testsuite/sim/arm/thumb/push.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for push {$rlist}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global push
-push:
-	push {0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/ror.cgs b/sim/testsuite/sim/arm/thumb/ror.cgs
deleted file mode 100644
index 991fa66..0000000
--- a/sim/testsuite/sim/arm/thumb/ror.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for ror $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_ror
-alu_ror:
-	ror r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/sbc.cgs b/sim/testsuite/sim/arm/thumb/sbc.cgs
deleted file mode 100644
index 078b061..0000000
--- a/sim/testsuite/sim/arm/thumb/sbc.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for sbc $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_sbc
-alu_sbc:
-	sbc r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/stmia.cgs b/sim/testsuite/sim/arm/thumb/stmia.cgs
deleted file mode 100644
index 0e1c30c..0000000
--- a/sim/testsuite/sim/arm/thumb/stmia.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for stmia $rb!,{$rlist}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global stmia
-stmia:
-	stmia r0!,{0}
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/str-imm.cgs b/sim/testsuite/sim/arm/thumb/str-imm.cgs
deleted file mode 100644
index ce75941..0000000
--- a/sim/testsuite/sim/arm/thumb/str-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for str $rd,[$rb,#${offset5-7}]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_imm
-str_imm:
-	str r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/str-sprel.cgs b/sim/testsuite/sim/arm/thumb/str-sprel.cgs
deleted file mode 100644
index 132edfb..0000000
--- a/sim/testsuite/sim/arm/thumb/str-sprel.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for str ${bit10-rd},[sp,#$word8]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str_sprel
-str_sprel:
-	str r0,[sp,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/str.cgs b/sim/testsuite/sim/arm/thumb/str.cgs
deleted file mode 100644
index 073e20b..0000000
--- a/sim/testsuite/sim/arm/thumb/str.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for str $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global str
-str:
-	str r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/strb-imm.cgs b/sim/testsuite/sim/arm/thumb/strb-imm.cgs
deleted file mode 100644
index 2b5bcf7..0000000
--- a/sim/testsuite/sim/arm/thumb/strb-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for strb $rd,[$rb,#$offset5]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb_imm
-strb_imm:
-	strb r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/strb.cgs b/sim/testsuite/sim/arm/thumb/strb.cgs
deleted file mode 100644
index b7cb763..0000000
--- a/sim/testsuite/sim/arm/thumb/strb.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for strb $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strb
-strb:
-	strb r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/strh-imm.cgs b/sim/testsuite/sim/arm/thumb/strh-imm.cgs
deleted file mode 100644
index 9500288..0000000
--- a/sim/testsuite/sim/arm/thumb/strh-imm.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for strh $rd,[$rb,#${offset5-6}]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh_imm
-strh_imm:
-	strh r0,[r0,#0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/strh.cgs b/sim/testsuite/sim/arm/thumb/strh.cgs
deleted file mode 100644
index 13f3a0d..0000000
--- a/sim/testsuite/sim/arm/thumb/strh.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for strh $rd,[$rb,$ro]
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global strh
-strh:
-	strh r0,[r0,r0]
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/sub-sp.cgs b/sim/testsuite/sim/arm/thumb/sub-sp.cgs
deleted file mode 100644
index e676f58..0000000
--- a/sim/testsuite/sim/arm/thumb/sub-sp.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for add sp,#-$sword7
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub_sp
-sub_sp:
-	add sp,#-0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/sub.cgs b/sim/testsuite/sim/arm/thumb/sub.cgs
deleted file mode 100644
index 91cd7ab..0000000
--- a/sim/testsuite/sim/arm/thumb/sub.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for sub $rd,$rs,$rn
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global sub
-sub:
-	sub r0,r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/subi.cgs b/sim/testsuite/sim/arm/thumb/subi.cgs
deleted file mode 100644
index 044efd0..0000000
--- a/sim/testsuite/sim/arm/thumb/subi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for sub $rd,$rs,#$offset3
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global subi
-subi:
-	sub r0,r0,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/subi8.cgs b/sim/testsuite/sim/arm/thumb/subi8.cgs
deleted file mode 100644
index 0c4d717..0000000
--- a/sim/testsuite/sim/arm/thumb/subi8.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for sub ${bit10-rd},#$offset8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global subi8
-subi8:
-	sub r0,#0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/swi.cgs b/sim/testsuite/sim/arm/thumb/swi.cgs
deleted file mode 100644
index 1724c14..0000000
--- a/sim/testsuite/sim/arm/thumb/swi.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for swi $value8
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global swi
-swi:
-	swi 0
-
-	pass

diff --git a/sim/testsuite/sim/arm/thumb/testutils.inc b/sim/testsuite/sim/arm/thumb/testutils.inc
deleted file mode 100644
index bdae29b..0000000
--- a/sim/testsuite/sim/arm/thumb/testutils.inc
+++ /dev/null

@@ -1,91 +0,0 @@
-# FIXME: wip, copied from ../testutils.inc
-# r0-r3 are used as tmps, consider them call clobbered by these macros.
-# This uses the angel rom monitor calls.
-# ??? How do we use the \@ facility of .macros ???
-# @ is the comment char!
-
-	.macro a_mvi_h_gr reg, val
-	ldr \reg,[pc]
-	b . + 8
-	.word \val
-	.endm
-
-	.macro mvaddr_h_gr reg, addr
-	ldr \reg,[pc]
-	b . + 8
-	.word \val
-	.endm
-
-	.macro start
-	.data
-failmsg:
-	.asciz "fail\n"
-passmsg:
-	.asciz "pass\n"
-	.text
-
-do_pass:
-	ldr r1, passmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 0
-passmsg_addr:
-	.word passmsg
-
-do_fail:
-	ldr r1, failmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 1
-failmsg_addr:
-	.word failmsg
-
-	.global _start
-_start:
-	.endm
-
-# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
-
-	.macro pass
-	b do_pass
-	.endm
-
-	.macro fail
-	b do_fail
-	.endm
-
-	.macro exit rc
-	mov r1, #\rc
-	mov r0, #0x2a @ decimal 42
-	swi #1
-	# If that returns, punt with a sigill.
-	stc 0,cr0,[r0]
-	.endm
-
-# Other macros know this only clobbers r0.
-	.macro test_h_gr reg, val
-	mvaddr_h_gr r0, \val
-	cmp \reg, r0
-	beq . + 8
-	fail
-	.endm
-
-	.macro mvi_h_cc c, n, v, z
-	ldi8 r0, 0
-	ldi8 r1, 1
-	.if xxx
-	cmp r0, r1
-	.else
-	cmp r1, r0
-	.endif
-	.endm
-
-	.macro test_h_cc c, n, v, z
-	.if xxx
-	bc . + 8
-	fail
-	.else
-	bnc . + 8
-	fail
-	.endif
-	.endm

diff --git a/sim/testsuite/sim/arm/thumb/tst.cgs b/sim/testsuite/sim/arm/thumb/tst.cgs
deleted file mode 100644
index 068fccc..0000000
--- a/sim/testsuite/sim/arm/thumb/tst.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for tst $rd,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global alu_tst
-alu_tst:
-	tst r0,r0
-
-	pass

diff --git a/sim/testsuite/sim/arm/tst.cgs b/sim/testsuite/sim/arm/tst.cgs
deleted file mode 100644
index f071707..0000000
--- a/sim/testsuite/sim/arm/tst.cgs
+++ /dev/null

@@ -1,36 +0,0 @@
-# arm testcase for tst${cond}${set-cc?} $rn,$imm12
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global tst_imm
-tst_imm:
-	tst00 pc,0
-
-	pass
-# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global tst_reg_imm_shift
-tst_reg_imm_shift:
-	tst00 pc,pc,pc,lsl 0
-
-	pass
-# arm testcase for tst$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global tst_reg_reg_shift
-tst_reg_reg_shift:
-	tst00 pc,pc,pc,lsl pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/umlal.cgs b/sim/testsuite/sim/arm/umlal.cgs
deleted file mode 100644
index 1c17fb6..0000000
--- a/sim/testsuite/sim/arm/umlal.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for umlal$cond${set-cc?} $rdlo,$rdhi,$rm,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global umlal
-umlal:
-	umlal00 pc,pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/umull.cgs b/sim/testsuite/sim/arm/umull.cgs
deleted file mode 100644
index a58541c..0000000
--- a/sim/testsuite/sim/arm/umull.cgs
+++ /dev/null

@@ -1,12 +0,0 @@
-# arm testcase for umull$cond${set-cc?} $rdlo,$rdhi,$rm,$rs
-# mach: unfinished
-
-	.include "testutils.inc"
-
-	start
-
-	.global umull
-umull:
-	umull00 pc,pc,pc,pc
-
-	pass

diff --git a/sim/testsuite/sim/arm/xscale/blx.cgs b/sim/testsuite/sim/arm/xscale/blx.cgs
deleted file mode 100644
index 854647b..0000000
--- a/sim/testsuite/sim/arm/xscale/blx.cgs
+++ /dev/null

@@ -1,31 +0,0 @@
-# arm testcase for bl$cond $offset24
-# mach: all
-
-	.include "testutils.inc"
-
-	start
-
-        .arm
-        blx thumb
-	
-        .thumb
-	.thumb_func
-thumb:  
-	nop
-        blx     next
-        blx     PASS
-        nop
-        nop
-
-        .section text1, "ax"
-        .arm
-next:
-        add     r0, r1, r0
-        bx      lr
-
-FAIL:
-	fail
-PASS:   
-	pass
-
-

diff --git a/sim/testsuite/sim/arm/xscale/mia.cgs b/sim/testsuite/sim/arm/xscale/mia.cgs
deleted file mode 100644
index a3f729e..0000000
--- a/sim/testsuite/sim/arm/xscale/mia.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# XSCALE testcase for MIA
-# mach: xscale
-# as: -mcpu=xscale
-
-	.include "testutils.inc"
-
-	start
-
-	.global mia
-mia:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar        acc0, r0, r1
-
-	mia	   acc0, r2, r3
-	
-	mra        r0, r1, acc0
-	
-	test_h_gr  r0, 0x354f53c4
-	test_h_gr  r1, 0x4e330b5e
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/xscale/miaph.cgs b/sim/testsuite/sim/arm/xscale/miaph.cgs
deleted file mode 100644
index 53fb201..0000000
--- a/sim/testsuite/sim/arm/xscale/miaph.cgs
+++ /dev/null

@@ -1,35 +0,0 @@
-# XSCALE testcase for MIAPH
-# mach: xscale
-# as: -mcpu=xscale
-
-	.include "testutils.inc"
-
-	start
-
-	.global miaph
-miaph:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar	   acc0, r0, r1
-
-	miaph	   acc0, r2, r3
-	
-	mra	   r0, r1, acc0
-	
-	test_h_gr  r0, 0xfec3f9f4
-	test_h_gr  r1, 0x55667787
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/xscale/miaxy.cgs b/sim/testsuite/sim/arm/xscale/miaxy.cgs
deleted file mode 100644
index 624564e..0000000
--- a/sim/testsuite/sim/arm/xscale/miaxy.cgs
+++ /dev/null

@@ -1,89 +0,0 @@
-# XSCALE testcase for MIAxy
-# mach: xscale
-# as: -mcpu=xscale
-
-	.include "testutils.inc"
-
-	start
-
-	.global miaXY
-miaXY:
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-
-	# Test Bottom Bottom Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar	   acc0, r0, r1
-
-	miaBB	   acc0, r2, r3
-	
-	mra	   r0, r1, acc0
-	
-	test_h_gr  r0, 0x05f753c4
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Bottom Top Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar	   acc0, r0, r1
-
-	miaBT	   acc0, r2, r3
-	
-	mra	   r0, r1, acc0
-	
-	test_h_gr  r0, 0xeeede364
-	test_h_gr  r1, 0x55667787
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Top Bottom Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar	   acc0, r0, r1
-
-	miaTB	   acc0, r2, r3
-	
-	mra	   r0, r1, acc0
-	
-	test_h_gr  r0, 0x0ec85c04
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	# Test Top Top Multilply Accumulate
-	
-	mvi_h_gr   r0, 0x11223344
-	mvi_h_gr   r1, 0x55667788
-	mvi_h_gr   r2, 0x12345678
-	mvi_h_gr   r3, 0x9abcdef0
-
-	mar	   acc0, r0, r1
-
-	miaTT	   acc0, r2, r3
-	
-	mra	   r0, r1, acc0
-	
-	test_h_gr  r0, 0x09eed974
-	test_h_gr  r1, 0x55667788
-	test_h_gr  r2, 0x12345678
-	test_h_gr  r3, 0x9abcdef0
-
-	pass

diff --git a/sim/testsuite/sim/arm/xscale/mra.cgs b/sim/testsuite/sim/arm/xscale/mra.cgs
deleted file mode 100644
index be4d9df..0000000
--- a/sim/testsuite/sim/arm/xscale/mra.cgs
+++ /dev/null

@@ -1,30 +0,0 @@
-# XScale testcase for MAR and MRA
-# mach: xscale
-# as: -mcpu=xscale
-
-	.include "testutils.inc"
-
-	start
-
-	.global mar_mra
-mar_mra:
-	mvi_h_gr   r2,0
-	mvi_h_gr   r3,0
-	mvi_h_gr   r4,0x0000EFA0
-	mvi_h_gr   r5,0xA0A0A0A0
-
-	# Enable access to CoProcessors 0 & 1 before
-        # we attempt these instructions.
-
-	mvi_h_gr   r1, 3
-	mcr        p15, 0, r1, cr15, cr1, 0
-	
-	mar        acc0, r5, r4
-	mra        r2, r3, acc0
-	
-	test_h_gr  r2,0xA0A0A0A0
-	test_h_gr  r3,0x0000EFA0
-	test_h_gr  r4,0x0000EFA0
-	test_h_gr  r5,0xA0A0A0A0
-	
-	pass

diff --git a/sim/testsuite/sim/arm/xscale/testutils.inc b/sim/testsuite/sim/arm/xscale/testutils.inc
deleted file mode 100644
index ae49db8..0000000
--- a/sim/testsuite/sim/arm/xscale/testutils.inc
+++ /dev/null

@@ -1,118 +0,0 @@
-# r0-r3 are used as tmps, consider them call clobbered by these macros.
-# This uses the angel rom monitor calls.
-# ??? How do we use the \@ facility of .macros ???
-# @ is the comment char!
-
-	.macro mvi_h_gr reg, val
-	ldr \reg,[pc]
-	b . + 8
-	.word \val
-	.endm
-
-	.macro mvaddr_h_gr reg, addr
-	ldr \reg,[pc]
-	b . + 8
-	.word \addr
-	.endm
-
-	.macro start
-	.data
-failmsg:
-	.asciz "fail\n"
-passmsg:
-	.asciz "pass\n"
-	.text
-
-do_pass:
-	ldr r1, passmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 0
-passmsg_addr:
-	.word passmsg
-
-do_fail:
-	ldr r1, failmsg_addr
-	mov r0, #4
-	swi #0x123456
-	exit 1
-failmsg_addr:
-	.word failmsg
-
-	.global _start
-_start:
-	.endm
-
-# *** Other macros know pass/fail are 4 bytes in size!  Yuck.
-
-	.macro pass
-	b do_pass
-	.endm
-
-	.macro fail
-	b do_fail
-	.endm
-
-	.macro exit rc
-	# ??? This works with the ARMulator but maybe not others.
-	#mov r0, #\rc
-	#swi #1
-	# This seems to be portable (though it ignores rc).
-	mov r0,#0x18
-	mvi_h_gr r1, 0x20026
-	swi #0x123456
-	# If that returns, punt with a sigill.
-	stc 0,cr0,[r0]
-	.endm
-
-# Other macros know this only clobbers r0.
-# WARNING: It also clobbers the condition codes (FIXME).
-	.macro test_h_gr reg, val
-	mvaddr_h_gr r0, \val
-	cmp \reg, r0
-	beq . + 8
-	fail
-	.endm
-
-	.macro mvi_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	bic r1, r1, #0xf0000000
-	orr r1, r1, r0
-	msr cpsr, r1
-	# ??? nops needed
-	.endm
-
-# ??? Preserve condition codes?
-	.macro test_h_cnvz c, n, v, z
-	mov r0, #0
-	.if \c
-	orr r0, r0, #0x20000000
-	.endif
-	.if \n
-	orr r0, r0, #0x80000000
-	.endif
-	.if \v
-	orr r0, r0, #0x10000000
-	.endif
-	.if \z
-	orr r0, r0, #0x40000000
-	.endif
-	mrs r1, cpsr
-	and r1, r1, #0xf0000000
-	cmp r0, r1
-	beq . + 8
-	fail
-	.endm

diff --git a/sim/testsuite/sim/arm/xscale/xscale.exp b/sim/testsuite/sim/arm/xscale/xscale.exp
deleted file mode 100644
index 3756929..0000000
--- a/sim/testsuite/sim/arm/xscale/xscale.exp
+++ /dev/null

@@ -1,28 +0,0 @@
-# XSCALE simulator testsuite.
-
-if { [istarget xscale*-*-*] } {
-    # load support procs (none yet)
-    # load_lib cgen.exp
-
-    # all machines
-    set all_machs "xscale"
-
-    if [is_remote host] {
-      remote_download host $srcdir/$subdir/testutils.inc
-    }
-
-    # The .cgs suffix is for "cgen .s".
-    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
-	# If we're only testing specific files and this isn't one of them,
-	# skip it.
-	if ![runtest_file_p $runtests $src] {
-	    continue
-	}
-
-	run_sim_test $src $all_machs
-    }
-
-    if [is_remote host] {
-      remote_file host delete testutils.inc
-    }
-}

diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog
deleted file mode 100644
index 83d1b57..0000000
--- a/sim/testsuite/sim/h8300/ChangeLog
+++ /dev/null

@@ -1,200 +0,0 @@
-2003-04-11  Michael Snyder  <msnyder@redhat.com>
-
-	* mac.s: New file.  Test multiply-accumulator insns.
-	* allinsn.exp: Add mac tests.
-
-2003-04-10  Michael Snyder  <msnyder@redhat.com>
-
-	* brabc.s: New file.  Test for bra/bc and bra/bs.
-	* allinsn.exp: Add bra/bc test.
-	* testsuite.inc: New macro memcmp.
-	* bfld.s: Un-comment insns, assembler works now.
-
-	* bfld.s: Add tests for bfst insn.
-	* bfld.s: New file.  Test for bfld insn.
-	* allinsn.exp: Add bfld test.
-
-2003-04-09  Michael Snyder  <msnyder@redhat.com>
-
-	* movmd.s: New file.  Test for movmd insn.
-	* allinsn.exp: Add movmd test.
-	* movsd.s: Un-comment movsd instructions (assembler works now).
-	* movsd.s: New file.  Test for movsd insn.
-	* allinsn.exp: Add movsd test.
-	* add.b.s: Add tests for ABS8 mode.
-
-2003-04-08  Michael Snyder  <msnyder@redhat.com>
-
-	* bset.s: New file, test bset and bclr.
-	* allinsn.exp: Add bset test.
-	* and.b.s: Add test for andc ccr.
-	* or.b.s:  Add test for orc  ccr.
-	* xor.b.s: Add test for xorc ccr.
-
-2003-04-07  Michael Snyder  <msnyder@redhat.com>
-
-	* testutils.inc (_write_and_exit): Rewrite for new syscall lib.
-	(pass, fail): Use new syscall abi.
-
-2003-04-04  Michael Snyder  <msnyder@redhat.com>
-
-	* rotl.s: Add INDEXB, INDEXW, INDEXL tests.
-	* rotl.s, rotr.s, rotxl.s, rotxr.s: New files.
-	* allinsn.exp: Add rot insn tests.
-
-2003-04-03  Michael Snyder  <msnyder@redhat.com>
-
-	* shift.s: Remove.  Replace with
-	* shal.s, shar.s, shll.s, shlr.s: New files.
-	* allinsn.exp: Invoke new test files.
-	* ext.w.s, ext.l.s: New files, tests for exts and extu.
-
-2003-04-02  Michael Snyder  <msnyder@redhat.com>
-
-	* bra.s: New file, test for branch insns.
-	* allinsn.exp: Add bra.s.
-	* adds.s: Add ccr flags checking.
-
-2003-04-01  Michael Snyder  <msnyder@redhat.com>
-
-	* shift.s: Add lots of tests.
-	* mov.b.s: Add word and long tests.
-	* neg.s: New file, test neg instructions.
-	* allinsn.exp: Add neg test.
-
-2003-03-31  Michael Snyder  <msnyder@redhat.com>
-
-	* addx.s: Add word and long tests.
-
-2003-03-28  Michael Snyder  <msnyder@redhat.com>
-
-	* mov.w.s: Add a bunch more tests for new addressing modes.
-	* add.l.s: Comment fixes.
-	* not.s: Add tests for word and long operations.
-	* not.s: Fill out remaining tests for byte operation.
-	* add.l.s: Fix up .if directives for h8h, h8s.
-	* mov.l.s: Simplify results checking.
-	* add.l.s: Add several dozen new tests for new addressing modes.
-
-2003-03-25  Michael Snyder  <msnyder@redhat.com>
-
-	* mov.l.s: A sampling of tests for esoteric addressing modes.
-	* mov.l.s: Finish tests for immediate and register direct modes.
-	* mov.l.s: Simplify, add more tests.
-	* mov.l.s: Add more new tests.
-
-2003-03-13  Michael Snyder  <msnyder@redhat.com>
-
-	* not.s: New test.
-	* allinsn.exp: Add not.s test.
-	* add.b.s, add.w.s, addx.s and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
-	Un-comment assembler instructions: assembler should handle 'em all.
-
-2003-03-04  Michael Snyder  <msnyder@redhat.com>
-
-	* add.b.s: Add DISP16, DISP32, ABS16, ABS32.
-	* sub.b.s: Add POSTINC, POSTDEC, RDIND.
-	* or.b.s, xor.b.s: Add RDPOSTINC, RDPREINC, RDPREDEC.
-
-2003-03-03  Michael Snyder  <msnyder@redhat.com>
-
-	* add.b.s, addx.s, and.b.s, cmp.b.s: Add RDPOSTINC, 
-	RDPREINC, RDPREDEC.
-	* add.b.s, addx.s, and.b.s, cmp.b.s, or.b.s, xor.b.s: Add RDPOSTDEC.
-
-2003-02-28  Michael Snyder  <msnyder@redhat.com>
-
-	* add.b.s, and.b.s, cmp.b.s, or.b.s, sub.b.s, xor.b.s:
-	Add tests for RDIND.  Also add RDPOSTDEC to cmp.b.s.
-	* allinsn.exp: All tests run for all machine flavors.
-
-2003-02-27  Michael Snyder  <msnyder@redhat.com>
-
-	* add.l.s, adds.s, addx.s, and.l.s, cmp.l.s, cmp.w.s, jmp.s, 
-	or.l.s, or.w.s, sub.l.s, sub.w.s, xor.l.s, xor.w.s): 
-	Substitute actual assembler instructions for data words!
-	* addx.s: Add tests for RDIND and RDPOSTDEC.
-	* shifts.s: New file.
-	* allinsn.exp: Add shifts.s.
-	* testutils.inc: Add assembler directive ".h8300sx".
-	* add.w.s, add.l.s, ...: Add linker directive "-m h8300sxelf".
-
-2003-02-25  Michael Snyder  <msnyder@redhat.com>
-
-	* adds.s, addw.s: New files.
-	* testutils.inc (set_ccr, set_carry_flag, test_carry_clear,
-	test_carry_set, test_ovf_clear, test_ovf_set, test_zero_clear,
-	test_zero_set, test_neg_clear, test_neg_set): New macros.
-
-2003-02-24  Michael Snyder  <msnyder@redhat.com>
-
-	* stc.c: Extend tests to all h8300s opcodes.
-	* ldc.s: New file.
-
-	* stc.s: New file.
-	* allinsn.exp: Add stc test.
-	* and.l.s: 'and.l imm:16 clears upper half of dest. reg.
-	* testutils.inc: Add kludge for h8sx.
-	(set_gr_a5a5, set_grs_a5a5, test_gr_a5a5, test_grs_a5a5,
-	set_ccr_zero): New macros.
-
-2003-02-18  Michael Snyder  <msnyder@redhat.com>
-
-	* daa.s: New file.
-	* das.s: New file.
-	* dec.s: New file.
-	* inc.s: New file.
-	* or.b.s: New file.
-	* or.w.s: New file.
-	* or.l.s: New file.
-	* xor.b.s: New file.
-	* xor.w.s: New file.
-	* xor.l.s: New file.
-	* and.l.s: Fix expected result.
-	* allinsn.exp: Add new tests.
-
-2003-02-12  Michael Snyder  <msnyder@redhat.com>
-
-	* and.b.s: New file.
-	* and.w.s: New file.
-	* and.l.s: New file.
-	* cmp.b.s: New file.
-	* cmp.w.s: New file.
-	* cmp.l.s: New file.
-	* jmp.s: New file.
-	* add.w.s: Add test for 3-bit immediate operand.
-	* add.l.s: Add test for 3-bit and 16-bit immediate operands.
-	* mov.b.s (dst_addr16, dst_addr32): Delete.	
-	* nop.s: Simplify using testutils.inc macros.
-	* sub.w.s: Add test for 3-bit immediate operand.
-	* sub.l.s: Add test for 3-bit and 16-bit immediate operands.
-
-2003-02-07  Michael Snyder  <msnyder@redhat.com>
-
-	* mov.b.s: Add tests for more addressing modes.
-	(src_addr16, src_addr32, dst_addr16, dst_addr32): Delete.
-	* mov.b.s: Add prospective tests for h8sx modes.
-	* mov.w.s: New file (test for 'mov.w').
-	* mov.l.s: New file (test for 'mov.l').
-	* sub.b.s: New file (test for 'sub.b').
-	* sub.w.s: New file (test for 'sub.w').
-	* sub.l.s: New file (test for 'sub.l').
-	* allinsn.exp: Turn new tests on.
-
-2003-02-06  Michael Snyder  <msnyder@redhat.com>
-
-	* allinsn.exp: New file.
-	* testutils.inc: New file.
-	* nop.s: New file (test for 'nop' insn).
-	* add.b.s: New file (test for 'add.b').
-	* add.w.s: New file (test for 'add.w').
-	* add.l.s: New file (test for 'add.l').
-	* mov.b.s: New file (test for 'mov.b');
-
-Local Variables:
-mode: change-log
-left-margin: 8
-fill-column: 74
-version-control: never
-change-log-default-name: "ChangeLog"
-End:

diff --git a/sim/testsuite/sim/h8300/add.b.s b/sim/testsuite/sim/h8300/add.b.s
deleted file mode 100644
index f1e4ebf..0000000
--- a/sim/testsuite/sim/h8300/add.b.s
+++ /dev/null

@@ -1,778 +0,0 @@
-# Hitachi H8 testcase 'add.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# add.b #xx:8, rd	;                     8   rd xxxxxxxx
-	# add.b #xx:8, @erd	;         7 d rd ???? 8 ???? xxxxxxxx
-	# add.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
-	# add.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
-	# add.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
-	# add.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
-	# add.b #xx:8, @(d:16, erd)	; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
-	# add.b #xx:8, @(d:32, erd)	; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
-	# add.b #xx:8, @aa:8		; 7 f aaaaaaaa 8 ???? xxxxxxxx
-	# add.b #xx:8, @aa:16		; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
-	# add.b #xx:8, @aa:32		; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
-	# add.b rs, rd		;                     0 8 rs rd
-	# add.b reg8, @erd	;         7 d rd ???? 0 8 rs ????
-	# add.b reg8, @erd+	;         0 1 7     9 8 rd 1 rs
-	# add.b reg8, @erd-	;         0 1 7     9 a rd 1 rs
-	# add.b reg8, @+erd	;         0 1 7     9 9 rd 1 rs
-	# add.b reg8, @-erd	;         0 1 7     9 b rd 1 rs
-	# add.b reg8, @(d:16, erd)	; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
-	# add.b reg8, @(d:32, erd)	; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
-	# add.b reg8, @aa:8		; 7 f aaaaaaaa 0 8 rs ????
-	# add.b reg8, @aa:16		; 6 a 1 1??? aa:16 0 8 rs ????
-	# add.b reg8, @aa:32		; 6 a 3 1??? aa:32 0 8 rs ????
-	#
-
-	# Coming soon:
-	# add.b #xx:8, @(d:2, erd)	; 0 1 7 b30 | b21 | dd:2,  8 ???? xxxxxxxx
-	# add.b reg8, @(d:2, erd)	; 0 1 7 9 dd:2 rd32 1 rs8
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0
-post_byte:	.byte 0
-
-	start
-	
-add_b_imm8_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.b #xx:8,Rd
-	add.b	#5:8, r0l	; Immediate 8-bit src, reg8 dst
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5aa r0	; add result:	a5 + 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5aa er0	; add result:	 a5 + 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-add_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	add.b	#5:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest, er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#5, r0l
-	beq	.L1
-	fail
-.L1:
-
-add_b_imm8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	add.b	#5:8, @er0+	; Immediate 8-bit src, reg post-inc dst
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 post_byte, er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#10, r0l
-	beq	.L2
-	fail
-.L2:
-
-add_b_imm8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	add.b	#5:8, @er0-	; Immediate 8-bit src, reg post-dec dst
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 pre_byte, er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#15, r0l
-	beq	.L3
-	fail
-.L3:
-
-add_b_imm8_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@+eRd
-	mov	#pre_byte, er0
-	add.b	#5:8, @+er0	; Immediate 8-bit src, reg pre-inc dst
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#20, r0l
-	beq	.L4
-	fail
-.L4:
-
-add_b_imm8_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@-eRd
-	mov	#post_byte, er0
-	add.b	#5:8, @-er0	; Immediate 8-bit src, reg pre-dec dst
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#25, r0l
-	beq	.L5
-	fail
-.L5:
-
-add_b_imm8_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@(dd:16, eRd)
-	mov	#post_byte, er0
-	add.b	#5:8, @(-1:16, er0)	; Immediate 8-bit src, 16-bit reg disp dest.
-;;; 	.word	0x0174
-;;; 	.word	0x6e08
-;;; 	.word	0xffff
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32   post_byte, er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#30, r0l
-	beq	.L6
-	fail
-.L6:
-
-add_b_imm8_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@(dd:32, eRd)
-	mov	#pre_byte, er0
-	add.b	#5:8, @(1:32, er0)	; Immediate 8-bit src, 32-bit reg disp. dest.
-;;; 	.word	0x7804
-;;; 	.word	0x6a28
-;;; 	.word	0x0000
-;;; 	.word	0x0001
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 pre_byte, er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#35, r0l
-	beq	.L7
-	fail
-.L7:
-
-add_b_imm8_abs8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b reg8,@aa:8
-	;; NOTE: for abs8, we will use the SBR register as a base,
-	;; since otherwise we would have to make sure that the destination
-	;; was in the zero page.
-	;;
-	mov	#byte_dest-100, er0
-	ldc	er0, sbr
-	add.b	#5, @100:8	; 8-bit reg src, 8-bit absolute dest
-;;; 	.word	0x7f64
-;;; 	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32  byte_dest-100, er0	; reg 0 has base address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#40, r0l
-	beq	.L8
-	fail
-.L8:
-
-add_b_imm8_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@aa:16
-	add.b	#5:8, @byte_dest:16	; Immediate 8-bit src, 16-bit absolute dest
-;;;  	.word	0x6a18
-;;; 	.word	byte_dest
-;;;  	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#45, r0l
-	beq	.L9
-	fail
-.L9:
-
-add_b_imm8_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b #xx:8,@aa:32
-	add.b	#5:8, @byte_dest:32	; Immediate 8-bit src, 32-bit absolute dest
-;;;  	.word	0x6a38
-;;; 	.long	byte_dest
-;;;  	.word	0x8005
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#50, r0l
-	beq	.L10
-	fail
-.L10:
-
-.endif
-
-add_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.b Rs,Rd
-	mov.b	#5, r0h
-	add.b	r0h, r0l	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0x05aa r0	; add result:	a5 + 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a505aa er0	; add result:	a5 + 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-add_b_reg8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@eRd	; Add to register indirect
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	add.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x0890
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#55, r0l
-	beq	.L11
-	fail
-.L11:
-
-add_b_reg8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@eRd+	; Add to register post-increment
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	add.b	r1l, @er0+	; reg8 src, reg post-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x8019
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#60, r0l
-	beq	.L12
-	fail
-.L12:
-
-add_b_reg8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@eRd-	; Add to register post-decrement
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	add.b	r1l, @er0-	; reg8 src, reg post-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xa019
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#65, r0l
-	beq	.L13
-	fail
-.L13:
-
-add_b_reg8_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@+eRd	; Add to register pre-increment
-	mov	#pre_byte, er0
-	mov	#5, r1l
-	add.b	r1l, @+er0	; reg8 src, reg pre-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x9019
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#70, r0l
-	beq	.L14
-	fail
-.L14:
-
-add_b_reg8_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@-eRd	; Add to register pre-decrement
-	mov	#post_byte, er0
-	mov	#5, r1l
-	add.b	r1l, @-er0	; reg8 src, reg pre-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xb019
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#75, r0l
-	beq	.L15
-	fail
-.L15:
-
-add_b_reg8_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@(dd:16, eRd)	; Add to register + 16-bit displacement
-	mov	#pre_byte, er0
-	mov	#5, r1l
-	add.b	r1l, @(1:16, er0)	; reg8 src, 16-bit reg disp dest
-;;;  	.word	0x0179
-;;;  	.word	0xc019
-;;;  	.word	0x0001
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#80, r0l
-	beq	.L16
-	fail
-.L16:
-
-add_b_reg8_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b rs8,@-eRd	; Add to register plus 32-bit displacement
-	mov	#post_byte, er0
-	mov	#5, r1l
-	add.b	r1l, @(-1:32, er0)	; reg8 src, 32-bit reg disp dest
-;;; 	.word	0x0179
-;;; 	.word	0xd819
-;;; 	.word	0xffff
-;;; 	.word	0xffff
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#85, r0l
-	beq	.L17
-	fail
-.L17:
-
-add_b_reg8_abs8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b reg8,@aa:8
-	;; NOTE: for abs8, we will use the SBR register as a base,
-	;; since otherwise we would have to make sure that the destination
-	;; was in the zero page.
-	;;
-	mov	#byte_dest-100, er0
-	ldc	er0, sbr
-	mov	#5, r1l
-	add.b	r1l, @100:8	; 8-bit reg src, 8-bit absolute dest
-;;; 	.word	0x7f64
-;;; 	.word	0x0890
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32  byte_dest-100, er0	; reg 0 has base address
-	test_h_gr32  0xa5a5a505 er1	; reg 1 has test load
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#90, r0l
-	beq	.L18
-	fail
-.L18:
-
-add_b_reg8_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b reg8,@aa:16
-	mov	#5, r0l
-	add.b	r0l, @byte_dest:16	; 8-bit reg src, 16-bit absolute dest
-;;; 	.word	0x6a18
-;;; 	.word	byte_dest
-;;; 	.word	0x0880
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32  0xa5a5a505 er0	; reg 0 has test load
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#95, r0l
-	beq	.L19
-	fail
-.L19:
-
-add_b_reg8_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.b reg8,@aa:32
-	mov	#5, r0l
-	add.b	r0l, @byte_dest:32	; 8-bit reg src, 32-bit absolute dest
-;;; 	.word	0x6a38
-;;; 	.long	byte_dest
-;;; 	.word	0x0880
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er0	; reg 0 has test load
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#100, r0l
-	beq	.L20
-	fail
-.L20:
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/add.l.s b/sim/testsuite/sim/h8300/add.l.s
deleted file mode 100644
index 1673c5c..0000000
--- a/sim/testsuite/sim/h8300/add.l.s
+++ /dev/null

@@ -1,1865 +0,0 @@
-# Hitachi H8 testcase 'add.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# add.l xx:3, erd
-	# add.l xx:16, erd
-	# add.l xx:32, erd
-	# add.l xx:16, @erd
-	# add.l xx:16, @erd+
-	# add.l xx:16, @erd-
-	# add.l xx:16, @+erd
-	# add.l xx:16, @-erd
-	# add.l xx:16, @(dd:2, erd)
-	# add.l xx:16, @(dd:16, erd)
-	# add.l xx:16, @(dd:32, erd)
-	# add.l xx:16, @aa:16
-	# add.l xx:16, @aa:32
-	# add.l xx:32, @erd+
-	# add.l xx:32, @erd-
-	# add.l xx:32, @+erd
-	# add.l xx:32, @-erd
-	# add.l xx:32, @(dd:2, erd)
-	# add.l xx:32, @(dd:16, erd)
-	# add.l xx:32, @(dd:32, erd)
-	# add.l xx:32, @aa:16
-	# add.l xx:32, @aa:32
-	# add.l ers, erd
-	# add.l ers, @erd
-	# add.l ers, @erd+
-	# add.l ers, @erd-
-	# add.l ers, @+erd
-	# add.l ers, @-erd
-	# add.l ers, @(dd:2, erd)
-	# add.l ers, @(dd:16, erd)
-	# add.l ers, @(dd:32, erd)
-	# add.l ers, @aa:16
-	# add.l ers, @aa:32
-	# add.l ers, erd
-	# add.l @ers, erd
-	# add.l @ers+, erd
-	# add.l @ers-, erd
-	# add.l @+ers, erd
-	# add.l @-ers, erd
-	# add.l @(dd:2, ers), erd
-	# add.l @(dd:16, ers), erd
-	# add.l @(dd:32, ers), erd
-	# add.l @aa:16, erd
-	# add.l @aa:32, erd
-	# add.l @ers, @erd
-	# add.l @ers+, @erd+
-	# add.l @ers-, @erd-
-	# add.l @+ers, +@erd
-	# add.l @-ers, @-erd
-	# add.l @(dd:2, ers), @(dd:2, erd)
-	# add.l @(dd:16, ers), @(dd:16, erd)
-	# add.l @(dd:32, ers), @(dd:32, erd)
-	# add.l @aa:16, @aa:16
-	# add.l @aa:32, @aa:32
-
-	start
-
-	.data
-	.align	4
-long_src:
-	.long	0x12345678
-long_dst:
-	.long	0x87654321
-
-	.text
-
-	;;
-	;; Add long from immediate source
-	;; 
-
-.if (sim_cpu == h8sx)
-add_l_imm3_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:3, erd
-	add.l	#0x3:3, er0	; Immediate 16-bit operand
-;;;	.word	0x0ab8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a5a8 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_imm16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, erd
-	add.l	#0x1234, er0	; Immediate 16-bit operand
-;;;	.word	0x7a18
-;;;	.word	0x1234
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5b7d9 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-add_l_imm32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, erd
-	add.l	#0x12345678, er0	; Immediate 32-bit operand
-;;;	.word	0x7a10
-;;;	.long	0x12345678
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-add_l_imm16_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @erd
-	mov.l	#long_dst, er1
-	add.l	#0xdead:16, @er1	; Register indirect operand
-;;;	.word	0x010e
-;;;	.word	0x0110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext11
-	fail
-.Lnext11:
-	mov.l	#0x87654321, @long_dst	; Initialize it again for the next use.
-
-add_l_imm16_to_postinc:		; post-increment from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @erd+
-	mov.l	#long_dst, er1
-	add.l	#0xdead:16, @er1+	; Imm16, register post-incr operands.
-;;;	.word	0x010e
-;;;	.word	0x8110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext12
-	fail
-.Lnext12:
-	mov.l	#0x87654321, @long_dst	; initialize it again for the next use.
-
-add_l_imm16_to_postdec:		; post-decrement from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @erd-
-	mov.l	#long_dst, er1
-	add.l	#0xdead:16, @er1-	; Imm16, register post-decr operands.
-;;;	.word	0x010e
-;;;	.word	0xa110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext13
-	fail
-.Lnext13:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @+erd
-	mov.l	#long_dst-4, er1
-	add.l	#0xdead:16, @+er1	; Imm16, register pre-incr operands
-;;;	.word	0x010e
-;;;	.word	0x9110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext14
-	fail
-.Lnext14:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @-erd
-	mov.l	#long_dst+4, er1
-	add.l	#0xdead:16, @-er1	; Imm16, register pre-decr operands
-;;;	.word	0x010e
-;;;	.word	0xb110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext15
-	fail
-.Lnext15:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	add.l	#0xdead:16, @(3:2, er1)	; Imm16, reg plus 2-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0x3110
-;;;	.word	0xdead
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext16
-	fail
-.Lnext16:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	add.l	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0xc110
-;;;	.word	0xdead
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext17
-	fail
-.Lnext17:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	add.l	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0xc910
-;;;	.word	0xdead
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext18
-	fail
-.Lnext18:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @aa:16
-	add.l	#0xdead:16, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x010e
-;;;	.word	0x4010
-;;;	.word	0xdead
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext19
-	fail
-.Lnext19:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm16_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:16, @aa:32
-	add.l	#0xdead:16, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x010e
-;;;	.word	0x4810
-;;;	.word	0xdead
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x876621ce, @long_dst
-	beq	.Lnext20
-	fail
-.Lnext20:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @erd
-	mov.l	#long_dst, er1
-	add.l	#0xcafedead:32, @er1	; Register indirect operand
-;;;	.word	0x010e
-;;;	.word	0x0118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext21
-	fail
-.Lnext21:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_postinc:		; post-increment from imm32 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @erd+
-	mov.l	#long_dst, er1
-	add.l	#0xcafedead:32, @er1+	; Imm32, register post-incr operands.
-;;;	.word	0x010e
-;;;	.word	0x8118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext22
-	fail
-.Lnext22:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_postdec:		; post-decrement from imm32 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @erd-
-	mov.l	#long_dst, er1
-	add.l	#0xcafedead:32, @er1-	; Imm32, register post-decr operands.
-;;;	.word	0x010e
-;;;	.word	0xa118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext23
-	fail
-.Lnext23:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @+erd
-	mov.l	#long_dst-4, er1
-	add.l	#0xcafedead:32, @+er1	; Imm32, register pre-incr operands
-;;;	.word	0x010e
-;;;	.word	0x9118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext24
-	fail
-.Lnext24:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @-erd
-	mov.l	#long_dst+4, er1
-	add.l	#0xcafedead:32, @-er1	; Imm32, register pre-decr operands
-;;;	.word	0x010e
-;;;	.word	0xb118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext25
-	fail
-.Lnext25:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	add.l	#0xcafedead:32, @(3:2, er1)	; Imm32, reg plus 2-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0x3118
-;;;	.long	0xcafedead
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext26
-	fail
-.Lnext26:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	add.l	#0xcafedead:32, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0xc118
-;;;	.long	0xcafedead
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext27
-	fail
-.Lnext27:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	add.l	#0xcafedead:32, @(8:32, er1)   ; Register plus 32-bit disp. operand
-;;;	.word	0x010e
-;;;	.word	0xc918
-;;;	.long	0xcafedead
-;;;	.long	8
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext28
-	fail
-.Lnext28:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l #xx:32, @aa:16
-	add.l	#0xcafedead:32, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x010e
-;;;	.word	0x4018
-;;;	.long	0xcafedead
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext29
-	fail
-.Lnext29:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_imm32_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  add.l #xx:32, @aa:32
-	add.l	#0xcafedead:32, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x010e
-;;;	.word	0x4818
-;;;	.long	0xcafedead
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x526421ce, @long_dst
-	beq	.Lnext30
-	fail
-.Lnext30:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-.endif
-
-	;;
-	;; Add long from register source
-	;; 
-
-add_l_reg32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, erd
-	mov.l	#0x12345678, er1
-	add.l	er1, er0	; Register 32-bit operand
-;;;	.word	0x0a90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-	
-	test_h_gr32 0xb7d9fc1d er0	; add result
-	test_h_gr32 0x12345678 er1	; add src unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-add_l_reg32_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @erd
-	mov.l	#long_dst, er1
-	add.l	er0, @er1	; Register indirect operand
-;;;	.word	0x0109
-;;;	.word	0x0110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext44
-	fail
-.Lnext44:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_postinc:		; post-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @erd+
-	mov.l	#long_dst, er1
-	add.l	er0, @er1+	; Register post-incr operand
-;;;	.word	0x0109
-;;;	.word	0x8110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext49
-	fail
-.Lnext49:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_postdec:		; post-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @erd-
-	mov.l	#long_dst, er1
-	add.l	er0, @er1-	; Register post-decr operand
-;;;	.word	0x0109
-;;;	.word	0xa110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext50
-	fail
-.Lnext50:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @+erd
-	mov.l	#long_dst-4, er1
-	add.l	er0, @+er1	; Register pre-incr operand
-;;;	.word	0x0109
-;;;	.word	0x9110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext51
-	fail
-.Lnext51:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @-erd
-	mov.l	#long_dst+4, er1
-	add.l	er0, @-er1	; Register pre-decr operand
-;;;	.word	0x0109
-;;;	.word	0xb110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext48
-	fail
-.Lnext48:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	add.l	er0, @(3:2, er1)	; Register plus 2-bit disp. operand
-;;;	.word	0x0109
-;;;	.word	0x3110
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext52
-	fail
-.Lnext52:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	add.l	er0, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x0109
-;;;	.word	0xc110
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext45
-	fail
-.Lnext45:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	add.l	er0, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x0109
-;;;	.word	0xc910
-;;;	.long	8
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext46
-	fail
-.Lnext46:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @aa:16
-	add.l	er0, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x0109
-;;;	.word	0x4110
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext41
-	fail
-.Lnext41:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-add_l_reg32_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l ers, @aa:32
-	add.l	er0, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x0109
-;;;	.word	0x4910
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=1 C=1
-	test_neg_clear
-	test_zero_clear
-	test_ovf_set
-	test_carry_set
-	
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x2d0ae8c6, @long_dst
-	beq	.Lnext42
-	fail
-.Lnext42:
-	mov.l	#0x87654321, @long_dst	; Re-initialize it for the next use.
-
-	;;
-	;; Add long to register destination.
-	;; 
-
-add_l_indirect_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers, Rd
-	mov.l	#long_src, er1
-	add.l	@er1, er0	; Register indirect operand
-;;;	.word	0x010a
-;;;	.word	0x0110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_postinc_to_reg32:		; post-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers+, erd
-	mov.l	#long_src, er1
-	add.l	@er1+, er0	; Register post-incr operand
-;;;	.word	0x010a
-;;;	.word	0x8110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_h_gr32	long_src+4, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_postdec_to_reg32:		; post-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers-, erd
-	mov.l	#long_src, er1
-	add.l	@er1-, er0	; Register post-decr operand
-;;;	.word	0x010a
-;;;	.word	0xa110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_h_gr32	long_src-4, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_preinc_to_reg32:		; pre-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @+ers, erd
-	mov.l	#long_src-4, er1
-	add.l	@+er1, er0	; Register pre-incr operand
-;;;	.word	0x010a
-;;;	.word	0x9110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_predec_to_reg32:		; pre-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @-ers, erd
-	mov.l	#long_src+4, er1
-	add.l	@-er1, er0	; Register pre-decr operand
-;;;	.word	0x010a
-;;;	.word	0xb110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	
-add_l_disp2_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:2, ers), erd
-	mov.l	#long_src-1, er1
-	add.l	@(1:2, er1), er0	; Register plus 2-bit disp. operand
-;;; 	.word	0x010a
-;;; 	.word	0x1110
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src-1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_disp16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:16, ers), erd
-	mov.l	#long_src+0x1234, er1
-	add.l	@(-0x1234:16, er1), er0	; Register plus 16-bit disp. operand
-;;;	.word	0x010a
-;;;	.word	0xc110
-;;;	.word	-0x1234
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src+0x1234, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_disp32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:32, ers), erd
-	mov.l	#long_src+65536, er1
-	add.l	@(-65536:32, er1), er0	; Register plus 32-bit disp. operand
-;;;	.word	0x010a
-;;;	.word	0xc910
-;;;	.long	-65536
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src+65536, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_abs16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @aa:16, erd
-	add.l	@long_src:16, er0	; 16-bit address-direct operand
-;;;	.word	0x010a
-;;;	.word	0x4010
-;;;	.word	@long_src
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-add_l_abs32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @aa:32, erd
-	add.l	@long_src:32, er0	; 32-bit address-direct operand
-;;;	.word	0x010a
-;;;	.word	0x4810
-;;;	.long	@long_src
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xb7d9fc1d er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-
-	;;
-	;; Add long from memory to memory
-	;; 
-
-add_l_indirect_to_indirect:	; reg indirect, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers, @erd
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	add.l	@er1, @er0
-;;;	.word	0x0104
-;;;	.word	0x691c
-;;;	.word	0x0010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst	; FIXME
-	beq	.Lnext55
-	fail
-.Lnext55:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext56
-	fail
-.Lnext56:			; OK, pass on.
-
-add_l_postinc_to_postinc:	; reg post-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers+, @erd+
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	add.l	@er1+, @er0+
-;;;	.word	0x0104
-;;;	.word	0x6d1c
-;;;	.word	0x8010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst+4 er0
-	test_h_gr32  long_src+4 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext65
-	fail
-.Lnext65:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext66
-	fail
-.Lnext66:			; OK, pass on.
-
-add_l_postdec_to_postdec:	; reg post-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @ers-, @erd-
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	add.l	@er1-, @er0-
-;;;	.word	0x0106
-;;;	.word	0x6d1c
-;;;	.word	0xa010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-4 er0
-	test_h_gr32  long_src-4 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext75
-	fail
-.Lnext75:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext76
-	fail
-.Lnext76:			; OK, pass on.
-
-add_l_preinc_to_preinc:		; reg pre-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @+ers, @+erd
-	mov.l	#long_src-4, er1
-	mov.l	#long_dst-4, er0
-	add.l	@+er1, @+er0
-;;;	.word	0x0105
-;;;	.word	0x6d1c
-;;;	.word	0x9010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext85
-	fail
-.Lnext85:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext86
-	fail
-.Lnext86:				; OK, pass on.
-
-add_l_predec_to_predec:		; reg pre-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @-ers, @-erd
-	mov.l	#long_src+4, er1
-	mov.l	#long_dst+4, er0
-	add.l	@-er1, @-er0
-;;;	.word	0x0107
-;;;	.word	0x6d1c
-;;;	.word	0xb010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext95
-	fail
-.Lnext95:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext96
-	fail
-.Lnext96:			; OK, pass on.
-
-add_l_disp2_to_disp2:		; reg 2-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:2, ers), @(dd:2, erd)
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	add.l	@(1:2, er1), @(2:2, er0)
-;;; 	.word	0x0105
-;;;	.word	0x691c
-;;; 	.word	0x2010
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext105
-	fail
-.Lnext105:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext106
-	fail
-.Lnext106:			; OK, pass on.
-
-add_l_disp16_to_disp16:		; reg 16-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:16, ers), @(dd:16, erd)
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	add.l	@(1:16, er1), @(2:16, er0)
-;;; 	.word	0x0104
-;;;	.word	0x6f1c
-;;; 	.word	0x0001
-;;; 	.word	0xc010
-;;; 	.word	0x0002
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext115
-	fail
-.Lnext115:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext116
-	fail
-.Lnext116:			; OK, pass on.
-
-add_l_disp32_to_disp32:		; reg 32-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @(dd:32, ers), @(dd:32, erd)
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	add.l	@(1:32, er1), @(2:32, er0)
-;;; 	.word	0x7894
-;;;	.word	0x6b2c
-;;; 	.word	0xc9c8
-;;;	.long	1
-;;;	.word	0xc810
-;;;	.long	2
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext125
-	fail
-.Lnext125:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext126
-	fail
-.Lnext126:				; OK, pass on.
-
-add_l_abs16_to_abs16:		; 16-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @aa:16, @aa:16
-	add.l	@long_src:16, @long_dst:16
-;;; 	.word	0x0104
-;;;	.word	0x6b0c
-;;;	.word	@long_src
-;;; 	.word	0x4010
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext135
-	fail
-.Lnext135:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext136
-	fail
-.Lnext136:				; OK, pass on.
-
-add_l_abs32_to_abs32:		; 32-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; add.l @aa:32, @aa:32
-	add.l	@long_src:32, @long_dst:32
-;;; 	.word	0x0104
-;;;	.word	0x6b2c
-;;;	.long	@long_src
-;;; 	.word	0x4810
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0x99999999, @long_dst
-	beq	.Lnext145
-	fail
-.Lnext145:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0x87654321, @long_dst
-	cmp.l	#0x99999999, @long_dst
-	bne	.Lnext146
-	fail
-.Lnext146:				; OK, pass on.
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/add.w.s b/sim/testsuite/sim/h8300/add.w.s
deleted file mode 100644
index c38bf69..0000000
--- a/sim/testsuite/sim/h8300/add.w.s
+++ /dev/null

@@ -1,87 +0,0 @@
-# Hitachi H8 testcase 'add.w'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# add.w xx:3, rd	; 0 a 0xxx rd	(sx only)
-	# add.w xx:16, rd	; 7 9 1 rd imm16
-	# add.w rs, rd		; 0 9 rs rd
-	#
-
-	start
-	
-.if (sim_cpu == h8sx)		; 3-bit immediate mode only for h8sx
-add_w_imm3:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.w #xx:3,Rd	; Immediate 3-bit operand
-	add.w	#7, r0		; FIXME will not assemble yet
-;	.word	0x0a70		; Fake it until assembler will take it.
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5ac r0	; add result:	a5a5 + 7
-	test_h_gr32 0xa5a5a5ac er0	; add result:	a5a5 + 7
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-	
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-add_w_imm16:
-	;; add.w immediate not available in h8300 mode.
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.w #xx:16,Rd
-	add.w	#0x111, r0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa6b6 r0	; add result:	a5a5 + 111
-	test_h_gr32 0xa5a5a6b6 er0	; add result:	a5a5 + 111
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-	
-add_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.w Rs,Rd
-	mov.w	#0x111, r1
-	add.w	r1, r0		; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa6b6 r0	; add result:	a5a5 + 111
-	test_h_gr16 0x0111 r1
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a6b6 er0	; add result:	a5a5 + 111
-	test_h_gr32 0xa5a50111 er1
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/adds.s b/sim/testsuite/sim/h8300/adds.s
deleted file mode 100644
index 9789e87..0000000
--- a/sim/testsuite/sim/h8300/adds.s
+++ /dev/null

@@ -1,74 +0,0 @@
-# Hitachi H8 testcase 'adds'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# adds #1, erd		; 0 b 0 xerd
-	# adds #2, erd		; 0 b 8 xerd
-	# adds #4, erd		; 0 b 9 xerd
-	#
-
-	start
-.if (sim_cpu)			; 32 bit only
-adds_1:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	adds	#1, er0
-
-	test_cc_clear		; adds should not affect any condition codes
-	test_h_gr32  0xa5a5a5a6 er0	; result of adds #1
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-adds_2:
-	set_grs_a5a5
-	set_ccr_zero
-
-	adds	#2, er0
-
-	test_cc_clear		; adds should not affect any condition codes
-	test_h_gr32  0xa5a5a5a7 er0	; result of adds #2
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-adds_4:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	adds	#4, er0
-
-	test_cc_clear		; adds should not affect any condition codes
-	test_h_gr32  0xa5a5a5a9 er0	; result of adds #4
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	pass
-.endif	
-	exit 0

diff --git a/sim/testsuite/sim/h8300/addx.s b/sim/testsuite/sim/h8300/addx.s
deleted file mode 100644
index 27697a7..0000000
--- a/sim/testsuite/sim/h8300/addx.s
+++ /dev/null

@@ -1,993 +0,0 @@
-# Hitachi H8 testcase 'addx'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# addx.b #xx:8, rd8	; 9 rd8 xxxxxxxx
-	# addx.b #xx:8, @erd	; 7 d erd ???? 9 ???? xxxxxxxx 
-	# addx.b #xx:8, @erd-	; 0 1 7 6 6 c erd 1??? 9 ???? xxxxxxxx
-	# addx.b rs8, rd8	; 0 e rs8 rd8
-	# addx.b rs8, @erd	; 7 d erd ???? 0 e rs8 ????
-	# addx.b rs8, @erd-	; 0 1 7 6 6 c erd 1??? 0 e rs8 ????
-	# addx.b @ers, rd8	; 7 c ers ???? 0 e ???? rd8
-	# addx.b @ers-, rd8	; 0 1 7 6 6 c ers 00?? 0 e ???? rd8
-	# addx.b @ers, @erd	; 0 1 7 4 6 8 ers d 0 erd 1 ???? 
-	# addx.b @ers-, @erd-	; 0 1 7 6 6 c ers d a erd 1 ????
-	#
-	# coming soon:
-	# word ops
-	# long ops	
-
-.data
-byte_src:	.byte 0x5
-byte_dest:	.byte 0
-
-	.align 2
-word_src:	.word 0x505
-word_dest:	.word 0
-
-	.align 4
-long_src:	.long 0x50505
-long_dest:	.long 0
-
-
-	start
-
-addx_b_imm8_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b #xx:8,Rd	; Addx with carry initially zero.
-	addx.b	#5, r0l		; Immediate 8-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0xa5aa r0	; add result:	a5 + 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5aa er0	; add result:	 a5 + 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_b_imm8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b #xx:8,Rd	; Addx with carry initially one.
-	set_carry_flag 1
-	addx.b	#5, r0l		; Immediate 8-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0xa5ab r0	; add result:	a5 + 5 + 1
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5ab er0	; add result:	 a5 + 5 + 1
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-addx_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b #xx:8,@eRd	; Addx to register indirect
-	mov	#byte_dest, er0
-	addx.b	#5, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.b	#5, @byte_dest
-	beq	.Lb1
-	fail
-.Lb1:
-
-addx_b_imm8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b #xx:8,@eRd-	; Addx to register post-decrement
-	mov	#byte_dest, er0
-	addx.b	#5, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0	; er0 contains address minus one
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.b	#10, @byte_dest
-	beq	.Lb2
-	fail
-.Lb2:
-.endif
-
-addx_b_reg8_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b Rs,Rd	; addx with carry initially zero
-	mov.b	#5, r0h
-	addx.b	r0h, r0l	; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0x05aa r0	; add result:	a5 + 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a505aa er0	; add result:	a5 + 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b Rs,Rd	; addx with carry initially one
-	mov.b	#5, r0h
-	set_carry_flag 1
-	addx.b	r0h, r0l	; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0x05ab r0	; add result:	a5 + 5 + 1
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a505ab er0	; add result:	a5 + 5 + 1
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-addx_b_reg8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b rs8,@eRd	; Addx to register indirect
-	mov	#byte_dest, er0
-	mov.b	#5, r1l
-	addx.b	r1l, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.b	#15, @byte_dest
-	beq	.Lb3
-	fail
-.Lb3:
-
-addx_b_reg8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b rs8,@eRd-	; Addx to register post-decrement
-	mov	#byte_dest, er0
-	mov.b	#5, r1l
-	addx.b	r1l, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a505 er1	; er1 contains the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.b	#20, @byte_dest
-	beq	.Lb4
-	fail
-.Lb4:
-
-addx_b_rsind_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b @eRs,rd8	; Addx from reg indirect to reg
-	mov	#byte_src, er0
-	addx.b	@er0, r1l
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_src er0	; er0 still contains address
-	test_h_gr32 0xa5a5a5aa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_b_rspostdec_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b @eRs-,rd8	; Addx to register post-decrement
-	mov	#byte_src, er0
-	addx.b	@er0-, r1l
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_src-1 er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a5aa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_b_rsind_rsind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b @eRs,rd8	; Addx from reg indirect to reg
-	mov	#byte_src, er0
-	mov	#byte_dest, er1
-	addx.b	@er0, @er1
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_src er0	; er0 still contains src address
-	test_h_gr32 byte_dest er1	; er1 still contains dst address
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.b	#25, @byte_dest
-	beq	.Lb5
-	fail
-.Lb5:
-
-addx_b_rspostdec_rspostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.b @eRs-,rd8	; Addx to register post-decrement
-	mov	#byte_src, er0
-	mov	#byte_dest, er1
-	addx.b	@er0-, @er1-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_src-1 er0	; er0 contains src address minus one
-	test_h_gr32 byte_dest-1 er1	; er1 contains dst address minus one
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.b	#30, @byte_dest
-	beq	.Lb6
-	fail
-.Lb6:
-
-addx_w_imm16_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w #xx:16,Rd	; Addx with carry initially zero.
-	addx.w	#0x505, r0	; Immediate 16-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0xaaaa r0	; add result:	0xa5a5 + 0x505
-	test_h_gr32 0xa5a5aaaa er0	; add result:	 0xa5a5 + 0x505
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_w_imm16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w #xx:16,Rd	; Addx with carry initially one.
-	set_carry_flag 1
-	addx.w	#0x505, r0	; Immediate 16-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr16 0xaaab r0	; add result:	0xa5a5 + 0x505 + 1
-	test_h_gr32 0xa5a5aaab er0	; add result:	 0xa5a5 + 0x505 + 1
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_w_imm16_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w #xx:16,@eRd	; Addx to register indirect
-	mov	#word_dest, er0
-	addx.w	#0x505, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0	; er0 still contains address
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.w	#0x505, @word_dest
-	beq	.Lw1
-	fail
-.Lw1:
-
-addx_w_imm16_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w #xx:16,@eRd-	; Addx to register post-decrement
-	mov	#word_dest, er0
-	addx.w	#0x505, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0	; er0 contains address minus one
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.w	#0xa0a, @word_dest
-	beq	.Lw2
-	fail
-.Lw2:
-
-addx_w_reg16_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w Rs,Rd	; addx with carry initially zero
-	mov.w	#0x505, e0
-	addx.w	e0, r0		; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0x0505aaaa er0	; add result:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w Rs,Rd	; addx with carry initially one
-	mov.w	#0x505, e0
-	set_carry_flag 1
-	addx.w	e0, r0		; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0x0505aaab er0	; add result:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_w_reg16_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w rs8,@eRd	; Addx to register indirect
-	mov	#word_dest, er0
-	mov.w	#0x505, r1
-	addx.w	r1, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a50505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.w	#0xf0f, @word_dest
-	beq	.Lw3
-	fail
-.Lw3:
-
-addx_w_reg16_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w rs8,@eRd-	; Addx to register post-decrement
-	mov	#word_dest, er0
-	mov.w	#0x505, r1
-	addx.w	r1, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0	; er0 contains address minus one
-	test_h_gr32 0xa5a50505  er1	; er1 contains the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.w	#0x1414, @word_dest
-	beq	.Lw4
-	fail
-.Lw4:
-
-addx_w_rsind_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w @eRs,rd8	; Addx from reg indirect to reg
-	mov	#word_src, er0
-	addx.w	@er0, r1
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 word_src er0	; er0 still contains address
-	test_h_gr32 0xa5a5aaaa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_w_rspostdec_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w @eRs-,rd8	; Addx to register post-decrement
-	mov	#word_src, er0
-	addx.w	@er0-, r1
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 word_src-2 er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5aaaa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_w_rsind_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w @eRs,rd8	; Addx from reg indirect to reg
-	mov	#word_src, er0
-	mov	#word_dest, er1
-	addx.w	@er0, @er1
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_src er0	; er0 still contains src address
-	test_h_gr32 word_dest er1	; er1 still contains dst address
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.w	#0x1919, @word_dest
-	beq	.Lw5
-	fail
-.Lw5:
-
-addx_w_rspostdec_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.w @eRs-,rd8	; Addx to register post-decrement
-	mov	#word_src, er0
-	mov	#word_dest, er1
-	addx.w	@er0-, @er1-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 word_src-2 er0	; er0 contains src address minus one
-	test_h_gr32 word_dest-2 er1	; er1 contains dst address minus one
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.w	#0x1e1e, @word_dest
-	beq	.Lw6
-	fail
-.Lw6:
-
-addx_l_imm32_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l #xx:32,Rd	; Addx with carry initially zero.
-	addx.l	#0x50505, er0	; Immediate 32-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0xa5aaaaaa er0	; add result:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_l_imm32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l #xx:32,Rd	; Addx with carry initially one.
-	set_carry_flag 1
-	addx.l	#0x50505, er0	; Immediate 32-bit operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0xa5aaaaab er0	; add result:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_l_imm32_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l #xx:32,@eRd	; Addx to register indirect
-	mov	#long_dest, er0
-	addx.l	#0x50505, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0	; er0 still contains address
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.l	#0x50505, @long_dest
-	beq	.Ll1
-	fail
-.Ll1:
-
-addx_l_imm32_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l #xx:32,@eRd-	; Addx to register post-decrement
-	mov	#long_dest, er0
-	addx.l	#0x50505, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0	; er0 contains address minus one
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.l	#0xa0a0a, @long_dest
-	beq	.Ll2
-	fail
-.Ll2:
-
-addx_l_reg32_0:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l Rs,Rd	; addx with carry initially zero
-	mov.l	#0x50505, er0
-	addx.l	er0, er1	; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0x50505    er0	; add load
-	test_h_gr32 0xa5aaaaaa er1	; add result:
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l Rs,Rd	; addx with carry initially one
-	mov.l	#0x50505, er0
-	set_carry_flag 1
-	addx.l	er0, er1	; Register operand
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 0x50505    er0	; add result:
-	test_h_gr32 0xa5aaaaab er1	; add result:
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-addx_l_reg32_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l rs8,@eRd	; Addx to register indirect
-	mov	#long_dest, er0
-	mov.l	#0x50505, er1
-	addx.l	er1, @er0
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0	; er0 still contains address
-	test_h_gr32 0x50505   er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.l	#0xf0f0f, @long_dest
-	beq	.Ll3
-	fail
-.Ll3:
-
-addx_l_reg32_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l rs8,@eRd-	; Addx to register post-decrement
-	mov	#long_dest, er0
-	mov.l	#0x50505, er1
-	addx.l	er1, @er0-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0	; er0 contains address minus one
-	test_h_gr32 0x50505     er1	; er1 contains the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the add to memory.
-	cmp.l	#0x141414, @long_dest
-	beq	.Ll4
-	fail
-.Ll4:
-
-addx_l_rsind_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l @eRs,rd8	; Addx from reg indirect to reg
-	mov	#long_src, er0
-	addx.l	@er0, er1
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 long_src er0	; er0 still contains address
-	test_h_gr32 0xa5aaaaaa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_l_rspostdec_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l @eRs-,rd8	; Addx to register post-decrement
-	mov	#long_src, er0
-	addx.l	@er0-, er1
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 long_src-4 er0	; er0 contains address minus one
-	test_h_gr32 0xa5aaaaaa er1	; er1 contains the sum
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-addx_l_rsind_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l @eRs,rd8	; Addx from reg indirect to reg
-	mov	#long_src, er0
-	mov	#long_dest, er1
-	addx.l	@er0, @er1
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_src er0	; er0 still contains src address
-	test_h_gr32 long_dest er1	; er1 still contains dst address
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.l	#0x191919, @long_dest
-	beq	.Ll5
-	fail
-.Ll5:
-
-addx_l_rspostdec_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  addx.l @eRs-,rd8	; Addx to register post-decrement
-	mov	#long_src, er0
-	mov	#long_dest, er1
-	addx.l	@er0-, @er1-
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 long_src-4 er0	; er0 contains src address minus one
-	test_h_gr32 long_dest-4 er1	; er1 contains dst address minus one
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	;; Now check the result of the add to memory.
-	cmp.l	#0x1e1e1e, @long_dest
-	beq	.Ll6
-	fail
-.Ll6:
-.endif
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/allinsn.exp b/sim/testsuite/sim/h8300/allinsn.exp
deleted file mode 100644
index 23e2cc9..0000000
--- a/sim/testsuite/sim/h8300/allinsn.exp
+++ /dev/null

@@ -1,55 +0,0 @@
-# Hitachi H8/300 (h, s, sx) simulator testsuite
-
-set all "h8300 h8300h h8300s h8sx"
-
-if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then {
-    run_sim_test add.b.s $all
-    run_sim_test add.w.s $all
-    run_sim_test add.l.s $all
-    run_sim_test adds.s  $all
-    run_sim_test addx.s  $all
-    run_sim_test and.b.s $all
-    run_sim_test and.w.s $all
-    run_sim_test and.l.s $all
-    run_sim_test bfld.s  h8sx
-    run_sim_test bra.s   $all
-    run_sim_test bset.s  $all
-    run_sim_test cmp.b.s $all
-    run_sim_test cmp.w.s $all
-    run_sim_test cmp.l.s $all
-    run_sim_test daa.s   $all
-    run_sim_test das.s   $all
-    run_sim_test dec.s   $all
-    run_sim_test ext.w.s $all
-    run_sim_test ext.l.s $all
-    run_sim_test inc.s   $all
-    run_sim_test jmp.s   $all
-    run_sim_test ldc.s   $all
-    run_sim_test mac.s   $all
-    run_sim_test mov.b.s $all
-    run_sim_test mov.w.s $all
-    run_sim_test mov.l.s $all
-    run_sim_test movmd.s h8sx
-    run_sim_test movsd.s h8sx
-    run_sim_test neg.s   $all
-    run_sim_test nop.s   $all
-    run_sim_test not.s   $all
-    run_sim_test or.b.s  $all
-    run_sim_test or.w.s  $all
-    run_sim_test or.l.s  $all
-    run_sim_test rotl.s  $all
-    run_sim_test rotr.s  $all
-    run_sim_test rotxl.s $all
-    run_sim_test rotxr.s $all
-    run_sim_test shal.s  $all
-    run_sim_test shar.s  $all
-    run_sim_test shll.s  $all
-    run_sim_test shlr.s  $all
-    run_sim_test stc.s   $all
-    run_sim_test sub.b.s $all
-    run_sim_test sub.w.s $all
-    run_sim_test sub.l.s $all
-    run_sim_test xor.b.s $all
-    run_sim_test xor.w.s $all
-    run_sim_test xor.l.s $all
-}

diff --git a/sim/testsuite/sim/h8300/and.b.s b/sim/testsuite/sim/h8300/and.b.s
deleted file mode 100644
index 3377674..0000000
--- a/sim/testsuite/sim/h8300/and.b.s
+++ /dev/null

@@ -1,491 +0,0 @@
-# Hitachi H8 testcase 'and.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# and.b #xx:8, rd	;                     e rd   xxxxxxxx
-	# and.b #xx:8, @erd	;         7 d rd ???? e ???? xxxxxxxx
-	# and.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? e ???? xxxxxxxx
-	# and.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? e ???? xxxxxxxx
-	# and.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? e ???? xxxxxxxx
-	# and.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? e ???? xxxxxxxx
-	# and.b rs, rd		;                     1 6 rs rd
-	# and.b reg8, @erd	;         7 d rd ???? 1 6 rs ????
-	# and.b reg8, @erd+	;         0 1 7     9 8 rd 6 rs
-	# and.b reg8, @erd-	;         0 1 7     9 a rd 6 rs
-	# and.b reg8, @+erd	;         0 1 7     9 9 rd 6 rs
-	# and.b reg8, @-erd	;         0 1 7     9 b rd 6 rs
-	#
-	# andc #xx:8, ccr	;         0 6 xxxxxxxx
-	# andc #xx:8, exr	; 0 1 4 1 0 6 xxxxxxxx
-
-	# Coming soon:
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0xa5
-post_byte:	.byte 0
-
-	start
-	
-and_b_imm8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.b #xx:8,Rd
-	and.b	#0xaa, r0l	; Immediate 8-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a0 r0	; and result:	a5 & aa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5a0 er0	; and result:	 a5 & aa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-and_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	and.b	#0xaa:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0xe0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L1
-	fail
-.L1:
-
-and_b_imm8_rdpostinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	and.b	#0x55:8, @er0+	; Immediate 8-bit src, reg post-incr dest
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xe055
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 post_byte, er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x05, r0l
-	beq	.L2
-	fail
-.L2:
-
-and_b_imm8_rdpostdec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	and.b	#0xaa:8, @er0-	; Immediate 8-bit src, reg post-decr dest
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0xe0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 pre_byte, er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L3
-	fail
-.L3:
-
-and_b_imm8_rdpreinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b #xx:8,@+eRd
-	mov	#pre_byte, er0
-	and.b	#0x55:8, @+er0	; Immediate 8-bit src, reg pre-incr dest
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0xe055
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x05, r0l
-	beq	.L4
-	fail
-.L4:
-
-and_b_imm8_rdpredec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b #xx:8,@-eRd
-	mov	#post_byte, er0
-	and.b	#0xaa:8, @-er0	; Immediate 8-bit src, reg pre-decr dest
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0xe0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L5
-	fail
-.L5:
-
-
-.endif
-
-and_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.b Rs,Rd
-	mov.b	#0xaa, r0h
-	and.b	r0h, r0l	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xaaa0 r0	; and result:	a5 & aa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5aaa0 er0	; and result:	a5 & aa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-and_b_reg8_rdind:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b rs8,@eRd	; And to register indirect
-	mov	#byte_dest, er0
-	mov	#0x55, r1l
-	and.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x1690
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a555 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x05, r0l
-	beq	.L6
-	fail
-.L6:
-
-and_b_reg8_rdpostinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b rs8,@eRd+	; And to register post-incr
-	mov	#byte_dest, er0
-	mov	#0xaa, r1l
-	and.b	r1l, @er0+	; reg8 src, reg post-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x8069
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a5aa er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L7
-	fail
-.L7:
-
-and_b_reg8_rdpostdec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b rs8,@eRd-	; And to register post-decr
-	mov	#byte_dest, er0
-	mov	#0x55, r1l
-	and.b	r1l, @er0-	; reg8 src, reg post-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xa069
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a555 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x05, r0l
-	beq	.L8
-	fail
-.L8:
-
-and_b_reg8_rdpreinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b rs8,@+eRd	; And to register post-incr
-	mov	#pre_byte, er0
-	mov	#0xaa, r1l
-	and.b	r1l, @+er0	; reg8 src, reg post-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x9069
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a5aa er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L9
-	fail
-.L9:
-
-and_b_reg8_rdpredec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  and.b rs8,@-eRd	; And to register post-decr
-	mov	#post_byte, er0
-	mov	#0x55, r1l
-	and.b	r1l, @-er0	; reg8 src, reg post-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xb069
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a555 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the and to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x05, r0l
-	beq	.L10
-	fail
-.L10:
-
-andc_imm8_ccr:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  andc #xx:8,ccr
-	set_ccr 0xff
-
-	test_neg_set
-	andc	#0xf7, ccr	; Immediate 8-bit operand (neg flag)
-	test_neg_clear
-
-	test_zero_set
-	andc	#0xfb, ccr	; Immediate 8-bit operand (zero flag)
-	test_zero_clear
-
-	test_ovf_set
-	andc	#0xfd, ccr	; Immediate 8-bit operand (overflow flag)
-	test_ovf_clear
-
-	test_carry_set
-	andc	#0xfe, ccr	; Immediate 8-bit operand (carry flag)
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/and.l.s b/sim/testsuite/sim/h8300/and.l.s
deleted file mode 100644
index ac09edc..0000000
--- a/sim/testsuite/sim/h8300/and.l.s
+++ /dev/null

@@ -1,77 +0,0 @@
-# Hitachi H8 testcase 'and.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu == h8sx)		; 16-bit immediate is only available on sx.
-and_l_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.l #xx:16,Rd
-	and.l	#0xaaaa:16, er0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0x0000a0a0 er0	; and result:	 a5a5a5a5 & aaaa
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-and_l_imm32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.l #xx:32,Rd
-	and.l	#0xaaaaaaaa, er0	; Immediate 32-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa0a0a0a0 er0	; and result:	 a5a5a5a5 & aaaaaaaa
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-and_l_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.l Rs,Rd
-	mov.l	#0xaaaaaaaa, er1
-	and.l	er1, er0	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa0a0a0a0 er0	; and result:	a5a5a5a5 & aaaaaaaa
-	test_h_gr32 0xaaaaaaaa er1	; Make sure er1 is unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/and.w.s b/sim/testsuite/sim/h8300/and.w.s
deleted file mode 100644
index 4267179..0000000
--- a/sim/testsuite/sim/h8300/and.w.s
+++ /dev/null

@@ -1,61 +0,0 @@
-# Hitachi H8 testcase 'and.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-and_w_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.w #xx:16,Rd
-	and.w	#0xaaaa, r0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa0a0 r0	; and result:	a5a5 & aaaa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a0a0 er0	; and result:	 a5a5 & aaaa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-and_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  and.w Rs,Rd
-	mov.w	#0xaaaa, r1
-	and.w	r1, r0		; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa0a0 r0	; and result:	a5a5 & aaaa
-	test_h_gr16 0xaaaa r1	; Make sure r1 is unchanged
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a0a0 er0	; and result:	a5a5 & aaaa
-	test_h_gr32 0xa5a5aaaa er1	; Make sure er1 is unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/bfld.s b/sim/testsuite/sim/h8300/bfld.s
deleted file mode 100644
index 7c55007..0000000
--- a/sim/testsuite/sim/h8300/bfld.s
+++ /dev/null

@@ -1,286 +0,0 @@
-# Hitachi H8 testcase 'bfld', 'bfst'
-# mach(): h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	.data
-byte_src:	.byte	0xa5
-byte_dst:	.byte	0
-
-	start
-
-.if (sim_cpu == h8sx)
-bfld_imm8_ind:
-	set_grs_a5a5
-	mov	#byte_src, er2
-
-	;; bfld #xx:8, @ers, rd8
-	set_ccr_zero
-	bfld	#1, @er2, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	bfld	#2, @er2, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	set_ccr_zero
-	bfld	#7, @er2, r1l
-	test_cc_clear
-	test_h_gr8 5 r1l
-
-	set_ccr_zero
-	bfld	#0x10, @er2, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	set_ccr_zero
-	bfld	#0x20, @er2, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	bfld	#0xf0, @er2, r1l
-	test_cc_clear
-	test_h_gr8 0xa r1l
-
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 0xa5a5a50a er1
-	test_h_gr32 byte_src   er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-bfld_imm8_abs16:
-	set_grs_a5a5
-
-	;; bfld #xx:8, @aa:16, rd8
-	set_ccr_zero
-	bfld	#0x80, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	bfld	#0x40, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	set_ccr_zero
-	bfld	#0xe0, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 0x5 r1l
-
-	set_ccr_zero
-	bfld	#0x3c, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 9 r1l
-
-	set_ccr_zero
-	bfld	#0xfe, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 0x52 r1l
-
-	set_ccr_zero
-	bfld	#0, @byte_src:16, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 0xa5a5a500 er1
-	test_h_gr32 0xa5a5a5a5 er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-bfst_imm8_ind:
-	set_grs_a5a5
-	mov	#byte_dst, er2
-
-	;; bfst rd8, #xx:8, @ers
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #1, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf901
-
-	test_cc_clear
-	cmp.b	#1, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #2, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf902
-
-	test_cc_clear
-	cmp.b	#2, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #7, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf907
-
-	test_cc_clear
-	cmp.b	#5, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x10, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf910
-
-	test_cc_clear
-	cmp.b	#0x10, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x20, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf920
-
-	test_cc_clear
-	cmp.b	#0x20, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0xf0, @er2
-;;; 	.word	0x7d20
-;;; 	.word	0xf9f0
-
-	test_cc_clear
-	cmp.b	#0x50, @byte_dst
-	bne	fail1:16
-
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 0xa5a5a5a5 er1
-	test_h_gr32 byte_dst   er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-bfst_imm8_abs32:
-	set_grs_a5a5
-
-	;; bfst #xx:8, @aa:32, rd8
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x80, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf980
-
-	test_cc_clear
-	cmp.b	#0x80, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x40, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf940
-
-	test_cc_clear
-	cmp.b	#0x40, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0xe0, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf9e0
-
-	test_cc_clear
-	cmp.b	#0xa0, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x3c, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf93c
-
-	test_cc_clear
-	cmp.b	#0x14, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0xfe, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf9fe
-
-	test_cc_clear
-	cmp.b	#0x4a, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf900
-
-	test_cc_clear
-	cmp.b	#0x0, @byte_dst
-	bne	fail1:16
-
-	mov.b	#0, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x38, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf938
-
-	test_cc_clear
-	cmp.b	#0x28, @byte_dst
-	bne	fail1:16
-
-	;;
-	;; Now let's do one in which the bits in the destination
-	;; are appropriately combined with the bits in the source.
-	;;
-
-	mov.b	#0xc3, @byte_dst
-	set_ccr_zero
-	bfst	r1l, #0x3c, @byte_dst:32
-;;; 	.word	0x6a38
-;;; 	.long	byte_dst
-;;; 	.word	0xf93c
-
-	test_cc_clear
-	cmp.b	#0xd7, @byte_dst
-	bne	fail1:16
-
-	test_grs_a5a5
-
-.endif
-	pass
-
-	exit 0
-
-fail1:	fail
-	

diff --git a/sim/testsuite/sim/h8300/bra.s b/sim/testsuite/sim/h8300/bra.s
deleted file mode 100644
index 7da2611..0000000
--- a/sim/testsuite/sim/h8300/bra.s
+++ /dev/null

@@ -1,165 +0,0 @@
-# Hitachi H8 testcase 'bra'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-.if (sim_cpu == h8sx)	
-	.data
-	.align 4
-disp8:	.long	tgt_reg8 
-disp16:	.long	tgt_reg16
-disp32:	.long	tgt_reg32
-dslot:	.byte	0
-	.text
-.endif
-
-bra_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  bra dd:8		; 8-bit displacement
-	bra tgt_8:8
-;;;	.word	0x40xx		; where "xx" is tgt_8 - '.'.
-	fail
-
-tgt_8:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)			; not available in h8/300 mode
-bra_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  bra dd:16		; 16-bit displacement
-	bra tgt_24:16	; NOTE: hard-coded to avoid relaxing.
-;;; 	.word 0x5800
-;;; 	.word tgt_24 - .
-	fail
-
-tgt_24:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if	(sim_cpu == h8sx)
-bra_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  bra rn.b		; 8-bit register indirect
-	sub.l	#src8, @disp8
-	mov.l	@disp8, er5
-;;; 	bra	er5.b
-	.word	0x5955
-src8:	fail
-	
-tgt_reg8:
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-;;; 	test_h_gr32 tgt_reg8 er5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-bra_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  bra rn.w		; 16-bit register indirect
-	sub.l	#src16, @disp16
-	mov.l	@disp16, er5
-;;; 	bra	er5.w
-	.word	0x5956
-src16:	fail
-	
-tgt_reg16:
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-;;; 	test_h_gr32 tgt_reg16 er5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-bra_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  bra ern		; 32-bit register indirect
-	sub.l	#src32, @disp32
-	mov.l	@disp32, er5
-;;; 	bra	er5.l
-	.word	0x5957
-src32:	fail
-
-tgt_reg32:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-;;; 	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-bra_s:	set_grs_a5a5
-	set_ccr_zero
-
-;;; 	bra/s	tgt_post_delay
-	.word	0x4017
-	;; The following instruction is in the delay slot, and should execute.
-	mov.b	#1, @dslot
-	;; After this, the next instructions should not execute.
-	fail
-	
-tgt_post_delay:
-	test_cc_clear
-	cmp.b	#0, @dslot	; Should be non-zero if delay slot executed.
-	bne	dslot_ok
-	fail
-
-dslot_ok:
-	test_gr_a5a5 0		; Make sure all general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-
-	pass
-	exit 0
-
-	
\ No newline at end of file

diff --git a/sim/testsuite/sim/h8300/brabc.s b/sim/testsuite/sim/h8300/brabc.s
deleted file mode 100644
index 119d8d9..0000000
--- a/sim/testsuite/sim/h8300/brabc.s
+++ /dev/null

@@ -1,107 +0,0 @@
-# Hitachi H8 testcase 'bra/bc'
-# mach(): h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	.data
-byte_src:	.byte	0xa5
-
-	start
-
-.if (sim_cpu == h8sx)
-brabc_ind_disp8:
-	set_grs_a5a5
-	mov	#byte_src, er1
-	set_ccr_zero
-	;; bra/bc xx:3, @erd, disp8
-	bra/bc	#1, @er1, .Lpass1:8
-;;; 	.word	0x7c10
-;;; 	.word	0x4110
-	fail
-.Lpass1:
-	bra/bc	#2, @er1, .Lfail1:8
-;;; 	.word	0x7c10
-;;; 	.word	0x4202
-	bra	.Lpass2
-.Lfail1:
-	fail
-.Lpass2:	
-	test_cc_clear
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 byte_src   er1
-	test_h_gr32 0xa5a5a5a5 er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-brabc_abs16_disp16:
-	set_grs_a5a5
-	set_ccr_zero
-	;; bra/bc xx:3, @aa:16, disp16
-	bra/bc	#1, @byte_src:16, .Lpass3:16
-	fail
-.Lpass3:
-	bra/bc	#2, @byte_src:16, .Lfail2:16
-	bra	.Lpass4
-.Lfail2:
-	fail
-.Lpass4:	
-	test_cc_clear
-	test_grs_a5a5
-
-brabs_ind_disp8:
-	set_grs_a5a5
-	mov	#byte_src, er1
-	set_ccr_zero
-	;; bra/bs xx:3, @erd, disp8
-	bra/bs	#2, @er1, .Lpass5:8
-;;; 	.word	0x7c10
-;;; 	.word	0x4a10
-	fail
-.Lpass5:
-	bra/bs	#1, @er1, .Lfail3:8
-;;; 	.word	0x7c10
-;;; 	.word	0x4902
-	bra	.Lpass6
-.Lfail3:
-	fail
-.Lpass6:
-	test_cc_clear
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 byte_src   er1
-	test_h_gr32 0xa5a5a5a5 er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-brabs_abs32_disp16:
-	set_grs_a5a5
-	set_ccr_zero
-	;; bra/bs xx:3, @aa:32, disp16
-	bra/bs	#2, @byte_src:32, .Lpass7:16
-	fail
-.Lpass7:
-	bra/bs	#1, @byte_src:32, .Lfail4:16
-	bra	.Lpass8
-.Lfail4:
-	fail
-.Lpass8:
-	test_cc_clear
-	test_grs_a5a5
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s
deleted file mode 100644
index ecf5237..0000000
--- a/sim/testsuite/sim/h8300/bset.s
+++ /dev/null

@@ -1,841 +0,0 @@
-# Hitachi H8 testcase 'bset', 'bclr'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	#
-	# bset xx:3, rd8	;                   7 0 ?xxx rd8
-	# bclr xx:3, rd8	;                   7 2 ?xxx rd8
-	# bset xx:3, @erd	; 7 d 0rd ????      7 0 ?xxx ????
-	# bclr xx:3, @erd	; 7 d 0rd ????      7 2 ?xxx ????
-	# bset xx:3, @abs16	; 6 a 1 1??? aa:16  7 0 ?xxx ????
-	# bclr xx:3, @abs16	; 6 a 1 1??? aa:16  7 2 ?xxx ???? 
-	# bset reg8, rd8	;                   6 0 rs8  rd8
-	# bclr reg8, rd8	;                   6 2 rs8  rd8
-	# bset reg8, @erd	; 7 d 0rd ????      6 0 rs8  ????
-	# bclr reg8, @erd	; 7 d 0rd ????      6 2 rs8  ????
-	# bset reg8, @abs32	; 6 a 3 1??? aa:32  6 0 rs8  ????
-	# bclr reg8, @abs32	; 6 a 3 1??? aa:32  6 2 rs8  ???? 
-	#
-	# bset/eq xx:3, rd8
-	# bclr/eq xx:3, rd8
-	# bset/ne xx:3, rd8
-	# bclr/ne xx:3, rd8
-
-	.data
-byte_dst:	.byte 0
-
-	start
-
-bset_imm3_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset xx:3, rd8
-	mov	#0, r1l
-	set_ccr_zero
-	bset	#0, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	bset	#1, r1l
-	test_cc_clear
-	test_h_gr8 3 r1l
-
-	set_ccr_zero
-	bset	#2, r1l
-	test_cc_clear
-	test_h_gr8 7 r1l
-
-	set_ccr_zero
-	bset	#3, r1l
-	test_cc_clear
-	test_h_gr8 15 r1l
-
-	set_ccr_zero
-	bset	#4, r1l
-	test_cc_clear
-	test_h_gr8 31 r1l
-
-	set_ccr_zero
-	bset	#5, r1l
-	test_cc_clear
-	test_h_gr8 63 r1l
-
-	set_ccr_zero
-	bset	#6, r1l
-	test_cc_clear
-	test_h_gr8 127 r1l
-
-	set_ccr_zero
-	bset	#7, r1l
-	test_cc_clear
-	test_h_gr8 255 r1l
-
-.if (sim_cpu == h8300)
-	test_h_gr16 0xa5ff, r1
-.else
-	test_h_gr32  0xa5a5a5ff er1
-.endif
-
-bclr_imm3_reg8:	
-	set_ccr_zero
-	bclr	#7, r1l
-	test_cc_clear
-	test_h_gr8 127 r1l
-
-	set_ccr_zero
-	bclr	#6, r1l
-	test_cc_clear
-	test_h_gr8 63 r1l
-
-	set_ccr_zero
-	bclr	#5, r1l
-	test_cc_clear
-	test_h_gr8 31 r1l
-
-	set_ccr_zero
-	bclr	#4, r1l
-	test_cc_clear
-	test_h_gr8 15 r1l
-
-	set_ccr_zero
-	bclr	#3, r1l
-	test_cc_clear
-	test_h_gr8 7 r1l
-
-	set_ccr_zero
-	bclr	#2, r1l
-	test_cc_clear
-	test_h_gr8 3 r1l
-
-	set_ccr_zero
-	bclr	#1, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	bclr	#0, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-.if (sim_cpu == h8300)
-	test_h_gr16 0xa500 r1
-.else
-	test_h_gr32  0xa5a5a500 er1
-.endif
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)
-bset_imm3_ind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset xx:3, @erd
-	mov	#byte_dst, er1
-	set_ccr_zero
-	bset	#0, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 1 r2l
-
-	set_ccr_zero
-	bset	#1, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 3 r2l
-
-	set_ccr_zero
-	bset	#2, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 7 r2l
-
-	set_ccr_zero
-	bset	#3, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 15 r2l
-
-	set_ccr_zero
-	bset	#4, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 31 r2l
-
-	set_ccr_zero
-	bset	#5, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 63 r2l
-
-	set_ccr_zero
-	bset	#6, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 127 r2l
-
-	set_ccr_zero
-	bset	#7, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 255 r2l
-
-.if (sim_cpu == h8300)
-	test_h_gr16  0xa5ff r2
-.else
-	test_h_gr32  0xa5a5a5ff er2
-.endif
-
-bclr_imm3_ind:	
-	set_ccr_zero
-	bclr	#7, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 127 r2l
-
-	set_ccr_zero
-	bclr	#6, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 63 r2l
-
-	set_ccr_zero
-	bclr	#5, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 31 r2l
-
-	set_ccr_zero
-	bclr	#4, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 15 r2l
-
-	set_ccr_zero
-	bclr	#3, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 7  r2l
-
-	set_ccr_zero
-	bclr	#2, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 3  r2l
-
-	set_ccr_zero
-	bclr	#1, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 1  r2l
-
-	set_ccr_zero
-	bclr	#0, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 0  r2l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-.if (sim_cpu == h8300)
-	test_h_gr16  byte_dst r1
-	test_h_gr16  0xa500   r2
-.else
-	test_h_gr32  byte_dst   er1
-	test_h_gr32  0xa5a5a500 er2
-.endif
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-bset_imm3_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset xx:3, @aa:16
-	set_ccr_zero
-	bset	#0, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 1 r2l
-
-	set_ccr_zero
-	bset	#1, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 3 r2l
-
-	set_ccr_zero
-	bset	#2, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 7 r2l
-
-	set_ccr_zero
-	bset	#3, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 15 r2l
-
-	set_ccr_zero
-	bset	#4, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 31 r2l
-
-	set_ccr_zero
-	bset	#5, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 63 r2l
-
-	set_ccr_zero
-	bset	#6, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 127 r2l
-
-	set_ccr_zero
-	bset	#7, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 255 r2l
-
-.if (sim_cpu == h8300)
-	test_h_gr16  0xa5ff r2
-.else
-	test_h_gr32  0xa5a5a5ff er2
-.endif
-
-bclr_imm3_abs16:	
-	set_ccr_zero
-	bclr	#7, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 127 r2l
-
-	set_ccr_zero
-	bclr	#6, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 63 r2l
-
-	set_ccr_zero
-	bclr	#5, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 31 r2l
-
-	set_ccr_zero
-	bclr	#4, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 15 r2l
-
-	set_ccr_zero
-	bclr	#3, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 7  r2l
-
-	set_ccr_zero
-	bclr	#2, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 3  r2l
-
-	set_ccr_zero
-	bclr	#1, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 1  r2l
-
-	set_ccr_zero
-	bclr	#0, @byte_dst:16
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 0  r2l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-.if (sim_cpu == h8300)
-	test_h_gr16  0xa500   r2
-.else
-	test_h_gr32  0xa5a5a500 er2
-.endif
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-bset_rs8_rd8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset rs8, rd8
-	mov	#0, r1h
-	mov	#0, r1l
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	mov	#1, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 3 r1l
-
-	mov	#2, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 7 r1l
-
-	mov	#3, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 15 r1l
-
-	mov	#4, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 31 r1l
-
-	mov	#5, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 63 r1l
-
-	mov	#6, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 127 r1l
-
-	mov	#7, r1h
-	set_ccr_zero
-	bset	r1h, r1l
-	test_cc_clear
-	test_h_gr8 255 r1l
-
-.if (sim_cpu == h8300)
-	test_h_gr16 0x07ff, r1
-.else
-	test_h_gr32  0xa5a507ff er1
-.endif
-
-bclr_rs8_rd8:	
-	mov	#7, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 127 r1l
-
-	mov	#6, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 63 r1l
-
-	mov	#5, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 31 r1l
-
-	mov	#4, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 15 r1l
-
-	mov	#3, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 7 r1l
-
-	mov	#2, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 3 r1l
-
-	mov	#1, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 1 r1l
-
-	mov	#0, r1h
-	set_ccr_zero
-	bclr	r1h, r1l
-	test_cc_clear
-	test_h_gr8 0 r1l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-.if (sim_cpu == h8300)
-	test_h_gr16 0x0000 r1
-.else
-	test_h_gr32  0xa5a50000 er1
-.endif
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)
-bset_rs8_ind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset rs8, @erd
-	mov	#byte_dst, er1
-	mov	#0, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 1 r2l
-
-	mov	#1, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 3 r2l
-
-	mov	#2, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 7 r2l
-
-	mov	#3, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 15 r2l
-
-	mov	#4, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 31 r2l
-
-	mov	#5, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 63 r2l
-
-	mov	#6, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 127 r2l
-
-	mov	#7, r2h
-	set_ccr_zero
-	bset	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 255 r2l
-
-.if (sim_cpu == h8300)
-	test_h_gr16  0x07ff r2
-.else
-	test_h_gr32  0xa5a507ff er2
-.endif
-
-bclr_rs8_ind:	
-	mov	#7, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 127 r2l
-
-	mov	#6, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 63 r2l
-
-	mov	#5, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 31 r2l
-
-	mov	#4, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 15 r2l
-
-	mov	#3, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 7  r2l
-
-	mov	#2, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 3  r2l
-
-	mov	#1, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 1  r2l
-
-	mov	#0, r2h
-	set_ccr_zero
-	bclr	r2h, @er1
-	test_cc_clear
-	mov	@er1, r2l
-	test_h_gr8 0  r2l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-.if (sim_cpu == h8300)
-	test_h_gr16  byte_dst r1
-	test_h_gr16  0x0000   r2
-.else
-	test_h_gr32  byte_dst   er1
-	test_h_gr32  0xa5a50000 er2
-.endif
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-bset_rs8_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset rs8, @aa:32
-	mov	#0, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 1 r2l
-
-	mov	#1, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 3 r2l
-
-	mov	#2, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 7 r2l
-
-	mov	#3, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 15 r2l
-
-	mov	#4, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 31 r2l
-
-	mov	#5, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 63 r2l
-
-	mov	#6, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 127 r2l
-
-	mov	#7, r2h
-	set_ccr_zero
-	bset	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 255 r2l
-
-.if (sim_cpu == h8300)
-	test_h_gr16  0x07ff r2
-.else
-	test_h_gr32  0xa5a507ff er2
-.endif
-
-bclr_rs8_abs32:	
-	mov	#7, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 127 r2l
-
-	mov	#6, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 63 r2l
-
-	mov	#5, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 31 r2l
-
-	mov	#4, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 15 r2l
-
-	mov	#3, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 7  r2l
-
-	mov	#2, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 3  r2l
-
-	mov	#1, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 1  r2l
-
-	mov	#0, r2h
-	set_ccr_zero
-	bclr	r2h, @byte_dst:32
-	test_cc_clear
-	mov	@byte_dst, r2l
-	test_h_gr8 0  r2l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-.if (sim_cpu == h8300)
-	test_h_gr16  0x0000   r2
-.else
-	test_h_gr32  0xa5a50000 er2
-.endif
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu == h8sx)
-bset_eq_imm3_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-
-	;;  bset/eq xx:3, rd8
-	mov	#0, @byte_dst
-	set_ccr_zero
-	bset/eq	#0, @byte_dst:16 ; Zero is clear, should have no effect.
-	test_cc_clear
-	mov	@byte_dst, r1l
-	test_h_gr8 0 r1l
-
-	set_ccr_zero
-	orc	#4, ccr		; Set zero flag
-	bset/eq	#0, @byte_dst:16 ; Zero is set: operation should succeed.
-
-	test_neg_clear
-	test_zero_set
-	test_ovf_clear
-	test_carry_clear
-
-	mov	@byte_dst, r1l
-	test_h_gr8 1 r1l
-
-bclr_eq_imm3_abs32:
-	mov	#1, @byte_dst
-	set_ccr_zero
-	bclr/eq	#0, @byte_dst:32 ; Zero is clear, should have no effect.
-	test_cc_clear
-	mov	@byte_dst, r1l
-	test_h_gr8 1 r1l
-
-	set_ccr_zero
-	orc	#4, ccr		; Set zero flag
-	bclr/eq	#0, @byte_dst:32 ; Zero is set: operation should succeed.
-	test_neg_clear
-	test_zero_set
-	test_ovf_clear
-	test_carry_clear
-	mov	@byte_dst, r1l
-	test_h_gr8 0 r1l
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-.if (sim_cpu == h8300)
-	test_h_gr16 0xa500 r1
-.else
-	test_h_gr32  0xa5a5a500 er1
-.endif
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	pass
-	exit 0

diff --git a/sim/testsuite/sim/h8300/cmp.b.s b/sim/testsuite/sim/h8300/cmp.b.s
deleted file mode 100644
index 3e57ae7..0000000
--- a/sim/testsuite/sim/h8300/cmp.b.s
+++ /dev/null

@@ -1,625 +0,0 @@
-# Hitachi H8 testcase 'cmp.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# cmp.b #xx:8, rd	;                     a rd   xxxxxxxx
-	# cmp.b #xx:8, @erd	;         7 d rd ???? a ???? xxxxxxxx
-	# cmp.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
-	# cmp.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
-	# cmp.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
-	# cmp.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
-	# cmp.b rs, rd		;                     1 c rs rd
-	# cmp.b reg8, @erd	;         7 d rd ???? 1 c rs ????
-	# cmp.b reg8, @erd+	;         0 1 7     9 8 rd 2 rs
-	# cmp.b reg8, @erd-	;         0 1 7     9 a rd 2 rs
-	# cmp.b reg8, @+erd	;         0 1 7     9 9 rd 2 rs
-	# cmp.b reg8, @-erd	;         0 1 7     9 b rd 2 rs
-	#
-
-	# Coming soon:
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0xa5
-post_byte:	.byte 0
-
-	start
-	
-cmp_b_imm8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.b #xx:8,Rd
-	cmp.b	#0xa5, r0l	; Immediate 8-bit src, reg8 dest
-	beq	.Leq1
-	fail
-.Leq1:	cmp.b	#0xa6, r0l
-	blt	.Llt1
-	fail
-.Llt1:	cmp.b	#0xa4, r0l
-	bgt	.Lgt1
-	fail
-.Lgt1:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a5 r0	; r0 unchanged
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5a5 er0	; er0 unchanged
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-cmp_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	cmp.b	#0xa5:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0xa0a5
-	beq	.Leq2
-	fail
-.Leq2:	set_ccr_zero
-	cmp.b	#0xa6, @er0
-;;; 	.word	0x7d00
-;;; 	.word	0xa0a6
-	blt	.Llt2
-	fail
-.Llt2:	set_ccr_zero
-	cmp.b	#0xa4, @er0
-;;; 	.word	0x7d00
-;;; 	.word	0xa0a4
-	bgt	.Lgt2
-	fail
-.Lgt2:		
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L2
-	fail
-.L2:
-
-cmp_b_imm8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	cmp.b	#0xa5:8, @er0+	; Immediate 8-bit src, reg postinc dst
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a5
-	beq	.Leq3
-	fail
-.Leq3:	test_h_gr32 post_byte er0	; er0 contains address plus one
-	mov	#byte_dest, er0
-	set_ccr_zero
-	cmp.b	#0xa6, @er0+
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a6
-	blt	.Llt3
-	fail
-.Llt3:	test_h_gr32 post_byte er0	; er0 contains address plus one
-	mov	#byte_dest, er0
-	set_ccr_zero
-	cmp.b	#0xa4, @er0+
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a4
-	bgt	.Lgt3
-	fail
-.Lgt3:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L3
-	fail
-.L3:
-
-cmp_b_imm8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	cmp.b	#0xa5:8, @er0-	; Immediate 8-bit src, reg postdec dst
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a5
-	beq	.Leq4
-	fail
-.Leq4:	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	mov	#byte_dest, er0
-	set_ccr_zero
-	cmp.b	#0xa6, @er0-
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a6
-	blt	.Llt4
-	fail
-.Llt4:	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	mov	#byte_dest, er0
-	set_ccr_zero
-	cmp.b	#0xa4, @er0-
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a4
-	bgt	.Lgt4
-	fail
-.Lgt4:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L4
-	fail
-.L4:
-
-cmp_b_imm8_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b #xx:8,@+eRd
-	mov	#pre_byte, er0
-	cmp.b	#0xa5:8, @+er0	; Immediate 8-bit src, reg pre-inc dst
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a5
-	beq	.Leq5
-	fail
-.Leq5:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#pre_byte, er0
-	set_ccr_zero
-	cmp.b	#0xa6, @+er0
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a6
-	blt	.Llt5
-	fail
-.Llt5:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#pre_byte, er0
-	set_ccr_zero
-	cmp.b	#0xa4, @+er0
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a4
-	bgt	.Lgt5
-	fail
-.Lgt5:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L5
-	fail
-.L5:
-
-cmp_b_imm8_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b #xx:8,@-eRd
-	mov	#post_byte, er0
-	cmp.b	#0xa5:8, @-er0	; Immediate 8-bit src, reg pre-dec dst
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a5
-	beq	.Leq6
-	fail
-.Leq6:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#post_byte, er0
-	set_ccr_zero
-	cmp.b	#0xa6, @-er0
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a6
-	blt	.Llt6
-	fail
-.Llt6:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#post_byte, er0
-	set_ccr_zero
-	cmp.b	#0xa4, @-er0
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0xa0a4
-	bgt	.Lgt6
-	fail
-.Lgt6:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L6
-	fail
-.L6:
-
-
-.endif
-
-cmp_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.b Rs,Rd
-	mov.b	#0xa5, r0h
-	cmp.b	r0h, r0l	; Reg8 src, reg8 dst
-	beq	.Leq7
-	fail
-.Leq7:	mov.b	#0xa6, r0h
-	cmp.b	r0h, r0l
-	blt	.Llt7
-	fail
-.Llt7:	mov.b	#0xa4, r0h
-	cmp.b	r0h, r0l
-	bgt	.Lgt7
-	fail
-.Lgt7:
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa4a5 r0	; r0l unchanged.
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a4a5 er0	; r0l unchanged
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-cmp_b_reg8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b rs8,@eRd	; cmp reg8 to register indirect
-	mov	#byte_dest, er0
-	mov	#0xa5, r1l
-	cmp.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x1c90
-	beq	.Leq8
-	fail
-.Leq8:	set_ccr_zero
-	mov	#0xa6, r1l
-	cmp.b	r1l, @er0
-;;; 	.word	0x7d00
-;;; 	.word	0x1c90
-	blt	.Llt8
-	fail
-.Llt8:	set_ccr_zero
-	mov	#0xa4, r1l
-	cmp.b	r1l, @er0
-;;; 	.word	0x7d00
-;;; 	.word	0x1c90
-	bgt	.Lgt8
-	fail
-.Lgt8:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a5a4 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (no change).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L8
-	fail
-.L8:
-
-cmp_b_reg8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b reg8,@eRd+
-	mov	#byte_dest, er0
-	mov	#0xa5, r1l
-	cmp.b	r1l, @er0+	; Immediate 8-bit src, reg post-incr dst
-;;; 	.word	0x0179
-;;; 	.word	0x8029
-	beq	.Leq9
-	fail
-.Leq9:	test_h_gr32 post_byte er0	; er0 contains address plus one
-	mov	#byte_dest er0
-	mov	#0xa6, r1l
-	set_ccr_zero
-	cmp.b	r1l, @er0+
-;;; 	.word	0x0179
-;;; 	.word	0x8029
-	blt	.Llt9
-	fail
-.Llt9:	test_h_gr32 post_byte er0	; er0 contains address plus one
-	mov	#byte_dest er0
-	mov	#0xa4, r1l
-	set_ccr_zero
-	cmp.b	r1l, @er0+
-;;; 	.word	0x0179
-;;; 	.word	0x8029
-	bgt	.Lgt9
-	fail
-.Lgt9:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a5a4 er1	; er1 contains test load
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L9
-	fail
-.L9:
-
-cmp_b_reg8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b reg8,@eRd-
-	mov	#byte_dest, er0
-	mov	#0xa5, r1l
-	cmp.b	r1l, @er0-	; Immediate 8-bit src, reg postdec dst
-;;; 	.word	0x0179
-;;; 	.word	0xa029
-	beq	.Leq10
-	fail
-.Leq10:	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	mov	#byte_dest er0
-	mov	#0xa6, r1l
-	set_ccr_zero
-	cmp.b	r1l, @er0-
-;;; 	.word	0x0179
-;;; 	.word	0xa029
-	blt	.Llt10
-	fail
-.Llt10:	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	mov	#byte_dest er0
-	mov	#0xa4, r1l
-	set_ccr_zero
-	cmp.b	r1l, @er0-
-;;; 	.word	0x0179
-;;; 	.word	0xa029
-	bgt	.Lgt10
-	fail
-.Lgt10:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a5a4 er1	; er1 contains test load
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L10
-	fail
-.L10:
-
-cmp_b_reg8_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b reg8,@+eRd
-	mov	#pre_byte, er0
-	mov	#0xa5, r1l
-	cmp.b	r1l, @+er0	; Immediate 8-bit src, reg post-incr dst
-;;; 	.word	0x0179
-;;; 	.word	0x9029
-	beq	.Leq11
-	fail
-.Leq11:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#pre_byte er0
-	mov	#0xa6, r1l
-	set_ccr_zero
-	cmp.b	r1l, @+er0
-;;; 	.word	0x0179
-;;; 	.word	0x9029
-	blt	.Llt11
-	fail
-.Llt11:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#pre_byte er0
-	mov	#0xa4, r1l
-	set_ccr_zero
-	cmp.b	r1l, @+er0
-;;; 	.word	0x0179
-;;; 	.word	0x9029
-	bgt	.Lgt11
-	fail
-.Lgt11:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a5a4 er1	; er1 contains test load
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L11
-	fail
-.L11:
-
-cmp_b_reg8_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  cmp.b reg8,@-eRd
-	mov	#post_byte, er0
-	mov	#0xa5, r1l
-	cmp.b	r1l, @-er0	; Immediate 8-bit src, reg postdec dst
-;;; 	.word	0x0179
-;;; 	.word	0xb029
-	beq	.Leq12
-	fail
-.Leq12:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#post_byte er0
-	mov	#0xa6, r1l
-	set_ccr_zero
-	cmp.b	r1l, @-er0
-;;; 	.word	0x0179
-;;; 	.word	0xb029
-	blt	.Llt12
-	fail
-.Llt12:	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	mov	#post_byte er0
-	mov	#0xa4, r1l
-	set_ccr_zero
-	cmp.b	r1l, @-er0
-;;; 	.word	0x0179
-;;; 	.word	0xb029
-	bgt	.Lgt12
-	fail
-.Lgt12:
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_h_gr32 0xa5a5a5a4 er1	; er1 contains test load
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the cmp to memory (memory unchanged).
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L12
-	fail
-.L12:
-
-.endif
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/cmp.l.s b/sim/testsuite/sim/h8300/cmp.l.s
deleted file mode 100644
index 55f235a..0000000
--- a/sim/testsuite/sim/h8300/cmp.l.s
+++ /dev/null

@@ -1,106 +0,0 @@
-# Hitachi H8 testcase 'cmp.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu == h8sx)		; 3-bit immediate mode only for h8sx
-cmp_l_imm3:			; 
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.l #xx:3,eRd	; Immediate 3-bit operand
-	mov.l	#5, er0
-	cmp.l	#5, er0
-	beq	eq3
-	fail
-eq3:
-	cmp.l	#6, er0
-	blt	lt3
-	fail
-lt3:
-	cmp.l	#4, er0
-	bgt	gt3
-	fail
-gt3:	
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0x00000005 er0	; er0 unchanged
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-cmp_l_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.l #xx:8,Rd
-	cmp.l	#0xa5a5a5a5, er0	; Immediate 16-bit operand
-	beq	eqi
-	fail
-eqi:	cmp.l	#0xa5a5a5a6, er0
-	blt	lti
-	fail
-lti:	cmp.l	#0xa5a5a5a4, er0
-	bgt	gti
-	fail
-gti:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a5 er0	; er0 unchanged
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-cmp_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.l Rs,Rd
-	mov.l	#0xa5a5a5a5, er1
-	cmp.l	er1, er0		; Register operand
-	beq	eqr
-	fail
-eqr:	mov.l	#0xa5a5a5a6, er1
-	cmp.l	er1, er0
-	blt	ltr
-	fail
-ltr:	mov.l	#0xa5a5a5a4, er1
-	cmp.l	er1, er0
-	bgt	gtr
-	fail
-gtr:
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a5 er0	; r0 unchanged
-	test_h_gr32 0xa5a5a5a4 er1	; r1 unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/cmp.w.s b/sim/testsuite/sim/h8300/cmp.w.s
deleted file mode 100644
index 2c69dbd..0000000
--- a/sim/testsuite/sim/h8300/cmp.w.s
+++ /dev/null

@@ -1,110 +0,0 @@
-# Hitachi H8 testcase 'cmp.w'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-.if (sim_cpu == h8sx)		; 3-bit immediate mode only for h8sx
-cmp_w_imm3:			; 
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.w #xx:3,Rd	; Immediate 3-bit operand
-	mov.w	#5, r0
-	cmp.w	#5, r0
-	beq	eq3
-	fail
-eq3:
-	cmp.w	#6, r0
-	blt	lt3
-	fail
-lt3:
-	cmp.w	#4, r0
-	bgt	gt3
-	fail
-gt3:	
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0xa5a50005 er0	; er0 unchanged
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-cmp_w_imm16:			; cmp.w immediate not available in h8300 mode.
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.w #xx:8,Rd
-	cmp.w	#0xa5a5, r0	; Immediate 16-bit operand
-	beq	eqi
-	fail
-eqi:	cmp.w	#0xa5a6, r0
-	blt	lti
-	fail
-lti:	cmp.w	#0xa5a4, r0
-	bgt	gti
-	fail
-gti:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a5 r0	; r0 unchanged
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5a5 er0	; er0 unchanged
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-	
-cmp_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  cmp.w Rs,Rd
-	mov.w	#0xa5a5, r1
-	cmp.w	r1, r0		; Register operand
-	beq	eqr
-	fail
-eqr:	mov.w	#0xa5a6, r1
-	cmp.w	r1, r0
-	blt	ltr
-	fail
-ltr:	mov.w	#0xa5a4, r1
-	cmp.w	r1, r0
-	bgt	gtr
-	fail
-gtr:
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a5 r0	; r0 unchanged.
-	test_h_gr16 0xa5a4 r1	; r1 unchanged.
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5a5 er0	; r0 unchanged
-	test_h_gr32 0xa5a5a5a4 er1	; r1 unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/daa.s b/sim/testsuite/sim/h8300/daa.s
deleted file mode 100644
index 5f81eba..0000000
--- a/sim/testsuite/sim/h8300/daa.s
+++ /dev/null

@@ -1,36 +0,0 @@
-# Hitachi H8 testcase 'daa'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-daa_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  daa Rd
-	daa	r0l		; register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr8 5 r0l
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/das.s b/sim/testsuite/sim/h8300/das.s
deleted file mode 100644
index 9317f19..0000000
--- a/sim/testsuite/sim/h8300/das.s
+++ /dev/null

@@ -1,36 +0,0 @@
-# Hitachi H8 testcase 'das'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-das_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  das Rd
-	das	r0l		; register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/dec.s b/sim/testsuite/sim/h8300/dec.s
deleted file mode 100644
index 122f311..0000000
--- a/sim/testsuite/sim/h8300/dec.s
+++ /dev/null

@@ -1,117 +0,0 @@
-# Hitachi H8 testcase 'dec.b, dec.w, dec.l'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-dec_b:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  dec.b Rd
-	dec.b	r0h		; Decrement 8-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa4a5 r0	; dec result: a4|a5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a4a5 er0	; dec result: a5|a5|a4|a5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-dec_w_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  dec.w #1, Rd
-	dec.w	#1, r0		; Decrement 16-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a4 r0	; dec result: a5|a4
-
-	test_h_gr32 0xa5a5a5a4 er0	; dec result:	a5|a5|a5|a4
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-dec_w_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  dec.w #2, Rd
-	dec.w	#2, r0		; Decrement 16-bit reg by two
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a3 r0	; dec result: a5|a3
-
-	test_h_gr32 0xa5a5a5a3 er0	; dec result:	a5|a5|a5|a3
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-dec_l_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  dec.l #1, eRd
-	dec.l	#1, er0		; Decrement 32-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a4 er0	; dec result:	a5|a5|a5|a4
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-dec_l_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  dec.l #2, eRd
-	dec.l	#2, er0		; Decrement 32-bit reg by two
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a3 er0	; dec result:	a5|a5|a5|a3
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/ext.l.s b/sim/testsuite/sim/h8300/ext.l.s
deleted file mode 100644
index 43a713d..0000000
--- a/sim/testsuite/sim/h8300/ext.l.s
+++ /dev/null

@@ -1,1146 +0,0 @@
-# Hitachi H8 testcase 'exts.l, extu.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-	.align 4
-pos:	.long	0xffff0001
-neg:	.long	0x00008000
-
-pos2:	.long	0xffffff01
-neg2:	.long	0x00000080
-
-	.text
-
-exts_l_reg32_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l ern32
-	mov.w	#1, r0
-	exts.l	er0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0x00000001 er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-exts_l_reg32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l ern32
-	mov.w	#0xffff, r0
-	exts.l	er0
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  0xffffffff er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-extu_l_reg32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l ern32
-	mov.w	#0xffff, r0
-	extu.l	er0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0x0000ffff er0	; result of zero extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-exts_l_ind_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32
-	mov.l	#pos, er1
-	exts.l	@er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos
-	beq	.Lslindp
-	fail
-.Lslindp:
-	mov.l	#0xffff0001, @pos	; Restore initial value
-
-exts_l_ind_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32
-	mov.l	#neg, er1
-	exts.l	@er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffff8000, @neg
-	beq     .Lslindn
-	fail
-.Lslindn:
-;;;  Note:	 leave the value as 0xffff8000, so that extu has work to do.
-	
-extu_l_ind_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @ern32
-	mov.l	#neg, er1
-	extu.l	@er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulindn
-	fail
-.Lulindn:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-exts_l_postinc_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32+
-	mov.l	#pos, er1
-	exts.l	@er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos+4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos
-	beq	.Lslpostincp
-	fail
-.Lslpostincp:
-	mov.l	#0xffff0001, @pos	; Restore initial value
-
-exts_l_postinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32+
-	mov.l	#neg, er1
-	exts.l	@er1+
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg+4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffff8000, @neg
-	beq     .Lslpostincn
-	fail
-.Lslpostincn:
-;;;  Note:	 leave the value as 0xffff8000, so that extu has work to do.
-	
-extu_l_postinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @ern32+
-	mov.l	#neg, er1
-	extu.l	@er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg+4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulpostincn
-	fail
-.Lulpostincn:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-exts_l_postdec_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32-
-	mov.l	#pos, er1
-	exts.l	@er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos-4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos
-	beq	.Lslpostdecp
-	fail
-.Lslpostdecp:
-	mov.l	#0xffff0001, @pos	; Restore initial value
-
-exts_l_postdec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @ern32-
-	mov.l	#neg, er1
-	exts.l	@er1-
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg-4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffff8000, @neg
-	beq     .Lslpostdecn
-	fail
-.Lslpostdecn:
-;;;  Note:	 leave the value as 0xffff8000, so that extu has work to do.
-	
-extu_l_postdec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @ern32-
-	mov.l	#neg, er1
-	extu.l	@er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-4 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulpostdecn
-	fail
-.Lulpostdecn:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-exts_l_preinc_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @+ern32
-	mov.l	#pos-4, er1
-	exts.l	@+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos
-	beq	.Lslpreincp
-	fail
-.Lslpreincp:
-	mov.l	#0xffff0001, @pos	; Restore initial value
-
-exts_l_preinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @+ern32
-	mov.l	#neg-4, er1
-	exts.l	@+er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffff8000, @neg
-	beq     .Lslpreincn
-	fail
-.Lslpreincn:
-;;;  Note:	 leave the value as 0xffff8000, so that extu has work to do.
-	
-extu_l_preinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @+ern32
-	mov.l	#neg-4, er1
-	extu.l	@+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulpreincn
-	fail
-.Lulpreincn:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-exts_l_predec_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @-ern32
-	mov.l	#pos+4, er1
-	exts.l	@-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos
-	beq	.Lslpredecp
-	fail
-.Lslpredecp:
-	mov.l	#0xffff0001, @pos	; Restore initial value
-
-exts_l_predec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l @-ern32
-	mov.l	#neg+4, er1
-	exts.l	@-er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffff8000, @neg
-	beq     .Lslpredecn
-	fail
-.Lslpredecn:
-;;;  Note:	 leave the value as 0xffff8000, so that extu has work to do.
-	
-extu_l_predec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @-ern32
-	mov.l	#neg+4, er1
-	extu.l	@-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulpredecn
-	fail
-.Lulpredecn:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-extu_l_disp2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @(dd:2, ern32)
-	mov.l	#neg-2, er1
-	extu.l	@(2:2, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-2 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Luldisp2n
-	fail
-.Luldisp2n:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-extu_l_disp16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @(dd:16, ern32)
-	mov.l	#neg-44, er1
-	extu.l	@(44:16, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-44 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Luldisp16n
-	fail
-.Luldisp16n:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-extu_l_disp32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @(dd:32, ern32)
-	mov.l	#neg+444, er1
-	extu.l	@(-444:32, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg+444 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Luldisp32n
-	fail
-.Luldisp32n:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-extu_l_abs16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @aa:16
-	extu.l	@neg:16
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulabs16n
-	fail
-.Lulabs16n:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-extu_l_abs32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l @aa:32
-	extu.l	@neg:32
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00008000, @neg
-	beq     .Lulabs32n
-	fail
-.Lulabs32n:
-;;;  Note:	 leave the value as 0x00008000, so that extu has work to do.
-
-
-
-	#
-	# exts #2, nn
-	#
-
-exts_l_reg32_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, ern32
-	mov.b	#1, r0l
-	exts.l	#2, er0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0x00000001 er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-exts_l_reg32_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, ern32
-	mov.b	#0xff, r0l
-	exts.l	#2, er0
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  0xffffffff er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-extu_l_reg32_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, ern32
-	mov.b	#0xff, r0l
-	extu.l	#2, er0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0x000000ff er0	; result of zero extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-exts_l_ind_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32
-	mov.l	#pos2, er1
-	exts.l	#2, @er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos2
-	beq	.Lslindp2
-	fail
-.Lslindp2:
-	mov.l	#0xffffff01, @pos2	; Restore initial value
-
-exts_l_ind_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32
-	mov.l	#neg2, er1
-	exts.l	#2, @er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  neg2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffffff80, @neg2
-	beq     .Lslindn2
-	fail
-.Lslindn2:
-;;;  Note:	 leave the value as 0xffffff80, so that extu has work to do.
-
-extu_l_ind_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @ern32
-	mov.l	#neg2, er1
-	extu.l	#2, @er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulindn2
-	fail
-.Lulindn2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-exts_l_postinc_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32+
-	mov.l	#pos2, er1
-	exts.l	#2, @er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos2+4 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos2
-	beq	.Lslpostincp2
-	fail
-.Lslpostincp2:
-	mov.l	#0xffffff01, @pos2	; Restore initial value
-
-exts_l_postinc_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32+
-	mov.l	#neg2, er1
-	exts.l	#2, @er1+
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  neg2+4 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffffff80, @neg2
-	beq     .Lslpostincn2
-	fail
-.Lslpostincn2:
-;;;  Note:	 leave the value as 0xffffff80, so that extu has work to do.
-
-extu_l_postinc_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @ern32+
-	mov.l	#neg2, er1
-	extu.l	#2, @er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2+4 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulpostincn2
-	fail
-.Lulpostincn2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-exts_l_postdec_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32-
-	mov.l	#pos2, er1
-	exts.l	#2, @er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos2-4 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos2
-	beq	.Lslpostdecp2
-	fail
-.Lslpostdecp2:
-	mov.l	#0xffffff01, @pos2	; Restore initial value
-
-exts_l_postdec_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @ern32-
-	mov.l	#neg2, er1
-	exts.l	#2, @er1-
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  neg2-4 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffffff80, @neg2
-	beq     .Lslpostdecn2
-	fail
-.Lslpostdecn2:
-;;;  Note:	 leave the value as 0xffffff80, so that extu has work to do.
-
-extu_l_postdec_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @ern32-
-	mov.l	#neg2, er1
-	extu.l	#2, @er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2-4 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulpostdecn2
-	fail
-.Lulpostdecn2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-exts_l_preinc_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @+ern32
-	mov.l	#pos2-4, er1
-	exts.l	#2, @+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos2
-	beq	.Lslpreincp2
-	fail
-.Lslpreincp2:
-	mov.l	#0xffffff01, @pos2	; Restore initial value
-
-exts_l_preinc_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @+ern32
-	mov.l	#neg2-4, er1
-	exts.l	#2, @+er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  neg2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffffff80, @neg2
-	beq     .Lslpreincn2
-	fail
-.Lslpreincn2:
-;;;  Note:	 leave the value as 0xffffff80, so that extu has work to do.
-
-extu_l_preinc_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @+ern32
-	mov.l	#neg2-4, er1
-	extu.l	#2, @+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulpreincn2
-	fail
-.Lulpreincn2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-exts_l_predec_2_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @-ern32
-	mov.l	#pos2+4, er1
-	exts.l	#2, @-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.l	#0x00000001, @pos2
-	beq	.Lslpredecp2
-	fail
-.Lslpredecp2:
-	mov.l	#0xffffff01, @pos2	; Restore initial value
-
-exts_l_predec_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.l #2, @-ern32
-	mov.l	#neg2+4, er1
-	exts.l	#2, @-er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_ovf_clear
-	test_zero_clear
-	test_carry_clear
-
-	test_h_gr32  neg2 er1	; result of sign extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0xffffff80, @neg2
-	beq     .Lslpredecn2
-	fail
-.Lslpredecn2:
-;;;  Note:	 leave the value as 0xffffff80, so that extu has work to do.
-
-extu_l_predec_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @-ern32
-	mov.l	#neg2+4, er1
-	extu.l	#2, @-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulpredecn2
-	fail
-.Lulpredecn2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-extu_l_disp2_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @(dd:2, ern32)
-	mov.l	#neg2-2, er1
-	extu.l	#2, @(2:2, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2-2 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Luldisp2n2
-	fail
-.Luldisp2n2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-extu_l_disp16_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @(dd:16, ern32)
-	mov.l	#neg2-44, er1
-	extu.l	#2, @(44:16, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2-44 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Luldisp16n2
-	fail
-.Luldisp16n2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-extu_l_disp32_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @(dd:32, ern32)
-	mov.l	#neg2+444, er1
-	extu.l	#2, @(-444:32, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg2+444 er1	; result of zero extend
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Luldisp32n2
-	fail
-.Luldisp32n2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-extu_l_abs16_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @aa:16
-	extu.l	#2, @neg2:16
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulabs16n2
-	fail
-.Lulabs16n2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-extu_l_abs32_2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.l #2, @aa:32
-	extu.l	#2, @neg2:32
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-        cmp.l   #0x00000080, @neg2
-	beq     .Lulabs32n2
-	fail
-.Lulabs32n2:
-;;;  Note:	 leave the value as 0x00000080, like it started out.
-
-.endif
-
-	pass
-
-	exit 0
-
-
-
-

diff --git a/sim/testsuite/sim/h8300/ext.w.s b/sim/testsuite/sim/h8300/ext.w.s
deleted file mode 100644
index 417dd0c..0000000
--- a/sim/testsuite/sim/h8300/ext.w.s
+++ /dev/null

@@ -1,580 +0,0 @@
-# Hitachi H8 testcase 'exts.w, extu.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-	.align 2
-pos:	.word	0xff01
-neg:	.word	0x0080
-
-	.text
-
-exts_w_reg16_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w rn16
-	mov.b	#1, r0l
-	exts.w	r0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0xa5a50001 er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-exts_w_reg16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w rn16
-	mov.b	#0xff, r0l
-	exts.w	r0
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  0xa5a5ffff er0	; result of sign extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-extu_w_reg16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w rn16
-	mov.b	#0xff, r0l
-	extu.w	r0
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  0xa5a500ff er0	; result of zero extend
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-exts_w_ind_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern
-	mov.l	#pos, er1
-	exts.w	@er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0001, @pos
-	beq	.Lswindp
-	fail
-.Lswindp:
-	mov.w	#0xff01, @pos	; Restore initial value
-
-exts_w_ind_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern
-	mov.l	#neg, er1
-	exts.w	@er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0xff80, @neg
-	beq	.Lswindn
-	fail
-.Lswindn:
-	;; Note: leave the value as 0xff80, so that extu has work to do.
-	
-extu_w_ind_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @ern
-	mov.l	#neg, er1
-	extu.w	@er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwindn
-	fail
-.Luwindn:
-	;; Note: leave the value as 0x0080, like it started out.
-
-exts_w_postinc_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern+
-	mov.l	#pos, er1
-	exts.w	@er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos+2 er1	; er1 still contains target address plus 2
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0001, @pos
-	beq	.Lswpostincp
-	fail
-.Lswpostincp:
-	mov.w	#0xff01, @pos	; Restore initial value
-
-exts_w_postinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern+
-	mov.l	#neg, er1
-	exts.w	@er1+
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg+2 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0xff80, @neg
-	beq	.Lswpostincn
-	fail
-.Lswpostincn:
-	;; Note: leave the value as 0xff80, so that extu has work to do.
-	
-extu_w_postinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @ern+
-	mov.l	#neg, er1
-	extu.w	@er1+
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg+2 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwpostincn
-	fail
-.Luwpostincn:
-	;; Note: leave the value as 0x0080, like it started out.
-
-exts_w_postdec_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern-
-	mov.l	#pos, er1
-	exts.w	@er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos-2 er1	; er1 still contains target address plus 2
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0001, @pos
-	beq	.Lswpostdecp
-	fail
-.Lswpostdecp:
-	mov.w	#0xff01, @pos	; Restore initial value
-
-exts_w_postdec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @ern-
-	mov.l	#neg, er1
-	exts.w	@er1-
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg-2 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0xff80, @neg
-	beq	.Lswpostdecn
-	fail
-.Lswpostdecn:
-	;; Note: leave the value as 0xff80, so that extu has work to do.
-	
-extu_w_postdec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @ern-
-	mov.l	#neg, er1
-	extu.w	@er1-
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-2 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwpostdecn
-	fail
-.Luwpostdecn:
-	;; Note: leave the value as 0x0080, like it started out.
-
-exts_w_preinc_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @+ern
-	mov.l	#pos-2, er1
-	exts.w	@+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address plus 2
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0001, @pos
-	beq	.Lswpreincp
-	fail
-.Lswpreincp:
-	mov.w	#0xff01, @pos	; Restore initial value
-
-exts_w_preinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @+ern
-	mov.l	#neg-2, er1
-	exts.w	@+er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0xff80, @neg
-	beq	.Lswpreincn
-	fail
-.Lswpreincn:
-	;; Note: leave the value as 0xff80, so that extu has work to do.
-	
-extu_w_preinc_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @+ern
-	mov.l	#neg-2, er1
-	extu.w	@+er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwpreincn
-	fail
-.Luwpreincn:
-	;; Note: leave the value as 0x0080, like it started out.
-
-exts_w_predec_p:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @-ern
-	mov.l	#pos+2, er1
-	exts.w	@-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  pos er1	; er1 still contains target address plus 2
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0001, @pos
-	beq	.Lswpredecp
-	fail
-.Lswpredecp:
-	mov.w	#0xff01, @pos	; Restore initial value
-
-exts_w_predec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; exts.w @-ern
-	mov.l	#neg+2, er1
-	exts.w	@-er1
-
-	;; Test ccr		H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0xff80, @neg
-	beq	.Lswpredecn
-	fail
-.Lswpredecn:
-	;; Note: leave the value as 0xff80, so that extu has work to do.
-	
-extu_w_predec_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @-ern
-	mov.l	#neg+2, er1
-	extu.w	@-er1
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwpredecn
-	fail
-.Luwpredecn:
-	;; Note: leave the value as 0x0080, like it started out.
-
-extu_w_disp2_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @(dd:2, ern)
-	mov.l	#neg-1, er1
-	extu.w	@(1:2, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-1 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwdisp2n
-	fail
-.Luwdisp2n:
-	;; Note: leave the value as 0x0080, like it started out.
-
-extu_w_disp16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @(dd:16, ern)
-	mov.l	#neg-44, er1
-	extu.w	@(44:16, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg-44 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwdisp16n
-	fail
-.Luwdisp16n:
-	;; Note: leave the value as 0x0080, like it started out.
-
-extu_w_disp32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @(dd:32, ern)
-	mov.l	#neg+444, er1
-	extu.w	@(-444:32, er1)
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_h_gr32  neg+444 er1	; er1 still contains target address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwdisp32n
-	fail
-.Luwdisp32n:
-	;; Note: leave the value as 0x0080, like it started out.
-
-extu_w_abs16_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @aa:16
-	extu.w	@neg:16
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwabs16n
-	fail
-.Luwabs16n:
-	;; Note: leave the value as 0x0080, like it started out.
-
-extu_w_abs32_n:
-	set_grs_a5a5
-	set_ccr_zero
-	;; extu.w @aa:32
-	extu.w	@neg:32
-
-	;; Test ccr		H=0 N=0 Z=0 V=0 C=0
-	test_cc_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	cmp.w	#0x0080, @neg
-	beq	.Luwabs32n
-	fail
-.Luwabs32n:
-	;; Note: leave the value as 0x0080, like it started out.
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/inc.s b/sim/testsuite/sim/h8300/inc.s
deleted file mode 100644
index 69d2c3b..0000000
--- a/sim/testsuite/sim/h8300/inc.s
+++ /dev/null

@@ -1,117 +0,0 @@
-# Hitachi H8 testcase 'inc, inc.w, inc.l'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-inc_b:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  inc.b Rd
-	inc.b	r0h		; Increment 8-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa6a5 r0	; inc result: a6|a5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a6a5 er0	; inc result: a5|a5|a6|a5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-inc_w_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  inc.w #1, Rd
-	inc.w	#1, r0		; Increment 16-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a6 r0	; inc result: a5|a6
-
-	test_h_gr32 0xa5a5a5a6 er0	; inc result:	a5|a5|a5|a6
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-inc_w_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  inc.w #2, Rd
-	inc.w	#2, r0		; Increment 16-bit reg by two
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a7 r0	; inc result: a5|a7
-
-	test_h_gr32 0xa5a5a5a7 er0	; inc result:	a5|a5|a5|a7
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-inc_l_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  inc.l #1, eRd
-	inc.l	#1, er0		; Increment 32-bit reg by one
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a6 er0	; inc result:	a5|a5|a5|a6
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-inc_l_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  inc.l #2, eRd
-	inc.l	#2, er0		; Increment 32-bit reg by two
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5a5a7 er0	; inc result:	a5|a5|a5|a7
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/jmp.s b/sim/testsuite/sim/h8300/jmp.s
deleted file mode 100644
index 805bafe..0000000
--- a/sim/testsuite/sim/h8300/jmp.s
+++ /dev/null

@@ -1,103 +0,0 @@
-# Hitachi H8 testcase 'jmp'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-.if 0				; this one isn't right -- it's an indirect
-jmp_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  jmp @aa:8		; 8-bit displacement
-	jmp @@.Ltgt_8:8
-	fail
-
-.Ltgt_8:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-jmp_24:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  jmp @aa:24		; 24-bit address
-	jmp @.Ltgt_24:24
-	fail
-
-.Ltgt_24:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if	(sim_cpu)		; Non-zero means h8300h, h8300s, or h8sx
-jmp_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  jmp @ern		; register indirect
-	mov.l	#.Ltgt_reg, er5
-	jmp	@er5
-	fail
-	
-.Ltgt_reg:
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_h_gr32 .Ltgt_reg er5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu == h8sx)
-jmp_32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  jmp @aa:32		; 32-bit address
-;	jmp @.Ltgt_32:32	; NOTE:	hard-coded to avoid relaxing
-	.word	0x5908
-	.long	.Ltgt_32
-	fail
-
-.Ltgt_32:	
-	test_cc_clear
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	pass
-	exit 0
-
-	
\ No newline at end of file

diff --git a/sim/testsuite/sim/h8300/ldc.s b/sim/testsuite/sim/h8300/ldc.s
deleted file mode 100644
index 4e9765a..0000000
--- a/sim/testsuite/sim/h8300/ldc.s
+++ /dev/null

@@ -1,375 +0,0 @@
-# Hitachi H8 testcase 'ldc'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-	.data
-byte_pre:
-	.byte	0
-byte_src:
-	.byte	0xff
-byte_post:
-	.byte	0
-	
-	start
-
-ldc_imm8_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0xff, ccr	; set all ccr flags high, immediate operand
-	bcs	.L1		; carry flag set?
-	fail
-.L1:	bvs	.L2		; overflow flag set?
-	fail
-.L2:	beq	.L3		; zero flag set?
-	fail
-.L3:	bmi	.L4		; neg flag set?
-	fail
-.L4:
-	ldc	#0, ccr		; set all ccr flags low, immediate operand
-	bcc	.L5		; carry flag clear?
-	fail
-.L5:	bvc	.L6		; overflow flag clear?
-	fail
-.L6:	bne	.L7		; zero flag clear?
-	fail
-.L7:	bpl	.L8		; neg flag clear?
-	fail
-.L8:
-	test_cc_clear
-	test_grs_a5a5
-	
-ldc_reg8_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#0xff, r0h
-	ldc	r0h, ccr	; set all ccr flags high, reg operand
-	bcs	.L11		; carry flag set?
-	fail
-.L11:	bvs	.L12		; overflow flag set?
-	fail
-.L12:	beq	.L13		; zero flag set?
-	fail
-.L13:	bmi	.L14		; neg flag set?
-	fail
-.L14:
-	mov	#0, r0h
-	ldc	r0h, ccr	; set all ccr flags low, reg operand
-	bcc	.L15		; carry flag clear?
-	fail
-.L15:	bvc	.L16		; overflow flag clear?
-	fail
-.L16:	bne	.L17		; zero flag clear?
-	fail
-.L17:	bpl	.L18		; neg flag clear?
-	fail
-.L18:
-	test_cc_clear
-	test_h_gr16  0x00a5 r0	; Register 0 modified by test procedure.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8300s || sim_cpu == h8sx)	; Earlier versions, no exr
-ldc_imm8_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	ldc	#0x87, exr	; set exr to 0x87
-
-	stc	exr, r0l	; retrieve and check exr value
-	cmp.b	#0x87, r0l
-	beq	.L19
-	fail
-.L19:
-	test_h_gr16  0xa587 r0	; Register 0 modified by test procedure.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-ldc_reg8_exr:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	mov	#0x87, r0h
-	ldc	r0h, exr	; set exr to 0x87
-
-	stc	exr, r0l	; retrieve and check exr value
-	cmp.b	#0x87, r0l
-	beq	.L21
-	fail
-.L21:
-	test_h_gr16  0x8787 r0	; Register 0 modified by test procedure.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_abs16_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	@byte_src:16, ccr	; abs16 src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_abs16_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	ldc	@byte_src:16, exr	; abs16 src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_abs32_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	@byte_src:32, ccr	; abs32 src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_abs32_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	ldc	@byte_src:32, exr	; abs32 src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_disp16_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_pre, er1
-	ldc	@(1:16, er1), ccr	; disp16 src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_h_gr32 byte_pre, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_disp16_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	mov	#byte_post, er1
-	ldc	@(-1:16, er1), exr	; disp16 src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_h_gr32 byte_post, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_disp32_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_pre, er1
-	ldc	@(1:32, er1), ccr	; disp32 src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_h_gr32 byte_pre, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_disp32_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	mov	#byte_post, er1
-	ldc	@(-1:32, er1), exr	; disp16 src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_h_gr32 byte_post, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_postinc_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_src, er1
-	ldc	@er1+, ccr	; postinc src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_h_gr32 byte_post, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-ldc_postinc_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	mov	#byte_src, er1
-	ldc	@er1+, exr	; postinc src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_h_gr32 byte_post, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-ldc_ind_ccr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_src, er1
-	ldc	@er1, ccr	; postinc src
-	stc	ccr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a5ff er0	; ff in r0l, a5 elsewhere.
-	test_h_gr32 byte_src, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-ldc_ind_exr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0, exr
-	mov	#byte_src, er1
-	ldc	@er1, exr	; postinc src
-	stc	exr, r0l	; copy into general reg
-
-	test_h_gr32 0xa5a5a587 er0	; 87 in r0l, a5 elsewhere.
-	test_h_gr32 byte_src, er1	; er1 still contains address
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-	
-.if (sim_cpu == h8sx)		; New vbr and sbr registers for h8sx
-ldc_reg_sbr:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#0xaaaaaaaa, er0
-	ldc	er0, sbr	; set sbr to 0xaaaaaaaa
- 	stc	sbr, er1	; retreive and check sbr value
-
-	test_h_gr32 0xaaaaaaaa er1
-	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-ldc_reg_vbr:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#0xaaaaaaaa, er0
-	ldc	er0, vbr	; set sbr to 0xaaaaaaaa
-	stc	vbr, er1	; retreive and check sbr value
-
-	test_h_gr32 0xaaaaaaaa er1
-	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/mac.s b/sim/testsuite/sim/h8300/mac.s
deleted file mode 100644
index 0388b98..0000000
--- a/sim/testsuite/sim/h8300/mac.s
+++ /dev/null

@@ -1,263 +0,0 @@
-# Hitachi H8 testcase 'mac'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	.data
-src1:	.word	0
-src2:	.word	0
-
-array:	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-	.word	0x7fff
-
-	start
-
-.if (sim_cpu)
-_clrmac:
-	set_grs_a5a5
-	set_ccr_zero
-	clrmac
-	test_cc_clear
-	test_grs_a5a5
-	;; Now see if the mac is actually clear...
-	stmac	mach, er0
-	test_zero_set
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er0
-	stmac	macl, er1
-	test_zero_set
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er1
-
-ld_stmac:
-	set_grs_a5a5
-	sub.l	er2, er2
-	set_ccr_zero
-	ldmac	er1, macl
-	stmac	macl, er2
-	test_ovf_clear
-	test_carry_clear
-	;; neg and zero are undefined
-	test_h_gr32 0xa5a5a5a5 er2
-
-	sub.l	er2, er2
-	set_ccr_zero
-	ldmac	er1, mach
-	stmac	mach, er2
-	test_ovf_clear
-	test_carry_clear
-	;; neg and zero are undefined
-	test_h_gr32 0x0001a5 er2
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mac_2x2:
-	set_grs_a5a5
-	mov.w	#2, r1
-	mov.w	r1, @src1
-	mov.w	#2, r2
-	mov.w	r2, @src2
-	mov	#src1, er1
-	mov	#src2, er2
-	set_ccr_zero
-	clrmac
-	mac	@er1+, @er2+
-	test_cc_clear
-	
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 src1+2     er1
-	test_h_gr32 src2+2     er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-	stmac	macl, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 4 er0
-
-	stmac	mach, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er0
-
-mac_same_reg_2x4:
-	;; Use same reg for src and dst.  Should be incremented twice,
-	;; and fetch values from consecutive locations.
-	set_grs_a5a5
-	mov.w	#2, r1
-	mov.w	r1, @src1
-	mov.w	#4, r2
-	mov.w	r2, @src2
-	mov	#src1, er1
-
-	set_ccr_zero
-	clrmac
-	mac	@er1+, @er1+	; same register for src and dst
-	test_cc_clear
-	
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 src1+4     er1
-	test_h_gr32 0xa5a50004 er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-	stmac	macl, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 8 er0
-
-	stmac	mach, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er0
-
-mac_0x0:
-	set_grs_a5a5
-	mov.w	#0, r1
-	mov.w	r1, @src1
-	mov.w	#0, r2
-	mov.w	r2, @src2
-	mov	#src1, er1
-	mov	#src2, er2
-	set_ccr_zero
-	clrmac
-	mac	@er1+, @er2+
-	test_cc_clear
-	
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 src1+2     er1
-	test_h_gr32 src2+2     er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-	stmac	macl, er0
-	test_zero_set		; zero flag is set
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er0	; result is zero
-
-	stmac	mach, er0
-	test_zero_set
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0 er0
-
-mac_neg2x2:
-	set_grs_a5a5
-	mov.w	#-2, r1
-	mov.w	r1, @src1
-	mov.w	#2, r2
-	mov.w	r2, @src2
-	mov	#src1, er1
-	mov	#src2, er2
-	set_ccr_zero
-	clrmac
-	mac	@er1+, @er2+
-	test_cc_clear
-	
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 src1+2     er1
-	test_h_gr32 src2+2     er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-	stmac	macl, er0
-	test_zero_clear
-	test_neg_set		; neg flag is set
-	test_ovf_clear
-	test_h_gr32 -4 er0	; result is negative
-
-	stmac	mach, er0
-	test_zero_clear
-	test_neg_set
-	test_ovf_clear
-	test_h_gr32 -1 er0	; negative sign extend
-
-mac_array:
-	;; Use same reg for src and dst, pointing to an array of shorts
-	set_grs_a5a5
-	mov	#array, er1
-
-	set_ccr_zero
-	clrmac
-	mac	@er1+, @er1+	; same register for src and dst
-	mac	@er1+, @er1+	; repeat 8 times
-	mac	@er1+, @er1+
-	mac	@er1+, @er1+
-	mac	@er1+, @er1+
-	mac	@er1+, @er1+
-	mac	@er1+, @er1+
-	mac	@er1+, @er1+
-	test_cc_clear
-	
-	test_h_gr32 0xa5a5a5a5 er0
-	test_h_gr32 array+32     er1
-	test_h_gr32 0xa5a5a5a5 er2
-	test_h_gr32 0xa5a5a5a5 er3
-	test_h_gr32 0xa5a5a5a5 er4
-	test_h_gr32 0xa5a5a5a5 er5
-	test_h_gr32 0xa5a5a5a5 er6
-	test_h_gr32 0xa5a5a5a5 er7
-
-	stmac	macl, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 0xfff80008 er0
-
-	stmac	mach, er0
-	test_zero_clear
-	test_neg_clear
-	test_ovf_clear
-	test_h_gr32 1 er0	; result is greater than 32 bits
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/mov.b.s b/sim/testsuite/sim/h8300/mov.b.s
deleted file mode 100644
index 0c27aa3..0000000
--- a/sim/testsuite/sim/h8300/mov.b.s
+++ /dev/null

@@ -1,1495 +0,0 @@
-# Hitachi H8 testcase 'mov.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-	.align	4
-byte_src:
-	.byte	0x77
-byte_dst:
-	.byte	0
-
-	.text
-
-	;;
-	;; Move byte from immediate source
-	;; 
-
-.if (sim_cpu == h8sx)
-mov_b_imm8_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, rd
-	mov.b	#0x77:8, r0l	; Immediate 3-bit operand
-;;;	.word	0xf877
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu == h8sx)
-mov_b_imm4_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:4, @aa:16
-	mov.b	#0xf:4, @byte_dst:16	; 16-bit address-direct operand
-;;;	.word	0x6adf
-;;;	.word	@byte_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xf, @byte_dst
-	beq	.Lnext21
-	fail
-.Lnext21:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm4_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:4, @aa:32
-	mov.b	#0xf:4, @byte_dst:32	; 32-bit address-direct operand
-;;;	.word	0x6aff
-;;;	.long	@byte_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xf, @byte_dst
-	beq	.Lnext22
-	fail
-.Lnext22:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @erd
-	mov.l	#byte_dst, er1
-	mov.b	#0xa5:8, @er1	; Register indirect operand
-;;;	.word	0x017d
-;;;	.word	0x01a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext1
-	fail
-.Lnext1:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_postinc:		; post-increment from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @erd+
-	mov.l	#byte_dst, er1
-	mov.b	#0xa5:8, @er1+	; Imm8, register post-incr operands.
-;;;	.word	0x017d
-;;;	.word	0x81a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst+1, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext2
-	fail
-.Lnext2:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_postdec:		; post-decrement from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @erd-
-	mov.l	#byte_dst, er1
-	mov.b	#0xa5:8, @er1-	; Imm8, register post-decr operands.
-;;;	.word	0x017d
-;;;	.word	0xa1a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-1, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext3
-	fail
-.Lnext3:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @+erd
-	mov.l	#byte_dst-1, er1
-	mov.b	#0xa5:8, @+er1	; Imm8, register pre-incr operands
-;;;	.word	0x017d
-;;;	.word	0x91a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext4
-	fail
-.Lnext4:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @-erd
-	mov.l	#byte_dst+1, er1
-	mov.b	#0xa5:8, @-er1	; Imm8, register pre-decr operands
-;;;	.word	0x017d
-;;;	.word	0xb1a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext5
-	fail
-.Lnext5:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @(dd:2, erd)
-	mov.l	#byte_dst-3, er1
-	mov.b	#0xa5:8, @(3:2, er1)	; Imm8, reg plus 2-bit disp. operand
-;;;	.word	0x017d
-;;;	.word	0x31a5
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext6
-	fail
-.Lnext6:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @(dd:16, erd)
-	mov.l	#byte_dst-4, er1
-	mov.b	#0xa5:8, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x017d
-;;;	.word	0x6f90
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext7
-	fail
-.Lnext7:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @(dd:32, erd)
-	mov.l	#byte_dst-8, er1
-	mov.b	#0xa5:8, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x017d
-;;;	.word	0xc9a5
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext8
-	fail
-.Lnext8:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @aa:16
-	mov.b	#0xa5:8, @byte_dst:16	; 16-bit address-direct operand
-;;;	.word	0x017d
-;;;	.word	0x40a5
-;;;	.word	@byte_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext9
-	fail
-.Lnext9:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_imm8_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b #xx:8, @aa:32
-	mov.b	#0xa5:8, @byte_dst:32	; 32-bit address-direct operand
-;;;	.word	0x017d
-;;;	.word	0x48a5
-;;;	.long	@byte_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	#0xa5, @byte_dst
-	beq	.Lnext10
-	fail
-.Lnext10:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-.endif
-
-	;;
-	;; Move byte from register source
-	;; 
-
-mov_b_reg8_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, erd
-	mov.b	#0x12, r1l
-	mov.b	r1l, r0l	; Register 8-bit operand
-;;;	.word	0x0c98
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-	test_h_gr16 0xa512 r0
-	test_h_gr16 0xa512 r1	; mov src unchanged
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a512 er0
-	test_h_gr32 0xa5a5a512 er1	; mov src unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-
-mov_b_reg8_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @erd
-	mov.l	#byte_dst, er1
-	mov.b	r0l, @er1	; Register indirect operand
-;;;	.word	0x6898
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r2l, r0l
-	beq	.Lnext44
-	fail
-.Lnext44:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_b_reg8_to_postinc:		; post-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @erd+
-	mov.l	#byte_dst, er1
-	mov.b	r0l, @er1+	; Register post-incr operand
-;;;	.word	0x0173
-;;;	.word	0x6c98
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst+1, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	r2l, @byte_dst
-	beq	.Lnext49
-	fail
-.Lnext49:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_reg8_to_postdec:		; post-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @erd-
-	mov.l	#byte_dst, er1
-	mov.b	r0l, @er1-	; Register post-decr operand
-;;;	.word	0x0171
-;;;	.word	0x6c98
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-1, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	r2l, @byte_dst
-	beq	.Lnext50
-	fail
-.Lnext50:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-
-mov_b_reg8_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @+erd
-	mov.l	#byte_dst-1, er1
-	mov.b	r0l, @+er1	; Register pre-incr operand
-;;;	.word	0x0172
-;;;	.word	0x6c98
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	r2l, @byte_dst
-	beq	.Lnext51
-	fail
-.Lnext51:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-.endif
-
-mov_b_reg8_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @-erd
-	mov.l	#byte_dst+1, er1
-	mov.b	r0l, @-er1	; Register pre-decr operand
-;;;	.word	0x6c98
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r2l, r0l
-	beq	.Lnext48
-	fail
-.Lnext48:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_b_reg8_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @(dd:2, erd)
-	mov.l	#byte_dst-3, er1
-	mov.b	r0l, @(3:2, er1)	; Register plus 2-bit disp. operand
-;;;	.word	0x0173
-;;;	.word	0x6898
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	byte_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	r2l, @byte_dst
-	beq	.Lnext52
-	fail
-.Lnext52:
-	mov.b	#0, @byte_dst	; zero it again for the next use.
-.endif
-
-mov_b_reg8_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @(dd:16, erd)
-	mov.l	#byte_dst-4, er1
-	mov.b	r0l, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x6e98
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	byte_dst-4, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r2l, r0l
-	beq	.Lnext45
-	fail
-.Lnext45:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-mov_b_reg8_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @(dd:32, erd)
-	mov.l	#byte_dst-8, er1
-	mov.b	r0l, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x7810
-;;;	.word	0x6aa8
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	byte_dst-8, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r2l, r0l
-	beq	.Lnext46
-	fail
-.Lnext46:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-mov_b_reg8_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @aa:16
-	mov.b	r0l, @byte_dst:16	; 16-bit address-direct operand
-;;;	.word	0x6a88
-;;;	.word	@byte_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r0l, r1l
-	beq	.Lnext41
-	fail
-.Lnext41:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-mov_b_reg8_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b ers, @aa:32
-	mov.b	r0l, @byte_dst:32	; 32-bit address-direct operand
-;;;	.word	0x6aa8
-;;;	.long	@byte_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.b	@byte_dst, r0l
-	cmp.b	r0l, r1l
-	beq	.Lnext42
-	fail
-.Lnext42:
-	mov.b	#0, r0l
-	mov.b	r0l, @byte_dst	; zero it again for the next use.
-
-	;;
-	;; Move byte to register destination.
-	;; 
-
-mov_b_indirect_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers, rd
-	mov.l	#byte_src, er1
-	mov.b	@er1, r0l	; Register indirect operand
-;;;	.word	0x6818
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_h_gr32	byte_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_postinc_to_reg8:		; post-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers+, rd
-
-	mov.l	#byte_src, er1
-	mov.b	@er1+, r0l	; Register post-incr operand
-;;;	.word	0x6c18
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_h_gr32	byte_src+1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-mov_b_postdec_to_reg8:		; post-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers-, rd
-
-	mov.l	#byte_src, er1
-	mov.b	@er1-, r0l	; Register post-decr operand
-;;;	.word	0x0172
-;;;	.word	0x6c18
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_h_gr32	byte_src-1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_preinc_to_reg8:		; pre-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @+ers, rd
-
-	mov.l	#byte_src-1, er1
-	mov.b	@+er1, r0l	; Register pre-incr operand
-;;;	.word	0x0171
-;;;	.word	0x6c18
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_h_gr32	byte_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_predec_to_reg8:		; pre-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @-ers, rd
-
-	mov.l	#byte_src+1, er1
-	mov.b	@-er1, r0l	; Register pre-decr operand
-;;;	.word	0x0173
-;;;	.word	0x6c18
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_h_gr32	byte_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	
-mov_b_disp2_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:2, ers), rd
-	mov.l	#byte_src-1, er1
-	mov.b	@(1:2, er1), r0l	; Register plus 2-bit disp. operand
-;;; 	.word	0x0171
-;;; 	.word	0x6818
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	byte_src-1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-mov_b_disp16_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:16, ers), rd
-	mov.l	#byte_src+0x1234, er1
-	mov.b	@(-0x1234:16, er1), r0l	; Register plus 16-bit disp. operand
-;;;	.word	0x6e18
-;;;	.word	-0x1234
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	byte_src+0x1234, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_disp32_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:32, ers), rd
-	mov.l	#byte_src+65536, er1
-	mov.b	@(-65536:32, er1), r0l	; Register plus 32-bit disp. operand
-;;;	.word	0x7810
-;;;	.word	0x6a28
-;;;	.long	-65536
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	byte_src+65536, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_abs16_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @aa:16, rd
-	mov.b	@byte_src:16, r0l	; 16-bit address-direct operand
-;;;	.word	0x6a08
-;;;	.word	@byte_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_b_abs32_to_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @aa:32, rd
-	mov.b	@byte_src:32, r0l	; 32-bit address-direct operand
-;;;	.word	0x6a28
-;;;	.long	@byte_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a5a577 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-	;;
-	;; Move byte from memory to memory
-	;; 
-
-mov_b_indirect_to_indirect:	; reg indirect, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers, @erd
-
-	mov.l	#byte_src, er1
-	mov.l	#byte_dst, er0
-	mov.b	@er1, @er0
-;;;	.word	0x0178
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst er0
-	test_h_gr32  byte_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext55
-	fail
-.Lnext55:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext56
-	fail
-.Lnext56:			; OK, pass on.
-
-mov_b_postinc_to_postinc:	; reg post-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers+, @erd+
-
-	mov.l	#byte_src, er1
-	mov.l	#byte_dst, er0
-	mov.b	@er1+, @er0+
-;;;	.word	0x0178
-;;;	.word	0x8180
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst+1 er0
-	test_h_gr32  byte_src+1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext65
-	fail
-.Lnext65:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext66
-	fail
-.Lnext66:			; OK, pass on.
-
-mov_b_postdec_to_postdec:	; reg post-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @ers-, @erd-
-
-	mov.l	#byte_src, er1
-	mov.l	#byte_dst, er0
-	mov.b	@er1-, @er0-
-;;;	.word	0x0178
-;;;	.word	0xa1a0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst-1 er0
-	test_h_gr32  byte_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext75
-	fail
-.Lnext75:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext76
-	fail
-.Lnext76:			; OK, pass on.
-
-mov_b_preinc_to_preinc:		; reg pre-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @+ers, @+erd
-
-	mov.l	#byte_src-1, er1
-	mov.l	#byte_dst-1, er0
-	mov.b	@+er1, @+er0
-;;;	.word	0x0178
-;;;	.word	0x9190
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst er0
-	test_h_gr32  byte_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext85
-	fail
-.Lnext85:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext86
-	fail
-.Lnext86:				; OK, pass on.
-
-mov_b_predec_to_predec:		; reg pre-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @-ers, @-erd
-
-	mov.l	#byte_src+1, er1
-	mov.l	#byte_dst+1, er0
-	mov.b	@-er1, @-er0
-;;;	.word	0x0178
-;;;	.word	0xb1b0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst er0
-	test_h_gr32  byte_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext95
-	fail
-.Lnext95:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext96
-	fail
-.Lnext96:			; OK, pass on.
-
-mov_b_disp2_to_disp2:		; reg 2-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:2, ers), @(dd:2, erd)
-
-	mov.l	#byte_src-1, er1
-	mov.l	#byte_dst-2, er0
-	mov.b	@(1:2, er1), @(2:2, er0)
-;;; 	.word	0x0178
-;;; 	.word	0x1120
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst-2 er0
-	test_h_gr32  byte_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext105
-	fail
-.Lnext105:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext106
-	fail
-.Lnext106:			; OK, pass on.
-
-mov_b_disp16_to_disp16:		; reg 16-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:16, ers), @(dd:16, erd)
-
-	mov.l	#byte_src-1, er1
-	mov.l	#byte_dst-2, er0
-	mov.b	@(1:16, er1), @(2:16, er0)
-;;; 	.word	0x0178
-;;; 	.word	0xc1c0
-;;; 	.word	0x0001
-;;; 	.word	0x0002
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst-2 er0
-	test_h_gr32  byte_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext115
-	fail
-.Lnext115:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext116
-	fail
-.Lnext116:			; OK, pass on.
-
-mov_b_disp32_to_disp32:		; reg 32-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @(dd:32, ers), @(dd:32, erd)
-
-	mov.l	#byte_src-1, er1
-	mov.l	#byte_dst-2, er0
-	mov.b	@(1:32, er1), @(2:32, er0)
-;;; 	.word	0x0178
-;;; 	.word	0xc9c8
-;;;	.long	1
-;;;	.long	2
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  byte_dst-2 er0
-	test_h_gr32  byte_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext125
-	fail
-.Lnext125:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext126
-	fail
-.Lnext126:				; OK, pass on.
-
-mov_b_abs16_to_abs16:		; 16-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @aa:16, @aa:16
-
-	mov.b	@byte_src:16, @byte_dst:16
-;;; 	.word	0x0178
-;;; 	.word	0x4040
-;;;	.word	@byte_src
-;;;	.word	@byte_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext135
-	fail
-.Lnext135:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext136
-	fail
-.Lnext136:				; OK, pass on.
-
-mov_b_abs32_to_abs32:		; 32-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.b @aa:32, @aa:32
-
-	mov.b	@byte_src:32, @byte_dst:32
-;;; 	.word	0x0178
-;;; 	.word	0x4848
-;;;	.long	@byte_src
-;;;	.long	@byte_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.b	@byte_src, @byte_dst
-	beq	.Lnext145
-	fail
-.Lnext145:
-	;; Now clear the destination location, and verify that.
-	mov.b	#0, @byte_dst
-	cmp.b	@byte_src, @byte_dst
-	bne	.Lnext146
-	fail
-.Lnext146:				; OK, pass on.
-
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/mov.l.s b/sim/testsuite/sim/h8300/mov.l.s
deleted file mode 100644
index 5a222c8..0000000
--- a/sim/testsuite/sim/h8300/mov.l.s
+++ /dev/null

@@ -1,2160 +0,0 @@
-# Hitachi H8 testcase 'mov.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-	.align	4
-long_src:
-	.long	0x77777777
-long_dst:
-	.long	0
-
-	.text
-
-	;;
-	;; Move long from immediate source
-	;; 
-
-.if (sim_cpu == h8sx)
-mov_l_imm3_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:3, erd
-	mov.l	#0x3:3, er0	; Immediate 3-bit operand
-;;;	.word	0x0fb8
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x3 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_imm16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, erd
-	mov.l	#0x1234, er0	; Immediate 16-bit operand
-;;;	.word	0x7a08
-;;;	.word	0x1234
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x1234 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-mov_l_imm32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, erd
-	mov.l	#0x12345678, er0	; Immediate 32-bit operand
-;;;	.word	0x7a00
-;;;	.long	0x12345678
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x12345678 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-mov_l_imm8_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @erd
-	mov.l	#long_dst, er1
-	mov.l	#0xa5:8, @er1	; Register indirect operand
-;;;	.word	0x010d
-;;;	.word	0x01a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext1
-	fail
-.Lnext1:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_postinc:		; post-increment from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @erd+
-	mov.l	#long_dst, er1
-	mov.l	#0xa5:8, @er1+	; Imm8, register post-incr operands.
-;;;	.word	0x010d
-;;;	.word	0x81a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext2
-	fail
-.Lnext2:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_postdec:		; post-decrement from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @erd-
-	mov.l	#long_dst, er1
-	mov.l	#0xa5:8, @er1-	; Imm8, register post-decr operands.
-;;;	.word	0x010d
-;;;	.word	0xa1a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext3
-	fail
-.Lnext3:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @+erd
-	mov.l	#long_dst-4, er1
-	mov.l	#0xa5:8, @+er1	; Imm8, register pre-incr operands
-;;;	.word	0x010d
-;;;	.word	0x91a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext4
-	fail
-.Lnext4:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @-erd
-	mov.l	#long_dst+4, er1
-	mov.l	#0xa5:8, @-er1	; Imm8, register pre-decr operands
-;;;	.word	0x010d
-;;;	.word	0xb1a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext5
-	fail
-.Lnext5:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	mov.l	#0xa5:8, @(3:2, er1)	; Imm8, reg plus 2-bit disp. operand
-;;;	.word	0x010d
-;;;	.word	0x31a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext6
-	fail
-.Lnext6:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	mov.l	#0xa5:8, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x010d
-;;;	.word	0x6f90
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext7
-	fail
-.Lnext7:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	mov.l	#0xa5:8, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x010d
-;;;	.word	0xc9a5
-;;;	.long	8
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext8
-	fail
-.Lnext8:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @aa:16
-	mov.l	#0xa5:8, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x010d
-;;;	.word	0x40a5
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext9
-	fail
-.Lnext9:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm8_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:8, @aa:32
-	mov.l	#0xa5:8, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x010d
-;;;	.word	0x48a5
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xa5, @long_dst
-	beq	.Lnext10
-	fail
-.Lnext10:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @erd
-	mov.l	#long_dst, er1
-	mov.l	#0xdead:16, @er1	; Register indirect operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext11
-	fail
-.Lnext11:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_postinc:		; post-increment from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @erd+
-	mov.l	#long_dst, er1
-	mov.l	#0xdead:16, @er1+	; Imm16, register post-incr operands.
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x8100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext12
-	fail
-.Lnext12:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_postdec:		; post-decrement from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @erd-
-	mov.l	#long_dst, er1
-	mov.l	#0xdead:16, @er1-	; Imm16, register post-decr operands.
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0xa100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext13
-	fail
-.Lnext13:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @+erd
-	mov.l	#long_dst-4, er1
-	mov.l	#0xdead:16, @+er1	; Imm16, register pre-incr operands
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x9100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext14
-	fail
-.Lnext14:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @-erd
-	mov.l	#long_dst+4, er1
-	mov.l	#0xdead:16, @-er1	; Imm16, register pre-decr operands
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0xb100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext15
-	fail
-.Lnext15:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	mov.l	#0xdead:16, @(3:2, er1)	; Imm16, reg plus 2-bit disp. operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x3100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext16
-	fail
-.Lnext16:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	mov.l	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0xc100
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext17
-	fail
-.Lnext17:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	mov.l	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0xc900
-;;;	.long	8
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext18
-	fail
-.Lnext18:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @aa:16
-	mov.l	#0xdead:16, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x4000
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext19
-	fail
-.Lnext19:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm16_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:16, @aa:32
-	mov.l	#0xdead:16, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x7a7c
-;;;	.word	0xdead
-;;;	.word	0x4800
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xdead, @long_dst
-	beq	.Lnext20
-	fail
-.Lnext20:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @erd
-	mov.l	#long_dst, er1
-	mov.l	#0xcafedead:32, @er1	; Register indirect operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext21
-	fail
-.Lnext21:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_postinc:		; post-increment from imm32 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @erd+
-	mov.l	#long_dst, er1
-	mov.l	#0xcafedead:32, @er1+	; Imm32, register post-incr operands.
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x8100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext22
-	fail
-.Lnext22:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_postdec:		; post-decrement from imm32 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @erd-
-	mov.l	#long_dst, er1
-	mov.l	#0xcafedead:32, @er1-	; Imm32, register post-decr operands.
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0xa100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext23
-	fail
-.Lnext23:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @+erd
-	mov.l	#long_dst-4, er1
-	mov.l	#0xcafedead:32, @+er1	; Imm32, register pre-incr operands
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x9100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext24
-	fail
-.Lnext24:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @-erd
-	mov.l	#long_dst+4, er1
-	mov.l	#0xcafedead:32, @-er1	; Imm32, register pre-decr operands
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0xb100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext25
-	fail
-.Lnext25:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	mov.l	#0xcafedead:32, @(3:2, er1)	; Imm32, reg plus 2-bit disp. operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x3100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext26
-	fail
-.Lnext26:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	mov.l	#0xcafedead:32, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0xc100
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext27
-	fail
-.Lnext27:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	mov.l	#0xcafedead:32, @(8:32, er1)   ; Register plus 32-bit disp. operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0xc900
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext28
-	fail
-.Lnext28:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l #xx:32, @aa:16
-	mov.l	#0xcafedead:32, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x4000
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext29
-	fail
-.Lnext29:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_imm32_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  mov.l #xx:32, @aa:32
-	mov.l	#0xcafedead:32, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x7a74
-;;;	.long	0xcafedead
-;;;	.word	0x4800
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	#0xcafedead, @long_dst
-	beq	.Lnext30
-	fail
-.Lnext30:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-.endif
-
-	;;
-	;; Move long from register source
-	;; 
-
-mov_l_reg32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, erd
-	mov.l	#0x12345678, er1
-	mov.l	er1, er0	; Register 32-bit operand
-;;;	.word	0x0f90
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-	test_h_gr32 0x12345678 er0
-	test_h_gr32 0x12345678 er1	; mov src unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_reg32_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @erd
-	mov.l	#long_dst, er1
-	mov.l	er0, @er1	; Register indirect operand
-;;;	.word	0x0100
-;;;	.word	0x6990
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er2, er0
-	beq	.Lnext44
-	fail
-.Lnext44:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_l_reg32_to_postinc:		; post-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @erd+
-	mov.l	#long_dst, er1
-	mov.l	er0, @er1+	; Register post-incr operand
-;;;	.word	0x0103
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst+4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	er2, @long_dst
-	beq	.Lnext49
-	fail
-.Lnext49:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_reg32_to_postdec:		; post-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @erd-
-	mov.l	#long_dst, er1
-	mov.l	er0, @er1-	; Register post-decr operand
-;;;	.word	0x0101
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	er2, @long_dst
-	beq	.Lnext50
-	fail
-.Lnext50:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-
-mov_l_reg32_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @+erd
-	mov.l	#long_dst-4, er1
-	mov.l	er0, @+er1	; Register pre-incr operand
-;;;	.word	0x0102
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	er2, @long_dst
-	beq	.Lnext51
-	fail
-.Lnext51:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-.endif				; h8sx
-
-mov_l_reg32_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @-erd
-	mov.l	#long_dst+4, er1
-	mov.l	er0, @-er1	; Register pre-decr operand
-;;;	.word	0x0100
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er2, er0
-	beq	.Lnext48
-	fail
-.Lnext48:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_l_reg32_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @(dd:2, erd)
-	mov.l	#long_dst-3, er1
-	mov.l	er0, @(3:2, er1)	; Register plus 2-bit disp. operand
-;;;	.word	0x0103
-;;;	.word	0x6990
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	long_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	er2, @long_dst
-	beq	.Lnext52
-	fail
-.Lnext52:
-	mov.l	#0, @long_dst	; zero it again for the next use.
-.endif				; h8sx
-
-mov_l_reg32_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @(dd:16, erd)
-	mov.l	#long_dst-4, er1
-	mov.l	er0, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x0100
-;;;	.word	0x6f90
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	long_dst-4, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er2, er0
-	beq	.Lnext45
-	fail
-.Lnext45:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-mov_l_reg32_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @(dd:32, erd)
-	mov.l	#long_dst-8, er1
-	mov.l	er0, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x7890
-;;;	.word	0x6ba0
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	long_dst-8, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er2, er0
-	beq	.Lnext46
-	fail
-.Lnext46:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-mov_l_reg32_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @aa:16
-	mov.l	er0, @long_dst:16	; 16-bit address-direct operand
-;;;	.word	0x0100
-;;;	.word	0x6b80
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er0, er1
-	beq	.Lnext41
-	fail
-.Lnext41:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-mov_l_reg32_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l ers, @aa:32
-	mov.l	er0, @long_dst:32	; 32-bit address-direct operand
-;;;	.word	0x0100
-;;;	.word	0x6ba0
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.l	#0, er0
-	mov.l	@long_dst, er0
-	cmp.l	er0, er1
-	beq	.Lnext42
-	fail
-.Lnext42:
-	mov.l	#0, er0
-	mov.l	er0, @long_dst	; zero it again for the next use.
-
-	;;
-	;; Move long to register destination.
-	;; 
-
-mov_l_indirect_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers, erd
-	mov.l	#long_src, er1
-	mov.l	@er1, er0	; Register indirect operand
-;;;	.word	0x0100
-;;;	.word	0x6910
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_postinc_to_reg32:		; post-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers+, erd
-
-	mov.l	#long_src, er1
-	mov.l	@er1+, er0	; Register post-incr operand
-;;;	.word	0x0100
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_h_gr32	long_src+4, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-mov_l_postdec_to_reg32:		; post-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers-, erd
-
-	mov.l	#long_src, er1
-	mov.l	@er1-, er0	; Register post-decr operand
-;;;	.word	0x0102
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_h_gr32	long_src-4, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_preinc_to_reg32:		; pre-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @+ers, erd
-
-	mov.l	#long_src-4, er1
-	mov.l	@+er1, er0	; Register pre-incr operand
-;;;	.word	0x0101
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_predec_to_reg32:		; pre-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @-ers, erd
-
-	mov.l	#long_src+4, er1
-	mov.l	@-er1, er0	; Register pre-decr operand
-;;;	.word	0x0103
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_h_gr32	long_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	
-mov_l_disp2_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:2, ers), erd
-	mov.l	#long_src-1, er1
-	mov.l	@(1:2, er1), er0	; Register plus 2-bit disp. operand
-;;; 	.word	0x0101
-;;; 	.word	0x6910
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src-1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif				; h8sx
-
-mov_l_disp16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:16, ers), erd
-	mov.l	#long_src+0x1234, er1
-	mov.l	@(-0x1234:16, er1), er0	; Register plus 16-bit disp. operand
-;;;	.word	0x0100
-;;;	.word	0x6f10
-;;;	.word	-0x1234
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src+0x1234, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_disp32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:32, ers), erd
-	mov.l	#long_src+65536, er1
-	mov.l	@(-65536:32, er1), er0	; Register plus 32-bit disp. operand
-;;;	.word	0x7890
-;;;	.word	0x6b20
-;;;	.long	-65536
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	long_src+65536, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_abs16_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @aa:16, erd
-	mov.l	@long_src:16, er0	; 16-bit address-direct operand
-;;;	.word	0x0100
-;;;	.word	0x6b00
-;;;	.word	@long_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_l_abs32_to_reg32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @aa:32, erd
-	mov.l	@long_src:32, er0	; 32-bit address-direct operand
-;;;	.word	0x0100
-;;;	.word	0x6b20
-;;;	.long	@long_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0x77777777 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-
-.if (sim_cpu == h8sx)
-
-	;;
-	;; Move long from memory to memory
-	;; 
-
-mov_l_indirect_to_indirect:	; reg indirect, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers, @erd
-
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	mov.l	@er1, @er0
-;;;	.word	0x0108
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext55
-	fail
-.Lnext55:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext56
-	fail
-.Lnext56:			; OK, pass on.
-
-mov_l_postinc_to_postinc:	; reg post-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers+, @erd+
-
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	mov.l	@er1+, @er0+
-;;;	.word	0x0108
-;;;	.word	0x8180
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst+4 er0
-	test_h_gr32  long_src+4 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext65
-	fail
-.Lnext65:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext66
-	fail
-.Lnext66:			; OK, pass on.
-
-mov_l_postdec_to_postdec:	; reg post-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @ers-, @erd-
-
-	mov.l	#long_src, er1
-	mov.l	#long_dst, er0
-	mov.l	@er1-, @er0-
-;;;	.word	0x0108
-;;;	.word	0xa1a0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-4 er0
-	test_h_gr32  long_src-4 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext75
-	fail
-.Lnext75:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext76
-	fail
-.Lnext76:			; OK, pass on.
-
-mov_l_preinc_to_preinc:		; reg pre-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @+ers, @+erd
-
-	mov.l	#long_src-4, er1
-	mov.l	#long_dst-4, er0
-	mov.l	@+er1, @+er0
-;;;	.word	0x0108
-;;;	.word	0x9190
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext85
-	fail
-.Lnext85:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext86
-	fail
-.Lnext86:				; OK, pass on.
-
-mov_l_predec_to_predec:		; reg pre-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @-ers, @-erd
-
-	mov.l	#long_src+4, er1
-	mov.l	#long_dst+4, er0
-	mov.l	@-er1, @-er0
-;;;	.word	0x0108
-;;;	.word	0xb1b0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst er0
-	test_h_gr32  long_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext95
-	fail
-.Lnext95:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext96
-	fail
-.Lnext96:			; OK, pass on.
-
-mov_l_disp2_to_disp2:		; reg 2-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:2, ers), @(dd:2, erd)
-
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	mov.l	@(1:2, er1), @(2:2, er0)
-;;; 	.word	0x0108
-;;; 	.word	0x1120
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext105
-	fail
-.Lnext105:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext106
-	fail
-.Lnext106:			; OK, pass on.
-
-mov_l_disp16_to_disp16:		; reg 16-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:16, ers), @(dd:16, erd)
-
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	mov.l	@(1:16, er1), @(2:16, er0)
-;;; 	.word	0x0108
-;;; 	.word	0xc1c0
-;;; 	.word	0x0001
-;;; 	.word	0x0002
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext115
-	fail
-.Lnext115:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext116
-	fail
-.Lnext116:			; OK, pass on.
-
-mov_l_disp32_to_disp32:		; reg 32-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @(dd:32, ers), @(dd:32, erd)
-
-	mov.l	#long_src-1, er1
-	mov.l	#long_dst-2, er0
-	mov.l	@(1:32, er1), @(2:32, er0)
-;;; 	.word	0x0108
-;;; 	.word	0xc9c8
-;;;	.long	1
-;;;	.long	2
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  long_dst-2 er0
-	test_h_gr32  long_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext125
-	fail
-.Lnext125:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext126
-	fail
-.Lnext126:				; OK, pass on.
-
-mov_l_abs16_to_abs16:		; 16-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @aa:16, @aa:16
-
-	mov.l	@long_src:16, @long_dst:16
-;;; 	.word	0x0108
-;;; 	.word	0x4040
-;;;	.word	@long_src
-;;;	.word	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext135
-	fail
-.Lnext135:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext136
-	fail
-.Lnext136:				; OK, pass on.
-
-mov_l_abs32_to_abs32:		; 32-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.l @aa:32, @aa:32
-
-	mov.l	@long_src:32, @long_dst:32
-;;; 	.word	0x0108
-;;; 	.word	0x4848
-;;;	.long	@long_src
-;;;	.long	@long_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.l	@long_src, @long_dst
-	beq	.Lnext145
-	fail
-.Lnext145:
-	;; Now clear the destination location, and verify that.
-	mov.l	#0, @long_dst
-	cmp.l	@long_src, @long_dst
-	bne	.Lnext146
-	fail
-.Lnext146:				; OK, pass on.
-
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/mov.w.s b/sim/testsuite/sim/h8300/mov.w.s
deleted file mode 100644
index 6f460c8..0000000
--- a/sim/testsuite/sim/h8300/mov.w.s
+++ /dev/null

@@ -1,1857 +0,0 @@
-# Hitachi H8 testcase 'mov.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-	.align	2
-word_src:
-	.word	0x7777
-word_dst:
-	.word	0
-
-	.text
-
-	;;
-	;; Move word from immediate source
-	;; 
-
-.if (sim_cpu == h8sx)
-mov_w_imm3_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:3, rd
-	mov.w	#0x3:3, r0	; Immediate 3-bit operand
-;;;	.word	0x0f30
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a50003 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-mov_w_imm16_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, rd
-	mov.w	#0x1234, r0	; Immediate 16-bit operand
-;;;	.word	0x7900
-;;;	.word	0x1234
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a51234 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-mov_w_imm4_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:4, @aa:16
-	mov.w	#0xf:4, @word_dst:16	; 4-bit imm to 16-bit address-direct 
-;;;	.word	0x6bdf
-;;;	.word	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xf, @word_dst
-	beq	.Lnext21
-	fail
-.Lnext21:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm4_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:4, @aa:32
-	mov.w	#0xf:4, @word_dst:32	; 4-bit imm to 32-bit address-direct 
-;;;	.word	0x6bff
-;;;	.long	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xf, @word_dst
-	beq	.Lnext22
-	fail
-.Lnext22:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @erd
-	mov.l	#word_dst, er1
-	mov.w	#0xa5:8, @er1	; Register indirect operand
-;;;	.word	0x015d
-;;;	.word	0x01a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext1
-	fail
-.Lnext1:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_postinc:		; post-increment from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @erd+
-	mov.l	#word_dst, er1
-	mov.w	#0xa5:8, @er1+	; Imm8, register post-incr operands.
-;;;	.word	0x015d
-;;;	.word	0x81a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst+2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext2
-	fail
-.Lnext2:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_postdec:		; post-decrement from imm8 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @erd-
-	mov.l	#word_dst, er1
-	mov.w	#0xa5:8, @er1-	; Imm8, register post-decr operands.
-;;;	.word	0x015d
-;;;	.word	0xa1a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext3
-	fail
-.Lnext3:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @+erd
-	mov.l	#word_dst-2, er1
-	mov.w	#0xa5:8, @+er1	; Imm8, register pre-incr operands
-;;;	.word	0x015d
-;;;	.word	0x91a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext4
-	fail
-.Lnext4:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @-erd
-	mov.l	#word_dst+2, er1
-	mov.w	#0xa5:8, @-er1	; Imm8, register pre-decr operands
-;;;	.word	0x015d
-;;;	.word	0xb1a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext5
-	fail
-.Lnext5:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @(dd:2, erd)
-	mov.l	#word_dst-3, er1
-	mov.w	#0xa5:8, @(3:2, er1)	; Imm8, reg plus 2-bit disp. operand
-;;;	.word	0x015d
-;;;	.word	0x31a5
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext6
-	fail
-.Lnext6:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @(dd:16, erd)
-	mov.l	#word_dst-4, er1
-	mov.w	#0xa5:8, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x015d
-;;;	.word	0x6f90
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext7
-	fail
-.Lnext7:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @(dd:32, erd)
-	mov.l	#word_dst-8, er1
-	mov.w	#0xa5:8, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x015d
-;;;	.word	0xc9a5
-;;;	.long	8
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext8
-	fail
-.Lnext8:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @aa:16
-	mov.w	#0xa5:8, @word_dst:16	; 16-bit address-direct operand
-;;;	.word	0x015d
-;;;	.word	0x40a5
-;;;	.word	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext9
-	fail
-.Lnext9:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm8_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:8, @aa:32
-	mov.w	#0xa5:8, @word_dst:32	; 32-bit address-direct operand
-;;;	.word	0x015d
-;;;	.word	0x48a5
-;;;	.long	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xa5, @word_dst
-	beq	.Lnext10
-	fail
-.Lnext10:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @erd
-	mov.l	#word_dst, er1
-	mov.w	#0xdead:16, @er1	; Register indirect operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext11
-	fail
-.Lnext11:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_postinc:		; post-increment from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @erd+
-	mov.l	#word_dst, er1
-	mov.w	#0xdead:16, @er1+	; Imm16, register post-incr operands.
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x8100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst+2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext12
-	fail
-.Lnext12:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_postdec:		; post-decrement from imm16 to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @erd-
-	mov.l	#word_dst, er1
-	mov.w	#0xdead:16, @er1-	; Imm16, register post-decr operands.
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0xa100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext13
-	fail
-.Lnext13:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @+erd
-	mov.l	#word_dst-2, er1
-	mov.w	#0xdead:16, @+er1	; Imm16, register pre-incr operands
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x9100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext14
-	fail
-.Lnext14:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @-erd
-	mov.l	#word_dst+2, er1
-	mov.w	#0xdead:16, @-er1	; Imm16, register pre-decr operands
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0xb100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext15
-	fail
-.Lnext15:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @(dd:2, erd)
-	mov.l	#word_dst-3, er1
-	mov.w	#0xdead:16, @(3:2, er1)	; Imm16, reg plus 2-bit disp. operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x3100
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext16
-	fail
-.Lnext16:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @(dd:16, erd)
-	mov.l	#word_dst-4, er1
-	mov.w	#0xdead:16, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0xc100
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-4, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext17
-	fail
-.Lnext17:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @(dd:32, erd)
-	mov.l	#word_dst-8, er1
-	mov.w	#0xdead:16, @(8:32, er1)   ; Register plus 32-bit disp. operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0xc900
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-8, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext18
-	fail
-.Lnext18:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @aa:16
-	mov.w	#0xdead:16, @word_dst:16	; 16-bit address-direct operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x4000
-;;;	.word	@word_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext19
-	fail
-.Lnext19:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_imm16_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w #xx:16, @aa:32
-	mov.w	#0xdead:16, @word_dst:32	; 32-bit address-direct operand
-;;;	.word	0x7974
-;;;	.word	0xdead
-;;;	.word	0x4800
-;;;	.long	@word_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	#0xdead, @word_dst
-	beq	.Lnext20
-	fail
-.Lnext20:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-.endif
-
-	;;
-	;; Move word from register source
-	;; 
-
-mov_w_reg16_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, erd
-	mov.w	#0x1234, r1
-	mov.w	r1, r0		; Register 16-bit operand
-;;;	.word	0x0d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-	test_h_gr16 0x1234 r0
-	test_h_gr16 0x1234 r1	; mov src unchanged
-.if (sim_cpu)
-	test_h_gr32 0xa5a51234 er0
-	test_h_gr32 0xa5a51234 er1	; mov src unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-
-mov_w_reg16_to_indirect:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @erd
-	mov.l	#word_dst, er1
-	mov.w	r0, @er1	; Register indirect operand
-;;;	.word	0x6990
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r2, r0
-	beq	.Lnext44
-	fail
-.Lnext44:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_w_reg16_to_postinc:		; post-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @erd+
-	mov.l	#word_dst, er1
-	mov.w	r0, @er1+	; Register post-incr operand
-;;;	.word	0x0153
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst+2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	r2, @word_dst
-	beq	.Lnext49
-	fail
-.Lnext49:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_reg16_to_postdec:		; post-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @erd-
-	mov.l	#word_dst, er1
-	mov.w	r0, @er1-	; Register post-decr operand
-;;;	.word	0x0151
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-2, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	r2, @word_dst
-	beq	.Lnext50
-	fail
-.Lnext50:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-
-mov_w_reg16_to_preinc:		; pre-increment from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @+erd
-	mov.l	#word_dst-2, er1
-	mov.w	r0, @+er1	; Register pre-incr operand
-;;;	.word	0x0152
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	r2, @word_dst
-	beq	.Lnext51
-	fail
-.Lnext51:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-.endif
-
-mov_w_reg16_to_predec:		; pre-decrement from register to mem
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @-erd
-	mov.l	#word_dst+2, er1
-	mov.w	r0, @-er1	; Register pre-decr operand
-;;;	.word	0x6d90
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r2, r0
-	beq	.Lnext48
-	fail
-.Lnext48:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-.if (sim_cpu == h8sx)
-mov_w_reg16_to_disp2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @(dd:2, erd)
-	mov.l	#word_dst-3, er1
-	mov.w	r0, @(3:2, er1)	; Register plus 2-bit disp. operand
-;;;	.word	0x0153
-;;;	.word	0x6990
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_h_gr32	word_dst-3, er1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	r2, @word_dst
-	beq	.Lnext52
-	fail
-.Lnext52:
-	mov.w	#0, @word_dst	; zero it again for the next use.
-.endif
-
-mov_w_reg16_to_disp16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @(dd:16, erd)
-	mov.l	#word_dst-4, er1
-	mov.w	r0, @(4:16, er1)	; Register plus 16-bit disp. operand
-;;;	.word	0x6f90
-;;;	.word	0x0004
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	word_dst-4, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r2, r0
-	beq	.Lnext45
-	fail
-.Lnext45:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-mov_w_reg16_to_disp32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @(dd:32, erd)
-	mov.l	#word_dst-8, er1
-	mov.w	r0, @(8:32, er1)	; Register plus 32-bit disp. operand
-;;;	.word	0x7810
-;;;	.word	0x6ba0
-;;;	.long	8
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32	word_dst-8, er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r2, r0
-	beq	.Lnext46
-	fail
-.Lnext46:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-mov_w_reg16_to_abs16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @aa:16
-	mov.w	r0, @word_dst:16	; 16-bit address-direct operand
-;;;	.word	0x6b80
-;;;	.word	@word_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r0, r1
-	beq	.Lnext41
-	fail
-.Lnext41:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-mov_w_reg16_to_abs32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w ers, @aa:32
-	mov.w	r0, @word_dst:32	; 32-bit address-direct operand
-;;;	.word	0x6ba0
-;;;	.long	@word_dst
-
-	;; test ccr		; H=0 N=1 Z=0 V=0 C=0
-	test_neg_set
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure _ALL_ general regs not disturbed
-	test_gr_a5a5 1		; (first, because on h8/300 we must use one
-	test_gr_a5a5 2		; to examine the destination memory).
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	mov.w	#0, r0
-	mov.w	@word_dst, r0
-	cmp.w	r0, r1
-	beq	.Lnext42
-	fail
-.Lnext42:
-	mov.w	#0, r0
-	mov.w	r0, @word_dst	; zero it again for the next use.
-
-	;;
-	;; Move word to register destination.
-	;; 
-
-mov_w_indirect_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers, rd
-	mov.l	#word_src, er1
-	mov.w	@er1, r0	; Register indirect operand
-;;;	.word	0x6910
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_h_gr32	word_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_postinc_to_reg16:		; post-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers+, rd
-
-	mov.l	#word_src, er1
-	mov.w	@er1+, r0	; Register post-incr operand
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_h_gr32	word_src+2, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-mov_w_postdec_to_reg16:		; post-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers-, rd
-
-	mov.l	#word_src, er1
-	mov.w	@er1-, r0	; Register post-decr operand
-;;;	.word	0x0152
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_h_gr32	word_src-2, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_preinc_to_reg16:		; pre-increment from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @+ers, rd
-
-	mov.l	#word_src-2, er1
-	mov.w	@+er1, r0	; Register pre-incr operand
-;;;	.word	0x0151
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_h_gr32	word_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_predec_to_reg16:		; pre-decrement from mem to register
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @-ers, rd
-
-	mov.l	#word_src+2, er1
-	mov.w	@-er1, r0	; Register pre-decr operand
-;;;	.word	0x0153
-;;;	.word	0x6d10
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_h_gr32	word_src, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	
-mov_w_disp2_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:2, ers), rd
-	mov.l	#word_src-1, er1
-	mov.w	@(1:2, er1), r0	; Register plus 2-bit disp. operand
-;;; 	.word	0x0151
-;;; 	.word	0x6910
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	word_src-1, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-mov_w_disp16_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:16, ers), rd
-	mov.l	#word_src+0x1234, er1
-	mov.w	@(-0x1234:16, er1), r0	; Register plus 16-bit disp. operand
-;;;	.word	0x6f10
-;;;	.word	-0x1234
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	word_src+0x1234, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_disp32_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:32, ers), rd
-	mov.l	#word_src+65536, er1
-	mov.w	@(-65536:32, er1), r0	; Register plus 32-bit disp. operand
-;;;	.word	0x7810
-;;;	.word	0x6b20
-;;;	.long	-65536
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0	; mov result:	a5a5 | 7777
-
-	test_h_gr32	word_src+65536, er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_abs16_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @aa:16, rd
-	mov.w	@word_src:16, r0	; 16-bit address-direct operand
-;;;	.word	0x6b00
-;;;	.word	@word_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-mov_w_abs32_to_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @aa:32, rd
-	mov.w	@word_src:32, r0	; 32-bit address-direct operand
-;;;	.word	0x6b20
-;;;	.long	@word_src
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_h_gr32 0xa5a57777 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-	;;
-	;; Move word from memory to memory
-	;; 
-
-mov_w_indirect_to_indirect:	; reg indirect, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers, @erd
-
-	mov.l	#word_src, er1
-	mov.l	#word_dst, er0
-	mov.w	@er1, @er0
-;;;	.word	0x0158
-;;;	.word	0x0100
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst er0
-	test_h_gr32  word_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext55
-	fail
-.Lnext55:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext56
-	fail
-.Lnext56:			; OK, pass on.
-
-mov_w_postinc_to_postinc:	; reg post-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers+, @erd+
-
-	mov.l	#word_src, er1
-	mov.l	#word_dst, er0
-	mov.w	@er1+, @er0+
-;;;	.word	0x0158
-;;;	.word	0x8180
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst+2 er0
-	test_h_gr32  word_src+2 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext65
-	fail
-.Lnext65:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext66
-	fail
-.Lnext66:			; OK, pass on.
-
-mov_w_postdec_to_postdec:	; reg post-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @ers-, @erd-
-
-	mov.l	#word_src, er1
-	mov.l	#word_dst, er0
-	mov.w	@er1-, @er0-
-;;;	.word	0x0158
-;;;	.word	0xa1a0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst-2 er0
-	test_h_gr32  word_src-2 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext75
-	fail
-.Lnext75:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext76
-	fail
-.Lnext76:			; OK, pass on.
-
-mov_w_preinc_to_preinc:		; reg pre-increment, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @+ers, @+erd
-
-	mov.l	#word_src-2, er1
-	mov.l	#word_dst-2, er0
-	mov.w	@+er1, @+er0
-;;;	.word	0x0158
-;;;	.word	0x9190
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst er0
-	test_h_gr32  word_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext85
-	fail
-.Lnext85:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext86
-	fail
-.Lnext86:				; OK, pass on.
-
-mov_w_predec_to_predec:		; reg pre-decrement, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @-ers, @-erd
-
-	mov.l	#word_src+2, er1
-	mov.l	#word_dst+2, er0
-	mov.w	@-er1, @-er0
-;;;	.word	0x0158
-;;;	.word	0xb1b0
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst er0
-	test_h_gr32  word_src er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext95
-	fail
-.Lnext95:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext96
-	fail
-.Lnext96:			; OK, pass on.
-
-mov_w_disp2_to_disp2:		; reg 2-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:2, ers), @(dd:2, erd)
-
-	mov.l	#word_src-1, er1
-	mov.l	#word_dst-2, er0
-	mov.w	@(1:2, er1), @(2:2, er0)
-;;; 	.word	0x0158
-;;; 	.word	0x1120
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst-2 er0
-	test_h_gr32  word_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext105
-	fail
-.Lnext105:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext106
-	fail
-.Lnext106:			; OK, pass on.
-
-mov_w_disp16_to_disp16:		; reg 16-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:16, ers), @(dd:16, erd)
-
-	mov.l	#word_src-1, er1
-	mov.l	#word_dst-2, er0
-	mov.w	@(1:16, er1), @(2:16, er0)
-;;; 	.word	0x0158
-;;; 	.word	0xc1c0
-;;; 	.word	0x0001
-;;; 	.word	0x0002
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst-2 er0
-	test_h_gr32  word_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext115
-	fail
-.Lnext115:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext116
-	fail
-.Lnext116:			; OK, pass on.
-
-mov_w_disp32_to_disp32:		; reg 32-bit disp, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @(dd:32, ers), @(dd:32, erd)
-
-	mov.l	#word_src-1, er1
-	mov.l	#word_dst-2, er0
-	mov.w	@(1:32, er1), @(2:32, er0)
-;;; 	.word	0x0158
-;;; 	.word	0xc9c8
-;;;	.long	1
-;;;	.long	2
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	;; Verify the affected registers.
-
-	test_h_gr32  word_dst-2 er0
-	test_h_gr32  word_src-1 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext125
-	fail
-.Lnext125:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext126
-	fail
-.Lnext126:				; OK, pass on.
-
-mov_w_abs16_to_abs16:		; 16-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @aa:16, @aa:16
-
-	mov.w	@word_src:16, @word_dst:16
-;;; 	.word	0x0158
-;;; 	.word	0x4040
-;;;	.word	@word_src
-;;;	.word	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext135
-	fail
-.Lnext135:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext136
-	fail
-.Lnext136:				; OK, pass on.
-
-mov_w_abs32_to_abs32:		; 32-bit absolute addr, memory to memory
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;; mov.w @aa:32, @aa:32
-
-	mov.w	@word_src:32, @word_dst:32
-;;; 	.word	0x0158
-;;; 	.word	0x4848
-;;;	.long	@word_src
-;;;	.long	@word_dst
-
-	;; test ccr		; H=0 N=0 Z=0 V=0 C=0
-	test_neg_clear
-	test_zero_clear
-	test_ovf_clear
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure *NO* general registers are changed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the move to memory.
-	cmp.w	@word_src, @word_dst
-	beq	.Lnext145
-	fail
-.Lnext145:
-	;; Now clear the destination location, and verify that.
-	mov.w	#0, @word_dst
-	cmp.w	@word_src, @word_dst
-	bne	.Lnext146
-	fail
-.Lnext146:				; OK, pass on.
-
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/movmd.s b/sim/testsuite/sim/h8300/movmd.s
deleted file mode 100644
index fefdc33..0000000
--- a/sim/testsuite/sim/h8300/movmd.s
+++ /dev/null

@@ -1,129 +0,0 @@
-# Hitachi H8 testcase 'movmd'
-# mach(): h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	.data
-byte_src:
-	.byte	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
-byte_dst:
-	.byte	0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
-
-	.align 2
-word_src:
-	.word	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
-word_dst:
-	.word	0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
-
-	.align 4
-long_src:
-	.long	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
-long_dst:
-	.long	0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
-
-	start
-.if (sim_cpu == h8sx)
-movmd_b:#
-	# Byte block transfer
-	#
-	set_grs_a5a5
-
-	mov	#byte_src, er5
-	mov	#byte_dst, er6
-	mov	#10, r4
-	set_ccr_zero
-	;; movmd.b
-	movmd.b
-;;; 	.word	0x7b94
-
-	test_cc_clear
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_h_gr32  0xa5a50000  er4
-	test_h_gr32  byte_src+10 er5
-	test_h_gr32  byte_dst+10 er6
-	test_gr_a5a5 7
-
-	#
-	# Now make sure exactly 10 bytes were transferred.
-	memcmp	byte_src byte_dst 10
-	cmp.b	#0, @byte_dst+10
-	beq	.L0
-	fail
-.L0:
-
-movmd_w:#
-	# Word block transfer
-	#
-	set_grs_a5a5
-
-	mov	#word_src, er5
-	mov	#word_dst, er6
-	mov	#10, r4
-	set_ccr_zero
-	;; movmd.w
-	movmd.w
-;;; 	.word	0x7ba4
-
-	test_cc_clear
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_h_gr32  0xa5a50000  er4
-	test_h_gr32  word_src+20 er5
-	test_h_gr32  word_dst+20 er6
-	test_gr_a5a5 7
-
-	#
-	# Now make sure exactly 20 bytes were transferred.
-	memcmp	word_src word_dst 20
-	cmp.w	#0, @word_dst+20
-	beq	.L1
-	fail
-.L1:
-
-movmd_l:#
-	# Long block transfer
-	#
-	set_grs_a5a5
-
-	mov	#long_src, er5
-	mov	#long_dst, er6
-	mov	#10, r4
-	set_ccr_zero
-	;; movmd.b
-	movmd.l
-;;; 	.word	0x7bb4
-
-	test_cc_clear
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_h_gr32  0xa5a50000  er4
-	test_h_gr32  long_src+40 er5
-	test_h_gr32  long_dst+40 er6
-	test_gr_a5a5 7
-
-	#
-	# Now make sure exactly 40 bytes were transferred.
-	memcmp	long_src long_dst 40
-	cmp.l	#0, @long_dst+40
-	beq	.L2
-	fail
-.L2:
-
-.endif	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/movsd.s b/sim/testsuite/sim/h8300/movsd.s
deleted file mode 100644
index 2689c53..0000000
--- a/sim/testsuite/sim/h8300/movsd.s
+++ /dev/null

@@ -1,100 +0,0 @@
-# Hitachi H8 testcase 'movsd'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	.data
-src:	.byte	'h', 'e', 'l', 'l', 'o', 0
-dst1:	.byte	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-dst2:	.byte	0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-
-	start
-.if (sim_cpu == h8sx)	
-movsd_n:#
-	# In this test, the transfer will stop after n bytes.
-	#
-	set_grs_a5a5
-
-	mov	#src,  er5
-	mov	#dst1, er6
-	mov	#4, r4
-	set_ccr_zero
-	;; movsd.b disp:16
-	movsd.b	fail1:16
-;;; 	.word	0x7b84
-;;; 	.word	0x02
-	
-	bra	pass1
-fail1:	fail
-pass1:	test_cc_clear
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_h_gr32  0xa5a50000 er4
-	test_h_gr32  src+4  er5
-	test_h_gr32  dst1+4 er6
-	test_gr_a5a5 7
-
-	#
-	# Now make sure exactly 4 bytes were transferred.
-	cmp.b	@src, @dst1
-	bne	fail1:16
-	cmp.b	@src+1, @dst1+1
-	bne	fail1:16
-	cmp.b	@src+2, @dst1+2
-	bne	fail1:16
-	cmp.b	@src+3, @dst1+3
-	bne	fail1:16
-	cmp.b	@src+4, @dst1+4
-	beq	fail1:16
-
-movsd_s:#
-	# In this test, the entire null-terminated string is transferred.
-	#
-	set_grs_a5a5
-
-	mov	#src,  er5
-	mov	#dst2, er6
-	mov	#8, r4
-	set_ccr_zero
-	;; movsd.b disp:16
-	movsd.b	pass2:16
-;;; 	.word	0x7b84
-;;; 	.word	0x10
-
-fail2:	fail
-pass2:	test_cc_clear
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_h_gr32  0xa5a50002 er4
-	test_h_gr32  src+6  er5
-	test_h_gr32  dst2+6 er6
-	test_gr_a5a5 7
-	#
-	# Now make sure 5 bytes were transferred, and the 6th is zero.
-	cmp.b	@src, @dst2
-	bne	fail2:16
-	cmp.b	@src+1, @dst2+1
-	bne	fail2:16
-	cmp.b	@src+2, @dst2+2
-	bne	fail2:16
-	cmp.b	@src+3, @dst2+3
-	bne	fail2:16
-	cmp.b	@src+4, @dst2+4
-	bne	fail2:16
-	cmp.b	#0,     @dst2+5
-	bne	fail2:16
-.endif	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/neg.s b/sim/testsuite/sim/h8300/neg.s
deleted file mode 100644
index efb0313..0000000
--- a/sim/testsuite/sim/h8300/neg.s
+++ /dev/null

@@ -1,1022 +0,0 @@
-# Hitachi H8 testcase 'neg.b, neg.w, neg.l'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# neg.b rd	;                     1 7 8  rd
-	# neg.b @erd	;         7 d rd ???? 1 7 8  ignore
-	# neg.b @erd+	; 0 1 7 4 6 c rd 1??? 1 7 8  ignore
-	# neg.b @erd-	; 0 1 7 6 6 c rd 1??? 1 7 8  ignore
-	# neg.b @+erd	; 0 1 7 5 6 c rd 1??? 1 7 8  ignore
-	# neg.b @-erd	; 0 1 7 7 6 c rd 1??? 1 7 8  ignore
-	# neg.b @(d:2,  erd)	; 0 1 7 01dd  6 8 rd 8 1 7 8  ignore
-	# neg.b @(d:16, erd)	; 0 1 7  4 6 e rd 1??? dd:16 1 7 8  ignore
-	# neg.b @(d:32, erd)	; 7 8 rd 4 6 a  2 1??? dd:32 1 7 8  ignore
-	# neg.b @aa:16		; 6 a 1 1??? aa:16 1 7 8  ignore
-	# neg.b @aa:32		; 6 a 3 1??? aa:32 1 7 8  ignore
-	# word operations
-	# long operations
-	#
-	# Coming soon:
-	# neg.b @aa:8		; 7 f aaaaaaaa 1 7 8  ignore
-	#
-
-	.data
-byte_dest:	.byte 0xa5
-	.align 2
-word_dest:	.word 0xa5a5
-	.align 4
-long_dest:	.long 0xa5a5a5a5
-	start
-
-	#
-	# Note:	apparently carry is set for neg of anything except zero.
-	#
-	
-	#
-	# 8-bit byte operations 
-	#
-
-neg_b_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b Rd
-	neg	r0l		; 8-bit register
-;;;	.word	0x1788
-	
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	cmp.b	#0x5b, r0l	; result of "neg 0xa5"
-	beq	.Lbrd
-	fail
-.Lbrd:	
-	test_h_gr16 0xa55b r0	; r0 changed by 'neg'
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a55b er0	; er0 changed by 'neg' 
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-neg_b_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @eRd
-	mov	#byte_dest, er0
-	neg.b	@er0		; register indirect operand
-;;;	.word	0x7d00
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	cmp.b	#0x5b, @er0	; memory contents changed
-	beq	.Lbind
-	fail
-.Lbind:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @eRd+
-	mov	#byte_dest, er0	; register post-increment operand
-	neg.b	@er0+
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest+1 er0	; er0 contains address plus one
-	cmp.b	#0xa5, @-er0
-	beq	.Lbpostinc
-	fail
-.Lbpostinc:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @eRd-
-	mov	#byte_dest, er0	; register post-decrement operand
-	neg.b	@er0-
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0	; er0 contains address minus one
-	cmp.b	#0x5b, @+er0
-	beq	.Lbpostdec
-	fail
-.Lbpostdec:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @+eRd
-	mov	#byte_dest-1, er0
-	neg.b	@+er0			; reg pre-increment operand
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5, @er0
-	beq	.Lbpreinc
-	fail
-.Lbpreinc:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @-eRd
-	mov	#byte_dest+1, er0
-	neg.b	@-er0		; reg pre-decr operand
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5b, @er0
-	beq	.Lbpredec
-	fail
-.Lbpredec:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @(dd:2, erd)
-	mov	#byte_dest-1, er0
-	neg.b	@(1:2, er0)	; reg plus 2-bit displacement
-;;; 	.word	0x0175
-;;; 	.word	0x6808
-;;; 	.word	0x1780
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5, @+er0
-	beq	.Lbdisp2
-	fail
-.Lbdisp2:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @(dd:16, erd)
-	mov	#byte_dest+100, er0
-	neg.b	@(-100:16, er0)	; reg plus 16-bit displacement
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	-100
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5b, @byte_dest
-	beq	.Lbdisp16
-	fail
-.Lbdisp16:
-	test_h_gr32 byte_dest+100 er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @(dd:32, erd)
-	mov	#byte_dest-0xfffff, er0
-	neg.b	@(0xfffff:32, er0)	; reg plus 32-bit displacement
-;;;	.word	0x7804
-;;;	.word	0x6a28
-;;;	.long	0xfffff
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5, @byte_dest
-	beq	.Lbdisp32
-	fail
-.Lbdisp32:
-	test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @aa:16
-	neg.b	@byte_dest:16	; 16-bit absolute address
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5b, @byte_dest
-	beq	.Lbabs16
-	fail
-.Lbabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_b_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.b @aa:32
-	neg.b	@byte_dest:32	; 32-bit absolute address
-;;;	.word	0x6a38
-;;;	.long	byte_dest
-;;;	.word	0x1780
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5, @byte_dest
-	beq	.Lbabs32
-	fail
-.Lbabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	#
-	# 16-bit word operations
-	#
-
-.if (sim_cpu)			; any except plain-vanilla h8/300
-neg_w_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w Rd
-	neg	r1		; 16-bit register operand
-;;;	.word	0x1791
-	
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	cmp.w	#0x5a5b, r1	; result of "neg 0xa5a5"
-	beq	.Lwrd
-	fail
-.Lwrd:	
-	test_h_gr32 0xa5a55a5b er1	; er1 changed by 'neg' 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-neg_w_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @eRd
-	mov	#word_dest, er1
-	neg.w	@er1		; register indirect operand
-;;;	.word	0x0154
-;;;	.word	0x6d18
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5b, @word_dest	; memory contents changed
-	beq	.Lwind
-	fail
-.Lwind:
-	test_h_gr32 word_dest er1	; er1 still contains address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @eRd+
-	mov	#word_dest, er1	; register post-increment operand
-	neg.w	@er1+
-;;;	.word	0x0154
-;;;	.word	0x6d18
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwpostinc
-	fail
-.Lwpostinc:
-	test_h_gr32 word_dest+2 er1	; er1 contains address plus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @eRd-
-	mov	#word_dest, er1
-	neg.w	@er1-
-;;;	.word	0x0156
-;;;	.word	0x6d18
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5b, @word_dest
-	beq	.Lwpostdec
-	fail
-.Lwpostdec:
-	test_h_gr32 word_dest-2 er1	; er1 contains address minus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @+eRd
-	mov	#word_dest-2, er1
-	neg.w	@+er1		; reg pre-increment operand
-;;;	.word	0x0155
-;;;	.word	0x6d18
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwpreinc
-	fail
-.Lwpreinc:
-	test_h_gr32 word_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @-eRd
-	mov	#word_dest+2, er1
-	neg.w	@-er1		; reg pre-decr operand
-;;;	.word	0x0157
-;;;	.word	0x6d18
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5b, @word_dest
-	beq	.Lwpredec
-	fail
-.Lwpredec:
-	test_h_gr32 word_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @(dd:2, erd)
-	mov	#word_dest-1, er1
-	neg.w	@(1:2, er1)	; reg plus 2-bit displacement
-;;; 	.word	0x0155
-;;; 	.word	0x6918
-;;; 	.word	0x1790
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwdisp2
-	fail
-.Lwdisp2:
-	test_h_gr32 word_dest-1 er1	; er1 contains address minus one
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @(dd:16, erd)
-	mov	#word_dest+100, er1
-	neg.w	@(-100:16, er1)	; reg plus 16-bit displacement
-;;;	.word	0x0154
-;;;	.word	0x6f18
-;;;	.word	-100
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5b, @word_dest
-	beq	.Lwdisp16
-	fail
-.Lwdisp16:
-	test_h_gr32 word_dest+100 er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @(dd:32, erd)
-	mov	#word_dest-0xfffff, er1
-	neg.w	@(0xfffff:32, er1)	; reg plus 32-bit displacement
-;;;	.word	0x7814
-;;;	.word	0x6b28
-;;;	.long	0xfffff
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwdisp32
-	fail
-.Lwdisp32:
-	test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @aa:16
-	neg.w	@word_dest:16	; 16-bit absolute address
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5b, @word_dest
-	beq	.Lwabs16
-	fail
-.Lwabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_w_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.w @aa:32
-	neg.w	@word_dest:32	; 32-bit absolute address
-;;;	.word	0x6b38
-;;;	.long	word_dest
-;;;	.word	0x1790
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwabs32
-	fail
-.Lwabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif				; h8sx
-.endif				; h8/300
-
-	#
-	# 32-bit word operations
-	#
-
-.if (sim_cpu)			; any except plain-vanilla h8/300
-neg_l_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l eRd
-	neg	er1		; 32-bit register operand
-;;;	.word	0x17b1
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, er1	; result of "neg 0xa5a5a5a5"
-	beq	.Llrd
-	fail
-.Llrd:	
-	test_h_gr32 0x5a5a5a5b er1	; er1 changed by 'neg' 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-neg_l_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @eRd
-	mov	#long_dest, er1
-	neg.l	@er1		; register indirect operand
-;;;	.word	0x0104
-;;;	.word	0x6d18
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, @long_dest	; memory contents changed
-	beq	.Llind
-	fail
-.Llind:
-	test_h_gr32 long_dest er1	; er1 still contains address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @eRd+
-	mov	#long_dest, er1	; register post-increment operand
-	neg.l	@er1+
-;;;	.word	0x0104
-;;;	.word	0x6d18
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llpostinc
-	fail
-.Llpostinc:
-	test_h_gr32 long_dest+4 er1	; er1 contains address plus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @eRd-
-	mov	#long_dest, er1
-	neg.l	@er1-
-;;;	.word	0x0106
-;;;	.word	0x6d18
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, @long_dest
-	beq	.Llpostdec
-	fail
-.Llpostdec:
-	test_h_gr32 long_dest-4 er1	; er1 contains address minus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @+eRd
-	mov	#long_dest-4, er1
-	neg.l	@+er1		; reg pre-increment operand
-;;;	.word	0x0105
-;;;	.word	0x6d18
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llpreinc
-	fail
-.Llpreinc:
-	test_h_gr32 long_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @-eRd
-	mov	#long_dest+4, er1
-	neg.l	@-er1		; reg pre-decr operand
-;;;	.word	0x0107
-;;;	.word	0x6d18
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, @long_dest
-	beq	.Llpredec
-	fail
-.Llpredec:
-	test_h_gr32 long_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @(dd:2, erd)
-	mov	#long_dest-1, er1
-	neg.l	@(1:2, er1)	; reg plus 2-bit displacement
-;;; 	.word	0x0105
-;;; 	.word	0x6918
-;;; 	.word	0x17b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Lldisp2
-	fail
-.Lldisp2:
-	test_h_gr32 long_dest-1 er1	; er1 contains address minus one
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @(dd:16, erd)
-	mov	#long_dest+100, er1
-	neg.l	@(-100:16, er1)	; reg plus 16-bit displacement
-;;;	.word	0x0104
-;;;	.word	0x6f18
-;;;	.word	-100
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, @long_dest
-	beq	.Lldisp16
-	fail
-.Lldisp16:
-	test_h_gr32 long_dest+100 er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @(dd:32, erd)
-	mov	#long_dest-0xfffff, er1
-	neg.l	@(0xfffff:32, er1)	; reg plus 32-bit displacement
-;;;	.word	0x7894
-;;;	.word	0x6b28
-;;;	.long	0xfffff
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Lldisp32
-	fail
-.Lldisp32:
-	test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @aa:16
-	neg.l	@long_dest:16	; 16-bit absolute address
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5b, @long_dest
-	beq	.Llabs16
-	fail
-.Llabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-neg_l_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  neg.l @aa:32
-	neg.l	@long_dest:32	; 32-bit absolute address
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;;	.long	long_dest
-;;;	.word	0x17b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llabs32
-	fail
-.Llabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif				; h8sx
-.endif				; h8/300
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/nop.s b/sim/testsuite/sim/h8300/nop.s
deleted file mode 100644
index 1d63b67..0000000
--- a/sim/testsuite/sim/h8300/nop.s
+++ /dev/null

@@ -1,26 +0,0 @@
-# Hitachi H8 testcase 'nop'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-nop:	set_grs_a5a5
-	set_ccr_zero
-
-	nop
-
-	test_cc_clear
-	test_grs_a5a5
-	
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/not.s b/sim/testsuite/sim/h8300/not.s
deleted file mode 100644
index d96f323..0000000
--- a/sim/testsuite/sim/h8300/not.s
+++ /dev/null

@@ -1,1009 +0,0 @@
-# Hitachi H8 testcase 'not.b, not.w, not.l'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# not.b rd	;                     1 7 0  rd
-	# not.b @erd	;         7 d rd ???? 1 7 0  ignore
-	# not.b @erd+	; 0 1 7 4 6 c rd 1??? 1 7 0  ignore
-	# not.b @erd-	; 0 1 7 6 6 c rd 1??? 1 7 0  ignore
-	# not.b @+erd	; 0 1 7 5 6 c rd 1??? 1 7 0  ignore
-	# not.b @-erd	; 0 1 7 7 6 c rd 1??? 1 7 0  ignore
-	# not.b @(d:2,  erd)	; 0 1 7 01dd  6 8 rd 8 1 7 0  ignore
-	# not.b @(d:16, erd)	; 0 1 7  4 6 e rd 1??? dd:16 1 7 0  ignore
-	# not.b @(d:32, erd)	; 7 8 rd 4 6 a  2 1??? dd:32 1 7 0  ignore
-	# not.b @aa:16		; 6 a 1 1??? aa:16 1 7 0  ignore
-	# not.b @aa:32		; 6 a 3 1??? aa:32 1 7 0  ignore
-	# word operations
-	# long operations
-	#
-	# Coming soon:
-	# not.b @aa:8		; 7 f aaaaaaaa 1 7 0  ignore
-	#
-
-.data
-byte_dest:	.byte 0xa5
-	.align 2
-word_dest:	.word 0xa5a5
-	.align 4
-long_dest:	.long 0xa5a5a5a5
-	start
-
-	#
-	# 8-bit byte operations 
-	#
-
-not_b_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  not.b Rd
-	not	r0l		; 8-bit register
-;;;	.word	0x1708
-	
-	cmp.b	#0x5a, r0l	; result of "not 0xa5"
-	beq	.Lbrd
-	fail
-.Lbrd:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa55a r0	; r0 changed by 'not'
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a55a er0	; er0 changed by 'not' 
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-not_b_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @eRd
-	mov	#byte_dest, er0
-	not.b	@er0		; register indirect operand
-;;;	.word	0x7d00
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	cmp.b	#0x5a:8, @er0	; memory contents changed
-	beq	.Lbind
-	fail
-.Lbind:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @eRd+
-	mov	#byte_dest, er0	; register post-increment operand
-	not.b	@er0+
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest+1 er0	; er0 contains address plus one
-	cmp.b	#0xa5:8, @-er0
-	beq	.Lbpostinc
-	fail
-.Lbpostinc:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @eRd-
-	mov	#byte_dest, er0	; register post-decrement operand
-	not.b	@er0-
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0	; er0 contains address minus one
-	cmp.b	#0x5a:8, @+er0
-;;; 	.word	0x0175
-;;; 	.word	0x6c08
-;;; 	.word	0xa05a
-	beq	.Lbpostdec
-	fail
-.Lbpostdec:
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @+eRd
-	mov	#byte_dest-1, er0
-	not.b	@+er0			; reg pre-increment operand
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5:8, @er0
-	beq	.Lbpreinc
-	fail
-.Lbpreinc:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @-eRd
-	mov	#byte_dest+1, er0
-	not.b	@-er0		; reg pre-decr operand
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5a:8, @er0
-	beq	.Lbpredec
-	fail
-.Lbpredec:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @(dd:2, erd)
-	mov	#byte_dest-1, er0
-	not.b	@(1:2, er0)	; reg plus 2-bit displacement
-;;; 	.word	0x0175
-;;; 	.word	0x6808
-;;; 	.word	0x1700
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5:8, @+er0
-	beq	.Lbdisp2
-	fail
-.Lbdisp2:
-	test_h_gr32 byte_dest er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @(dd:16, erd)
-	mov	#byte_dest+100, er0
-	not.b	@(-100:16, er0)	; reg plus 16-bit displacement
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	-100
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5a:8, @byte_dest
-	beq	.Lbdisp16
-	fail
-.Lbdisp16:
-	test_h_gr32 byte_dest+100 er0	; er0 contains destination address 
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @(dd:32, erd)
-	mov	#byte_dest-0xfffff, er0
-	not.b	@(0xfffff:32, er0)	; reg plus 32-bit displacement
-;;;	.word	0x7804
-;;;	.word	0x6a28
-;;;	.long	0xfffff
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5:8, @byte_dest
-	beq	.Lbdisp32
-	fail
-.Lbdisp32:
-	test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @aa:16
-	not.b	@byte_dest:16	; 16-bit absolute address
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.b	#0x5a:8, @byte_dest
-	beq	.Lbabs16
-	fail
-.Lbabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_b_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.b @aa:32
-	not.b	@byte_dest:32	; 32-bit absolute address
-;;;	.word	0x6a38
-;;;	.long	byte_dest
-;;;	.word	0x1700
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.b	#0xa5:8, @byte_dest
-	beq	.Lbabs32
-	fail
-.Lbabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-	#
-	# 16-bit word operations
-	#
-
-.if (sim_cpu)			; any except plain-vanilla h8/300
-not_w_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  not.w Rd
-	not	r1		; 16-bit register operand
-;;;	.word	0x1711
-	
-	cmp.w	#0x5a5a, r1	; result of "not 0xa5a5"
-	beq	.Lwrd
-	fail
-.Lwrd:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0xa5a55a5a er1	; er1 changed by 'not' 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-not_w_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @eRd
-	mov	#word_dest, er1
-	not.w	@er1		; register indirect operand
-;;;	.word	0x0154
-;;;	.word	0x6d18
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5a, @word_dest	; memory contents changed
-	beq	.Lwind
-	fail
-.Lwind:
-	test_h_gr32 word_dest er1	; er1 still contains address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @eRd+
-	mov	#word_dest, er1	; register post-increment operand
-	not.w	@er1+
-;;;	.word	0x0154
-;;;	.word	0x6d18
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwpostinc
-	fail
-.Lwpostinc:
-	test_h_gr32 word_dest+2 er1	; er1 contains address plus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @eRd-
-	mov	#word_dest, er1
-	not.w	@er1-
-;;;	.word	0x0156
-;;;	.word	0x6d18
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5a, @word_dest
-	beq	.Lwpostdec
-	fail
-.Lwpostdec:
-	test_h_gr32 word_dest-2 er1	; er1 contains address minus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @+eRd
-	mov	#word_dest-2, er1
-	not.w	@+er1		; reg pre-increment operand
-;;;	.word	0x0155
-;;;	.word	0x6d18
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwpreinc
-	fail
-.Lwpreinc:
-	test_h_gr32 word_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @-eRd
-	mov	#word_dest+2, er1
-	not.w	@-er1		; reg pre-decr operand
-;;;	.word	0x0157
-;;;	.word	0x6d18
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5a, @word_dest
-	beq	.Lwpredec
-	fail
-.Lwpredec:
-	test_h_gr32 word_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @(dd:2, erd)
-	mov	#word_dest-1, er1
-	not.w	@(1:2, er1)	; reg plus 2-bit displacement
-;;; 	.word	0x0155
-;;; 	.word	0x6918
-;;; 	.word	0x1710
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwdisp2
-	fail
-.Lwdisp2:
-	test_h_gr32 word_dest-1 er1	; er1 contains address minus one
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @(dd:16, erd)
-	mov	#word_dest+100, er1
-	not.w	@(-100:16, er1)	; reg plus 16-bit displacement
-;;;	.word	0x0154
-;;;	.word	0x6f18
-;;;	.word	-100
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5a, @word_dest
-	beq	.Lwdisp16
-	fail
-.Lwdisp16:
-	test_h_gr32 word_dest+100 er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @(dd:32, erd)
-	mov	#word_dest-0xfffff, er1
-	not.w	@(0xfffff:32, er1)	; reg plus 32-bit displacement
-;;;	.word	0x7814
-;;;	.word	0x6b28
-;;;	.long	0xfffff
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwdisp32
-	fail
-.Lwdisp32:
-	test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @aa:16
-	not.w	@word_dest:16	; 16-bit absolute address
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.w	#0x5a5a, @word_dest
-	beq	.Lwabs16
-	fail
-.Lwabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_w_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.w @aa:32
-	not.w	@word_dest:32	; 32-bit absolute address
-;;;	.word	0x6b38
-;;;	.long	word_dest
-;;;	.word	0x1710
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.w	#0xa5a5, @word_dest
-	beq	.Lwabs32
-	fail
-.Lwabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif				; h8sx
-.endif				; h8/300
-
-	#
-	# 32-bit word operations
-	#
-
-.if (sim_cpu)			; any except plain-vanilla h8/300
-not_l_reg16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  not.l eRd
-	not	er1		; 32-bit register operand
-;;;	.word	0x1731
-
-	cmp.l	#0x5a5a5a5a, er1	; result of "not 0xa5a5a5a5"
-	beq	.Llrd
-	fail
-.Llrd:	
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0x5a5a5a5a er1	; er1 changed by 'not' 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-not_l_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @eRd
-	mov	#long_dest, er1
-	not.l	@er1		; register indirect operand
-;;;	.word	0x0104
-;;;	.word	0x6d18
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5a, @long_dest	; memory contents changed
-	beq	.Llind
-	fail
-.Llind:
-	test_h_gr32 long_dest er1	; er1 still contains address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @eRd+
-	mov	#long_dest, er1	; register post-increment operand
-	not.l	@er1+
-;;;	.word	0x0104
-;;;	.word	0x6d18
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llpostinc
-	fail
-.Llpostinc:
-	test_h_gr32 long_dest+4 er1	; er1 contains address plus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @eRd-
-	mov	#long_dest, er1
-	not.l	@er1-
-;;;	.word	0x0106
-;;;	.word	0x6d18
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5a, @long_dest
-	beq	.Llpostdec
-	fail
-.Llpostdec:
-	test_h_gr32 long_dest-4 er1	; er1 contains address minus two
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_rdpreinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @+eRd
-	mov	#long_dest-4, er1
-	not.l	@+er1		; reg pre-increment operand
-;;;	.word	0x0105
-;;;	.word	0x6d18
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llpreinc
-	fail
-.Llpreinc:
-	test_h_gr32 long_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_rdpredec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @-eRd
-	mov	#long_dest+4, er1
-	not.l	@-er1		; reg pre-decr operand
-;;;	.word	0x0107
-;;;	.word	0x6d18
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5a, @long_dest
-	beq	.Llpredec
-	fail
-.Llpredec:
-	test_h_gr32 long_dest er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_disp2dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @(dd:2, erd)
-	mov	#long_dest-1, er1
-	not.l	@(1:2, er1)	; reg plus 2-bit displacement
-;;; 	.word	0x0105
-;;; 	.word	0x6918
-;;; 	.word	0x1730
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Lldisp2
-	fail
-.Lldisp2:
-	test_h_gr32 long_dest-1 er1	; er1 contains address minus one
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_disp16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @(dd:16, erd)
-	mov	#long_dest+100, er1
-	not.l	@(-100:16, er1)	; reg plus 16-bit displacement
-;;;	.word	0x0104
-;;;	.word	0x6f18
-;;;	.word	-100
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5a, @long_dest
-	beq	.Lldisp16
-	fail
-.Lldisp16:
-	test_h_gr32 long_dest+100 er1	; er1 contains destination address 
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_disp32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @(dd:32, erd)
-	mov	#long_dest-0xfffff, er1
-	not.l	@(0xfffff:32, er1)	; reg plus 32-bit displacement
-;;;	.word	0x7894
-;;;	.word	0x6b28
-;;;	.long	0xfffff
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Lldisp32
-	fail
-.Lldisp32:
-	test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_abs16dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @aa:16
-	not.l	@long_dest:16	; 16-bit absolute address
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	cmp.l	#0x5a5a5a5a, @long_dest
-	beq	.Llabs16
-	fail
-.Llabs16:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-not_l_abs32dst:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  not.l @aa:32
-	not.l	@long_dest:32	; 32-bit absolute address
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;;	.long	long_dest
-;;;	.word	0x1730
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	cmp.l	#0xa5a5a5a5, @long_dest
-	beq	.Llabs32
-	fail
-.Llabs32:
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif				; h8sx
-.endif				; h8/300
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/or.b.s b/sim/testsuite/sim/h8300/or.b.s
deleted file mode 100644
index fd06f08..0000000
--- a/sim/testsuite/sim/h8300/or.b.s
+++ /dev/null

@@ -1,493 +0,0 @@
-# Hitachi H8 testcase 'or.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# or.b #xx:8, rd	;                     c rd   xxxxxxxx
-	# or.b #xx:8, @erd	;         7 d rd ???? c ???? xxxxxxxx
-	# or.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
-	# or.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
-	# or.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
-	# or.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
-	# or.b rs, rd		;                     1 4 rs rd
-	# or.b reg8, @erd	;         7 d rd ???? 1 4 rs ????
-	# or.b reg8, @erd+	;         0 1 7     9 8 rd 4 rs
-	# or.b reg8, @erd-	;         0 1 7     9 a rd 4 rs
-	# or.b reg8, @+erd	;         0 1 7     9 9 rd 4 rs
-	# or.b reg8, @-erd	;         0 1 7     9 b rd 4 rs
-	#
-
-	# Coming soon:
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0xa5
-post_byte:	.byte 0
-
-	start
-	
-or_b_imm8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.b #xx:8,Rd
-	or.b	#0xaa, r0l	; Immediate 8-bit src, reg8 dest
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5af r0	; or result:	a5 | aa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5af er0	; or result:	 a5 | aa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-or_b_imm8_rdind:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	or.b	#0xaa:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0xc0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L1
-	fail
-.L1:
-
-or_b_imm8_rdpostinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	or.b	#0x55:8, @er0+	; Immediate 8-bit src, reg post-incr dest
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xc055
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 post_byte, er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xf5, r0l
-	beq	.L2
-	fail
-.L2:
-
-or_b_imm8_rdpostdec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	or.b	#0xaa:8, @er0-	; Immediate 8-bit src, reg post-decr dest
-;;;  	.word	0x0176
-;;;  	.word	0x6c08
-;;;  	.word	0xc0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 pre_byte, er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L3
-	fail
-.L3:
-
-or_b_imm8_rdpreinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b #xx:8,@+eRd
-	mov	#pre_byte, er0
-	or.b	#0x55:8, @+er0	; Immediate 8-bit src, reg pre-incr dest
-;;;  	.word	0x0175
-;;;  	.word	0x6c08
-;;;  	.word	0xc055
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xf5, r0l
-	beq	.L4
-	fail
-.L4:
-
-or_b_imm8_rdpredec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b #xx:8,@-eRd
-	mov	#post_byte, er0
-	or.b	#0xaa:8, @-er0	; Immediate 8-bit src, reg pre-decr dest
-;;; 	.word	0x0177
-;;; 	.word	0x6c08
-;;; 	.word	0xc0aa
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 contains destination address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L5
-	fail
-.L5:
-
-
-.endif
-
-or_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.b Rs,Rd
-	mov.b	#0xaa, r0h
-	or.b	r0h, r0l	; Reg8 src, reg8 dest
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xaaaf r0	; or result:	a5 | aa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5aaaf er0	; or result:	a5 | aa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-or_b_reg8_rdind:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b rs8,@eRd	; or reg8 to register indirect
-	mov	#byte_dest, er0
-	mov	#0xaa, r1l
-	or.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x1490
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a5aa er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L6
-	fail
-.L6:
-
-or_b_reg8_rdpostinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b rs8,@eRd+	; or reg8 to register indirect post-increment
-	mov	#byte_dest, er0
-	mov	#0x55, r1l
-	or.b	r1l, @er0+	; reg8 src, reg post-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x8049
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a555 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xf5, r0l
-	beq	.L7
-	fail
-.L7:
-
-or_b_reg8_rdpostdec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b rs8,@eRd-	; or reg8 to register indirect post-decrement
-	mov	#byte_dest, er0
-	mov	#0xaa, r1l
-	or.b	r1l, @er0-	; reg8 src, reg post-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xa049
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a5aa er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L8
-	fail
-.L8:
-
-or_b_reg8_rdpreinc:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b rs8,@+eRd	; or reg8 to register indirect pre-increment
-	mov	#pre_byte, er0
-	mov	#0x55, r1l
-	or.b	r1l, @+er0	; reg8 src, reg pre-incr dest
-;;; 	.word	0x0179
-;;; 	.word	0x9049
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address
-	test_h_gr32 0xa5a5a555 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xf5, r0l
-	beq	.L9
-	fail
-.L9:
-
-or_b_reg8_rdpredec:
-	mov	#byte_dest, er0
-	mov.b	#0xa5, r1l
-	mov.b	r1l, @er0
-
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  or.b rs8,@-eRd	; or reg8 to register indirect pre-decrement
-	mov	#post_byte, er0
-	mov	#0xaa, r1l
-	or.b	r1l, @-er0	; reg8 src, reg pre-decr dest
-;;; 	.word	0x0179
-;;; 	.word	0xb049
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 contains destination address
-	test_h_gr32 0xa5a5a5aa er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xaf, r0l
-	beq	.L10
-	fail
-.L10:
-
-orc_imm8_ccr:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  orc #xx:8,ccr
-
-	test_neg_clear
-	orc	#0x8, ccr	; Immediate 8-bit operand (neg flag)
-	test_neg_set
-
-	test_zero_clear
-	orc	#0x4, ccr	; Immediate 8-bit operand (zero flag)
-	test_zero_set
-
-	test_ovf_clear
-	orc	#0x2, ccr	; Immediate 8-bit operand (overflow flag)
-	test_ovf_set
-
-	test_carry_clear
-	orc	#0x1, ccr	; Immediate 8-bit operand (carry flag)
-	test_carry_set
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/or.l.s b/sim/testsuite/sim/h8300/or.l.s
deleted file mode 100644
index 03c3f22..0000000
--- a/sim/testsuite/sim/h8300/or.l.s
+++ /dev/null

@@ -1,77 +0,0 @@
-# Hitachi H8 testcase 'or.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu == h8sx)		; 16-bit immediate is only available on sx.
-or_l_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.l #xx:16,Rd
-	or.l	#0xaaaa, er0	; Immediate 16-bit operand 
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a5afaf er0	; or result:	 a5a5a5a5 | aaaa
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-or_l_imm32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.l #xx:32,Rd
-	or.l	#0xaaaaaaaa, er0	; Immediate 32-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xafafafaf er0	; or result:	 a5a5a5a5 | aaaaaaaa
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-or_l_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.l Rs,Rd
-	mov.l	#0xaaaaaaaa, er1
-	or.l	er1, er0	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xafafafaf er0	; or result:	a5a5a5a5 | aaaaaaaa
-	test_h_gr32 0xaaaaaaaa er1	; Make sure er1 is unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/or.w.s b/sim/testsuite/sim/h8300/or.w.s
deleted file mode 100644
index 32eef45..0000000
--- a/sim/testsuite/sim/h8300/or.w.s
+++ /dev/null

@@ -1,61 +0,0 @@
-# Hitachi H8 testcase 'or.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-or_w_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.w #xx:16,Rd
-	or.w	#0xaaaa, r0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xafaf r0	; or result:	a5a5 | aaaa
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5afaf er0	; or result:	 a5a5 | aaaa
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-or_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  or.w Rs,Rd
-	mov.w	#0xaaaa, r1
-	or.w	r1, r0		; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xafaf r0	; or result:	a5a5 | aaaa
-	test_h_gr16 0xaaaa r1	; Make sure r1 is unchanged
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5afaf er0	; or result:	a5a5 | aaaa
-	test_h_gr32 0xa5a5aaaa er1	; Make sure er1 is unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s
deleted file mode 100644
index 088345d..0000000
--- a/sim/testsuite/sim/h8300/rotl.s
+++ /dev/null

@@ -1,1212 +0,0 @@
-# Hitachi H8 testcase 'rotl'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-rotl_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.b	r0l		; shift left arithmetic by one
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	test_h_gr16 0xa54b r0	; 1010 0101 -> 0100 1011
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a54b er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_b_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotl.b	@er0	; shift right arithmetic by one, indirect
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbind1
-	fail
-.Lbind1:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexb16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.b	@(byte_dest-5:16, r0.b)	; indexed byte/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexb161
-	fail
-.Lbindexb161:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexw16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.b	@(byte_dest-256:16, r0.w)	; indexed byte/word
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexw161
-	fail
-.Lbindexw161:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexl16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.b	@(byte_dest+1:16, er0.l)	; indexed byte/long
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexl161
-	fail
-.Lbindexl161:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexb32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.b	@(byte_dest-5:32, r1.b)	; indexed byte/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexb321
-	fail
-.Lbindexb321:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexw32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.b	@(byte_dest-256:32, r1.w)	; indexed byte/word
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexw321
-	fail
-.Lbindexw321:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexl32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.b	@(byte_dest+1:32, er1.l)	; indexed byte/long
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0100 1011
-	cmp.b	#0x4b, @byte_dest
-	beq	.Lbindexl321
-	fail
-.Lbindexl321:
-	mov.b	#0xa5, @byte_dest
-
-.endif
-
-rotl_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.b	#2, r0l		; shift left arithmetic by two
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-
-	test_h_gr16 0xa596 r0	; 1010 0101 -> 1001 0110
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a596 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_b_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotl.b	#2, @er0	; shift right arithmetic by one, indirect
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbind2
-	fail
-.Lbind2:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexb16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.b	#2, @(byte_dest-5:16, r0.b)	; indexed byte/byte
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexb162
-	fail
-.Lbindexb162:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexw16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.b	#2, @(byte_dest-256:16, r0.w)	; indexed byte/word
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexw162
-	fail
-.Lbindexw162:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexl16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.b	#2, @(byte_dest+1:16, er0.l)	; indexed byte/long
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexl162
-	fail
-.Lbindexl162:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexb32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.b	#2, @(byte_dest-5:32, r1.b)	; indexed byte/byte
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexb322
-	fail
-.Lbindexb322:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexw32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.b	#2, @(byte_dest-256:32, r1.w)	; indexed byte/word
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexw322
-	fail
-.Lbindexw322:
-	mov.b	#0xa5, @byte_dest
-
-rotl_b_indexl32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.b	#2, @(byte_dest+1:32, er1.l)	; indexed byte/long
-
-	test_carry_clear	; H=0 N=1 Z=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1001 0110
-	cmp.b	#0x96, @byte_dest
-	beq	.Lbindexl322
-	fail
-.Lbindexl322:
-	mov.b	#0xa5, @byte_dest
-
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-rotl_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.w	r0		; shift left arithmetic by one
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	test_h_gr16 0x4b4b r0	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	test_h_gr32 0xa5a54b4b er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_w_indexb16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.w	@(word_dest-10:16, r0.b)	; indexed word/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexb161
-	fail
-.Lwindexb161:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexw16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.w	@(word_dest-512:16, r0.w)	; indexed word/word
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexw161
-	fail
-.Lwindexw161:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexl16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.w	@(word_dest+2:16, er0.l)	; indexed word/long
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexl161
-	fail
-.Lwindexl161:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexb32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.w	@(word_dest-10:32, r1.b)	; indexed word/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexb321
-	fail
-.Lwindexb321:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexw32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.w	@(word_dest-512:32, r1.w)	; indexed word/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexw321
-	fail
-.Lwindexw321:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexl32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.w	@(word_dest+2:32, er1.l)	; indexed word/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0100 1011 0100 1011
-	cmp.w	#0x4b4b, @word_dest
-	beq	.Lwindexl321
-	fail
-.Lwindexl321:
-	mov.w	#0xa5a5, @word_dest
-.endif
-
-rotl_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.w	#2, r0		; shift left arithmetic by two
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-	test_h_gr16 0x9696 r0	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	test_h_gr32 0xa5a59696 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_w_indexb16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.w	#2, @(word_dest-10:16, r0.b)	; indexed word/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexb162
-	fail
-.Lwindexb162:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexw16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.w	#2, @(word_dest-512:16, r0.w)	; indexed word/word
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexw162
-	fail
-.Lwindexw162:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexl16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.w	#2, @(word_dest+2:16, er0.l)	; indexed word/long
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexl162
-	fail
-.Lwindexl162:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexb32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.w	#2, @(word_dest-10:32, r1.b)	; indexed word/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexb322
-	fail
-.Lwindexb322:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexw32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.w	#2, @(word_dest-512:32, r1.w)	; indexed word/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexw322
-	fail
-.Lwindexw322:
-	mov.w	#0xa5a5, @word_dest
-
-rotl_w_indexl32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.w	#2, @(word_dest+2:32, er1.l)	; indexed word/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1001 0110 1001 0110
-	cmp.w	#0x9696, @word_dest
-	beq	.Lwindexl322
-	fail
-.Lwindexl322:
-	mov.w	#0xa5a5, @word_dest
-.endif
-
-rotl_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.l	er0		; shift left arithmetic by one
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	test_h_gr32 0x4b4b4b4b er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_l_indexb16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.l	@(long_dest-20:16, er0.b)	; indexed long/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexb161
-	fail
-.Llindexb161:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexw16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.l	@(long_dest-1024:16, er0.w)	; indexed long/word
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexw161
-	fail
-.Llindexw161:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexl16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.l	@(long_dest+4:16, er0.l)	; indexed long/long
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexl161
-	fail
-.Llindexl161:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexb32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.l	@(long_dest-20:32, er1.b)	; indexed long/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexb321
-	fail
-.Llindexb321:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexw32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.l	@(long_dest-1024:32, er1.w)	; indexed long/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexw321
-	fail
-.Llindexw321:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexl32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.l	@(long_dest+4:32, er1.l)	; indexed long/byte
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1011
-	cmp.l	#0x4b4b4b4b, @long_dest
-	beq	.Llindexl321
-	fail
-.Llindexl321:
-	mov.l	#0xa5a5a5a5, @long_dest
-.endif
-
-rotl_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotl.l	#2, er0		; shift left arithmetic by two
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	test_h_gr32 0x96969696 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotl_l_indexb16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r0l
-	rotl.l	#2, @(long_dest-20:16, er0.b)	; indexed long/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexb162
-	fail
-.Llindexb162:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexw16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r0
-	rotl.l	#2, @(long_dest-1024:16, er0.w)	; indexed long/word
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexw162
-	fail
-.Llindexw162:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexl16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er0
-	rotl.l	#2, @(long_dest+4:16, er0.l)	; indexed long/long
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexl162
-	fail
-.Llindexl162:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexb32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.b	#5, r1l
-	rotl.l	#2, @(long_dest-20:32, er1.b)	; indexed long/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a5a505 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexb322
-	fail
-.Llindexb322:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexw32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.w	#256, r1
-	rotl.l	#2, @(long_dest-1024:32, er1.w)	; indexed long/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xa5a50100 er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexw322
-	fail
-.Llindexw322:
-	mov.l	#0xa5a5a5a5, @long_dest
-
-rotl_l_indexl32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov.l	#0xffffffff, er1
-	rotl.l	#2, @(long_dest+4:32, er1.l)	; indexed long/byte
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  0xffffffff er1
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1001 0110 1001 0110 1001 0110 1001 0110
-	cmp.l	#0x96969696, @long_dest
-	beq	.Llindexl322
-	fail
-.Llindexl322:
-	mov.l	#0xa5a5a5a5, @long_dest
-.endif
-.endif
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s
deleted file mode 100644
index af5cba0..0000000
--- a/sim/testsuite/sim/h8300/rotr.s
+++ /dev/null

@@ -1,1802 +0,0 @@
-# Hitachi H8 testcase 'rotr'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-rotr_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	r0l		; shift right arithmetic by one
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xa5d2 r0	; 1010 0101 -> 1101 0010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a5d2 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotr_b_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	@er0	; shift right arithmetic by one, indirect
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbind1
-	fail
-.Lbind1:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	@er0+	; shift right arithmetic by one, postinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpostinc1
-	fail
-.Lbpostinc1:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	@er0-	; shift right arithmetic by one, postdec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpostdec1
-	fail
-.Lbpostdec1:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	rotr.b	@+er0	; shift right arithmetic by one, preinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpreinc1
-	fail
-.Lbpreinc1:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	rotr.b	@-er0	; shift right arithmetic by one, predec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpredec1
-	fail
-.Lbpredec1:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	rotr.b	@(2:2, er0)	; shift right arithmetic by one, disp2
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp21
-	fail
-.Lbdisp21:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	rotr.b	@(44:16, er0)	; shift right arithmetic by one, disp16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp161
-	fail
-.Lbdisp161:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	rotr.b	@(666:32, er0)	; shift right arithmetic by one, disp32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp321
-	fail
-.Lbdisp321:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	@byte_dest:16	; shift right arithmetic by one, abs16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbabs161
-	fail
-.Lbabs161:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	@byte_dest:32	; shift right arithmetic by one, abs32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbabs321
-	fail
-.Lbabs321:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-rotr_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	#2, r0l		; shift right arithmetic by two
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0xa569 r0	; 1010 0101 -> 0110 1001
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a569 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotr_b_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	#2, @er0	; shift right arithmetic by two, indirect
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbind2
-	fail
-.Lbind2:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	#2, @er0+	; shift right arithmetic by two, postinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbpostinc2
-	fail
-.Lbpostinc2:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotr.b	#2, @er0-	; shift right arithmetic by two, postdec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbpostdec2
-	fail
-.Lbpostdec2:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	rotr.b	#2, @+er0	; shift right arithmetic by two, preinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbpreinc2
-	fail
-.Lbpreinc2:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	rotr.b	#2, @-er0	; shift right arithmetic by two, predec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbpredec2
-	fail
-.Lbpredec2:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	rotr.b	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbdisp22
-	fail
-.Lbdisp22:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	rotr.b	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbdisp162
-	fail
-.Lbdisp162:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	rotr.b	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbdisp322
-	fail
-.Lbdisp322:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	#2, @byte_dest:16	; shift right arithmetic by two, abs16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbabs162
-	fail
-.Lbabs162:
-	mov.b	#0xa5, @byte_dest
-
-rotr_b_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.b	#2, @byte_dest:32	; shift right arithmetic by two, abs32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0110 1001
-	cmp.b	#0x69, @byte_dest
-	beq	.Lbabs322
-	fail
-.Lbabs322:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-rotr_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	r0		; shift right arithmetic by one
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0xd2d2 r0	; 1010 0101 1010 0101 -> 1101 0010 1101 0010
-	test_h_gr32 0xa5a5d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotr_w_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	@er0	; shift right arithmetic by one, indirect
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwind1
-	fail
-.Lwind1:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	@er0+	; shift right arithmetic by one, postinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpostinc1
-	fail
-.Lwpostinc1:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	@er0-	; shift right arithmetic by one, postdec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpostdec1
-	fail
-.Lwpostdec1:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotr.w	@+er0	; shift right arithmetic by one, preinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpreinc1
-	fail
-.Lwpreinc1:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	rotr.w	@-er0	; shift right arithmetic by one, predec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpredec1
-	fail
-.Lwpredec1:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotr.w	@(2:2, er0)	; shift right arithmetic by one, disp2
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp21
-	fail
-.Lwdisp21:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	rotr.w	@(44:16, er0)	; shift right arithmetic by one, disp16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp161
-	fail
-.Lwdisp161:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	rotr.w	@(666:32, er0)	; shift right arithmetic by one, disp32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp321
-	fail
-.Lwdisp321:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	@word_dest:16	; shift right arithmetic by one, abs16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwabs161
-	fail
-.Lwabs161:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	@word_dest:32	; shift right arithmetic by one, abs32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwabs321
-	fail
-.Lwabs321:
-	mov.w	#0xa5a5, @word_dest
-.endif
-	
-rotr_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	#2, r0		; shift right arithmetic by two
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0x6969 r0	; 1010 0101 1010 0101 -> 0110 1001 0110 1001
-	test_h_gr32 0xa5a56969 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotr_w_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	#2, @er0	; shift right arithmetic by two, indirect
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwind2
-	fail
-.Lwind2:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	#2, @er0+	; shift right arithmetic by two, postinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwpostinc2
-	fail
-.Lwpostinc2:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotr.w	#2, @er0-	; shift right arithmetic by two, postdec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwpostdec2
-	fail
-.Lwpostdec2:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotr.w	#2, @+er0	; shift right arithmetic by two, preinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwpreinc2
-	fail
-.Lwpreinc2:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	rotr.w	#2, @-er0	; shift right arithmetic by two, predec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwpredec2
-	fail
-.Lwpredec2:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotr.w	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwdisp22
-	fail
-.Lwdisp22:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	rotr.w	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwdisp162
-	fail
-.Lwdisp162:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	rotr.w	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwdisp322
-	fail
-.Lwdisp322:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	#2, @word_dest:16	; shift right arithmetic by two, abs16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwabs162
-	fail
-.Lwabs162:
-	mov.w	#0xa5a5, @word_dest
-
-rotr_w_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.w	#2, @word_dest:32	; shift right arithmetic by two, abs32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0110 1001 0110 1001  
-	cmp.w	#0x6969, @word_dest
-	beq	.Lwabs322
-	fail
-.Lwabs322:
-	mov.w	#0xa5a5, @word_dest
-.endif
-
-rotr_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	er0		; shift right arithmetic by one, register
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	test_h_gr32  0xd2d2d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotr_l_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	@er0	; shift right arithmetic by one, indirect
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llind1
-	fail
-.Llind1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	@er0+	; shift right arithmetic by one, postinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpostinc1
-	fail
-.Llpostinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	@er0-	; shift right arithmetic by one, postdec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpostdec1
-	fail
-.Llpostdec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	rotr.l	@+er0	; shift right arithmetic by one, preinc
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpreinc1
-	fail
-.Llpreinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	rotr.l	@-er0	; shift right arithmetic by one, predec
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpredec1
-	fail
-.Llpredec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	rotr.l	@(2:2, er0)	; shift right arithmetic by one, disp2
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp21
-	fail
-.Lldisp21:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	rotr.l	@(44:16, er0)	; shift right arithmetic by one, disp16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp161
-	fail
-.Lldisp161:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	rotr.l	@(666:32, er0)	; shift right arithmetic by one, disp32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp321
-	fail
-.Lldisp321:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	@long_dest:16	; shift right arithmetic by one, abs16
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llabs161
-	fail
-.Llabs161:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	@long_dest:32	; shift right arithmetic by one, abs32
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llabs321
-	fail
-.Llabs321:
-	mov	#0xa5a5a5a5, @long_dest
-.endif
-
-rotr_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	#2, er0		; shift right arithmetic by two, register
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	test_h_gr32  0x69696969 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-rotr_l_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	#2, @er0	; shift right arithmetic by two, indirect
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llind2
-	fail
-.Llind2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	#2, @er0+	; shift right arithmetic by two, postinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llpostinc2
-	fail
-.Llpostinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotr.l	#2, @er0-	; shift right arithmetic by two, postdec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llpostdec2
-	fail
-.Llpostdec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	rotr.l	#2, @+er0	; shift right arithmetic by two, preinc
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llpreinc2
-	fail
-.Llpreinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	rotr.l	#2, @-er0	; shift right arithmetic by two, predec
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llpredec2
-	fail
-.Llpredec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	rotr.l	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Lldisp22
-	fail
-.Lldisp22:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	rotr.l	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Lldisp162
-	fail
-.Lldisp162:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	rotr.l	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Lldisp322
-	fail
-.Lldisp322:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	#2, @long_dest:16	; shift right arithmetic by two, abs16
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llabs162
-	fail
-.Llabs162:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotr_l_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotr.l	#2, @long_dest:32	; shift right arithmetic by two, abs32
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x69696969, @long_dest
-	beq	.Llabs322
-	fail
-.Llabs322:
-	mov	#0xa5a5a5a5, @long_dest
-	
-.endif
-.endif
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s
deleted file mode 100644
index 3ae703e..0000000
--- a/sim/testsuite/sim/h8300/rotxl.s
+++ /dev/null

@@ -1,167 +0,0 @@
-# Hitachi H8 testcase 'rotxl'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-rotxl_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.b	r0l		; shift left arithmetic by one
-;;;	.word	0x1208
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	test_h_gr16 0xa54a r0	; 1010 0101 -> 0100 1010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a54a er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-rotxl_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.b	#2, r0l		; shift left arithmetic by two
-;;; 	.word	0x1248
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-
-	test_h_gr16 0xa595 r0	; 1010 0101 -> 1001 0101
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a595 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)			; Not available in h8300 mode
-rotxl_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.w	r0		; shift left arithmetic by one
-;;;	.word	0x1210
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	test_h_gr16 0x4b4a r0	; 1010 0101 1010 0101 -> 0100 1011 0100 1010
-	test_h_gr32 0xa5a54b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-rotxl_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.w	#2, r0		; shift left arithmetic by two
-;;;	.word	0x1250
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-	test_h_gr16 0x9695 r0	; 1010 0101 1010 0101 -> 1001 0110 1001 0101
-	test_h_gr32 0xa5a59695 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-rotxl_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.l	er0		; shift left arithmetic by one
-;;;	.word	1030
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1010
-	test_h_gr32 0x4b4b4b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-rotxl_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxl.l	#2, er0		; shift left arithmetic by two
-;;;	.word	0x1270
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear		
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1001 0110 1001 0110 1001 0110 1001 0101
-	test_h_gr32 0x96969695 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s
deleted file mode 100644
index 6fc5b2c..0000000
--- a/sim/testsuite/sim/h8300/rotxr.s
+++ /dev/null

@@ -1,2002 +0,0 @@
-# Hitachi H8 testcase 'rotxr'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-rotxr_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	r0l		; shift right arithmetic by one
-;;;	.word	0x1308
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0xa552 r0	; 1010 0101 -> 0101 0010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a552 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotxr_b_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x7d00
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbind1
-	fail
-.Lbind1:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpostinc1
-	fail
-.Lbpostinc1:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpostdec1
-	fail
-.Lbpostdec1:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	rotxr.b	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpreinc1
-	fail
-.Lbpreinc1:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	rotxr.b	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpredec1
-	fail
-.Lbpredec1:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	rotxr.b	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp21
-	fail
-.Lbdisp21:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	rotxr.b	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp161
-	fail
-.Lbdisp161:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	rotxr.b	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp321
-	fail
-.Lbdisp321:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	@byte_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbabs161
-	fail
-.Lbabs161:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	@byte_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x1300
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbabs321
-	fail
-.Lbabs321:
-	mov	#0xa5a5a5a5, @byte_dest
-.endif
-
-rotxr_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	#2, r0l		; shift right arithmetic by two
-;;;	.word	0x1348
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xa5a9 r0	; 1010 0101 -> 1010 1001
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a5a9 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotxr_b_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x7d00
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbind2
-	fail
-.Lbind2:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbpostinc2
-	fail
-.Lbpostinc2:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	rotxr.b	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbpostdec2
-	fail
-.Lbpostdec2:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	rotxr.b	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbpreinc2
-	fail
-.Lbpreinc2:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	rotxr.b	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbpredec2
-	fail
-.Lbpredec2:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	rotxr.b	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbdisp22
-	fail
-.Lbdisp22:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	rotxr.b	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbdisp162
-	fail
-.Lbdisp162:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	rotxr.b	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbdisp322
-	fail
-.Lbdisp322:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	#2, @byte_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbabs162
-	fail
-.Lbabs162:
-	mov	#0xa5a5a5a5, @byte_dest
-
-rotxr_b_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.b	#2, @byte_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x1340
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1010 1001
-	cmp.b	#0xa9, @byte_dest
-	beq	.Lbabs322
-	fail
-.Lbabs322:
-	mov	#0xa5a5a5a5, @byte_dest
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-rotxr_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	r0		; shift right arithmetic by one
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0x52d2 r0	; 1010 0101 1010 0101 -> 0101 0010 1101 0010
-	test_h_gr32 0xa5a552d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotxr_w_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwind1
-	fail
-.Lwind1:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpostinc1
-	fail
-.Lwpostinc1:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpostdec1
-	fail
-.Lwpostdec1:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotxr.w	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpreinc1
-	fail
-.Lwpreinc1:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	rotxr.w	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpredec1
-	fail
-.Lwpredec1:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotxr.w	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0156
-;;;	.word	0xa908
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp21
-	fail
-.Lwdisp21:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	rotxr.w	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp161
-	fail
-.Lwdisp161:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	rotxr.w	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp321
-	fail
-.Lwdisp321:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	@word_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwabs161
-	fail
-.Lwabs161:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	@word_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1310
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwabs321
-	fail
-.Lwabs321:
-	mov	#0xa5a5a5a5, @word_dest
-.endif
-	
-rotxr_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	#2, r0		; shift right arithmetic by two
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xa969 r0	; 1010 0101 1010 0101 -> 1010 1001 0110 1001
-	test_h_gr32 0xa5a5a969 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotxr_w_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwind2
-	fail
-.Lwind2:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwpostinc2
-	fail
-.Lwpostinc2:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	rotxr.w	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwpostdec2
-	fail
-.Lwpostdec2:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotxr.w	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwpreinc2
-	fail
-.Lwpreinc2:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	rotxr.w	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwpredec2
-	fail
-.Lwpredec2:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	rotxr.w	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0156
-;;;	.word	0xa908
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwdisp22
-	fail
-.Lwdisp22:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	rotxr.w	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwdisp162
-	fail
-.Lwdisp162:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	rotxr.w	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwdisp322
-	fail
-.Lwdisp322:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	#2, @word_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwabs162
-	fail
-.Lwabs162:
-	mov	#0xa5a5a5a5, @word_dest
-
-rotxr_w_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.w	#2, @word_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1350
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1010 1001 0110 1001  
-	cmp.w	#0xa969, @word_dest
-	beq	.Lwabs322
-	fail
-.Lwabs322:
-	mov	#0xa5a5a5a5, @word_dest
-.endif
-
-rotxr_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	er0		; shift right arithmetic by one, register
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	test_h_gr32  0x52d2d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-rotxr_l_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x0104
-;;;	.word	0xa908
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llind1
-	fail
-.Llind1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpostinc1
-	fail
-.Llpostinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpostdec1
-	fail
-.Llpostdec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	rotxr.l	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpreinc1
-	fail
-.Llpreinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	rotxr.l	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpredec1
-	fail
-.Llpredec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	rotxr.l	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0106
-;;;	.word	0xa908
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp21
-	fail
-.Lldisp21:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	rotxr.l	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp161
-	fail
-.Lldisp161:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	rotxr.l	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp321
-	fail
-.Lldisp321:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	@long_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llabs161
-	fail
-.Llabs161:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	@long_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1330
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llabs321
-	fail
-.Llabs321:
-	mov	#0xa5a5a5a5, @long_dest
-.endif
-
-rotxr_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	#2, er0		; shift right arithmetic by two, register
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	test_h_gr32  0xa9696969 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-rotxr_l_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x0104
-;;;	.word	0xa908
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llind2
-	fail
-.Llind2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llpostinc2
-	fail
-.Llpostinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	rotxr.l	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llpostdec2
-	fail
-.Llpostdec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	rotxr.l	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llpreinc2
-	fail
-.Llpreinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	rotxr.l	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llpredec2
-	fail
-.Llpredec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	rotxr.l	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0106
-;;;	.word	0xa908
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Lldisp22
-	fail
-.Lldisp22:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	rotxr.l	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Lldisp162
-	fail
-.Lldisp162:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	rotxr.l	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Lldisp322
-	fail
-.Lldisp322:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	#2, @long_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llabs162
-	fail
-.Llabs162:
-	mov	#0xa5a5a5a5, @long_dest
-
-rotxr_l_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	rotxr.l	#2, @long_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1370
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xa9696969, @long_dest
-	beq	.Llabs322
-	fail
-.Llabs322:
-	mov	#0xa5a5a5a5, @long_dest
-	
-.endif
-.endif
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s
deleted file mode 100644
index ccea907..0000000
--- a/sim/testsuite/sim/h8300/shal.s
+++ /dev/null

@@ -1,167 +0,0 @@
-# Hitachi H8 testcase 'shal'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-shal_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.b	r0l		; shift left arithmetic by one
-;;;	.word	0x1088
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_clear
-	test_h_gr16 0xa54a r0	; 1010 0101 -> 0100 1010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a54a er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shal_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.b	#2, r0l		; shift left arithmetic by two
-;;; 	.word	0x10c8
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_set
-
-	test_h_gr16 0xa594 r0	; 1010 0101 -> 1001 0100
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a594 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu)			; Not available in h8300 mode
-shal_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.w	r0		; shift left arithmetic by one
-;;;	.word	0x1090
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_clear
-	test_h_gr16 0x4b4a r0	; 1010 0101 1010 0101 -> 0100 1011 0100 1010
-	test_h_gr32 0xa5a54b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shal_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.w	#2, r0		; shift left arithmetic by two
-;;;	.word	0x10d0
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_set
-	test_h_gr16 0x9694 r0	; 1010 0101 1010 0101 -> 1001 0110 1001 0100
-	test_h_gr32 0xa5a59694 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shal_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.l	er0		; shift left arithmetic by one
-;;;	.word	10b0
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1010
-	test_h_gr32 0x4b4b4b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shal_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shal.l	#2, er0		; shift left arithmetic by two
-;;;	.word	0x10f0
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-;	test_ovf_clear		; FIXME
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1001 0110 1001 0110 1001 0110 1001 0100
-	test_h_gr32 0x96969694 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.endif
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s
deleted file mode 100644
index b0ea673..0000000
--- a/sim/testsuite/sim/h8300/shar.s
+++ /dev/null

@@ -1,2000 +0,0 @@
-# Hitachi H8 testcase 'shar'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-shar_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	r0l		; shift right arithmetic by one
-;;;	.word	0x1188
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xa5d2 r0	; 1010 0101 -> 1101 0010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a5d2 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shar_b_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x7d00
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbind1
-	fail
-.Lbind1:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpostinc1
-	fail
-.Lbpostinc1:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpostdec1
-	fail
-.Lbpostdec1:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	shar.b	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpreinc1
-	fail
-.Lbpreinc1:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	shar.b	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbpredec1
-	fail
-.Lbpredec1:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	shar.b	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp21
-	fail
-.Lbdisp21:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	shar.b	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp161
-	fail
-.Lbdisp161:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	shar.b	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbdisp321
-	fail
-.Lbdisp321:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	@byte_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbabs161
-	fail
-.Lbabs161:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	@byte_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x1180
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1101 0010
-	cmp.b	#0xd2, @byte_dest
-	beq	.Lbabs321
-	fail
-.Lbabs321:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-shar_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	#2, r0l		; shift right arithmetic by two
-;;;	.word	0x11c8
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0xa5e9 r0	; 1010 0101 -> 1110 1001
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a5e9 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shar_b_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x7d00
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbind2
-	fail
-.Lbind2:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbpostinc2
-	fail
-.Lbpostinc2:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shar.b	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbpostdec2
-	fail
-.Lbpostdec2:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	shar.b	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbpreinc2
-	fail
-.Lbpreinc2:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	shar.b	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbpredec2
-	fail
-.Lbpredec2:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	shar.b	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbdisp22
-	fail
-.Lbdisp22:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	shar.b	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbdisp162
-	fail
-.Lbdisp162:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	shar.b	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbdisp322
-	fail
-.Lbdisp322:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	#2, @byte_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbabs162
-	fail
-.Lbabs162:
-	mov.b	#0xa5, @byte_dest
-
-shar_b_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.b	#2, @byte_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x11c0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 1110 1001
-	cmp.b	#0xe9, @byte_dest
-	beq	.Lbabs322
-	fail
-.Lbabs322:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-shar_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	r0		; shift right arithmetic by one
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0xd2d2 r0	; 1010 0101 1010 0101 -> 1101 0010 1101 0010
-	test_h_gr32 0xa5a5d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shar_w_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwind1
-	fail
-.Lwind1:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpostinc1
-	fail
-.Lwpostinc1:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpostdec1
-	fail
-.Lwpostdec1:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shar.w	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpreinc1
-	fail
-.Lwpreinc1:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shar.w	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwpredec1
-	fail
-.Lwpredec1:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shar.w	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp21
-	fail
-.Lwdisp21:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shar.w	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp161
-	fail
-.Lwdisp161:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shar.w	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwdisp321
-	fail
-.Lwdisp321:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	@word_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwabs161
-	fail
-.Lwabs161:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	@word_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1190
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1101 0010 1101 0010 
-	cmp.w	#0xd2d2, @word_dest
-	beq	.Lwabs321
-	fail
-.Lwabs321:
-	mov.w	#0xa5a5, @word_dest
-.endif
-	
-shar_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	#2, r0		; shift right arithmetic by two
-;;;	.word	0x11d0
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xe969 r0	; 1010 0101 1010 0101 -> 1110 1001 0110 1001
-	test_h_gr32 0xa5a5e969 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shar_w_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x7d80
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwind2
-	fail
-.Lwind2:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwpostinc2
-	fail
-.Lwpostinc2:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shar.w	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwpostdec2
-	fail
-.Lwpostdec2:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shar.w	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwpreinc2
-	fail
-.Lwpreinc2:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shar.w	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwpredec2
-	fail
-.Lwpredec2:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shar.w	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwdisp22
-	fail
-.Lwdisp22:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shar.w	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwdisp162
-	fail
-.Lwdisp162:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shar.w	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwdisp322
-	fail
-.Lwdisp322:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	#2, @word_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwabs162
-	fail
-.Lwabs162:
-	mov.w	#0xa5a5, @word_dest
-
-shar_w_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.w	#2, @word_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x11d0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 1110 1001 0110 1001  
-	cmp.w	#0xe969, @word_dest
-	beq	.Lwabs322
-	fail
-.Lwabs322:
-	mov.w	#0xa5a5, @word_dest
-.endif
-
-shar_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	er0		; shift right arithmetic by one, register
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	test_h_gr32  0xd2d2d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shar_l_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	@er0	; shift right arithmetic by one, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llind1
-	fail
-.Llind1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	@er0+	; shift right arithmetic by one, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpostinc1
-	fail
-.Llpostinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	@er0-	; shift right arithmetic by one, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpostdec1
-	fail
-.Llpostdec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shar.l	@+er0	; shift right arithmetic by one, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpreinc1
-	fail
-.Llpreinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shar.l	@-er0	; shift right arithmetic by one, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llpredec1
-	fail
-.Llpredec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shar.l	@(2:2, er0)	; shift right arithmetic by one, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp21
-	fail
-.Lldisp21:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shar.l	@(44:16, er0)	; shift right arithmetic by one, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp161
-	fail
-.Lldisp161:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shar.l	@(666:32, er0)	; shift right arithmetic by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Lldisp321
-	fail
-.Lldisp321:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	@long_dest:16	; shift right arithmetic by one, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llabs161
-	fail
-.Llabs161:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	@long_dest:32	; shift right arithmetic by one, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x11b0
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0xd2d2d2d2, @long_dest
-	beq	.Llabs321
-	fail
-.Llabs321:
-	mov	#0xa5a5a5a5, @long_dest
-.endif
-
-shar_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	#2, er0		; shift right arithmetic by two, register
-;;;	.word	0x11f0
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	test_h_gr32  0xe9696969 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-shar_l_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	#2, @er0	; shift right arithmetic by two, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llind2
-	fail
-.Llind2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	#2, @er0+	; shift right arithmetic by two, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llpostinc2
-	fail
-.Llpostinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shar.l	#2, @er0-	; shift right arithmetic by two, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llpostdec2
-	fail
-.Llpostdec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shar.l	#2, @+er0	; shift right arithmetic by two, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llpreinc2
-	fail
-.Llpreinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shar.l	#2, @-er0	; shift right arithmetic by two, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llpredec2
-	fail
-.Llpredec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shar.l	#2, @(2:2, er0)	; shift right arithmetic by two, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Lldisp22
-	fail
-.Lldisp22:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shar.l	#2, @(44:16, er0)	; shift right arithmetic by two, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Lldisp162
-	fail
-.Lldisp162:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shar.l	#2, @(666:32, er0)	; shift right arithmetic by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr32  long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Lldisp322
-	fail
-.Lldisp322:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	#2, @long_dest:16	; shift right arithmetic by two, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llabs162
-	fail
-.Llabs162:
-	mov	#0xa5a5a5a5, @long_dest
-
-shar_l_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shar.l	#2, @long_dest:32	; shift right arithmetic by two, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x11f0
-
-	test_carry_clear		; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1110 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0xe9696969, @long_dest
-	beq	.Llabs322
-	fail
-.Llabs322:
-	mov	#0xa5a5a5a5, @long_dest
-	
-.endif
-.endif
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s
deleted file mode 100644
index fcff565..0000000
--- a/sim/testsuite/sim/h8300/shll.s
+++ /dev/null

@@ -1,308 +0,0 @@
-# Hitachi H8 testcase 'shll'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-shll_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.b	r0l		; shift left logical by one
-;;;	.word	0x1008
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0xa54a r0	; 1010 0101 -> 0100 1010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a54a er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.b	#2, r0l		; shift left logical by two
-;;; 	.word	0x1048
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-
-	test_h_gr16 0xa594 r0	; 1010 0101 -> 1001 0100
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a594 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shll_b_reg8_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.b	#4, r0l		; shift left logical by four
-;;;	.word	0x10a8
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0xa550 r0	; 1010 0101 -> 0101 0000
-	test_h_gr32 0xa5a5a550 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-shll_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.w	r0		; shift left logical by one
-;;;	.word	0x1010
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0x4b4a r0	; 1010 0101 1010 0101 -> 0100 1011 0100 1010
-	test_h_gr32 0xa5a54b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.w	#2, r0		; shift left logical by two
-;;;	.word	0x1050
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0x9694 r0	; 1010 0101 1010 0101 -> 1001 0110 1001 0100
-	test_h_gr32 0xa5a59694 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shll_w_reg16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.w	#4, r0		; shift left logical by four
-;;;	.word	0x1020
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0x5a50 r0	; 1010 0101 1010 0101 -> 0101 1010 0101 0000
-	test_h_gr32 0xa5a55a50 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_w_reg16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.w	#8, r0		; shift left logical by eight
-;;;	.word	0x1060
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0xa500 r0	; 1010 0101 1010 0101 -> 1010 0101 0000 0000
-	test_h_gr32 0xa5a5a500 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-shll_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.l	er0		; shift left logical by one
-;;;	.word	1030
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0100 1011 0100 1011 0100 1011 0100 1010
-	test_h_gr32 0x4b4b4b4a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.l	#2, er0		; shift left logical by two
-;;;	.word	0x1070
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1001 0110 1001 0110 1001 0110 1001 0100
-	test_h_gr32 0x96969694 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shll_l_reg32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.l	#4, er0		; shift left logical by four
-;;;	.word	0x1038
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 0101 1010 0101 1010 0101 1010 0101 0000
-	test_h_gr32 0x5a5a5a50 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_l_reg32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.l	#8, er0		; shift left logical by eight
-;;;	.word	0x1078
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	test_h_gr16 0xa500 r0	
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 1010 0101 1010 0101 1010 0101 0000 0000
-	test_h_gr32 0xa5a5a500 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shll_l_reg32_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shll.l	#16, er0	; shift left logical by sixteen
-;;;	.word	0x10f8
-
-	test_carry_set		; H=0 N=1 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_set
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 1010 0101 1010 0101 0000 0000 0000 0000
-	test_h_gr32 0xa5a50000 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-.endif
-
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s
deleted file mode 100644
index 14b80da..0000000
--- a/sim/testsuite/sim/h8300/shlr.s
+++ /dev/null

@@ -1,4018 +0,0 @@
-# Hitachi H8 testcase 'shlr'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-	.data
-byte_dest:	.byte	0xa5
-	.align 2
-word_dest:	.word	0xa5a5
-	.align 4
-long_dest:	.long	0xa5a5a5a5
-
-	.text
-
-shlr_b_reg8_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	r0l		; shift right logical by one
-;;;	.word	0x1108
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0xa552 r0	; 1010 0101 -> 0101 0010
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a552 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shlr_b_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	@er0	; shift right logical by one, indirect
-;;;	.word	0x7d00
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbind1
-	fail
-.Lbind1:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	@er0+	; shift right logical by one, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpostinc1
-	fail
-.Lbpostinc1:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	@er0-	; shift right logical by one, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpostdec1
-	fail
-.Lbpostdec1:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	shlr.b	@+er0	; shift right logical by one, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpreinc1
-	fail
-.Lbpreinc1:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	shlr.b	@-er0	; shift right logical by one, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbpredec1
-	fail
-.Lbpredec1:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	shlr.b	@(2:2, er0)	; shift right logical by one, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp21
-	fail
-.Lbdisp21:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	shlr.b	@(44:16, er0)	; shift right logical by one, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp161
-	fail
-.Lbdisp161:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	shlr.b	@(666:32, er0)	; shift right logical by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbdisp321
-	fail
-.Lbdisp321:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	@byte_dest:16	; shift right logical by one, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbabs161
-	fail
-.Lbabs161:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	@byte_dest:32	; shift right logical by one, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x1100
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0101 0010
-	cmp.b	#0x52, @byte_dest
-	beq	.Lbabs321
-	fail
-.Lbabs321:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-shlr_b_reg8_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#2, r0l		; shift right logical by two
-;;;	.word	0x1148
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0xa529 r0	; 1010 0101 -> 0010 1001
-.if (sim_cpu)
-	test_h_gr32 0xa5a5a529 er0
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shlr_b_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#2, @er0	; shift right logical by two, indirect
-;;;	.word	0x7d00
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbind2
-	fail
-.Lbind2:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#2, @er0+	; shift right logical by two, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbpostinc2
-	fail
-.Lbpostinc2:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#2, @er0-	; shift right logical by two, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbpostdec2
-	fail
-.Lbpostdec2:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	shlr.b	#2, @+er0	; shift right logical by two, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbpreinc2
-	fail
-.Lbpreinc2:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	shlr.b	#2, @-er0	; shift right logical by two, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbpredec2
-	fail
-.Lbpredec2:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	shlr.b	#2, @(2:2, er0)	; shift right logical by two, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbdisp22
-	fail
-.Lbdisp22:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	shlr.b	#2, @(44:16, er0)	; shift right logical by two, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbdisp162
-	fail
-.Lbdisp162:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	shlr.b	#2, @(666:32, er0)	; shift right logical by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbdisp322
-	fail
-.Lbdisp322:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#2, @byte_dest:16	; shift right logical by two, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbabs162
-	fail
-.Lbabs162:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#2, @byte_dest:32	; shift right logical by two, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x1140
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0010 1001
-	cmp.b	#0x29, @byte_dest
-	beq	.Lbabs322
-	fail
-.Lbabs322:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_reg8_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#4, r0l		; shift right logical by four
-;;;	.word	0x11a8
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0xa50a r0	; 1010 0101 -> 0000 1010 
-	test_h_gr32 0xa5a5a50a er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_b_ind_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#4, @er0	; shift right logical by four, indirect
-;;;	.word	0x7d00
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbind4
-	fail
-.Lbind4:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#4, @er0+	; shift right logical by four, postinc
-;;;	.word	0x0174
-;;;	.word	0x6c08
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest+1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbpostinc4
-	fail
-.Lbpostinc4:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_postdec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest, er0
-	shlr.b	#4, @er0-	; shift right logical by four, postdec
-;;;	.word	0x0176
-;;;	.word	0x6c08
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-1 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbpostdec4
-	fail
-.Lbpostdec4:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_preinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-1, er0
-	shlr.b	#4, @+er0	; shift right logical by four, preinc
-;;;	.word	0x0175
-;;;	.word	0x6c08
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbpreinc4
-	fail
-.Lbpreinc4:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_predec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest+1, er0
-	shlr.b	#4, @-er0	; shift right logical by four, predec
-;;;	.word	0x0177
-;;;	.word	0x6c08
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbpredec4
-	fail
-.Lbpredec4:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp2_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-2, er0
-	shlr.b	#4, @(2:2, er0)	; shift right logical by four, disp2
-;;;	.word	0x0176
-;;;	.word	0x6808
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbdisp24
-	fail
-.Lbdisp24:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-44, er0
-	shlr.b	#4, @(44:16, er0)	; shift right logical by four, disp16
-;;;	.word	0x0174
-;;;	.word	0x6e08
-;;;	.word	44
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbdisp164
-	fail
-.Lbdisp164:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_disp32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#byte_dest-666, er0
-	shlr.b	#4, @(666:32, er0)	; shift right logical by four, disp32
-;;;	.word	0x7884
-;;;	.word	0x6a28
-;;; 	.long	666
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 byte_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbdisp324
-	fail
-.Lbdisp324:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#4, @byte_dest:16	; shift right logical by four, abs16
-;;;	.word	0x6a18
-;;;	.word	byte_dest
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbabs164
-	fail
-.Lbabs164:
-	mov.b	#0xa5, @byte_dest
-
-shlr_b_abs32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.b	#4, @byte_dest:32	; shift right logical by four, abs32
-;;;	.word	0x6a38
-;;; 	.long	byte_dest
-;;;	.word	0x11a0
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 -> 0000 1010 
-	cmp.b	#0x0a, @byte_dest
-	beq	.Lbabs324
-	fail
-.Lbabs324:
-	mov.b	#0xa5, @byte_dest
-.endif
-
-.if (sim_cpu == h8sx)
-shlr_w_imm5_1:	
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#15:5, r0	; shift right logical by 5-bit immediate
-;;;	.word	0x038f
-;;;	.word	0x1110
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	; 1010 0101 1010 0101 -> 0000 0000 0000 0001
-	test_h_gr32 0xa5a50001 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu)			; Not available in h8300 mode
-shlr_w_reg16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	r0		; shift right logical by one
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	test_h_gr16 0x52d2 r0	; 1010 0101 1010 0101 -> 0101 0010 1101 0010
-	test_h_gr32 0xa5a552d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shlr_w_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	@er0	; shift right logical by one, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwind1
-	fail
-.Lwind1:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	@er0+	; shift right logical by one, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpostinc1
-	fail
-.Lwpostinc1:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	@er0-	; shift right logical by one, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpostdec1
-	fail
-.Lwpostdec1:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	@+er0	; shift right logical by one, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpreinc1
-	fail
-.Lwpreinc1:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shlr.w	@-er0	; shift right logical by one, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwpredec1
-	fail
-.Lwpredec1:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	@(2:2, er0)	; shift right logical by one, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp21
-	fail
-.Lwdisp21:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shlr.w	@(44:16, er0)	; shift right logical by one, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp161
-	fail
-.Lwdisp161:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shlr.w	@(666:32, er0)	; shift right logical by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwdisp321
-	fail
-.Lwdisp321:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	@word_dest:16	; shift right logical by one, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwabs161
-	fail
-.Lwabs161:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	@word_dest:32	; shift right logical by one, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1110
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0101 0010 1101 0010 
-	cmp.w	#0x52d2, @word_dest
-	beq	.Lwabs321
-	fail
-.Lwabs321:
-	mov.w	#0xa5a5, @word_dest
-.endif
-	
-shlr_w_reg16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#2, r0		; shift right logical by two
-;;;	.word	0x1150
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0x2969 r0	; 1010 0101 1010 0101 -> 0010 1001 0110 1001
-	test_h_gr32 0xa5a52969 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shlr_w_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#2, @er0	; shift right logical by two, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwind2
-	fail
-.Lwind2:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#2, @er0+	; shift right logical by two, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwpostinc2
-	fail
-.Lwpostinc2:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#2, @er0-	; shift right logical by two, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwpostdec2
-	fail
-.Lwpostdec2:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#2, @+er0	; shift right logical by two, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwpreinc2
-	fail
-.Lwpreinc2:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shlr.w	#2, @-er0	; shift right logical by two, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwpredec2
-	fail
-.Lwpredec2:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#2, @(2:2, er0)	; shift right logical by two, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwdisp22
-	fail
-.Lwdisp22:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shlr.w	#2, @(44:16, er0)	; shift right logical by two, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwdisp162
-	fail
-.Lwdisp162:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shlr.w	#2, @(666:32, er0)	; shift right logical by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwdisp322
-	fail
-.Lwdisp322:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#2, @word_dest:16	; shift right logical by two, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwabs162
-	fail
-.Lwabs162:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#2, @word_dest:32	; shift right logical by two, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1150
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0010 1001 0110 1001  
-	cmp.w	#0x2969, @word_dest
-	beq	.Lwabs322
-	fail
-.Lwabs322:
-	mov.w	#0xa5a5, @word_dest
-	
-shlr_w_reg16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#4, r0		; shift right logical by four
-;;;	.word	0x1120
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0x0a5a r0	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	test_h_gr32 0xa5a50a5a er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_w_ind_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#4, @er0	; shift right logical by four, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwind4
-	fail
-.Lwind4:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#4, @er0+	; shift right logical by four, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwpostinc4
-	fail
-.Lwpostinc4:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postdec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#4, @er0-	; shift right logical by four, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwpostdec4
-	fail
-.Lwpostdec4:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_preinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#4, @+er0	; shift right logical by four, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwpreinc4
-	fail
-.Lwpreinc4:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_predec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shlr.w	#4, @-er0	; shift right logical by four, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwpredec4
-	fail
-.Lwpredec4:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp2_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#4, @(2:2, er0)	; shift right logical by four, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwdisp24
-	fail
-.Lwdisp24:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shlr.w	#4, @(44:16, er0)	; shift right logical by four, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwdisp164
-	fail
-.Lwdisp164:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shlr.w	#4, @(666:32, er0)	; shift right logical by four, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwdisp324
-	fail
-.Lwdisp324:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#4, @word_dest:16	; shift right logical by four, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwabs164
-	fail
-.Lwabs164:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#4, @word_dest:32	; shift right logical by four, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1120
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 1010 0101 1010 
-	cmp.w	#0x0a5a, @word_dest
-	beq	.Lwabs324
-	fail
-.Lwabs324:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_reg16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#8, r0		; shift right logical by eight
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr16 0x00a5 r0	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	test_h_gr32 0xa5a500a5 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_w_ind_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#8, @er0	; shift right logical by eight, indirect
-;;;	.word	0x7d80
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwind8
-	fail
-.Lwind8:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postinc_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#8, @er0+	; shift right logical by eight, postinc
-;;;	.word	0x0154
-;;;	.word	0x6d08
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest+2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwpostinc8
-	fail
-.Lwpostinc8:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_postdec_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest, er0
-	shlr.w	#8, @er0-	; shift right logical by eight, postdec
-;;;	.word	0x0156
-;;;	.word	0x6d08
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwpostdec8
-	fail
-.Lwpostdec8:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_preinc_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#8, @+er0	; shift right logical by eight, preinc
-;;;	.word	0x0155
-;;;	.word	0x6d08
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwpreinc8
-	fail
-.Lwpreinc8:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_predec_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest+2, er0
-	shlr.w	#8, @-er0	; shift right logical by eight, predec
-;;;	.word	0x0157
-;;;	.word	0x6d08
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwpredec8
-	fail
-.Lwpredec8:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp2_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-2, er0
-	shlr.w	#8, @(2:2, er0)	; shift right logical by eight, disp2
-;;;	.word	0x0156
-;;;	.word	0x6908
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwdisp28
-	fail
-.Lwdisp28:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-44, er0
-	shlr.w	#8, @(44:16, er0)	; shift right logical by eight, disp16
-;;;	.word	0x0154
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwdisp168
-	fail
-.Lwdisp168:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_disp32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#word_dest-666, er0
-	shlr.w	#8, @(666:32, er0)	; shift right logical by eight, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 word_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwdisp328
-	fail
-.Lwdisp328:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#8, @word_dest:16	; shift right logical by eight, abs16
-;;;	.word	0x6b18
-;;;	.word	word_dest
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwabs168
-	fail
-.Lwabs168:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_w_abs32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.w	#8, @word_dest:32	; shift right logical by eight, abs32
-;;;	.word	0x6b38
-;;; 	.long	word_dest
-;;;	.word	0x1160
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 -> 0000 0000 1010 0101 
-	cmp.w	#0x00a5, @word_dest
-	beq	.Lwabs328
-	fail
-.Lwabs328:
-	mov.w	#0xa5a5, @word_dest
-
-shlr_l_imm5_1:	
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#31:5, er0	; shift right logical by 5-bit immediate
-;;;	.word	0x0399
-;;;	.word	0x1130
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0000 0000 0000 0000 0000 0000 0000 0001
-	test_h_gr32 0x1 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-shlr_l_reg32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	er0		; shift right logical by one, register
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	; 1010 0101 1010 0101 1010 0101 1010 0101 
-	; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	test_h_gr32 0x52d2d2d2 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-shlr_l_ind_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	@er0	; shift right logical by one, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llind1
-	fail
-.Llind1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	@er0+	; shift right logical by one, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpostinc1
-	fail
-.Llpostinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postdec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	@er0-	; shift right logical by one, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpostdec1
-	fail
-.Llpostdec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_preinc_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shlr.l	@+er0	; shift right logical by one, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpreinc1
-	fail
-.Llpreinc1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_predec_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shlr.l	@-er0	; shift right logical by one, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llpredec1
-	fail
-.Llpredec1:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp2_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shlr.l	@(2:2, er0)	; shift right logical by one, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp21
-	fail
-.Lldisp21:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shlr.l	@(44:16, er0)	; shift right logical by one, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp161
-	fail
-.Lldisp161:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shlr.l	@(666:32, er0)	; shift right logical by one, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Lldisp321
-	fail
-.Lldisp321:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs16_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	@long_dest:16	; shift right logical by one, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llabs161
-	fail
-.Llabs161:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs32_1:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	@long_dest:32	; shift right logical by one, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1130
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0101 0010 1101 0010 1101 0010 1101 0010
-	cmp.l	#0x52d2d2d2, @long_dest
-	beq	.Llabs321
-	fail
-.Llabs321:
-	mov	#0xa5a5a5a5, @long_dest
-.endif
-
-shlr_l_reg32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#2, er0		; shift right logical by two, register
-;;;	.word	0x1170
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	test_h_gr32 0x29696969 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-
-shlr_l_ind_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#2, @er0	; shift right logical by two, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llind2
-	fail
-.Llind2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#2, @er0+	; shift right logical by two, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llpostinc2
-	fail
-.Llpostinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postdec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#2, @er0-	; shift right logical by two, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llpostdec2
-	fail
-.Llpostdec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_preinc_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shlr.l	#2, @+er0	; shift right logical by two, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llpreinc2
-	fail
-.Llpreinc2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_predec_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shlr.l	#2, @-er0	; shift right logical by two, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llpredec2
-	fail
-.Llpredec2:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp2_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shlr.l	#2, @(2:2, er0)	; shift right logical by two, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Lldisp22
-	fail
-.Lldisp22:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shlr.l	#2, @(44:16, er0)	; shift right logical by two, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Lldisp162
-	fail
-.Lldisp162:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shlr.l	#2, @(666:32, er0)	; shift right logical by two, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Lldisp322
-	fail
-.Lldisp322:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs16_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#2, @long_dest:16	; shift right logical by two, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llabs162
-	fail
-.Llabs162:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs32_2:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#2, @long_dest:32	; shift right logical by two, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1170
-
-	test_carry_clear		; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0010 1001 0110 1001 0110 1001 0110 1001
-	cmp.l	#0x29696969, @long_dest
-	beq	.Llabs322
-	fail
-.Llabs322:
-	mov	#0xa5a5a5a5, @long_dest
-	
-shlr_l_reg32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#4, er0		; shift right logical by four, register
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 0000 1010 0101 1010 0101 1010 0101 1010 
-	test_h_gr32 0x0a5a5a5a er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_l_ind_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#4, @er0	; shift right logical by four, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llind4
-	fail
-.Llind4:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#4, @er0+	; shift right logical by four, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llpostinc4
-	fail
-.Llpostinc4:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postdec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#4, @er0-	; shift right logical by four, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llpostdec4
-	fail
-.Llpostdec4:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_preinc_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shlr.l	#4, @+er0	; shift right logical by four, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llpreinc4
-	fail
-.Llpreinc4:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_predec_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shlr.l	#4, @-er0	; shift right logical by four, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llpredec4
-	fail
-.Llpredec4:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp2_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shlr.l	#4, @(2:2, er0)	; shift right logical by four, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Lldisp24
-	fail
-.Lldisp24:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shlr.l	#4, @(44:16, er0)	; shift right logical by four, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Lldisp164
-	fail
-.Lldisp164:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shlr.l	#4, @(666:32, er0)	; shift right logical by four, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Lldisp324
-	fail
-.Lldisp324:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs16_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#4, @long_dest:16	; shift right logical by four, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llabs164
-	fail
-.Llabs164:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs32_4:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#4, @long_dest:32	; shift right logical by four, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1138
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 1010 0101 1010 0101 1010 0101 1010
-	cmp.l	#0x0a5a5a5a, @long_dest
-	beq	.Llabs324
-	fail
-.Llabs324:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_reg32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#8, er0		; shift right logical by eight, register
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	; -> 0000 0000 1010 0101 1010 0101 1010 0101 
-	test_h_gr32 0x00a5a5a5 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_l_ind_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#8, @er0	; shift right logical by eight, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llind8
-	fail
-.Llind8:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postinc_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#8, @er0+	; shift right logical by eight, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llpostinc8
-	fail
-.Llpostinc8:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postdec_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#8, @er0-	; shift right logical by eight, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llpostdec8
-	fail
-.Llpostdec8:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_preinc_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shlr.l	#8, @+er0	; shift right logical by eight, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llpreinc8
-	fail
-.Llpreinc8:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_predec_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shlr.l	#8, @-er0	; shift right logical by eight, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llpredec8
-	fail
-.Llpredec8:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp2_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shlr.l	#8, @(2:2, er0)	; shift right logical by eight, disp2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Lldisp28
-	fail
-.Lldisp28:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shlr.l	#8, @(44:16, er0)	; shift right logical by eight, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Lldisp168
-	fail
-.Lldisp168:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shlr.l	#8, @(666:32, er0)	; shift right logical by eight, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Lldisp328
-	fail
-.Lldisp328:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs16_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#8, @long_dest:16	; shift right logical by eight, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llabs168
-	fail
-.Llabs168:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs32_8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#8, @long_dest:32	; shift right logical by eight, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x1178
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 1010 0101 1010 0101 1010 0101
-	cmp.l	#0x00a5a5a5, @long_dest
-	beq	.Llabs328
-	fail
-.Llabs328:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_reg32_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#16, er0	; shift right logical by sixteen, register
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	test_h_gr32 0x0000a5a5 er0
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-shlr_l_ind_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#16, @er0	; shift right logical by sixteen, indirect
-;;;	.word	0x0104
-;;;	.word	0x6908
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llind16
-	fail
-.Llind16:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postinc_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#16, @er0+	; shift right logical by sixteen, postinc
-;;;	.word	0x0104
-;;;	.word	0x6d08
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest+4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llpostinc16
-	fail
-.Llpostinc16:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_postdec_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest, er0
-	shlr.l	#16, @er0-	; shift right logical by sixteen, postdec
-;;;	.word	0x0106
-;;;	.word	0x6d08
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-4 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llpostdec16
-	fail
-.Llpostdec16:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_preinc_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-4, er0
-	shlr.l	#16, @+er0	; shift right logical by sixteen, preinc
-;;;	.word	0x0105
-;;;	.word	0x6d08
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llpreinc16
-	fail
-.Llpreinc16:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_predec_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest+4, er0
-	shlr.l	#16, @-er0	; shift right logical by sixteen, predec
-;;;	.word	0x0107
-;;;	.word	0x6d08
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llpredec16
-	fail
-.Llpredec16:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp2_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-2, er0
-	shlr.l	#16, @(2:2, er0)	; shift right logical by 16, dest2
-;;;	.word	0x0106
-;;;	.word	0x6908
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-2 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Lldisp216
-	fail
-.Lldisp216:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp16_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-44, er0
-	shlr.l	#16, @(44:16, er0)	; shift right logical by 16, disp16
-;;;	.word	0x0104
-;;;	.word	0x6f08
-;;;	.word	44
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-44 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Lldisp1616
-	fail
-.Lldisp1616:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_disp32_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	mov	#long_dest-666, er0
-	shlr.l	#16, @(666:32, er0)	; shift right logical by 16, disp32
-;;;	.word	0x7884
-;;;	.word	0x6b28
-;;; 	.long	666
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_h_gr32 long_dest-666 er0
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Lldisp3216
-	fail
-.Lldisp3216:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs16_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#16, @long_dest:16	; shift right logical by 16, abs16
-;;;	.word	0x0104
-;;;	.word	0x6b08
-;;;	.word	long_dest
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llabs1616
-	fail
-.Llabs1616:
-	mov	#0xa5a5a5a5, @long_dest
-
-shlr_l_abs32_16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	shlr.l	#16, @long_dest:32	; shift right logical by 16, abs32
-;;;	.word	0x0104
-;;;	.word	0x6b28
-;;; 	.long	long_dest
-;;;	.word	0x11f8
-
-	test_carry_set		; H=0 N=0 Z=0 V=0 C=1
-	test_zero_clear
-	test_ovf_clear
-	test_neg_clear
-
-	test_gr_a5a5 0		; Make sure ALL general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	; 1010 0101 1010 0101 1010 0101 1010 0101
-	;; -> 0000 0000 0000 0000 1010 0101 1010 0101
-	cmp.l	#0x0000a5a5, @long_dest
-	beq	.Llabs3216
-	fail
-.Llabs3216:
-	mov	#0xa5a5a5a5, @long_dest
-.endif
-.endif
-	pass
-
-	exit 0
-

diff --git a/sim/testsuite/sim/h8300/stc.s b/sim/testsuite/sim/h8300/stc.s
deleted file mode 100644
index cbbd824..0000000
--- a/sim/testsuite/sim/h8300/stc.s
+++ /dev/null

@@ -1,389 +0,0 @@
-# Hitachi H8 testcase 'stc'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-	.data
-byte_dest1:
-	.byte	0
-byte_dest2:
-	.byte	0
-byte_dest3:
-	.byte	0
-byte_dest4:
-	.byte	0
-byte_dest5:
-	.byte	0
-byte_dest6:
-	.byte	0
-byte_dest7:
-	.byte	0
-byte_dest8:
-	.byte	0
-byte_dest9:
-	.byte	0
-byte_dest10:
-	.byte	0
-byte_dest11:
-	.byte	0
-byte_dest12:
-	.byte	0
-	
-	start
-
-stc_ccr_reg8:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0xff, ccr	; test value
-	stc	ccr, r0h	; copy test value to r0h
-
-	test_h_gr16  0xffa5 r0	; ff in r0h, a5 in r0l
-.if (sim_cpu)			; h/s/sx
-	test_h_gr32  0xa5a5ffa5 er0	; ff in r0h, a5 everywhere else
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8300s || sim_cpu == h8sx)	; Earlier versions, no exr
-stc_exr_reg8:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0x87, exr	; set exr to 0x87
-	stc	exr, r0l	; retrieve and check exr value
-	cmp.b	#0x87, r0l
-	beq	.L21
-	fail
-.L21:
-	test_h_gr32  0xa5a5a587 er0	; Register 0 modified by test procedure.
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_ccr_abs16:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0xff, ccr
-	stc	ccr, @byte_dest1:16	; abs16 dest
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_exr_abs16:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0x87, exr
-	stc	exr, @byte_dest2:16	; abs16 dest
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_ccr_abs32:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0xff, ccr
-	stc	ccr, @byte_dest3:32	; abs32 dest
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_exr_abs32:
-	set_grs_a5a5
-	set_ccr_zero
-
-	ldc	#0x87, exr
-	stc	exr, @byte_dest4:32	; abs32 dest
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_ccr_disp16:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest4, er1
-	ldc	#0xff, ccr
-	stc	ccr, @(1:16,er1)	; disp16 dest (5)
-
-	test_h_gr32 byte_dest4, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_exr_disp16:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest7, er1
-	ldc	#0x87, exr
-	stc	exr, @(-1:16,er1)	; disp16 dest (6)
-
-	test_h_gr32 byte_dest7, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_ccr_disp32:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest6, er1
-	ldc	#0xff, ccr
-	stc	ccr, @(1:32,er1)	; disp32 dest (7)
-
-	test_h_gr32 byte_dest6, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_exr_disp32:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest9, er1
-	ldc	#0x87, exr
-	stc	exr, @(-1:32,er1)	; disp16 dest (8)
-
-	test_h_gr32 byte_dest9, er1	; er1 still contains address
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_ccr_predecr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest10, er1
-	ldc	#0xff, ccr
-	stc	ccr, @-er1	; predecr dest (9)
-
-	test_h_gr32 byte_dest9, er1	; er1 still contains address 
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-stc_exr_predecr:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest11, er1
-	ldc	#0x87, exr
-	stc	exr, @-er1	; predecr dest (10)
-
-	test_h_gr32 byte_dest10, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-stc_ccr_ind:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest11, er1
-	ldc	#0xff, ccr
-	stc	ccr, @er1	; postinc dest (11)
-
-	test_h_gr32 byte_dest11, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-stc_exr_ind:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#byte_dest12, er1
-	ldc	#0x87, exr
-	stc	exr, @er1, exr	; postinc dest (12)
-
-	test_h_gr32 byte_dest12, er1	; er1 still contains address
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-	
-.if (sim_cpu == h8sx)		; New vbr and sbr registers for h8sx
-stc_sbr_reg:
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#0xaaaaaaaa, er0
-	ldc	er0, sbr	; set sbr to 0xaaaaaaaa
- 	stc	sbr, er1	; retreive and check sbr value
-
-	test_h_gr32 0xaaaaaaaa er1
-	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-stc_vbr_reg:	
-	set_grs_a5a5
-	set_ccr_zero
-
-	mov	#0xaaaaaaaa, er0
-	ldc	er0, vbr	; set sbr to 0xaaaaaaaa
-	stc	vbr, er1	; retreive and check sbr value
-
-	test_h_gr32 0xaaaaaaaa er1
-	test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-check_results:
-	;; Now check results
-	mov @byte_dest1, r0h
-	cmp.b	#0xff, r0h
-	beq .L1
-	fail
-
-.L1:	mov @byte_dest2, r0h
-	cmp.b	#0x87, r0h
-	beq .L2
-	fail
-
-.L2:	mov @byte_dest3, r0h
-	cmp.b	#0xff, r0h
-	beq .L3
-	fail
-
-.L3:	mov @byte_dest4, r0h
-	cmp.b	#0x87, r0h
-	beq .L4
-	fail
-
-.L4:	mov @byte_dest5, r0h
-	cmp.b	#0xff, r0h
-	beq .L5
-	fail
-
-.L5:	mov @byte_dest6, r0h
-	cmp.b	#0x87, r0h
-	beq .L6
-	fail
-
-.L6:	mov @byte_dest7, r0h
-	cmp.b	#0xff, r0h
-	beq .L7
-	fail
-
-.L7:	mov @byte_dest8, r0h
-	cmp.b	#0x87, r0h
-	beq .L8
-	fail
-
-.L8:	mov @byte_dest9, r0h
-	cmp.b	#0xff, r0h
-	beq .L9
-	fail
-
-.L9:	mov @byte_dest10, r0h
-	cmp.b	#0x87, r0h
-	beq .L10
-	fail
-
-.L10:	mov @byte_dest11, r0h
-	cmp.b	#0xff, r0h
-	beq .L11
-	fail
-
-.L11:	mov @byte_dest12, r0h
-	cmp.b	#0x87, r0h
-	beq .L12
-	fail
-
-.L12:	
-.endif
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/sub.b.s b/sim/testsuite/sim/h8300/sub.b.s
deleted file mode 100644
index 0183294..0000000
--- a/sim/testsuite/sim/h8300/sub.b.s
+++ /dev/null

@@ -1,289 +0,0 @@
-# Hitachi H8 testcase 'sub.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# sub.b #xx:8, rd	; <illegal>
-	# sub.b #xx:8, @erd	;         7 d rd ???? a ???? xxxxxxxx
-	# sub.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
-	# sub.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
-	# sub.b rs, rd		;                     1 8 rs rd
-	# sub.b reg8, @erd	;         7 d rd ???? 1 8 rs ????
-	# sub.b reg8, @erd+	;         0 1 7     9 8 rd 3 rs
-	# sub.b reg8, @erd-	;         0 1 7     9 a rd 3 rs
-	#
-
-	# Coming soon:
-	# sub.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
-	# sub.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
-	# sub.b reg8, @+erd	;         0 1 7     9 9 rd 3 rs
-	# sub.b reg8, @-erd	;         0 1 7     9 b rd 3 rs
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0xa5
-post_byte:	.byte 0
-
-	start
-	
-.if (0)				; Guess what?  Sub.b immediate reg8 is illegal!
-sub_b_imm8_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.b #xx:8,Rd
-	sub.b	#5, r0l		; Immediate 8-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa5a0 r0	; sub result:	a5 - 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a5a0 er0	; sub result:	 a5 - 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-.if (sim_cpu == h8sx)
-sub_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	sub.b	#5:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0xa105
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 byte_dest, er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa0, r0l
-	beq	.L1
-	fail
-.L1:
-
-sub_b_imm8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	sub.b	#5:8, @er0+	; Immediate 8-bit src, reg post-incr dest
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xa105
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 post_byte, er0	; er0 still contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x9b, r0l
-	beq	.L2
-	fail
-.L2:
-
-sub_b_imm8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	sub.b	#5:8, @er0-	; Immediate 8-bit src, reg post-decr dest
-;;; 	.word	0x0176
-;;; 	.word	0x6c08
-;;; 	.word	0xa105
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 pre_byte, er0	; er0 still contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x96, r0l
-	beq	.L3
-	fail
-.L3:
-
-.endif
-
-sub_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.b Rs,Rd
-	mov.b	#5, r0h
-	sub.b	r0h, r0l	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0x05a0 r0	; sub result:	a5 - 5
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a505a0 er0	; sub result:	a5 - 5
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-.if (sim_cpu == h8sx)
-sub_b_reg8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b rs8,@eRd	; Subx to register indirect
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	sub.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x1890
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x91, r0l
-	beq	.L4
-	fail
-.L4:
-
-sub_b_reg8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b rs8,@eRd+	; Subx to register indirect
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	sub.b	r1l, @er0+	; reg8 src, reg indirect dest
-;;; 	.word	0x0179
-;;; 	.word	0x8039
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 post_byte er0	; er0 still contains address plus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x8c, r0l
-	beq	.L5
-	fail
-.L5:
-
-sub_b_reg8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  sub.b rs8,@eRd-	; Subx to register indirect
-	mov	#byte_dest, er0
-	mov	#5, r1l
-	sub.b	r1l, @er0-	; reg8 src, reg indirect dest
-;;; 	.word	0x0179
-;;; 	.word	0xa039
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 pre_byte er0	; er0 still contains address minus one
-	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the sub to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x87, r0l
-	beq	.L6
-	fail
-.L6:
-
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/sub.l.s b/sim/testsuite/sim/h8300/sub.l.s
deleted file mode 100644
index 7f62f11..0000000
--- a/sim/testsuite/sim/h8300/sub.l.s
+++ /dev/null

@@ -1,91 +0,0 @@
-# Hitachi H8 testcase 'sub.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-
-.if (sim_cpu == h8sx)		; 
-sub_l_imm3:			; 3-bit immediate mode only for h8sx
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.l #xx:3,eRd	; Immediate 3-bit operand
-	sub.l	#7:3, er0
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0xa5a5a59e er0	; sub result:	a5a5 - 7
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-sub_l_imm16:			; sub immediate 16-bit value
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.l #xx:16,eRd	; Immediate 16-bit operand
-	sub.l	#0x1111:16, er0
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0x9494 r0	; sub result:	a5a5 - 1111
-	test_h_gr32 0xa5a59494 er0	; sub result:	a5a5 - 1111
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-	
-sub_l_imm32:
-	;; sub.l immediate not available in h8300 mode.
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.l #xx:32,Rd
-	sub.l	#0x11111111, er0	; Immediate 32-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0x94949494 er0	; sub result:	a5a5a5a5 - 11111111
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-sub.l.reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  add.l Rs,Rd
-	mov.l	#0x11111111, er1
-	sub.l	er1, er0	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr32 0x94949494 er0	; sub result:	a5a5a5a5 - 11111111
-	test_h_gr32 0x11111111 er1
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/sub.w.s b/sim/testsuite/sim/h8300/sub.w.s
deleted file mode 100644
index 2370250..0000000
--- a/sim/testsuite/sim/h8300/sub.w.s
+++ /dev/null

@@ -1,78 +0,0 @@
-# Hitachi H8 testcase 'sub.w'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-.if (sim_cpu == h8sx)		; 3-bit immediate mode only for h8sx
-sub_w_imm3:			; sub.w immediate not available in h8300 mode. 
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.w #xx:3,Rd	; Immediate 3-bit operand
-	sub.w	#7:3, r0
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa59e r0	; sub result:	a5a5 - 7
-	test_h_gr32 0xa5a5a59e er0	; sub result:	a5a5 - 7
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-	
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-sub_w_imm16:			; sub.w immediate not available in h8300 mode. 
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.w #xx:16,Rd
-	sub.w	#0x111, r0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa494 r0	; sub result:	a5a5 - 111
-	test_h_gr32 0xa5a5a494 er0	; sub result:	a5a5 - 111
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-	
-sub.w.reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  sub.w Rs,Rd
-	mov.w	#0x111, r1
-	sub.w	r1, r0		; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa494 r0	; sub result:	a5a5 - 111
-	test_h_gr16 0x0111 r1
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a494 er0	; sub result:	a5a5 - 111
-	test_h_gr32 0xa5a50111 er1
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/testutils.inc b/sim/testsuite/sim/h8300/testutils.inc
deleted file mode 100644
index fb8bdca..0000000
--- a/sim/testsuite/sim/h8300/testutils.inc
+++ /dev/null

@@ -1,341 +0,0 @@
-# Support macros for the Hitachi H8 assembly test cases.
-
-; Set up a minimal machine state
-	.macro start
-	.equ	h8300,  0
-	.equ	h8300h, 1
-	.equ	h8300s, 2
-	.equ	h8sx,   3
-	.if (sim_cpu == h8300s)
-	.h8300s
-	.else
-	.if (sim_cpu == h8300h)
-	.h8300h
-	.else
-	.if (sim_cpu == h8sx)
-	.h8300sx
-	.endif
-	.endif
-	.endif
-
-	.text
-	.align 2
-	.global _start
-_start:
-	jmp	_main
-
-	.data
-	.align 2
-	.global pass_str
-	.global fail_str
-	.global ok_str
-	.global pass_loc
-	.global fail_loc
-	.global ok_loc
-pass_str:
-	.ascii "pass\n"
-fail_str:
-	.ascii "fail\n"
-ok_str:
-	.ascii "ok\n"
-pass_loc16:
-	.word pass_str
-pass_loc32:
-	.long pass_str
-fail_loc16:
-	.word fail_str
-fail_loc32:
-	.long fail_str
-ok_loc16:
-	.word ok_str
-ok_loc32:
-	.long ok_str
-	.text
-
-	.global _write_and_exit
-_write_and_exit:
-;ssize_t write(int fd, const void *buf, size_t count);
-;Integer arguments have to be zero extended.
-.if (sim_cpu)
-#if __INT_MAX__ == 32767
-	extu.l  er0
-#endif
-.endif
-	jsr	@@0xc7
-	mov	#0, r0
-	jmp 	_exit
-
-	.global _exit
-_exit:
-	mov.b	r0l, r0h
-	mov.w	#0xdead, r1
-	mov.w	#0xbeef, r2
-	sleep
-
-	.global _main
-_main:
-	.endm
-
-
-; Exit with an exit code
-	.macro exit code
-	mov.w	#\code, r0
-	jmp	_exit
-	.endm
-
-; Output "pass\n"
-	.macro pass
-	mov.w	#0, r0		; fd == stdout
-.if (sim_cpu == h8300)
-	mov.w	#pass_str, r1	; buf == "pass\n"
-	mov.w	#5, r2		; len == 5
-.else
-	mov.l	#pass_str, er1	; buf == "pass\n"
-	mov.l	#5, er2		; len == 5
-.endif
-	jmp	_write_and_exit
-	.endm
-
-; Output "fail\n"
-	.macro fail
-	mov.w	#0, r0		; fd == stdout
-.if (sim_cpu == h8300)
-	mov.w	#fail_str, r1	; buf == "fail\n"
-	mov.w	#5, r2		; len == 5
-.else
-	mov.l	#fail_str, er1	; buf == "fail\n"
-	mov.l	#5, er2		; len == 5
-.endif
-	jmp	_write_and_exit
-	.endm
-
-
-; Load an 8-bit immediate value into a general register
-; (reg must be r0l - r7l or r0h - r7h)
-	.macro mvi_h_gr8 val reg
-	mov.b	#\val, \reg
-	.endm
-
-; Load a 16-bit immediate value into a general register
-; (reg must be r0 - r7)
-	.macro mvi_h_gr16 val reg
-	mov.w	#\val, \reg
-	.endm
-
-; Load a 32-bit immediate value into a general register
-; (reg must be er0 - er7)
-	.macro mvi_h_gr32 val reg
-	mov.l	#\val, \reg
-	.endm
-
-; Test the value of an 8-bit immediate against a general register
-; (reg must be r0l - r7l or r0h - r7h)
-	.macro test_h_gr8 val reg
-	cmp.b	#\val, \reg
-	beq	.Ltest_gr8\@
-	fail
-.Ltest_gr8\@:
-	.endm
-
-; Test the value of a 16-bit immediate against a general register
-; (reg must be r0 - r7)
-	.macro test_h_gr16 val reg h=h l=l
-	.if (sim_cpu == h8300)
-	test_h_gr8 (\val >> 8) \reg\h
-	test_h_gr8 (\val & 0xff) \reg\l
-	.else
-	cmp.w	#\val, \reg
-	beq	.Ltest_gr16\@
-	fail
-.Ltest_gr16\@:
-	.endif
-	.endm
-
-; Test the value of a 32-bit immediate against a general register
-; (reg must be er0 - er7)
-	.macro test_h_gr32 val reg
-	cmp.l	#\val, \reg
-	beq	.Ltest_gr32\@
-	fail
-.Ltest_gr32\@:
-	.endm
-
-; Set a general register to the fixed pattern 'a5a5a5a5'
-	.macro set_gr_a5a5 reg
-	.if (sim_cpu == 0)
-	; h8300
-	mov.w	#0xa5a5, r\reg
-	.else
-	mov.l	#0xa5a5a5a5, er\reg
-	.endif
-	.endm
-
-; Set all general registers to the fixed pattern 'a5a5a5a5'
-	.macro set_grs_a5a5
-	.if (sim_cpu == 0)
-	; h8300
-	mov.w	#0xa5a5, r0
-	mov.w	#0xa5a5, r1
-	mov.w	#0xa5a5, r2
-	mov.w	#0xa5a5, r3
-	mov.w	#0xa5a5, r4
-	mov.w	#0xa5a5, r5
-	mov.w	#0xa5a5, r6
-	mov.w	#0xa5a5, r7
-	.else
-	mov.l	#0xa5a5a5a5, er0
-	mov.l	#0xa5a5a5a5, er1
-	mov.l	#0xa5a5a5a5, er2
-	mov.l	#0xa5a5a5a5, er3
-	mov.l	#0xa5a5a5a5, er4
-	mov.l	#0xa5a5a5a5, er5
-	mov.l	#0xa5a5a5a5, er6
-	mov.l	#0xa5a5a5a5, er7
-	.endif
-	.endm
-
-; Test that a general register contains the fixed pattern 'a5a5a5a5'
-	.macro test_gr_a5a5 reg
-	.if (sim_cpu == 0)
-	; h8300
-	test_h_gr16 0xa5a5 r\reg
-	.else
-	test_h_gr32 0xa5a5a5a5 er\reg
-	.endif
-	.endm
-
-; Test that all general regs contain the fixed pattern 'a5a5a5a5'
-	.macro test_grs_a5a5
-	test_gr_a5a5 0
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	.endm
-
-; Set condition code register to an explicit value
-	.macro set_ccr val
-	ldc	#\val, ccr
-	.endm
-
-; Set all condition code flags to zero
-	.macro set_ccr_zero
-	ldc	#0, ccr
-	.endm
-
-; Set carry flag to value
-	.macro set_carry_flag val
-	.data
-scf\@:	.byte	0
-	.text
-	mov.b	r0l, @scf\@
-	mov.b	#\val:8, r0l
-	or.b	r0l, r0l
-	beq	.Lccf\@		; clear
-	stc	ccr, r0l	; set
-	or.b	#0x1, r0l
-	jmp	.Lecf\@
-.Lccf\@:			; clear
-	stc	ccr, r0l
-	and.b	#0xfe, r0l
-.Lecf\@:
-	ldc	r0l, ccr
-	mov	@scf\@, r0l
-	.endm
-
-; Test that carry flag is clear
-	.macro test_carry_clear
-	bcc	.Lcc\@
-	fail	; carry flag not clear
-.Lcc\@:
-	.endm
-
-; Test that carry flag is set
-	.macro test_carry_set
-	bcs	.Lcs\@
-	fail	; carry flag not clear
-.Lcs\@:
-	.endm
-
-; Test that overflow flag is clear
-	.macro test_ovf_clear
-	bvc	.Lvc\@
-	fail	; overflow flag not clear
-.Lvc\@:
-	.endm
-
-; Test that overflow flag is set
-	.macro test_ovf_set
-	bvs	.Lvs\@
-	fail	; overflow flag not clear
-.Lvs\@:
-	.endm
-
-; Test that zero flag is clear
-	.macro test_zero_clear
-	bne	.Lne\@
-	fail	; zero flag not clear
-.Lne\@:
-	.endm
-
-; Test that zero flag is set
-	.macro test_zero_set
-	beq	.Leq\@
-	fail	; zero flag not clear
-.Leq\@:
-	.endm
-
-; Test that neg flag is clear
-	.macro test_neg_clear
-	bpl	.Lneg\@
-	fail	; negative flag not clear
-.Lneg\@:
-	.endm
-
-; Test that neg flag is set
-	.macro test_neg_set
-	bmi	.Lneg\@
-	fail	; negative flag not clear
-.Lneg\@:
-	.endm
-
-; Test ccr against an explicit value
-	.macro test_ccr val
-	.data
-tccr\@:	.byte	0
-	.text
-	mov.b	r0l, @tccr\@
-	stc	ccr, r0l
-	cmp.b	#\val, r0l
-	bne .Ltcc\@
-	fail
-.Ltcc\@:
-	mov.b	@tccr\@, r0l
-	.endm
-
-; Test that all (accessable) condition codes are clear
-	.macro test_cc_clear
-	test_carry_clear
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-		; leaves H, I, U, and UI untested
-	.endm
-
-; Compare memory, fail if not equal (h8sx only, len > 0).
-	.macro memcmp src dst len
-	mov.l	#\src, er5
-	mov.l	#\dst, er6
-	mov.l	#\len, er4
-.Lmemcmp_\@:
-	cmp.b	@er5+, @er6+
-	beq	.Lmemcmp2_\@
-	fail
-.Lmemcmp2_\@:
-	dec.l	#1, er4
-	bne	.Lmemcmp_\@
-	.endm
-

diff --git a/sim/testsuite/sim/h8300/xor.b.s b/sim/testsuite/sim/h8300/xor.b.s
deleted file mode 100644
index 7005a95..0000000
--- a/sim/testsuite/sim/h8300/xor.b.s
+++ /dev/null

@@ -1,327 +0,0 @@
-# Hitachi H8 testcase 'xor.b'
-# mach(): all
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf	
-# ld(h8300s):	-m h8300self	
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	# Instructions tested:
-	# xor.b #xx:8, rd	;                     d rd   xxxxxxxx
-	# xor.b #xx:8, @erd	;         7 d rd ???? d ???? xxxxxxxx
-	# xor.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
-	# xor.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
-	# xor.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
-	# xor.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
-	# xor.b rs, rd		;                     1 5 rs rd
-	# xor.b reg8, @erd	;         7 d rd ???? 1 5 rs ????
-	# xor.b reg8, @erd+	;         0 1 7     9 8 rd 5 rs
-	# xor.b reg8, @erd-	;         0 1 7     9 a rd 5 rs
-	# xor.b reg8, @+erd	;         0 1 7     9 9 rd 5 rs
-	# xor.b reg8, @-erd	;         0 1 7     9 b rd 5 rs
-	#
-
-	# Coming soon:
-	# ...
-
-.data
-pre_byte:	.byte 0
-byte_dest:	.byte 0xa5
-post_byte:	.byte 0
-
-	start
-	
-xor_b_imm8_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.b #xx:8,Rd
-	xor.b	#0xff, r0l	; Immediate 8-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xa55a r0	; xor result:	a5 ^ ff
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5a55a er0	; xor result:	 a5 ^ ff
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-xor_b_imm8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b #xx:8,@eRd
-	mov	#byte_dest, er0
-	xor.b	#0xff:8, @er0	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x7d00
-;;; 	.word	0xd0ff
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 byte_dest, er0	; er0 still contains address
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the xor to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x5a, r0l
-	beq	.L1
-	fail
-.L1:
-
-xor_b_imm8_postinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b #xx:8,@eRd+
-	mov	#byte_dest, er0
-	xor.b	#0xff:8, @er0+	; Immediate 8-bit src, reg indirect dst
-;;; 	.word	0x0174
-;;; 	.word	0x6c08
-;;; 	.word	0xd0ff
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-	
-	test_h_gr32 post_byte, er0	; er0 contains address plus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the xor to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L2
-	fail
-.L2:
-
-xor_b_imm8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b #xx:8,@eRd-
-	mov	#byte_dest, er0
-	xor.b	#0xff:8, @er0-	; Immediate 8-bit src, reg indirect dst
-;;;  	.word	0x0176
-;;;  	.word	0x6c08
-;;;  	.word	0xd0ff
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-	
-	test_h_gr32 pre_byte, er0	; er0 contains address minus one
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the xor to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x5a, r0l
-	beq	.L3
-	fail
-.L3:
-
-
-.endif
-
-xor_b_reg8_reg8:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.b Rs,Rd
-	mov.b	#0xff, r0h
-	xor.b	r0h, r0l	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0xff5a r0	; xor result:	a5 ^ ff
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a5ff5a er0	; xor result:	a5 ^ ff
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.if (sim_cpu == h8sx)
-xor_b_reg8_rdind:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b rs8,@eRd	; xor reg8 to register indirect
-	mov	#byte_dest, er0
-	mov	#0xff, r1l
-	xor.b	r1l, @er0	; reg8 src, reg indirect dest
-;;; 	.word	0x7d00
-;;; 	.word	0x1590
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 byte_dest er0	; er0 still contains address
-	test_h_gr32 0xa5a5a5ff er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L4
-	fail
-.L4:
-
-xor_b_reg8_rdpostinc:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b rs8,@eRd+	; xor reg8 to register post-increment
-	mov	#byte_dest, er0
-	mov	#0xff, r1l
-	xor.b	r1l, @er0+	; reg8 src, reg post-increment dest
-;;; 	.word	0x0179
-;;; 	.word	0x8059
-
-	test_carry_clear	; H=0 N=0 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_clear
-
-	test_h_gr32 post_byte er0	; er0 contains address plus one
-	test_h_gr32 0xa5a5a5ff er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0x5a, r0l
-	beq	.L5
-	fail
-.L5:
-
-xor_b_reg8_rdpostdec:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xor.b rs8,@eRd-	; xor reg8 to register post-decrement
-	mov	#byte_dest, er0
-	mov	#0xff, r1l
-	xor.b	r1l, @er0-	; reg8 src, reg indirect dest
-;;; 	.word	0x0179
-;;; 	.word	0xa059
-
-	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
-	test_ovf_clear
-	test_zero_clear
-	test_neg_set
-
-	test_h_gr32 pre_byte er0	; er0 contains address minus one
-	test_h_gr32 0xa5a5a5ff er1	; er1 has the test load
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-	;; Now check the result of the or to memory.
-	sub.b	r0l, r0l
-	mov.b	@byte_dest, r0l
-	cmp.b	#0xa5, r0l
-	beq	.L6
-	fail
-.L6:
-
-xorc_imm8_ccr:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	set_ccr_zero
-
-	;;  xorc #xx:8,ccr
-
-	test_neg_clear
-	xorc	#0x8, ccr	; Immediate 8-bit operand (neg flag)
-	test_neg_set
-	xorc	#0x8, ccr
-	test_neg_clear
-
-	test_zero_clear
-	xorc	#0x4, ccr	; Immediate 8-bit operand (zero flag)
-	test_zero_set
-	xorc	#0x4, ccr
-	test_zero_clear
-
-	test_ovf_clear
-	xorc	#0x2, ccr	; Immediate 8-bit operand (overflow flag)
-	test_ovf_set
-	xorc	#0x2, ccr
-	test_ovf_clear
-
-	test_carry_clear
-	xorc	#0x1, ccr	; Immediate 8-bit operand (carry flag)
-	test_carry_set
-	xorc	#0x1, ccr
-	test_carry_clear
-
-	test_gr_a5a5 0		; Make sure other general regs not disturbed
-	test_gr_a5a5 1
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-.endif
-
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/xor.l.s b/sim/testsuite/sim/h8300/xor.l.s
deleted file mode 100644
index 67b2e49..0000000
--- a/sim/testsuite/sim/h8300/xor.l.s
+++ /dev/null

@@ -1,77 +0,0 @@
-# Hitachi H8 testcase 'xor.l'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf	
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu == h8sx)		; 16-bit immediate is only available on sx.
-xor_l_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.l #xx:16,Rd
-	xor.l	#0xffff:16, er0	; Immediate 16-bit operand 
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0xa5a55a5a er0	; xor result:	 a5a5a5a5 | ffff
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-xor_l_imm32:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.l #xx:32,Rd
-	xor.l	#0xffffffff, er0	; Immediate 32-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0x5a5a5a5a er0	; xor result:	 a5a5a5a5 ^ ffffffff
-
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-
-xor_l_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.l Rs,Rd
-	mov.l	#0xffffffff, er1
-	xor.l	er1, er0	; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-
-	test_h_gr32 0x5a5a5a5a er0	; xor result:	a5a5a5a5 ^ ffffffff
-	test_h_gr32 0xffffffff er1	; Make sure er1 is unchanged
-
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0

diff --git a/sim/testsuite/sim/h8300/xor.w.s b/sim/testsuite/sim/h8300/xor.w.s
deleted file mode 100644
index 3c5e5b8..0000000
--- a/sim/testsuite/sim/h8300/xor.w.s
+++ /dev/null

@@ -1,61 +0,0 @@
-# Hitachi H8 testcase 'xor.w'
-# mach(): h8300h h8300s h8sx
-# as(h8300):	--defsym sim_cpu=0
-# as(h8300h):	--defsym sim_cpu=1
-# as(h8300s):	--defsym sim_cpu=2
-# as(h8sx):	--defsym sim_cpu=3
-# ld(h8300h):	-m h8300helf
-# ld(h8300s):	-m h8300self
-# ld(h8sx):	-m h8300sxelf
-
-	.include "testutils.inc"
-
-	start
-	
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-xor_w_imm16:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.w #xx:16,Rd
-	xor.w	#0xffff, r0	; Immediate 16-bit operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0x5a5a r0	; xor result:	a5a5 ^ ffff
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a55a5a er0	; xor result:	 a5a5 ^ ffff
-.endif
-	test_gr_a5a5 1		; Make sure other general regs not disturbed
-	test_gr_a5a5 2
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-.endif
-
-xor_w_reg:
-	set_grs_a5a5		; Fill all general regs with a fixed pattern
-	;;  fixme set ccr
-
-	;;  xor.w Rs,Rd
-	mov.w	#0xffff, r1
-	xor.w	r1, r0		; Register operand
-
-	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
-	test_h_gr16 0x5a5a r0	; xor result:	a5a5 ^ ffff
-	test_h_gr16 0xffff r1	; Make sure r1 is unchanged
-.if (sim_cpu)			; non-zero means h8300h, s, or sx
-	test_h_gr32 0xa5a55a5a er0	; xor result:	a5a5 ^ ffff
-	test_h_gr32 0xa5a5ffff er1	; Make sure er1 is unchanged
-.endif
-	test_gr_a5a5 2		; Make sure other general regs not disturbed
-	test_gr_a5a5 3
-	test_gr_a5a5 4
-	test_gr_a5a5 5
-	test_gr_a5a5 6
-	test_gr_a5a5 7
-	
-	pass
-
-	exit 0