| //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft/c_dsp32alu_rrpmmp_sft.dsp |
| // Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, << |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| R0 = 0; |
| ASTAT = R0; |
| |
| |
| imm32 r0, 0x35678911; |
| imm32 r1, 0x2489ab1d; |
| imm32 r2, 0x34545515; |
| imm32 r3, 0x46667717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x67889b1d; |
| imm32 r2, 0x74445915; |
| imm32 r3, 0x86667797; |
| R0 = R0 +|- R0 , R7 = R0 -|+ R0 (ASR); |
| R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); |
| R2 = R0 +|- R2 , R5 = R0 -|+ R2 (ASR); |
| R3 = R0 +|- R3 , R4 = R0 -|+ R3 (ASR); |
| R4 = R0 +|- R4 , R3 = R0 -|+ R4 (ASR); |
| R5 = R0 +|- R5 , R2 = R0 -|+ R5 (ASR); |
| R6 = R0 +|- R6 , R1 = R0 -|+ R6 (ASR); |
| R7 = R0 +|- R7 , R0 = R0 -|+ R7 (ASR); |
| CHECKREG r0, 0x2AB3c48D; |
| CHECKREG r1, 0x2F3CE6C7; |
| CHECKREG r2, 0x326B1645; |
| CHECKREG r3, 0xf6F31DE5; |
| CHECKREG r4, 0x5E73E21A; |
| CHECKREG r5, 0x22FCE9BB; |
| CHECKREG r6, 0x262B1939; |
| CHECKREG r7, 0x2AB33B72; |
| |
| imm32 r0, 0xe5678911; |
| imm32 r1, 0x2e89ab1d; |
| imm32 r2, 0x34e45515; |
| imm32 r3, 0x466e7717; |
| imm32 r0, 0x5567ee1b; |
| imm32 r1, 0x6789abed; |
| imm32 r2, 0x7444551e; |
| imm32 r3, 0x86e67777; |
| R0 = R1 +|- R0 , R7 = R1 -|+ R0 (ASR); |
| R1 = R1 +|- R1 , R6 = R1 -|+ R1 (ASR); |
| R2 = R1 +|- R2 , R5 = R1 -|+ R2 (ASR); |
| R3 = R1 +|- R3 , R4 = R1 -|+ R3 (ASR); |
| R4 = R1 +|- R4 , R3 = R1 -|+ R4 (ASR); |
| R5 = R1 +|- R5 , R2 = R1 -|+ R5 (ASR); |
| R6 = R1 +|- R6 , R1 = R1 -|+ R6 (ASR); |
| R7 = R1 +|- R7 , R0 = R1 -|+ R7 (ASR); |
| CHECKREG r0, 0x1559d17D; |
| CHECKREG r1, 0x33C4d5F6; |
| CHECKREG r2, 0x36F31547; |
| CHECKREG r3, 0xfB9C1DDD; |
| CHECKREG r4, 0x6BEDE222; |
| CHECKREG r5, 0x3095eAB8; |
| CHECKREG r6, 0x33C42A09; |
| CHECKREG r7, 0x1E6A0479; |
| |
| imm32 r0, 0x15678911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x34445515; |
| imm32 r3, 0x46667717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x6789ab1d; |
| imm32 r2, 0x74445515; |
| imm32 r3, 0x86667777; |
| R0 = R2 +|- R0 , R7 = R2 -|+ R0 (ASR); |
| R1 = R2 +|- R1 , R6 = R2 -|+ R1 (ASR); |
| R2 = R2 +|- R2 , R5 = R2 -|+ R2 (ASR); |
| R3 = R2 +|- R3 , R4 = R2 -|+ R3 (ASR); |
| R4 = R2 +|- R4 , R3 = R2 -|+ R4 (ASR); |
| R5 = R2 +|- R5 , R2 = R2 -|+ R5 (ASR); |
| R6 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); |
| R7 = R2 +|- R7 , R0 = R2 -|+ R7 (ASR); |
| CHECKREG r0, 0x155A0CD1; |
| CHECKREG r1, 0x19E21551; |
| CHECKREG r2, 0x3A222A8A; |
| CHECKREG r3, 0xfEAA1DDD; |
| CHECKREG r4, 0x7599e222; |
| CHECKREG r5, 0x3A22d575; |
| CHECKREG r6, 0x203F1538; |
| CHECKREG r7, 0x24C81DB9; |
| |
| imm32 r0, 0x85678911; |
| imm32 r1, 0x2889ab1d; |
| imm32 r2, 0x34445515; |
| imm32 r3, 0x46667717; |
| imm32 r0, 0x5587891b; |
| imm32 r1, 0x6788ab1d; |
| imm32 r2, 0x74448515; |
| imm32 r3, 0x86667877; |
| R0 = R3 +|- R0 , R7 = R3 -|+ R0 (ASR); |
| R1 = R3 +|- R1 , R6 = R3 -|+ R1 (ASR); |
| R2 = R3 +|- R2 , R5 = R3 -|+ R2 (ASR); |
| R3 = R3 +|- R3 , R4 = R3 -|+ R3 (ASR); |
| R4 = R3 +|- R4 , R3 = R3 -|+ R4 (ASR); |
| R5 = R3 +|- R5 , R2 = R3 -|+ R5 (ASR); |
| R6 = R3 +|- R6 , R1 = R3 -|+ R6 (ASR); |
| R7 = R3 +|- R7 , R0 = R3 -|+ R7 (ASR); |
| CHECKREG r0, 0x15621E82; |
| CHECKREG r1, 0x19E22702; |
| CHECKREG r2, 0x1D111D80; |
| CHECKREG r3, 0xc3333C3B; |
| CHECKREG r4, 0xc333c3C4; |
| CHECKREG r5, 0xa6221EBA; |
| CHECKREG r6, 0xa9511538; |
| CHECKREG r7, 0xaDD11DB9; |
| |
| imm32 r0, 0x15678911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x34445515; |
| imm32 r3, 0x46667717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x6789ab1d; |
| imm32 r2, 0x74445515; |
| imm32 r3, 0x86667777; |
| R0 = R4 +|- R0 , R7 = R4 -|+ R0 (ASR); |
| R1 = R4 +|- R1 , R6 = R4 -|+ R1 (ASR); |
| R2 = R4 +|- R2 , R5 = R4 -|+ R2 (ASR); |
| R3 = R4 +|- R3 , R4 = R4 -|+ R3 (ASR); |
| R4 = R4 +|- R4 , R3 = R4 -|+ R4 (ASR); |
| R5 = R4 +|- R5 , R2 = R4 -|+ R5 (ASR); |
| R6 = R4 +|- R6 , R1 = R4 -|+ R6 (ASR); |
| R7 = R4 +|- R7 , R0 = R4 -|+ R7 (ASR); |
| CHECKREG r0, 0x33C0d337; |
| CHECKREG r1, 0x3848dBB8; |
| CHECKREG r2, 0x3B770636; |
| CHECKREG r3, 0x00001D9D; |
| CHECKREG r4, 0x1E660000; |
| CHECKREG r5, 0xe2EEf9CA; |
| CHECKREG r6, 0xe61D2448; |
| CHECKREG r7, 0xeAA62CC8; |
| |
| imm32 r0, 0x95678911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x39445515; |
| imm32 r3, 0x46967717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x6789ab1d; |
| imm32 r2, 0x74495515; |
| imm32 r3, 0x86669777; |
| R0 = R5 +|- R0 , R7 = R5 -|+ R0 (ASR); |
| R1 = R5 +|- R1 , R6 = R5 -|+ R1 (ASL); |
| R2 = R5 +|- R2 , R5 = R5 -|+ R2 (ASR); |
| R3 = R5 +|- R3 , R4 = R5 -|+ R3 (ASL); |
| R4 = R5 +|- R4 , R3 = R5 -|+ R4 (ASR); |
| R5 = R5 +|- R5 , R2 = R5 -|+ R5 (ASR); |
| R6 = R5 +|- R6 , R1 = R5 -|+ R6 (ASR); |
| R7 = R5 +|- R7 , R0 = R5 -|+ R7 (ASL); |
| CHECKREG r0, 0xE11E82E4; |
| CHECKREG r1, 0xe04424E7; |
| CHECKREG r2, 0x0000276F; |
| CHECKREG r3, 0xaaBD529D; |
| CHECKREG r4, 0x0c95D4D1; |
| CHECKREG r5, 0xb7520000; |
| CHECKREG r6, 0xd70EdB19; |
| CHECKREG r7, 0xfC2A7D1C; |
| |
| imm32 r0, 0x15678911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x34445515; |
| imm32 r3, 0x46667717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x6789ab1d; |
| imm32 r2, 0x74445515; |
| imm32 r3, 0x86667777; |
| R0 = R6 +|- R0 , R7 = R6 -|+ R0 (ASR); |
| R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); |
| R2 = R6 +|- R2 , R5 = R6 -|+ R2 (ASL); |
| R3 = R6 +|- R3 , R4 = R6 -|+ R3 (ASR); |
| R4 = R6 +|- R4 , R3 = R6 -|+ R4 (ASR); |
| R5 = R6 +|- R5 , R2 = R6 -|+ R5 (ASR); |
| R6 = R6 +|- R6 , R1 = R6 -|+ R6 (ASL); |
| R7 = R6 +|- R7 , R0 = R6 -|+ R7 (ASR); |
| CHECKREG r0, 0x5dAAd90D; |
| CHECKREG r1, 0x000031B0; |
| CHECKREG r2, 0x04BFe7B7; |
| CHECKREG r3, 0xd95C272E; |
| CHECKREG r4, 0x05AEe53D; |
| CHECKREG r5, 0xDa4B24B5; |
| CHECKREG r6, 0x7C280000; |
| CHECKREG r7, 0x1e7D26F3; |
| |
| imm32 r0, 0x67898911; |
| imm32 r1, 0xb789ab1d; |
| imm32 r2, 0x3b445515; |
| imm32 r3, 0x46b67717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x678bab1d; |
| imm32 r2, 0x7444b515; |
| imm32 r3, 0x86667b77; |
| R0 = R7 +|- R0 , R7 = R7 -|+ R0 (ASR); |
| R1 = R7 +|- R1 , R6 = R7 -|+ R1 (ASR); |
| R2 = R7 +|- R2 , R5 = R7 -|+ R2 (ASL); |
| R3 = R7 +|- R3 , R4 = R7 -|+ R3 (ASR); |
| R4 = R7 +|- R4 , R3 = R7 -|+ R4 (ASL); |
| R5 = R7 +|- R5 , R2 = R7 -|+ R5 (ASL); |
| R6 = R7 +|- R6 , R1 = R7 -|+ R6 (ASL); |
| R7 = R7 +|- R7 , R0 = R7 -|+ R7 (ASR); |
| CHECKREG r0, 0x0000d807; |
| CHECKREG r1, 0x4c163332; |
| CHECKREG r2, 0x07FAe47E; |
| CHECKREG r3, 0x6aF2038C; |
| CHECKREG r4, 0x273A5c90; |
| CHECKREG r5, 0x8a327b9E; |
| CHECKREG r6, 0x46162cEA; |
| CHECKREG r7, 0xe48B0000; |
| |
| imm32 r0, 0xe5678911; |
| imm32 r1, 0x2e89ab1d; |
| imm32 r2, 0x34ee5515; |
| imm32 r3, 0x4666e717; |
| imm32 r0, 0x5567891b; |
| imm32 r1, 0x6789ae1d; |
| imm32 r2, 0x744455e5; |
| imm32 r3, 0x8666777e; |
| R4 = R2 +|- R5 , R3 = R2 -|+ R5 (ASR); |
| R0 = R5 +|- R3 , R5 = R5 -|+ R3 (ASL); |
| R2 = R6 +|- R2 , R0 = R6 -|+ R2 (ASR); |
| R3 = R4 +|- R0 , R2 = R4 -|+ R0 (ASR); |
| R7 = R7 +|- R6 , R6 = R7 -|+ R6 (ASR); |
| R6 = R1 +|- R7 , R1 = R1 -|+ R7 (ASL); |
| R5 = R0 +|- R4 , R7 = R0 -|+ R4 (ASR); |
| R1 = R3 +|- R1 , R4 = R3 -|+ R1 (ASL); |
| CHECKREG r0, 0xE8e94167; |
| CHECKREG r1, 0x31084d1C; |
| CHECKREG r2, 0x0b291745; |
| CHECKREG r3, 0xF412d5de; |
| CHECKREG r4, 0x9f400a5C; |
| CHECKREG r5, 0xF4122a22; |
| CHECKREG r6, 0xf9B28924; |
| CHECKREG r7, 0xF4D71745; |
| |
| imm32 r0, 0xff678911; |
| imm32 r1, 0x2789ab1d; |
| imm32 r2, 0x3f445515; |
| imm32 r3, 0x46f67717; |
| imm32 r0, 0x556f891b; |
| imm32 r1, 0x6789fb1d; |
| imm32 r2, 0x74445f15; |
| imm32 r3, 0x866677f7; |
| R4 = R3 +|- R3 , R5 = R3 -|+ R3 (ASR); |
| R1 = R6 +|- R1 , R6 = R6 -|+ R1 (ASL); |
| R6 = R1 +|- R4 , R4 = R1 -|+ R4 (ASR); |
| R7 = R4 +|- R2 , R0 = R4 -|+ R2 (ASL); |
| R2 = R2 +|- R6 , R1 = R2 -|+ R6 (ASR); |
| R3 = R5 +|- R5 , R7 = R5 -|+ R5 (ASL); |
| R5 = R7 +|- R7 , R3 = R7 -|+ R7 (ASR); |
| R0 = R0 +|- R0 , R2 = R0 -|+ R0 (ASR); |
| CHECKREG r0, 0x53880000; |
| CHECKREG r1, 0x67eb368e; |
| CHECKREG r2, 0x0000da38; |
| CHECKREG r3, 0x0000dfdc; |
| CHECKREG r4, 0x1e080e07; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0xa46e0e07; |
| CHECKREG r7, 0x0000dfdc; |
| |
| pass |
