| //Original:/testcases/core/c_dsp32shift_lf/c_dsp32shift_lf.dsp |
| // Spec Reference: dsp32shift lshift |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| |
| |
| // lshift : mix data, count (+)= (half reg) |
| // d_reg = lshift (d BY d_lo) |
| // Rx by RLx |
| imm32 r0, 0x01210001; |
| imm32 r1, 0x12315678; |
| imm32 r2, 0x23416789; |
| imm32 r3, 0x3451789a; |
| imm32 r4, 0x856189ab; |
| imm32 r5, 0x96719abc; |
| imm32 r6, 0xa781abcd; |
| imm32 r7, 0xb891bcde; |
| R7 = LSHIFT R0 BY R0.L; |
| R6 = LSHIFT R1 BY R0.L; |
| R0 = LSHIFT R2 BY R0.L; |
| R1 = LSHIFT R3 BY R0.L; |
| R2 = LSHIFT R4 BY R0.L; |
| R3 = LSHIFT R5 BY R0.L; |
| R4 = LSHIFT R6 BY R0.L; |
| R5 = LSHIFT R7 BY R0.L; |
| CHECKREG r0, 0x4682CF12; |
| CHECKREG r1, 0xE2680000; |
| CHECKREG r2, 0x26AC0000; |
| CHECKREG r3, 0x6AF00000; |
| CHECKREG r4, 0xB3C00000; |
| CHECKREG r5, 0x00080000; |
| CHECKREG r6, 0x2462ACF0; |
| CHECKREG r7, 0x02420002; |
| |
| imm32 r0, 0x01220002; |
| imm32 r1, 0x12325678; |
| imm32 r2, 0x23426789; |
| imm32 r3, 0x3452789a; |
| imm32 r4, 0x956289ab; |
| imm32 r5, 0xa6729abc; |
| imm32 r6, 0xb782abcd; |
| imm32 r7, 0xc892bcde; |
| R1.L = 2; |
| R3 = LSHIFT R0 BY R1.L; |
| R4 = LSHIFT R1 BY R1.L; |
| R5 = LSHIFT R2 BY R1.L; |
| R6 = LSHIFT R3 BY R1.L; |
| R7 = LSHIFT R4 BY R1.L; |
| R0 = LSHIFT R5 BY R1.L; |
| R1 = LSHIFT R6 BY R1.L; |
| R2 = LSHIFT R7 BY R1.L; |
| CHECKREG r0, 0x34267890; |
| CHECKREG r1, 0x48800080; |
| CHECKREG r2, 0x23200020; |
| CHECKREG r3, 0x04880008; |
| CHECKREG r4, 0x48C80008; |
| CHECKREG r5, 0x8D099E24; |
| CHECKREG r6, 0x12200020; |
| CHECKREG r7, 0x23200020; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12335678; |
| imm32 r2, 0x23436789; |
| imm32 r3, 0x3453789a; |
| imm32 r4, 0x456389ab; |
| imm32 r5, 0x56739abc; |
| imm32 r6, 0x6783abcd; |
| imm32 r7, 0x789abcde; |
| R2 = 14; |
| R0 = LSHIFT R4 BY R2.L; |
| R1 = LSHIFT R5 BY R2.L; |
| R2 = LSHIFT R6 BY R2.L; |
| R3 = LSHIFT R7 BY R2.L; |
| CHECKREG r0, 0xE26AC000; |
| CHECKREG r1, 0xE6AF0000; |
| CHECKREG r2, 0xEAF34000; |
| CHECKREG r3, 0x789ABCDE; |
| |
| imm32 r0, 0x01240002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23446789; |
| imm32 r3, 0x3454789a; |
| imm32 r4, 0xa56489ab; |
| imm32 r5, 0xb6749abc; |
| imm32 r6, 0xc784abcd; |
| imm32 r7, 0xd894bcde; |
| R3.L = 15; |
| R4 = LSHIFT R0 BY R3.L; |
| R5 = LSHIFT R1 BY R3.L; |
| R6 = LSHIFT R2 BY R3.L; |
| R7 = LSHIFT R3 BY R3.L; |
| R0 = LSHIFT R4 BY R3.L; |
| R1 = LSHIFT R5 BY R3.L; |
| R2 = LSHIFT R6 BY R3.L; |
| R3 = LSHIFT R7 BY R3.L; |
| CHECKREG r0, 0x80000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x40000000; |
| CHECKREG r3, 0xC0000000; |
| CHECKREG r4, 0x00010000; |
| CHECKREG r5, 0x2B3C0000; |
| CHECKREG r6, 0x33C48000; |
| CHECKREG r7, 0x00078000; |
| |
| imm32 r0, 0x01250002; |
| imm32 r1, 0x12355678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3455789a; |
| imm32 r4, 0x456589ab; |
| imm32 r5, 0x56759abc; |
| imm32 r6, 0x6785abcd; |
| imm32 r7, 0x7895bcde; |
| R4.L = -1; |
| R7 = LSHIFT R0 BY R4.L; |
| R6 = LSHIFT R1 BY R4.L; |
| R5 = LSHIFT R2 BY R4.L; |
| R3 = LSHIFT R4 BY R4.L; |
| R2 = LSHIFT R5 BY R4.L; |
| R1 = LSHIFT R6 BY R4.L; |
| R0 = LSHIFT R7 BY R4.L; |
| R4 = LSHIFT R3 BY R4.L; |
| CHECKREG r0, 0x00494000; |
| CHECKREG r1, 0x048D559E; |
| CHECKREG r2, 0x08D159E2; |
| CHECKREG r3, 0x22B2FFFF; |
| CHECKREG r4, 0x11597FFF; |
| CHECKREG r5, 0x11A2B3C4; |
| CHECKREG r6, 0x091AAB3C; |
| CHECKREG r7, 0x00928001; |
| |
| imm32 r0, 0x01260002; |
| imm32 r1, 0x82365678; |
| imm32 r2, 0x93466789; |
| imm32 r3, 0xa456789a; |
| imm32 r4, 0xb56689ab; |
| imm32 r5, 0xc6769abc; |
| imm32 r6, 0xd786abcd; |
| imm32 r7, 0xe896bcde; |
| R5.L = -8; |
| R6 = LSHIFT R0 BY R5.L; |
| R7 = LSHIFT R1 BY R5.L; |
| R0 = LSHIFT R2 BY R5.L; |
| R1 = LSHIFT R3 BY R5.L; |
| R2 = LSHIFT R4 BY R5.L; |
| R3 = LSHIFT R5 BY R5.L; |
| R4 = LSHIFT R6 BY R5.L; |
| R5 = LSHIFT R7 BY R5.L; |
| CHECKREG r0, 0x00934667; |
| CHECKREG r1, 0x00A45678; |
| CHECKREG r2, 0x00B56689; |
| CHECKREG r3, 0x00C676FF; |
| CHECKREG r4, 0x00000126; |
| CHECKREG r5, 0x00008236; |
| CHECKREG r6, 0x00012600; |
| CHECKREG r7, 0x00823656; |
| |
| imm32 r0, 0x01270002; |
| imm32 r1, 0x12375678; |
| imm32 r2, 0x23476789; |
| imm32 r3, 0x3457789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56779abc; |
| imm32 r6, 0x6787abcd; |
| imm32 r7, 0x7897bcde; |
| R6.L = -15; |
| R7 = LSHIFT R0 BY R6.L; |
| R0 = LSHIFT R1 BY R6.L; |
| R1 = LSHIFT R2 BY R6.L; |
| R2 = LSHIFT R3 BY R6.L; |
| R3 = LSHIFT R4 BY R6.L; |
| R4 = LSHIFT R5 BY R6.L; |
| R5 = LSHIFT R6 BY R6.L; |
| R6 = LSHIFT R7 BY R6.L; |
| CHECKREG r0, 0x0000246E; |
| CHECKREG r1, 0x0000468E; |
| CHECKREG r2, 0x000068AE; |
| CHECKREG r3, 0x00008ACF; |
| CHECKREG r4, 0x0000ACEF; |
| CHECKREG r5, 0x0000CF0F; |
| CHECKREG r6, 0x00000000; |
| CHECKREG r7, 0x0000024E; |
| |
| imm32 r0, 0x01280002; |
| imm32 r1, 0x82385678; |
| imm32 r2, 0x93486789; |
| imm32 r3, 0xa458789a; |
| imm32 r4, 0xb56889ab; |
| imm32 r5, 0xc6789abc; |
| imm32 r6, 0xd788abcd; |
| imm32 r7, 0xe898bcde; |
| R7.L = -16; |
| R0 = LSHIFT R0 BY R7.L; |
| R1 = LSHIFT R1 BY R7.L; |
| R2 = LSHIFT R2 BY R7.L; |
| R3 = LSHIFT R3 BY R7.L; |
| R4 = LSHIFT R4 BY R7.L; |
| R5 = LSHIFT R5 BY R7.L; |
| R6 = LSHIFT R6 BY R7.L; |
| R7 = LSHIFT R7 BY R7.L; |
| CHECKREG r0, 0x00000128; |
| CHECKREG r1, 0x00008238; |
| CHECKREG r2, 0x00009348; |
| CHECKREG r3, 0x0000A458; |
| CHECKREG r4, 0x0000B568; |
| CHECKREG r5, 0x0000C678; |
| CHECKREG r6, 0x0000D788; |
| CHECKREG r7, 0x0000E898; |
| |
| imm32 r0, 0x81290002; |
| imm32 r1, 0x92395678; |
| imm32 r2, 0xa3496789; |
| imm32 r3, 0xb459789a; |
| imm32 r4, 0xc56989ab; |
| imm32 r5, 0xd6799abc; |
| imm32 r6, 0xe789abcd; |
| imm32 r7, 0xf899bcde; |
| R0.L = 4; |
| //r0 = lshift (r0 by rl0); |
| R1 = LSHIFT R1 BY R0.L; |
| R2 = LSHIFT R2 BY R0.L; |
| R3 = LSHIFT R3 BY R0.L; |
| R4 = LSHIFT R4 BY R0.L; |
| R5 = LSHIFT R5 BY R0.L; |
| R6 = LSHIFT R6 BY R0.L; |
| R7 = LSHIFT R7 BY R0.L; |
| CHECKREG r1, 0x23956780; |
| CHECKREG r2, 0x34967890; |
| CHECKREG r3, 0x459789A0; |
| CHECKREG r4, 0x56989AB0; |
| CHECKREG r5, 0x6799ABC0; |
| CHECKREG r6, 0x789ABCD0; |
| CHECKREG r7, 0x899BCDE0; |
| |
| imm32 r0, 0x012a0002; |
| imm32 r1, 0x123a5678; |
| imm32 r2, 0x234a6789; |
| imm32 r3, 0x345a789a; |
| imm32 r4, 0x456a89ab; |
| imm32 r5, 0x567a9abc; |
| imm32 r6, 0x678aabcd; |
| imm32 r7, 0xf89abcde; |
| R1.L = 2; |
| R7 = LSHIFT R0 BY R1.L; |
| R6 = LSHIFT R1 BY R1.L; |
| R5 = LSHIFT R2 BY R1.L; |
| R4 = LSHIFT R3 BY R1.L; |
| R3 = LSHIFT R4 BY R1.L; |
| R2 = LSHIFT R5 BY R1.L; |
| R0 = LSHIFT R6 BY R1.L; |
| R1 = LSHIFT R7 BY R1.L; |
| CHECKREG r0, 0x23A00020; |
| CHECKREG r1, 0x12A00020; |
| CHECKREG r2, 0x34A67890; |
| CHECKREG r3, 0x45A789A0; |
| CHECKREG r4, 0xD169E268; |
| CHECKREG r5, 0x8D299E24; |
| CHECKREG r6, 0x48E80008; |
| CHECKREG r7, 0x04A80008; |
| |
| |
| imm32 r0, 0x012b0002; |
| imm32 r1, 0x123b5678; |
| imm32 r2, 0x234b6789; |
| imm32 r3, 0x345b789a; |
| imm32 r4, 0x456b89ab; |
| imm32 r5, 0x567b9abc; |
| imm32 r6, 0x678babcd; |
| imm32 r7, 0x789bbcde; |
| R2.L = 15; |
| R0 = LSHIFT R0 BY R2.L; |
| R1 = LSHIFT R1 BY R2.L; |
| R3 = LSHIFT R3 BY R2.L; |
| R4 = LSHIFT R4 BY R2.L; |
| R5 = LSHIFT R5 BY R2.L; |
| R6 = LSHIFT R6 BY R2.L; |
| R7 = LSHIFT R7 BY R2.L; |
| R2 = LSHIFT R2 BY R2.L; |
| CHECKREG r0, 0x80010000; |
| CHECKREG r1, 0xAB3C0000; |
| CHECKREG r2, 0x80078000; |
| CHECKREG r3, 0xBC4D0000; |
| CHECKREG r4, 0xC4D58000; |
| CHECKREG r5, 0xCD5E0000; |
| CHECKREG r6, 0xD5E68000; |
| CHECKREG r7, 0xDE6F0000; |
| |
| imm32 r0, 0x012c0002; |
| imm32 r1, 0x123c5678; |
| imm32 r2, 0x234c6789; |
| imm32 r3, 0x345c789a; |
| imm32 r4, 0x456c89ab; |
| imm32 r5, 0x567c9abc; |
| imm32 r6, 0x678cabcd; |
| imm32 r7, 0x789cbcde; |
| R3.L = 16; |
| R0 = LSHIFT R0 BY R3.L; |
| R1 = LSHIFT R1 BY R3.L; |
| R2 = LSHIFT R2 BY R3.L; |
| R4 = LSHIFT R4 BY R3.L; |
| R5 = LSHIFT R5 BY R3.L; |
| R6 = LSHIFT R6 BY R3.L; |
| R7 = LSHIFT R7 BY R3.L; |
| R3 = LSHIFT R3 BY R3.L; |
| CHECKREG r0, 0x00020000; |
| CHECKREG r1, 0x56780000; |
| CHECKREG r2, 0x67890000; |
| CHECKREG r3, 0x00100000; |
| CHECKREG r4, 0x89AB0000; |
| CHECKREG r5, 0x9ABC0000; |
| CHECKREG r6, 0xABCD0000; |
| CHECKREG r7, 0xBCDE0000; |
| |
| imm32 r0, 0x012d0002; |
| imm32 r1, 0x123d5678; |
| imm32 r2, 0x234d6789; |
| imm32 r3, 0x345d789a; |
| imm32 r4, 0x456d89ab; |
| imm32 r5, 0x567d9abc; |
| imm32 r6, 0x678dabcd; |
| imm32 r7, 0x789dbcde; |
| R4.L = -9; |
| R7 = LSHIFT R0 BY R4.L; |
| R0 = LSHIFT R1 BY R4.L; |
| R1 = LSHIFT R2 BY R4.L; |
| R2 = LSHIFT R3 BY R4.L; |
| //r4 = lshift (r4 by rl4); |
| R3 = LSHIFT R5 BY R4.L; |
| R5 = LSHIFT R6 BY R4.L; |
| R6 = LSHIFT R7 BY R4.L; |
| CHECKREG r0, 0x00091EAB; |
| CHECKREG r1, 0x0011A6B3; |
| CHECKREG r2, 0x001A2EBC; |
| CHECKREG r3, 0x002B3ECD; |
| CHECKREG r4, 0x456DFFF7; |
| CHECKREG r5, 0x0033C6D5; |
| CHECKREG r6, 0x0000004B; |
| CHECKREG r7, 0x00009680; |
| |
| imm32 r0, 0x012e0002; |
| imm32 r1, 0x123e5678; |
| imm32 r2, 0x234e6789; |
| imm32 r3, 0x345e789a; |
| imm32 r4, 0x456e89ab; |
| imm32 r5, 0x567e9abc; |
| imm32 r6, 0x678eabcd; |
| imm32 r7, 0x789ebcde; |
| R5.L = -14; |
| R0 = LSHIFT R0 BY R5.L; |
| R1 = LSHIFT R1 BY R5.L; |
| R2 = LSHIFT R2 BY R5.L; |
| R3 = LSHIFT R3 BY R5.L; |
| R4 = LSHIFT R4 BY R5.L; |
| //r5 = lshift (r5 by rl5); |
| R6 = LSHIFT R6 BY R5.L; |
| R7 = LSHIFT R7 BY R5.L; |
| CHECKREG r0, 0x000004B8; |
| CHECKREG r1, 0x000048F9; |
| CHECKREG r2, 0x00008D39; |
| CHECKREG r3, 0x0000D179; |
| CHECKREG r4, 0x000115BA; |
| CHECKREG r5, 0x567EFFF2; |
| CHECKREG r6, 0x00019E3A; |
| CHECKREG r7, 0x0001E27A; |
| |
| |
| imm32 r0, 0x012f0002; |
| imm32 r1, 0x623f5678; |
| imm32 r2, 0x734f6789; |
| imm32 r3, 0x845f789a; |
| imm32 r4, 0x956f89ab; |
| imm32 r5, 0xa67f9abc; |
| imm32 r6, 0xc78fabcd; |
| imm32 r7, 0xd89fbcde; |
| R6.L = -15; |
| R0 = LSHIFT R0 BY R6.L; |
| R1 = LSHIFT R1 BY R6.L; |
| R2 = LSHIFT R2 BY R6.L; |
| R3 = LSHIFT R3 BY R6.L; |
| R4 = LSHIFT R4 BY R6.L; |
| R5 = LSHIFT R5 BY R6.L; |
| //r6 = lshift (r6 by rl6); |
| R7 = LSHIFT R7 BY R6.L; |
| CHECKREG r0, 0x0000025E; |
| CHECKREG r1, 0x0000C47E; |
| CHECKREG r2, 0x0000E69E; |
| CHECKREG r3, 0x000108BE; |
| CHECKREG r4, 0x00012ADF; |
| CHECKREG r5, 0x00014CFF; |
| CHECKREG r6, 0xC78FFFF1; |
| CHECKREG r7, 0x0001B13F; |
| |
| imm32 r0, 0x71230072; |
| imm32 r1, 0x82345678; |
| imm32 r2, 0x93456779; |
| imm32 r3, 0xa456787a; |
| imm32 r4, 0xb567897b; |
| imm32 r5, 0xc6789a7c; |
| imm32 r6, 0x6789ab7d; |
| imm32 r7, 0x789abc7e; |
| R7.L = -16; |
| R0 = LSHIFT R0 BY R7.L; |
| R1 = LSHIFT R1 BY R7.L; |
| R2 = LSHIFT R2 BY R7.L; |
| R3 = LSHIFT R3 BY R7.L; |
| R4 = LSHIFT R4 BY R7.L; |
| R5 = LSHIFT R5 BY R7.L; |
| R6 = LSHIFT R6 BY R7.L; |
| R7 = LSHIFT R7 BY R7.L; |
| CHECKREG r0, 0x00007123; |
| CHECKREG r1, 0x00008234; |
| CHECKREG r2, 0x00009345; |
| CHECKREG r3, 0x0000A456; |
| CHECKREG r4, 0x0000B567; |
| CHECKREG r5, 0x0000C678; |
| CHECKREG r6, 0x00006789; |
| CHECKREG r7, 0x0000789A; |
| |
| |
| pass |
