| # frv testcase for bcvlr $ICCi,$ccond,$hint | |
| # mach: all | |
| .include "testutils.inc" | |
| start | |
| .global bcvlr | |
| bcvlr: | |
| ; ccond is true | |
| set_spr_immed 128,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcvlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0x1 1 | |
| bcvlr icc1,0,1 | |
| set_spr_addr ok3,lr | |
| set_icc 0x2 2 | |
| bcvlr icc2,0,2 | |
| fail | |
| ok3: | |
| set_spr_addr ok4,lr | |
| set_icc 0x3 3 | |
| bcvlr icc3,0,3 | |
| fail | |
| ok4: | |
| set_spr_addr bad,lr | |
| set_icc 0x4 0 | |
| bcvlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0x5 1 | |
| bcvlr icc1,0,1 | |
| set_spr_addr ok7,lr | |
| set_icc 0x6 2 | |
| bcvlr icc2,0,2 | |
| fail | |
| ok7: | |
| set_spr_addr ok8,lr | |
| set_icc 0x7 3 | |
| bcvlr icc3,0,3 | |
| fail | |
| ok8: | |
| set_spr_addr bad,lr | |
| set_icc 0x8 0 | |
| bcvlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0x9 1 | |
| bcvlr icc1,0,1 | |
| set_spr_addr okb,lr | |
| set_icc 0xa 2 | |
| bcvlr icc2,0,2 | |
| fail | |
| okb: | |
| set_spr_addr okc,lr | |
| set_icc 0xb 3 | |
| bcvlr icc3,0,3 | |
| fail | |
| okc: | |
| set_spr_addr bad,lr | |
| set_icc 0xc 0 | |
| bcvlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0xd 1 | |
| bcvlr icc1,0,1 | |
| set_spr_addr okf,lr | |
| set_icc 0xe 2 | |
| bcvlr icc2,0,2 | |
| fail | |
| okf: | |
| set_spr_addr okg,lr | |
| set_icc 0xf 3 | |
| bcvlr icc3,0,3 | |
| fail | |
| okg: | |
| ; ccond is true | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcvlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x1 1 | |
| bcvlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okj,lr | |
| set_icc 0x2 2 | |
| bcvlr icc2,1,2 | |
| fail | |
| okj: | |
| set_spr_immed 1,lcr | |
| set_spr_addr okk,lr | |
| set_icc 0x3 3 | |
| bcvlr icc3,1,3 | |
| fail | |
| okk: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x4 0 | |
| bcvlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x5 1 | |
| bcvlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okn,lr | |
| set_icc 0x6 2 | |
| bcvlr icc2,1,2 | |
| fail | |
| okn: | |
| set_spr_immed 1,lcr | |
| set_spr_addr oko,lr | |
| set_icc 0x7 3 | |
| bcvlr icc3,1,3 | |
| fail | |
| oko: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x8 0 | |
| bcvlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x9 1 | |
| bcvlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okr,lr | |
| set_icc 0xa 2 | |
| bcvlr icc2,1,2 | |
| fail | |
| okr: | |
| set_spr_immed 1,lcr | |
| set_spr_addr oks,lr | |
| set_icc 0xb 3 | |
| bcvlr icc3,1,3 | |
| fail | |
| oks: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xc 0 | |
| bcvlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xd 1 | |
| bcvlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okv,lr | |
| set_icc 0xe 2 | |
| bcvlr icc2,1,2 | |
| fail | |
| okv: | |
| set_spr_immed 1,lcr | |
| set_spr_addr okw,lr | |
| set_icc 0xf 3 | |
| bcvlr icc3,1,3 | |
| fail | |
| okw: | |
| ; ccond is false | |
| set_spr_immed 128,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcvlr icc0,1,0 | |
| set_icc 0x1 1 | |
| bcvlr icc1,1,1 | |
| set_icc 0x2 2 | |
| bcvlr icc2,1,2 | |
| set_icc 0x3 3 | |
| bcvlr icc3,1,3 | |
| set_icc 0x4 0 | |
| bcvlr icc0,1,0 | |
| set_icc 0x5 1 | |
| bcvlr icc1,1,1 | |
| set_icc 0x6 2 | |
| bcvlr icc2,1,2 | |
| set_icc 0x7 3 | |
| bcvlr icc3,1,3 | |
| set_icc 0x8 0 | |
| bcvlr icc0,1,0 | |
| set_icc 0x9 1 | |
| bcvlr icc1,1,1 | |
| set_icc 0xa 2 | |
| bcvlr icc2,1,2 | |
| set_icc 0xb 3 | |
| bcvlr icc3,1,3 | |
| set_icc 0xc 0 | |
| bcvlr icc0,1,0 | |
| set_icc 0xd 1 | |
| bcvlr icc1,1,1 | |
| set_icc 0xe 2 | |
| bcvlr icc2,1,2 | |
| set_icc 0xf 3 | |
| bcvlr icc3,1,3 | |
| ; ccond is false | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcvlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x1 1 | |
| bcvlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0x2 2 | |
| bcvlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0x3 3 | |
| bcvlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0x4 0 | |
| bcvlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x5 1 | |
| bcvlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0x6 2 | |
| bcvlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0x7 3 | |
| bcvlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0x8 0 | |
| bcvlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x9 1 | |
| bcvlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0xa 2 | |
| bcvlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0xb 3 | |
| bcvlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0xc 0 | |
| bcvlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0xd 1 | |
| bcvlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0xe 2 | |
| bcvlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0xf 3 | |
| bcvlr icc3,0,3 | |
| pass | |
| bad: | |
| fail |