blob: 533b5045399f5ea2d477b64bc169756d2a2ad45d [file] [log] [blame]
# frv testcase for sllcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all
.include "testutils.inc"
start
.global sllcc
sllcc:
set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
sllcc gr8,gr7,gr8,icc0
test_icc 0 0 0 1 icc0
test_gr_immed 2,gr8
set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1
set_gr_immed 2,gr8
set_icc 0x0f,0 ; Set mask opposite of expected
sllcc gr8,gr7,gr8,icc0
test_icc 0 0 0 1 icc0
test_gr_immed 4,gr8
set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31
set_gr_immed 1,gr8
set_icc 0x07,0 ; Set mask opposite of expected
sllcc gr8,gr7,gr8,icc0
test_icc 1 0 0 1 icc0
test_gr_limmed 0x8000,0x0000,gr8
set_gr_limmed 0xdead,0xbeff,gr7 ; clear register
set_gr_immed 2,gr8
set_icc 0x08,0 ; Set mask opposite of expected
sllcc gr8,gr7,gr8,icc0
test_icc 0 1 1 0 icc0
test_gr_immed 0x00000000,gr8
pass