S12Z: Opcodes: Handle bit map operations with non-canonical operands.
opcodes/
* s12z-opc.c (bm_decode): Handle the RESERVERD0 case.
gas/
* testsuite/gas/s12z/bit-manip-invalid.d: Extend the test.
* testsuite/gas/s12z/bit-manip-invalid.s: Extend the test.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index d49ec4d..090df4b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * testsuite/gas/s12z/bit-manip-invalid.s: Extend test for BSET
+ and BCLR instructions with an invalid mode.
+ * testsuite/gas/s12z/bit-manip-invalid.d: ditto.
+
2019-04-19 Nick Clifton <nickc@redhat.com>
PR 24464
diff --git a/gas/testsuite/gas/s12z/bit-manip-invalid.d b/gas/testsuite/gas/s12z/bit-manip-invalid.d
index 571f435..d16a8f5 100644
--- a/gas/testsuite/gas/s12z/bit-manip-invalid.d
+++ b/gas/testsuite/gas/s12z/bit-manip-invalid.d
@@ -1,5 +1,5 @@
#objdump: -d
-#name: Test of disassembler behaviour by with invalid bit manipulation instructions
+#name: Test of disassembler behaviour with invalid bit manipulation instructions
#source: bit-manip-invalid.s
@@ -17,3 +17,7 @@
8: 03 65 12 brset d1, #4, \*\+18
b: 01 nop
c: 01 nop
+ d: ec 44 bclr d0, #0
+ f: ec 7c bclr d0, #7
+ 11: ed 5d bset d1, #3
+ 13: ed 7d bset d1, #7
diff --git a/gas/testsuite/gas/s12z/bit-manip-invalid.s b/gas/testsuite/gas/s12z/bit-manip-invalid.s
index 6876ba8..d0269953 100644
--- a/gas/testsuite/gas/s12z/bit-manip-invalid.s
+++ b/gas/testsuite/gas/s12z/bit-manip-invalid.s
@@ -8,4 +8,8 @@
nop
DC.L 0x03651201
nop
+ dc.w 0xEC44
+ dc.w 0xEC7C
+ dc.w 0xED5D
+ dc.w 0xED7D
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b4f85d3..2d0229c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -3,6 +3,11 @@
* s12z-opc.h: Add extern "C" bracketing to help
users who wish to use this interface in c++ code.
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.c (bm_decode): Handle bit map operations with the
+ "reserved0" mode.
+
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
diff --git a/opcodes/s12z-opc.c b/opcodes/s12z-opc.c
index 1f02f5d..e40f90e 100644
--- a/opcodes/s12z-opc.c
+++ b/opcodes/s12z-opc.c
@@ -1821,6 +1821,7 @@
switch (mode)
{
case BM_REG_IMM:
+ case BM_RESERVED0:
imm = (bm & 0x38) >> 3;
operand[(*n_operands)++] = create_immediate_operand (imm);
break;
@@ -1838,9 +1839,6 @@
case BM_RESERVED1:
operand[(*n_operands)++] = create_register_operand ((bm & 0x70) >> 4);
break;
- case BM_RESERVED0:
- assert (0);
- break;
}
}
