| commit | a9e2cefdf00202e0ba59825bd66a01ec41ac3ed0 | [log] [tgz] |
|---|---|---|
| author | Victor Do Nascimento <victor.donascimento@arm.com> | Wed Nov 15 17:21:39 2023 +0000 |
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | Tue Jan 09 10:16:40 2024 +0000 |
| tree | b62a75e4faa6bd99b6af833302c239d1457d2e74 | |
| parent | 92d8946670571118cccdbcd36d35300af33da4af [diff] |
aarch64: Implement TLBIP 128-bit instruction The addition of 128-bit page table descriptors and, with it, the addition of 128-bit system registers for these means that special "invalidate translation table entry" instructions are needed to cope with the new 128-bit model. This is introduced with the `tlbpi' instruction, implemented here.