| #objdump: -d --prefix-addresses --show-raw-insn |
| #name: MIPS CP2 doubleword memory access instructions |
| #as: -32 |
| |
| .*: +file format .*mips.* |
| |
| Disassembly of section \.text: |
| [0-9a-f]+ <[^>]*> d8000000 ldc2 \$0,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8010000 ldc2 \$1,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8020000 ldc2 \$2,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8030000 ldc2 \$3,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8040000 ldc2 \$4,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8050000 ldc2 \$5,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8060000 ldc2 \$6,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8070000 ldc2 \$7,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8080000 ldc2 \$8,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8090000 ldc2 \$9,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80a0000 ldc2 \$10,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80b0000 ldc2 \$11,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80c0000 ldc2 \$12,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80d0000 ldc2 \$13,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80e0000 ldc2 \$14,0\(zero\) |
| [0-9a-f]+ <[^>]*> d80f0000 ldc2 \$15,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8100000 ldc2 \$16,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8110000 ldc2 \$17,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8120000 ldc2 \$18,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8130000 ldc2 \$19,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8140000 ldc2 \$20,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8150000 ldc2 \$21,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8160000 ldc2 \$22,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8170000 ldc2 \$23,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8180000 ldc2 \$24,0\(zero\) |
| [0-9a-f]+ <[^>]*> d8190000 ldc2 \$25,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81a0000 ldc2 \$26,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81b0000 ldc2 \$27,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81c0000 ldc2 \$28,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81d0000 ldc2 \$29,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81e0000 ldc2 \$30,0\(zero\) |
| [0-9a-f]+ <[^>]*> d81f0000 ldc2 \$31,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8000000 sdc2 \$0,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8010000 sdc2 \$1,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8020000 sdc2 \$2,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8030000 sdc2 \$3,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8040000 sdc2 \$4,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8050000 sdc2 \$5,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8060000 sdc2 \$6,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8070000 sdc2 \$7,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8080000 sdc2 \$8,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8090000 sdc2 \$9,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80a0000 sdc2 \$10,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80b0000 sdc2 \$11,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80c0000 sdc2 \$12,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80d0000 sdc2 \$13,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80e0000 sdc2 \$14,0\(zero\) |
| [0-9a-f]+ <[^>]*> f80f0000 sdc2 \$15,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8100000 sdc2 \$16,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8110000 sdc2 \$17,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8120000 sdc2 \$18,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8130000 sdc2 \$19,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8140000 sdc2 \$20,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8150000 sdc2 \$21,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8160000 sdc2 \$22,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8170000 sdc2 \$23,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8180000 sdc2 \$24,0\(zero\) |
| [0-9a-f]+ <[^>]*> f8190000 sdc2 \$25,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81a0000 sdc2 \$26,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81b0000 sdc2 \$27,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81c0000 sdc2 \$28,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81d0000 sdc2 \$29,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81e0000 sdc2 \$30,0\(zero\) |
| [0-9a-f]+ <[^>]*> f81f0000 sdc2 \$31,0\(zero\) |
| \.\.\. |
