| [^:]*: Assembler messages: |
| [^:]*:10: Error: bad type in SIMD instruction -- `vrmlaldavh.s16 r0,r1,q2,q3' |
| [^:]*:11: Error: bad type in SIMD instruction -- `vrmlaldavh.i32 r0,r1,q2,q3' |
| [^:]*:12: Error: bad type in SIMD instruction -- `vrmlaldavha.s16 r0,r1,q2,q3' |
| [^:]*:13: Error: bad type in SIMD instruction -- `vrmlaldavha.i32 r0,r1,q2,q3' |
| [^:]*:14: Error: bad type in SIMD instruction -- `vrmlalvh.s16 r0,r1,q2,q3' |
| [^:]*:15: Error: bad type in SIMD instruction -- `vrmlalvh.i32 r0,r1,q2,q3' |
| [^:]*:16: Error: bad type in SIMD instruction -- `vrmlalvha.s16 r0,r1,q2,q3' |
| [^:]*:17: Error: bad type in SIMD instruction -- `vrmlalvha.i32 r0,r1,q2,q3' |
| [^:]*:18: Error: bad type in SIMD instruction -- `vrmlaldavhx.u32 r0,r1,q2,q3' |
| [^:]*:19: Error: bad type in SIMD instruction -- `vrmlaldavhax.u32 r0,r1,q2,q3' |
| [^:]*:20: Error: bad type in SIMD instruction -- `vrmlaldavhx.i32 r0,r1,q2,q3' |
| [^:]*:21: Error: bad type in SIMD instruction -- `vrmlaldavhax.i32 r0,r1,q2,q3' |
| [^:]*:22: Error: bad type in SIMD instruction -- `vrmlsldavh.s16 r0,r1,q2,q3' |
| [^:]*:23: Error: bad type in SIMD instruction -- `vrmlsldavh.u32 r0,r1,q2,q3' |
| [^:]*:24: Error: bad type in SIMD instruction -- `vrmlsldavha.s16 r0,r1,q2,q3' |
| [^:]*:25: Error: bad type in SIMD instruction -- `vrmlsldavha.u32 r0,r1,q2,q3' |
| [^:]*:26: Error: bad type in SIMD instruction -- `vrmlsldavhx.s16 r0,r1,q2,q3' |
| [^:]*:27: Error: bad type in SIMD instruction -- `vrmlsldavhx.u32 r0,r1,q2,q3' |
| [^:]*:28: Error: bad type in SIMD instruction -- `vrmlsldavhax.s16 r0,r1,q2,q3' |
| [^:]*:29: Error: bad type in SIMD instruction -- `vrmlsldavhax.u32 r0,r1,q2,q3' |
| [^:]*:30: Error: Odd register not allowed here -- `vrmlaldavh.s32 r1,r1,q2,q3' |
| [^:]*:31: Error: Even register not allowed here -- `vrmlaldavh.s32 r0,r0,q2,q3' |
| [^:]*:32: Error: r13 not allowed here -- `vrmlaldavh.s32 r0,sp,q2,q3' |
| [^:]*:33: Error: r15 not allowed here -- `vrmlaldavh.s32 r0,pc,q2,q3' |
| [^:]*:34: Error: Odd register not allowed here -- `vrmlaldavha.s32 r1,r1,q2,q3' |
| [^:]*:35: Error: Even register not allowed here -- `vrmlaldavha.s32 r0,r0,q2,q3' |
| [^:]*:36: Error: r13 not allowed here -- `vrmlaldavha.s32 r0,sp,q2,q3' |
| [^:]*:37: Error: r15 not allowed here -- `vrmlaldavha.s32 r0,pc,q2,q3' |
| [^:]*:38: Error: Odd register not allowed here -- `vrmlaldavhx.s32 r1,r1,q2,q3' |
| [^:]*:39: Error: Even register not allowed here -- `vrmlaldavhx.s32 r0,r0,q2,q3' |
| [^:]*:40: Error: r13 not allowed here -- `vrmlaldavhx.s32 r0,sp,q2,q3' |
| [^:]*:41: Error: r15 not allowed here -- `vrmlaldavhx.s32 r0,pc,q2,q3' |
| [^:]*:42: Error: Odd register not allowed here -- `vrmlaldavhax.s32 r1,r1,q2,q3' |
| [^:]*:43: Error: Even register not allowed here -- `vrmlaldavhax.s32 r0,r0,q2,q3' |
| [^:]*:44: Error: r13 not allowed here -- `vrmlaldavhax.s32 r0,sp,q2,q3' |
| [^:]*:45: Error: r15 not allowed here -- `vrmlaldavhax.s32 r0,pc,q2,q3' |
| [^:]*:46: Error: Odd register not allowed here -- `vrmlalvh.s32 r1,r1,q2,q3' |
| [^:]*:47: Error: Even register not allowed here -- `vrmlalvh.s32 r0,r0,q2,q3' |
| [^:]*:48: Error: r13 not allowed here -- `vrmlalvh.s32 r0,sp,q2,q3' |
| [^:]*:49: Error: r15 not allowed here -- `vrmlalvh.s32 r0,pc,q2,q3' |
| [^:]*:50: Error: Odd register not allowed here -- `vrmlalvha.s32 r1,r1,q2,q3' |
| [^:]*:51: Error: Even register not allowed here -- `vrmlalvha.s32 r0,r0,q2,q3' |
| [^:]*:52: Error: r13 not allowed here -- `vrmlalvha.s32 r0,sp,q2,q3' |
| [^:]*:53: Error: r15 not allowed here -- `vrmlalvha.s32 r0,pc,q2,q3' |
| [^:]*:54: Error: Odd register not allowed here -- `vrmlsldavh.s32 r1,r1,q2,q3' |
| [^:]*:55: Error: Even register not allowed here -- `vrmlsldavh.s32 r0,r0,q2,q3' |
| [^:]*:56: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:57: Error: r15 not allowed here -- `vrmlsldavh.s32 r0,pc,q2,q3' |
| [^:]*:58: Error: Odd register not allowed here -- `vrmlsldavha.s32 r1,r1,q2,q3' |
| [^:]*:59: Error: Even register not allowed here -- `vrmlsldavha.s32 r0,r0,q2,q3' |
| [^:]*:60: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:61: Error: r15 not allowed here -- `vrmlsldavha.s32 r0,pc,q2,q3' |
| [^:]*:62: Error: Odd register not allowed here -- `vrmlsldavhx.s32 r1,r1,q2,q3' |
| [^:]*:63: Error: Even register not allowed here -- `vrmlsldavhx.s32 r0,r0,q2,q3' |
| [^:]*:64: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:65: Error: r15 not allowed here -- `vrmlsldavhx.s32 r0,pc,q2,q3' |
| [^:]*:66: Error: Odd register not allowed here -- `vrmlsldavhax.s32 r1,r1,q2,q3' |
| [^:]*:67: Error: Even register not allowed here -- `vrmlsldavhax.s32 r0,r0,q2,q3' |
| [^:]*:68: Warning: instruction is UNPREDICTABLE with SP operand |
| [^:]*:69: Error: r15 not allowed here -- `vrmlsldavhax.s32 r0,pc,q2,q3' |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:70: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:71: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:72: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:73: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:75: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:78: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:79: Warning: instruction is UNPREDICTABLE in an IT block |
| [^:]*:81: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3' |
| [^:]*:82: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3' |
| [^:]*:84: Error: syntax error -- `vrmlaldavheq.s32 r0,r1,q2,q3' |
| [^:]*:85: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavht.s32 r0,r1,q2,q3' |
| [^:]*:87: Error: instruction missing MVE vector predication code -- `vrmlaldavh.s32 r0,r1,q2,q3' |
| [^:]*:89: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:90: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:92: Error: syntax error -- `vrmlaldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:93: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhat.s32 r0,r1,q2,q3' |
| [^:]*:95: Error: instruction missing MVE vector predication code -- `vrmlaldavha.s32 r0,r1,q2,q3' |
| [^:]*:97: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:98: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:100: Error: syntax error -- `vrmlaldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:101: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhxt.s32 r0,r1,q2,q3' |
| [^:]*:103: Error: instruction missing MVE vector predication code -- `vrmlaldavhx.s32 r0,r1,q2,q3' |
| [^:]*:105: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:106: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:108: Error: syntax error -- `vrmlaldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:109: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlaldavhaxt.s32 r0,r1,q2,q3' |
| [^:]*:111: Error: instruction missing MVE vector predication code -- `vrmlaldavhax.s32 r0,r1,q2,q3' |
| [^:]*:113: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3' |
| [^:]*:114: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3' |
| [^:]*:116: Error: syntax error -- `vrmlalvheq.s32 r0,r1,q2,q3' |
| [^:]*:117: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvht.s32 r0,r1,q2,q3' |
| [^:]*:119: Error: instruction missing MVE vector predication code -- `vrmlalvh.s32 r0,r1,q2,q3' |
| [^:]*:121: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3' |
| [^:]*:122: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3' |
| [^:]*:124: Error: syntax error -- `vrmlalvhaeq.s32 r0,r1,q2,q3' |
| [^:]*:125: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlalvhat.s32 r0,r1,q2,q3' |
| [^:]*:127: Error: instruction missing MVE vector predication code -- `vrmlalvha.s32 r0,r1,q2,q3' |
| [^:]*:129: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3' |
| [^:]*:130: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3' |
| [^:]*:132: Error: syntax error -- `vrmlsldavheq.s32 r0,r1,q2,q3' |
| [^:]*:133: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavht.s32 r0,r1,q2,q3' |
| [^:]*:135: Error: instruction missing MVE vector predication code -- `vrmlsldavh.s32 r0,r1,q2,q3' |
| [^:]*:137: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:138: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:140: Error: syntax error -- `vrmlsldavhaeq.s32 r0,r1,q2,q3' |
| [^:]*:141: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhat.s32 r0,r1,q2,q3' |
| [^:]*:143: Error: instruction missing MVE vector predication code -- `vrmlsldavha.s32 r0,r1,q2,q3' |
| [^:]*:145: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:146: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:148: Error: syntax error -- `vrmlsldavhxeq.s32 r0,r1,q2,q3' |
| [^:]*:149: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhxt.s32 r0,r1,q2,q3' |
| [^:]*:151: Error: instruction missing MVE vector predication code -- `vrmlsldavhx.s32 r0,r1,q2,q3' |
| [^:]*:153: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:154: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:156: Error: syntax error -- `vrmlsldavhaxeq.s32 r0,r1,q2,q3' |
| [^:]*:157: Error: vector predicated instruction should be in VPT/VPST block -- `vrmlsldavhaxt.s32 r0,r1,q2,q3' |
| [^:]*:159: Error: instruction missing MVE vector predication code -- `vrmlsldavhax.s32 r0,r1,q2,q3' |