| //Original:/proj/frio/dv/testcases/core/c_dsp32mac_dr_a1a0/c_dsp32mac_dr_a1a0.dsp |
| // Spec Reference: dsp32mac dr_a1a0 |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| A1 = A0 = 0; |
| R0 = 0; |
| ASTAT = R0; |
| |
| // The result accumulated in A , and stored to a reg half |
| imm32 r0, 0x13545abd; |
| imm32 r1, 0xb2bcfec7; |
| imm32 r2, 0xc1348679; |
| imm32 r3, 0xd0049007; |
| imm32 r4, 0xefbc5569; |
| imm32 r5, 0xcd35560b; |
| imm32 r6, 0xe00c807d; |
| imm32 r7, 0xf78e9008; |
| A1 = A0 = 0; |
| R6.H = (A1 += R0.L * R0.L), R6.L = (A0 = R0.L * R0.L); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1.H = (A1 += R2.L * R3.L), R1.L = (A0 -= R2.H * R3.L); |
| P3 = A1.w; |
| P4 = A0.w; |
| R2.H = (A1 -= R4.L * R5.L), R2.L = (A0 += R4.H * R5.H); |
| P5 = A1.w; |
| FP = A0.w; |
| R3.H = (A1 += R0.L * R7.L), R3.L = (A0 += R0.L * R7.H); |
| R4 = A1.w; |
| R5 = A0.w; |
| CHECKREG r0, 0x13545ABD; |
| CHECKREG r1, 0x7FFF0964; |
| CHECKREG r2, 0x71380FD8; |
| CHECKREG r3, 0x21D909DC; |
| CHECKREG r4, 0x21D8C27A; |
| CHECKREG r5, 0x09DB89BE; |
| CHECKREG r6, 0x40534053; |
| CHECKREG r7, 0xF78E9008; |
| CHECKREG p1, 0x4052DF12; |
| CHECKREG p2, 0x4052DF12; |
| CHECKREG p3, 0xAAA259B0; |
| CHECKREG p4, 0x0963CE3A; |
| CHECKREG p5, 0x713876AA; |
| CHECKREG fp, 0x0FD82A12; |
| |
| imm32 r0, 0x13545abd; |
| imm32 r1, 0x22bcfec7; |
| imm32 r2, 0x43348679; |
| imm32 r3, 0x50049007; |
| imm32 r4, 0x6fbc5569; |
| imm32 r5, 0x7d35560b; |
| imm32 r6, 0x800c807d; |
| imm32 r7, 0xf98e9008; |
| A1 = A0 = 0; |
| R0.H = (A1 += R1.L * R0.H), R0.L = (A0 = R1.L * R0.L); |
| P1 = A1.w; |
| P2 = A0.w; |
| R6.H = (A1 += R2.L * R2.H), R6.L = (A0 -= R2.H * R2.L); |
| P3 = A1.w; |
| P4 = A0.w; |
| R2.H = (A1 -= R4.L * R5.H), R2.L = (A0 += R4.H * R5.H); |
| P5 = A1.w; |
| FP = A0.w; |
| R3.H = (A1 += R3.L * R7.H), R3.L = (A0 -= R3.L * R7.H); |
| R4 = A1.w; |
| R5 = A0.w; |
| CHECKREG r0, 0xFFD1FF22; |
| CHECKREG r1, 0x22BCFEC7; |
| CHECKREG r2, 0x80007FFF; |
| CHECKREG r3, 0x80007FFF; |
| CHECKREG r4, 0x721A320A; |
| CHECKREG r5, 0xA6989CC2; |
| CHECKREG r6, 0xC0033EF0; |
| CHECKREG r7, 0xF98E9008; |
| CHECKREG p1, 0xFFD0BC98; |
| CHECKREG p2, 0xFF221DD6; |
| CHECKREG p3, 0xC002B3C0; |
| CHECKREG p4, 0x3EF026AE; |
| CHECKREG p5, 0x6C76CC46; |
| CHECKREG fp, 0xAC3C0286; |
| |
| imm32 r0, 0x13545abd; |
| imm32 r1, 0x42bcfec7; |
| imm32 r2, 0x51348679; |
| imm32 r3, 0x60049007; |
| imm32 r4, 0x7fbc5569; |
| imm32 r5, 0x8d35560b; |
| imm32 r6, 0x900c807d; |
| imm32 r7, 0xa78e9008; |
| A1 = A0 = 0; |
| R0.H = (A1 -= R1.H * R0.L), R0.L = (A0 = R1.L * R0.L); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1.H = (A1 += R2.H * R3.L), R1.L = (A0 -= R2.H * R3.L); |
| P3 = A1.w; |
| P4 = A0.w; |
| R2.H = (A1 = R4.H * R5.L), R2.L = (A0 += R4.H * R5.H); |
| P5 = A1.w; |
| FP = A0.w; |
| R3.H = (A1 -= R6.H * R7.L), R3.L = (A0 += R6.L * R7.H); |
| R4 = A1.w; |
| R5 = A0.w; |
| CHECKREG r0, 0xD0B1FF22; |
| CHECKREG r1, 0x89A8462B; |
| CHECKREG r2, 0x55DDD39D; |
| CHECKREG r3, 0xF3EF2BB9; |
| CHECKREG r4, 0xF3EEC968; |
| CHECKREG r5, 0x2BB8C982; |
| CHECKREG r6, 0x900C807D; |
| CHECKREG r7, 0xA78E9008; |
| CHECKREG p1, 0xD0B14668; |
| CHECKREG p2, 0xFF221DD6; |
| CHECKREG p3, 0x89A83740; |
| CHECKREG p4, 0x462B2CFE; |
| CHECKREG p5, 0x55DD4A28; |
| CHECKREG fp, 0xD39D28D6; |
| |
| imm32 r0, 0x03545abd; |
| imm32 r1, 0xb3bcfec7; |
| imm32 r2, 0x24348679; |
| imm32 r3, 0x60049007; |
| imm32 r4, 0x7fbc5569; |
| imm32 r5, 0x9d35560b; |
| imm32 r6, 0xa00c807d; |
| imm32 r7, 0x078e9008; |
| A1 = A0 = 0; |
| R0.H = (A1 += R1.H * R0.H), R0.L = (A0 -= R1.L * R0.L); |
| P1 = A1.w; |
| P2 = A0.w; |
| R1.H = (A1 -= R2.H * R3.H), R1.L = (A0 = R2.H * R3.L); |
| P3 = A1.w; |
| P4 = A0.w; |
| R2.H = (A1 = R4.H * R5.H), R2.L = (A0 += R4.H * R5.H); |
| P5 = A1.w; |
| FP = A0.w; |
| R3.H = (A1 += R6.H * R7.H), R3.L = (A0 -= R6.L * R7.H); |
| R4 = A1.w; |
| R5 = A0.w; |
| CHECKREG r0, 0xFE0400DE; |
| CHECKREG r1, 0xE2DCE054; |
| CHECKREG r2, 0x9D698000; |
| CHECKREG r3, 0x97C08545; |
| CHECKREG r4, 0x97BFB128; |
| CHECKREG r5, 0x85449604; |
| CHECKREG r6, 0xA00C807D; |
| CHECKREG r7, 0x078E9008; |
| CHECKREG p1, 0xFE045B60; |
| CHECKREG p2, 0x00DDE22A; |
| CHECKREG p3, 0xE2DC39C0; |
| CHECKREG p4, 0xE0547AD8; |
| CHECKREG p5, 0x9D697BD8; |
| CHECKREG fp, 0x7DBDF6B0; |
| |
| pass |