| //Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp |
| // Spec Reference: dsp32shift ashift/ashift |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| |
| |
| // ashift/ashift : positive data, count (+)=left (half reg) |
| // d_reg = ashift/ashift (d BY d_lo) |
| // Rx by RLx |
| imm32 r0, 0x01230000; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R5 = ASHIFT R0 BY R0.L (V); |
| R0 = ASHIFT R1 BY R0.L (V); |
| R1 = ASHIFT R2 BY R0.L (V); |
| R2 = ASHIFT R3 BY R0.L (V); |
| R3 = ASHIFT R4 BY R0.L (V); |
| R4 = ASHIFT R5 BY R0.L (V); |
| R7 = ASHIFT R6 BY R0.L (V); |
| R6 = ASHIFT R7 BY R0.L (V); |
| CHECKREG r0, 0x12345678; |
| CHECKREG r1, 0x00230067; |
| CHECKREG r2, 0x00340078; |
| CHECKREG r3, 0x0045FF89; |
| CHECKREG r4, 0x00010000; |
| CHECKREG r5, 0x01230000; |
| CHECKREG r6, 0x0000FFFF; |
| CHECKREG r7, 0x0067FFAB; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R1.L = 5; |
| R2 = ASHIFT R0 BY R1.L (V); |
| R3 = ASHIFT R1 BY R1.L (V); |
| R4 = ASHIFT R2 BY R1.L (V); |
| R5 = ASHIFT R3 BY R1.L (V); |
| R6 = ASHIFT R4 BY R1.L (V); |
| R7 = ASHIFT R5 BY R1.L (V); |
| R0 = ASHIFT R6 BY R1.L (V); |
| R1 = ASHIFT R7 BY R1.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x24600040; |
| CHECKREG r3, 0x468000A0; |
| CHECKREG r4, 0x8C000800; |
| CHECKREG r5, 0xD0001400; |
| CHECKREG r6, 0x80000000; |
| CHECKREG r7, 0x00008000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R2 = 15; |
| R3 = ASHIFT R0 BY R2.L (V); |
| R4 = ASHIFT R1 BY R2.L (V); |
| R5 = ASHIFT R2 BY R2.L (V); |
| R6 = ASHIFT R3 BY R2.L (V); |
| R7 = ASHIFT R4 BY R2.L (V); |
| R0 = ASHIFT R5 BY R2.L (V); |
| R1 = ASHIFT R6 BY R2.L (V); |
| R2 = ASHIFT R7 BY R2.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x80000000; |
| CHECKREG r4, 0x00000000; |
| CHECKREG r5, 0x00008000; |
| CHECKREG r6, 0x00000000; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R3.L = 16; |
| R4 = ASHIFT R0 BY R3.L (V); |
| R5 = ASHIFT R1 BY R3.L (V); |
| R6 = ASHIFT R2 BY R3.L (V); |
| R7 = ASHIFT R3 BY R3.L (V); |
| R0 = ASHIFT R4 BY R3.L (V); |
| R1 = ASHIFT R5 BY R3.L (V); |
| R2 = ASHIFT R6 BY R3.L (V); |
| R3 = ASHIFT R7 BY R3.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x00000000; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x00000000; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R4.L = -1; |
| R0 = ASHIFT R0 BY R4.L (V); |
| R1 = ASHIFT R1 BY R4.L (V); |
| R2 = ASHIFT R2 BY R4.L (V); |
| R3 = ASHIFT R3 BY R4.L (V); |
| R4 = ASHIFT R4 BY R4.L (V); |
| R5 = ASHIFT R5 BY R4.L (V); |
| R6 = ASHIFT R6 BY R4.L (V); |
| R7 = ASHIFT R7 BY R4.L (V); |
| CHECKREG r0, 0x00910001; |
| CHECKREG r1, 0x091A2B3C; |
| CHECKREG r2, 0x11A233C4; |
| CHECKREG r3, 0x1A2B3C4D; |
| CHECKREG r4, 0x22B3FFFF; |
| CHECKREG r5, 0x2B3CCD5E; |
| CHECKREG r6, 0x33C4D5E6; |
| CHECKREG r7, 0x3C4DDE6F; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R5.L = -6; |
| R6 = ASHIFT R0 BY R5.L (V); |
| R7 = ASHIFT R1 BY R5.L (V); |
| R0 = ASHIFT R2 BY R5.L (V); |
| R1 = ASHIFT R3 BY R5.L (V); |
| R2 = ASHIFT R4 BY R5.L (V); |
| R3 = ASHIFT R5 BY R5.L (V); |
| R4 = ASHIFT R6 BY R5.L (V); |
| R5 = ASHIFT R7 BY R5.L (V); |
| CHECKREG r0, 0x008D019E; |
| CHECKREG r1, 0x00D101E2; |
| CHECKREG r2, 0x0115FE26; |
| CHECKREG r3, 0x0159FFFF; |
| CHECKREG r4, 0x00000000; |
| CHECKREG r5, 0x00010005; |
| CHECKREG r6, 0x00040000; |
| CHECKREG r7, 0x00480159; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R6.L = -15; |
| R7 = ASHIFT R0 BY R6.L (V); |
| R0 = ASHIFT R1 BY R6.L (V); |
| R1 = ASHIFT R2 BY R6.L (V); |
| R2 = ASHIFT R3 BY R6.L (V); |
| R3 = ASHIFT R4 BY R6.L (V); |
| R4 = ASHIFT R5 BY R6.L (V); |
| R5 = ASHIFT R6 BY R6.L (V); |
| R6 = ASHIFT R7 BY R6.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x0000FFFF; |
| CHECKREG r4, 0x0000FFFF; |
| CHECKREG r5, 0x0000FFFF; |
| CHECKREG r6, 0x00000000; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R7.L = -16; |
| R0 = ASHIFT R0 BY R7.L (V); |
| R1 = ASHIFT R1 BY R7.L (V); |
| R2 = ASHIFT R2 BY R7.L (V); |
| R3 = ASHIFT R3 BY R7.L (V); |
| R4 = ASHIFT R4 BY R7.L (V); |
| R5 = ASHIFT R5 BY R7.L (V); |
| R6 = ASHIFT R6 BY R7.L (V); |
| R7 = ASHIFT R7 BY R7.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x0000FFFF; |
| CHECKREG r5, 0x0000FFFF; |
| CHECKREG r6, 0x0000FFFF; |
| CHECKREG r7, 0x0000FFFF; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R0.L = 4; |
| //r0 = ashift/ashift (r0 by rl0); |
| R1 = ASHIFT R1 BY R0.L (V); |
| R2 = ASHIFT R2 BY R0.L (V); |
| R3 = ASHIFT R3 BY R0.L (V); |
| R4 = ASHIFT R4 BY R0.L (V); |
| R5 = ASHIFT R5 BY R0.L (V); |
| R6 = ASHIFT R6 BY R0.L (V); |
| R7 = ASHIFT R7 BY R0.L (V); |
| CHECKREG r0, 0x01230004; |
| CHECKREG r1, 0x23406780; |
| CHECKREG r2, 0x34507890; |
| CHECKREG r3, 0x456089A0; |
| CHECKREG r4, 0x56709AB0; |
| CHECKREG r5, 0x6780ABC0; |
| CHECKREG r6, 0x7890BCD0; |
| CHECKREG r7, 0x89A0CDE0; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R1.L = 6; |
| R0 = ASHIFT R0 BY R1.L (V); |
| //r1 = ashift/ashift (r1 by rl1); |
| R2 = ASHIFT R2 BY R1.L (V); |
| R3 = ASHIFT R3 BY R1.L (V); |
| R4 = ASHIFT R4 BY R1.L (V); |
| R5 = ASHIFT R5 BY R1.L (V); |
| R6 = ASHIFT R6 BY R1.L (V); |
| R7 = ASHIFT R7 BY R1.L (V); |
| CHECKREG r0, 0x48C00080; |
| CHECKREG r1, 0x12340006; |
| CHECKREG r2, 0xD140E240; |
| CHECKREG r3, 0x15802680; |
| CHECKREG r4, 0x59C06AC0; |
| CHECKREG r5, 0x9E00AF00; |
| CHECKREG r6, 0xE240F340; |
| CHECKREG r7, 0x26803780; |
| |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R2.L = 15; |
| R0 = ASHIFT R0 BY R2.L (V); |
| R1 = ASHIFT R1 BY R2.L (V); |
| //r2 = ashift/ashift (r2 by rl2); |
| R3 = ASHIFT R3 BY R2.L (V); |
| R4 = ASHIFT R4 BY R2.L (V); |
| R5 = ASHIFT R5 BY R2.L (V); |
| R6 = ASHIFT R6 BY R2.L (V); |
| R7 = ASHIFT R7 BY R2.L (V); |
| CHECKREG r0, 0x80000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x2345000F; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x80008000; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x80008000; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R3.L = 16; |
| R0 = ASHIFT R0 BY R3.L (V); |
| R1 = ASHIFT R1 BY R3.L (V); |
| R2 = ASHIFT R2 BY R3.L (V); |
| //r3 = ashift/ashift (r3 by rl3); |
| R4 = ASHIFT R4 BY R3.L (V); |
| R5 = ASHIFT R5 BY R3.L (V); |
| R6 = ASHIFT R6 BY R3.L (V); |
| R7 = ASHIFT R7 BY R3.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x34560010; |
| CHECKREG r4, 0x00000000; |
| CHECKREG r5, 0x00000000; |
| CHECKREG r6, 0x00000000; |
| CHECKREG r7, 0x00000000; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R4.L = -9; |
| R0 = ASHIFT R0 BY R4.L (V); |
| R1 = ASHIFT R1 BY R4.L (V); |
| R2 = ASHIFT R2 BY R4.L (V); |
| R3 = ASHIFT R3 BY R4.L (V); |
| //r4 = ashift/ashift (r4 by rl4); |
| R5 = ASHIFT R5 BY R4.L (V); |
| R6 = ASHIFT R6 BY R4.L (V); |
| R7 = ASHIFT R7 BY R4.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x0009002B; |
| CHECKREG r2, 0x00110033; |
| CHECKREG r3, 0x001A003C; |
| CHECKREG r4, 0x4567FFF7; |
| CHECKREG r5, 0x002BFFCD; |
| CHECKREG r6, 0x0033FFD5; |
| CHECKREG r7, 0x003CFFDE; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R5.L = -14; |
| R0 = ASHIFT R0 BY R5.L (V); |
| R1 = ASHIFT R1 BY R5.L (V); |
| R2 = ASHIFT R2 BY R5.L (V); |
| R3 = ASHIFT R3 BY R5.L (V); |
| R4 = ASHIFT R4 BY R5.L (V); |
| //r5 = ashift/ashift (r5 by rl5); |
| R6 = ASHIFT R6 BY R5.L (V); |
| R7 = ASHIFT R7 BY R5.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000001; |
| CHECKREG r2, 0x00000001; |
| CHECKREG r3, 0x00000001; |
| CHECKREG r4, 0x0001FFFE; |
| CHECKREG r5, 0x5678FFF2; |
| CHECKREG r6, 0x0001FFFE; |
| CHECKREG r7, 0x0001FFFE; |
| |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R6.L = -15; |
| R0 = ASHIFT R0 BY R6.L (V); |
| R1 = ASHIFT R1 BY R6.L (V); |
| R2 = ASHIFT R2 BY R6.L (V); |
| R3 = ASHIFT R3 BY R6.L (V); |
| R4 = ASHIFT R4 BY R6.L (V); |
| R5 = ASHIFT R5 BY R6.L (V); |
| //r6 = ashift/ashift (r6 by rl6); |
| R7 = ASHIFT R7 BY R6.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x0000FFFF; |
| CHECKREG r5, 0x0000FFFF; |
| CHECKREG r6, 0x6789FFF1; |
| CHECKREG r7, 0x0000FFFF; |
| |
| imm32 r0, 0x01230002; |
| imm32 r1, 0x12345678; |
| imm32 r2, 0x23456789; |
| imm32 r3, 0x3456789a; |
| imm32 r4, 0x456789ab; |
| imm32 r5, 0x56789abc; |
| imm32 r6, 0x6789abcd; |
| imm32 r7, 0x789abcde; |
| R7.L = -16; |
| R0 = ASHIFT R0 BY R7.L (V); |
| R1 = ASHIFT R1 BY R7.L (V); |
| R2 = ASHIFT R2 BY R7.L (V); |
| R3 = ASHIFT R3 BY R7.L (V); |
| R4 = ASHIFT R4 BY R7.L (V); |
| R5 = ASHIFT R5 BY R7.L (V); |
| R6 = ASHIFT R6 BY R7.L (V); |
| R7 = ASHIFT R7 BY R7.L (V); |
| CHECKREG r0, 0x00000000; |
| CHECKREG r1, 0x00000000; |
| CHECKREG r2, 0x00000000; |
| CHECKREG r3, 0x00000000; |
| CHECKREG r4, 0x0000ffff; |
| CHECKREG r5, 0x0000ffff; |
| CHECKREG r6, 0x0000ffff; |
| CHECKREG r7, 0x0000ffff; |
| |
| pass |
