| //Original:/testcases/core/c_dsp32shift_vmax/c_dsp32shift_vmax.dsp |
| // Spec Reference: dsp32shift vmax |
| # mach: bfin |
| |
| .include "testutils.inc" |
| start |
| |
| |
| |
| imm32 r0, 0x11001001; |
| imm32 r1, 0x11001001; |
| imm32 r2, 0x12345678; |
| imm32 r3, 0x11001003; |
| imm32 r4, 0x11001004; |
| imm32 r5, 0x11001005; |
| imm32 r6, 0x11001006; |
| imm32 r7, 0x11001007; |
| A0 = R2; |
| R0.L = VIT_MAX( R0 ) (ASL); |
| R1.L = VIT_MAX( R1 ) (ASL); |
| R2.L = VIT_MAX( R2 ) (ASL); |
| R3.L = VIT_MAX( R3 ) (ASL); |
| R4.L = VIT_MAX( R4 ) (ASL); |
| R5.L = VIT_MAX( R5 ) (ASL); |
| R6.L = VIT_MAX( R6 ) (ASL); |
| R7.L = VIT_MAX( R7 ) (ASL); |
| CHECKREG r0, 0x11001100; |
| CHECKREG r1, 0x11001100; |
| CHECKREG r2, 0x12345678; |
| CHECKREG r3, 0x11001100; |
| CHECKREG r4, 0x11001100; |
| CHECKREG r5, 0x11001100; |
| CHECKREG r6, 0x11001100; |
| CHECKREG r7, 0x11001100; |
| |
| imm32 r0, 0xa1001001; |
| imm32 r1, 0x1b001001; |
| imm32 r2, 0x11c01002; |
| imm32 r3, 0x110d1003; |
| imm32 r4, 0x1100e004; |
| imm32 r5, 0x11001f05; |
| imm32 r6, 0x11001006; |
| imm32 r7, 0x11001001; |
| R1.L = VIT_MAX( R0 ) (ASL); |
| R2.L = VIT_MAX( R1 ) (ASL); |
| R3.L = VIT_MAX( R2 ) (ASL); |
| R4.L = VIT_MAX( R3 ) (ASL); |
| R5.L = VIT_MAX( R4 ) (ASL); |
| R6.L = VIT_MAX( R5 ) (ASL); |
| R7.L = VIT_MAX( R6 ) (ASL); |
| R0.L = VIT_MAX( R7 ) (ASL); |
| CHECKREG r0, 0xA1001B00; |
| CHECKREG r1, 0x1B001001; |
| CHECKREG r2, 0x11C01B00; |
| CHECKREG r3, 0x110D1B00; |
| CHECKREG r4, 0x11001B00; |
| CHECKREG r5, 0x11001B00; |
| CHECKREG r6, 0x11001B00; |
| CHECKREG r7, 0x11001B00; |
| |
| |
| imm32 r0, 0x20000000; |
| imm32 r1, 0x4300c001; |
| imm32 r2, 0x4040c002; |
| imm32 r3, 0x40056003; |
| imm32 r4, 0x4000c704; |
| imm32 r5, 0x4000c085; |
| imm32 r6, 0x4000c096; |
| imm32 r7, 0x4000c000; |
| R0.L = VIT_MAX( R0 ) (ASR); |
| R1.L = VIT_MAX( R1 ) (ASR); |
| R2.L = VIT_MAX( R2 ) (ASR); |
| R3.L = VIT_MAX( R3 ) (ASR); |
| R4.L = VIT_MAX( R4 ) (ASR); |
| R5.L = VIT_MAX( R5 ) (ASR); |
| R6.L = VIT_MAX( R6 ) (ASR); |
| R7.L = VIT_MAX( R7 ) (ASR); |
| CHECKREG r0, 0x20002000; |
| CHECKREG r1, 0x4300C001; |
| CHECKREG r2, 0x4040C002; |
| CHECKREG r3, 0x40056003; |
| CHECKREG r4, 0x40004000; |
| CHECKREG r5, 0x40004000; |
| CHECKREG r6, 0x40004000; |
| CHECKREG r7, 0x4000C000; |
| |
| imm32 r0, 0x10000000; |
| imm32 r1, 0x4200c001; |
| imm32 r2, 0x4030c002; |
| imm32 r3, 0x4004c003; |
| imm32 r4, 0x40005004; |
| imm32 r5, 0x4000c605; |
| imm32 r6, 0x4000c076; |
| imm32 r7, 0x4000c008; |
| R2.L = VIT_MAX( R0 ) (ASR); |
| R3.L = VIT_MAX( R1 ) (ASR); |
| R4.L = VIT_MAX( R2 ) (ASR); |
| R5.L = VIT_MAX( R3 ) (ASR); |
| R6.L = VIT_MAX( R4 ) (ASR); |
| R7.L = VIT_MAX( R5 ) (ASR); |
| R0.L = VIT_MAX( R6 ) (ASR); |
| R1.L = VIT_MAX( R7 ) (ASR); |
| CHECKREG r0, 0x10004030; |
| CHECKREG r1, 0x42004000; |
| CHECKREG r2, 0x40301000; |
| CHECKREG r3, 0x4004C001; |
| CHECKREG r4, 0x40004030; |
| CHECKREG r5, 0x4000C001; |
| CHECKREG r6, 0x40004030; |
| CHECKREG r7, 0x40004000; |
| |
| |
| pass |
