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| .IX Title "AS 1" |
| .TH AS 1 "binutils-2.11.90" "2001-06-12" "GNU" |
| .UC |
| .SH "NAME" |
| \&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler. |
| .SH "SYNOPSIS" |
| .IX Header "SYNOPSIS" |
| as [ \-a[cdhlns][=file] ] [ \-D ] [ \-\-defsym \fIsym\fR=\fIval\fR ] |
| [ \-f ] [ \-\-gstabs ] [ \-\-gdwarf2 ] [ \-\-help ] [ \-I \fIdir\fR ] |
| [ \-J ] [ \-K ] [ \-L ] |
| [ \-\-listing\*(--lhs-width=NUM ][ \-\-listing-lhs-width2=NUM ] |
| [ \-\-listing-rhs-width=NUM ][ \-\-listing-cont-lines=NUM ] |
| [ \-\-keep-locals ] [ \-o \fIobjfile\fR ] [ \-R ] [ \-\-statistics ] [ \-v ] |
| [ \-version ] [ \-\-version ] [ \-W ] [ \-\-warn ] [ \-\-fatal-warnings ] |
| [ \-w ] [ \-x ] [ \-Z ] [ \-\-target-help ] |
| [ \-marc[5|6|7|8] ] |
| [ \-EB | \-EL ] |
| [ \-m[arm]1 | \-m[arm]2 | \-m[arm]250 | \-m[arm]3 | |
| \-m[arm]6 | \-m[arm]60 | \-m[arm]600 | \-m[arm]610 | |
| \-m[arm]620 | \-m[arm]7[t][[d]m[i]][fe] | \-m[arm]70 | |
| \-m[arm]700 | \-m[arm]710[c] | \-m[arm]7100 | |
| \-m[arm]7500 | \-m[arm]8 | \-m[arm]810 | \-m[arm]9 | |
| \-m[arm]920 | \-m[arm]920t | \-m[arm]9tdmi | |
| \-mstrongarm | \-mstrongarm110 | \-mstrongarm1100 ] |
| [ \-m[arm]v2 | \-m[arm]v2a | \-m[arm]v3 | \-m[arm]v3m | |
| \-m[arm]v4 | \-m[arm]v4t | \-m[arm]v5 | \-[arm]v5t | |
| \-[arm]v5te ] |
| [ \-mthumb | \-mall ] |
| [ \-mfpa10 | \-mfpa11 | \-mfpe-old | \-mno-fpu ] |
| [ \-EB | \-EL ] |
| [ \-mapcs-32 | \-mapcs-26 | \-mapcs-float | |
| \-mapcs-reentrant ] |
| [ \-mthumb-interwork ] [ \-moabi ] [ \-k ] |
| [ \-O ] |
| [ \-O | \-n | \-N ] |
| [ \-mb | \-me ] |
| [ \-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite |
| \-Av8plus | \-Av8plusa | \-Av9 | \-Av9a ] |
| [ \-xarch=v8plus | \-xarch=v8plusa ] [ \-bump ] |
| [ \-32 | \-64 ] |
| [ \-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | |
| \-AKC | \-AMC ] |
| [ \-b ] [ \-no-relax ] |
| [ \-\-m32rx | \-\-[no-]warn-explicit-parallel-conflicts | |
| \-\-W[n]p ] |
| [ \-l ] [ \-m68000 | \-m68010 | \-m68020 | ... ] |
| [ \-jsri2bsr ] [ \-sifilter ] [ \-relax ] |
| [ \-mcpu=[210|340] ] |
| [ \-m68hc11 | \-m68hc12 ] |
| [ \-\-force-long-branchs ] [ \-\-short-branchs ] |
| [ \-\-strict-direct-mode ] [ \-\-print-insn-syntax ] |
| [ \-\-print-opcodes ] [ \-\-generate-example ] |
| [ \-nocpp ] [ \-EL ] [ \-EB ] [ \-G \fInum\fR ] [ \-mcpu=\fI\s-1CPU\s0\fR ] |
| [ \-mips1 ] [ \-mips2 ] [ \-mips3 ] [ \-mips4 ] [ \-mips5 ] |
| [ \-mips32 ] [ \-mips64 ] |
| [ \-m4650 ] [ \-no-m4650 ] |
| [ \-\-trap ] [ \-\-break ] [ \-n ] |
| [ \-\-emulation=\fIname\fR ] |
| [ \*(-- | \fIfiles\fR ... ] |
| .SH "DESCRIPTION" |
| .IX Header "DESCRIPTION" |
| \&\s-1GNU\s0 \f(CW\*(C`as\*(C'\fR is really a family of assemblers. |
| If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you |
| should find a fairly similar environment when you use it on another |
| architecture. Each version has much in common with the others, |
| including object file formats, most assembler directives (often called |
| \&\fIpseudo-ops\fR) and assembler syntax. |
| .PP |
| \&\f(CW\*(C`as\*(C'\fR is primarily intended to assemble the output of the |
| \&\s-1GNU\s0 C compiler for use by the linker |
| \&. Nevertheless, we've tried to make \f(CW\*(C`as\*(C'\fR |
| assemble correctly everything that other assemblers for the same |
| machine would assemble. |
| Any exceptions are documented explicitly. |
| This doesn't mean \f(CW\*(C`as\*(C'\fR always uses the same syntax as another |
| assembler for the same architecture; for example, we know of several |
| incompatible versions of 680x0 assembly language syntax. |
| .PP |
| Each time you run \f(CW\*(C`as\*(C'\fR it assembles exactly one source |
| program. The source program is made up of one or more files. |
| (The standard input is also a file.) |
| .PP |
| You give \f(CW\*(C`as\*(C'\fR a command line that has zero or more input file |
| names. The input files are read (from left file name to right). A |
| command line argument (in any position) that has no special meaning |
| is taken to be an input file name. |
| .PP |
| If you give \f(CW\*(C`as\*(C'\fR no file names it attempts to read one input file |
| from the \f(CW\*(C`as\*(C'\fR standard input, which is normally your terminal. You |
| may have to type \fBctl-D\fR to tell \f(CW\*(C`as\*(C'\fR there is no more program |
| to assemble. |
| .PP |
| Use \fB\--\fR if you need to explicitly name the standard input file |
| in your command line. |
| .PP |
| If the source is empty, \f(CW\*(C`as\*(C'\fR produces a small, empty object |
| file. |
| .PP |
| \&\f(CW\*(C`as\*(C'\fR may write warnings and error messages to the standard error |
| file (usually your terminal). This should not happen when a compiler |
| runs \f(CW\*(C`as\*(C'\fR automatically. Warnings report an assumption made so |
| that \f(CW\*(C`as\*(C'\fR could keep assembling a flawed program; errors report a |
| grave problem that stops the assembly. |
| .PP |
| If you are invoking \f(CW\*(C`as\*(C'\fR via the \s-1GNU\s0 C compiler (version 2), |
| you can use the \fB\-Wa\fR option to pass arguments through to the assembler. |
| The assembler arguments must be separated from each other (and the \fB\-Wa\fR) |
| by commas. For example: |
| .PP |
| .Vb 1 |
| \& gcc -c -g -O -Wa,-alh,-L file.c |
| .Ve |
| This passes two options to the assembler: \fB\-alh\fR (emit a listing to |
| standard output with with high-level and assembly source) and \fB\-L\fR (retain |
| local symbols in the symbol table). |
| .PP |
| Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler |
| command-line options are automatically passed to the assembler by the compiler. |
| (You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see |
| precisely what options it passes to each compilation pass, including the |
| assembler.) |
| .SH "OPTIONS" |
| .IX Header "OPTIONS" |
| .Ip "\f(CW\*(C`\-a[cdhlmns]\*(C'\fR" 4 |
| .IX Item "-a[cdhlmns]" |
| Turn on listings, in any of a variety of ways: |
| .RS 4 |
| .Ip "\f(CW\*(C`\-ac\*(C'\fR" 4 |
| .IX Item "-ac" |
| omit false conditionals |
| .Ip "\f(CW\*(C`\-ad\*(C'\fR" 4 |
| .IX Item "-ad" |
| omit debugging directives |
| .Ip "\f(CW\*(C`\-ah\*(C'\fR" 4 |
| .IX Item "-ah" |
| include high-level source |
| .Ip "\f(CW\*(C`\-al\*(C'\fR" 4 |
| .IX Item "-al" |
| include assembly |
| .Ip "\f(CW\*(C`\-am\*(C'\fR" 4 |
| .IX Item "-am" |
| include macro expansions |
| .Ip "\f(CW\*(C`\-an\*(C'\fR" 4 |
| .IX Item "-an" |
| omit forms processing |
| .Ip "\f(CW\*(C`\-as\*(C'\fR" 4 |
| .IX Item "-as" |
| include symbols |
| .Ip "\f(CW\*(C`=file\*(C'\fR" 4 |
| .IX Item "=file" |
| set the name of the listing file |
| .RE |
| .RS 4 |
| .Sp |
| You may combine these options; for example, use \fB\-aln\fR for assembly |
| listing without forms processing. The \fB=file\fR option, if used, must be |
| the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR. |
| .RE |
| .Ip "\f(CW\*(C`\-D\*(C'\fR" 4 |
| .IX Item "-D" |
| Ignored. This option is accepted for script compatibility with calls to |
| other assemblers. |
| .Ip "\f(CW\*(C`\-\-defsym \f(CIsym\f(CW=\f(CIvalue\f(CW\*(C'\fR" 4 |
| .IX Item "--defsym sym=value" |
| Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file. |
| \&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR |
| indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value. |
| .Ip "\f(CW\*(C`\-f\*(C'\fR" 4 |
| .IX Item "-f" |
| ``fast''\-\-\-skip whitespace and comment preprocessing (assume source is |
| compiler output). |
| .Ip "\f(CW\*(C`\-\-gstabs\*(C'\fR" 4 |
| .IX Item "--gstabs" |
| Generate stabs debugging information for each assembler line. This |
| may help debugging assembler code, if the debugger can handle it. |
| .Ip "\f(CW\*(C`\-\-gdwarf2\*(C'\fR" 4 |
| .IX Item "--gdwarf2" |
| Generate \s-1DWARF2\s0 debugging information for each assembler line. This |
| may help debugging assembler code, if the debugger can handle it. Note \- this |
| option is only supported by some targets, not all of them. |
| .Ip "\f(CW\*(C`\-\-help\*(C'\fR" 4 |
| .IX Item "--help" |
| Print a summary of the command line options and exit. |
| .Ip "\f(CW\*(C`\-\-target\-help\*(C'\fR" 4 |
| .IX Item "--target-help" |
| Print a summary of all target specific options and exit. |
| .Ip "\f(CW\*(C`\-I \f(CIdir\f(CW\*(C'\fR" 4 |
| .IX Item "-I dir" |
| Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives. |
| .Ip "\f(CW\*(C`\-J\*(C'\fR" 4 |
| .IX Item "-J" |
| Don't warn about signed overflow. |
| .Ip "\f(CW\*(C`\-K\*(C'\fR" 4 |
| .IX Item "-K" |
| This option is accepted but has no effect on the \s-1TARGET\s0 family. |
| .Ip "\f(CW\*(C`\-L\*(C'\fR" 4 |
| .IX Item "-L" |
| .Ip "\f(CW\*(C`\-\-keep\-locals\*(C'\fR" 4 |
| .IX Item "--keep-locals" |
| Keep (in the symbol table) local symbols. On traditional a.out systems |
| these start with \fBL\fR, but different systems have different local |
| label prefixes. |
| .Ip "\f(CW\*(C`\-\-listing\-lhs\-width=\f(CInumber\f(CW\*(C'\fR" 4 |
| .IX Item "--listing-lhs-width=number" |
| Set the maximum width, in words, of the output data column for an assembler |
| listing to \fInumber\fR. |
| .Ip "\f(CW\*(C`\-\-listing\-lhs\-width2=\f(CInumber\f(CW\*(C'\fR" 4 |
| .IX Item "--listing-lhs-width2=number" |
| Set the maximum width, in words, of the output data column for continuation |
| lines in an assembler listing to \fInumber\fR. |
| .Ip "\f(CW\*(C`\-\-listing\-rhs\-width=\f(CInumber\f(CW\*(C'\fR" 4 |
| .IX Item "--listing-rhs-width=number" |
| Set the maximum width of an input source line, as displayed in a listing, to |
| \&\fInumber\fR bytes. |
| .Ip "\f(CW\*(C`\-\-listing\-cont\-lines=\f(CInumber\f(CW\*(C'\fR" 4 |
| .IX Item "--listing-cont-lines=number" |
| Set the maximum number of lines printed in a listing for a single line of input |
| to \fInumber\fR + 1. |
| .Ip "\f(CW\*(C`\-o \f(CIobjfile\f(CW\*(C'\fR" 4 |
| .IX Item "-o objfile" |
| Name the object-file output from \f(CW\*(C`as\*(C'\fR \fIobjfile\fR. |
| .Ip "\f(CW\*(C`\-R\*(C'\fR" 4 |
| .IX Item "-R" |
| Fold the data section into the text section. |
| .Ip "\f(CW\*(C`\-\-statistics\*(C'\fR" 4 |
| .IX Item "--statistics" |
| Print the maximum space (in bytes) and total time (in seconds) used by |
| assembly. |
| .Ip "\f(CW\*(C`\-\-strip\-local\-absolute\*(C'\fR" 4 |
| .IX Item "--strip-local-absolute" |
| Remove local absolute symbols from the outgoing symbol table. |
| .Ip "\f(CW\*(C`\-v\*(C'\fR" 4 |
| .IX Item "-v" |
| .Ip "\f(CW\*(C`\-version\*(C'\fR" 4 |
| .IX Item "-version" |
| Print the \f(CW\*(C`as\*(C'\fR version. |
| .Ip "\f(CW\*(C`\-\-version\*(C'\fR" 4 |
| .IX Item "--version" |
| Print the \f(CW\*(C`as\*(C'\fR version and exit. |
| .Ip "\f(CW\*(C`\-W\*(C'\fR" 4 |
| .IX Item "-W" |
| .Ip "\f(CW\*(C`\-\-no\-warn\*(C'\fR" 4 |
| .IX Item "--no-warn" |
| Suppress warning messages. |
| .Ip "\f(CW\*(C`\-\-fatal\-warnings\*(C'\fR" 4 |
| .IX Item "--fatal-warnings" |
| Treat warnings as errors. |
| .Ip "\f(CW\*(C`\-\-warn\*(C'\fR" 4 |
| .IX Item "--warn" |
| Don't suppress warning messages or treat them as errors. |
| .Ip "\f(CW\*(C`\-w\*(C'\fR" 4 |
| .IX Item "-w" |
| Ignored. |
| .Ip "\f(CW\*(C`\-x\*(C'\fR" 4 |
| .IX Item "-x" |
| Ignored. |
| .Ip "\f(CW\*(C`\-Z\*(C'\fR" 4 |
| .IX Item "-Z" |
| Generate an object file even after errors. |
| .Ip "\f(CW\*(C`\-\- | \f(CIfiles\f(CW ...\*(C'\fR" 4 |
| .IX Item "-- | files ..." |
| Standard input, or source files to assemble. |
| .PP |
| The following options are available when as is configured for |
| an \s-1ARC\s0 processor. |
| .Ip "\f(CW\*(C`\-marc[5|6|7|8]\*(C'\fR" 4 |
| .IX Item "-marc[5|6|7|8]" |
| This option selects the core processor variant. |
| .Ip "\f(CW\*(C`\-EB | \-EL\*(C'\fR" 4 |
| .IX Item "-EB | -EL" |
| Select either big-endian (\-EB) or little-endian (\-EL) output. |
| .PP |
| The following options are available when as is configured for the \s-1ARM\s0 |
| processor family. |
| .Ip "\f(CW\*(C`\-m[arm][1|2|3|6|7|8|9][...] \*(C'\fR" 4 |
| .IX Item "-m[arm][1|2|3|6|7|8|9][...] " |
| Specify which \s-1ARM\s0 processor variant is the target. |
| .Ip "\f(CW\*(C`\-m[arm]v[2|2a|3|3m|4|4t|5|5t]\*(C'\fR" 4 |
| .IX Item "-m[arm]v[2|2a|3|3m|4|4t|5|5t]" |
| Specify which \s-1ARM\s0 architecture variant is used by the target. |
| .Ip "\f(CW\*(C`\-mthumb | \-mall\*(C'\fR" 4 |
| .IX Item "-mthumb | -mall" |
| Enable or disable Thumb only instruction decoding. |
| .Ip "\f(CW\*(C`\-mfpa10 | \-mfpa11 | \-mfpe\-old | \-mno\-fpu\*(C'\fR" 4 |
| .IX Item "-mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu" |
| Select which Floating Point architecture is the target. |
| .Ip "\f(CW\*(C`\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\*(C'\fR" 4 |
| .IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi" |
| Select which procedure calling convention is in use. |
| .Ip "\f(CW\*(C`\-EB | \-EL\*(C'\fR" 4 |
| .IX Item "-EB | -EL" |
| Select either big-endian (\-EB) or little-endian (\-EL) output. |
| .Ip "\f(CW\*(C`\-mthumb\-interwork\*(C'\fR" 4 |
| .IX Item "-mthumb-interwork" |
| Specify that the code has been generated with interworking between Thumb and |
| \&\s-1ARM\s0 code in mind. |
| .Ip "\f(CW\*(C`\-k\*(C'\fR" 4 |
| .IX Item "-k" |
| Specify that \s-1PIC\s0 code has been generated. |
| .PP |
| The following options are available when as is configured for |
| a D10V processor. |
| .Ip "\f(CW\*(C`\-O\*(C'\fR" 4 |
| .IX Item "-O" |
| Optimize output by parallelizing instructions. |
| .PP |
| The following options are available when as is configured for a D30V |
| processor. |
| .Ip "\f(CW\*(C`\-O\*(C'\fR" 4 |
| .IX Item "-O" |
| Optimize output by parallelizing instructions. |
| .Ip "\f(CW\*(C`\-n\*(C'\fR" 4 |
| .IX Item "-n" |
| Warn when nops are generated. |
| .Ip "\f(CW\*(C`\-N\*(C'\fR" 4 |
| .IX Item "-N" |
| Warn when a nop after a 32\-bit multiply instruction is generated. |
| .PP |
| The following options are available when as is configured for the |
| Intel 80960 processor. |
| .Ip "\f(CW\*(C`\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\*(C'\fR" 4 |
| .IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC" |
| Specify which variant of the 960 architecture is the target. |
| .Ip "\f(CW\*(C`\-b\*(C'\fR" 4 |
| .IX Item "-b" |
| Add code to collect statistics about branches taken. |
| .Ip "\f(CW\*(C`\-no\-relax\*(C'\fR" 4 |
| .IX Item "-no-relax" |
| Do not alter compare-and-branch instructions for long displacements; |
| error if necessary. |
| .PP |
| The following options are available when as is configured for the |
| Mitsubishi M32R series. |
| .Ip "\f(CW\*(C`\-\-m32rx\*(C'\fR" 4 |
| .IX Item "--m32rx" |
| Specify which processor in the M32R family is the target. The default |
| is normally the M32R, but this option changes it to the M32RX. |
| .Ip "\f(CW\*(C`\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\*(C'\fR" 4 |
| .IX Item "--warn-explicit-parallel-conflicts or --Wp" |
| Produce warning messages when questionable parallel constructs are |
| encountered. |
| .Ip "\f(CW\*(C`\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\*(C'\fR" 4 |
| .IX Item "--no-warn-explicit-parallel-conflicts or --Wnp" |
| Do not produce warning messages when questionable parallel constructs are |
| encountered. |
| .PP |
| The following options are available when as is configured for the |
| Motorola 68000 series. |
| .Ip "\f(CW\*(C`\-l\*(C'\fR" 4 |
| .IX Item "-l" |
| Shorten references to undefined symbols, to one word instead of two. |
| .Ip "\f(CW\*(C`\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\*(C'\fR" 4 |
| .IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030" |
| .Ip "\f(CW\*(C`| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\*(C'\fR" 4 |
| .IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332" |
| .Ip "\f(CW\*(C`| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\*(C'\fR" 4 |
| .IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200" |
| Specify what processor in the 68000 family is the target. The default |
| is normally the 68020, but this can be changed at configuration time. |
| .Ip "\f(CW\*(C`\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\*(C'\fR" 4 |
| .IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882" |
| The target machine does (or does not) have a floating-point coprocessor. |
| The default is to assume a coprocessor for 68020, 68030, and cpu32. Although |
| the basic 68000 is not compatible with the 68881, a combination of the |
| two can be specified, since it's possible to do emulation of the |
| coprocessor instructions with the main processor. |
| .Ip "\f(CW\*(C`\-m68851 | \-mno\-68851\*(C'\fR" 4 |
| .IX Item "-m68851 | -mno-68851" |
| The target machine does (or does not) have a memory-management |
| unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up. |
| .PP |
| For details about the \s-1PDP-11\s0 machine dependent features options, |
| see \f(CW@ref\fR{PDP-11\-Options}. |
| .Ip "\f(CW\*(C`\-mpic | \-mno\-pic\*(C'\fR" 4 |
| .IX Item "-mpic | -mno-pic" |
| Generate position-independent (or position-dependent) code. The |
| default is \f(CW\*(C`\-mpic\*(C'\fR. |
| .Ip "\f(CW\*(C`\-mall\*(C'\fR" 4 |
| .IX Item "-mall" |
| .Ip "\f(CW\*(C`\-mall\-extensions\*(C'\fR" 4 |
| .IX Item "-mall-extensions" |
| Enable all instruction set extensions. This is the default. |
| .Ip "\f(CW\*(C`\-mno\-extensions\*(C'\fR" 4 |
| .IX Item "-mno-extensions" |
| Disable all instruction set extensions. |
| .Ip "\f(CW\*(C`\-m\f(CIextension\f(CW | \-mno\-\f(CIextension\f(CW\*(C'\fR" 4 |
| .IX Item "-mextension | -mno-extension" |
| Enable (or disable) a particular instruction set extension. |
| .Ip "\f(CW\*(C`\-m\f(CIcpu\f(CW\*(C'\fR" 4 |
| .IX Item "-mcpu" |
| Enable the instruction set extensions supported by a particular \s-1CPU\s0, and |
| disable all other extensions. |
| .Ip "\f(CW\*(C`\-m\f(CImachine\f(CW\*(C'\fR" 4 |
| .IX Item "-mmachine" |
| Enable the instruction set extensions supported by a particular machine |
| model, and disable all other extensions. |
| .PP |
| The following options are available when as is configured for |
| a picoJava processor. |
| .Ip "\f(CW\*(C`\-mb\*(C'\fR" 4 |
| .IX Item "-mb" |
| Generate ``big endian'' format output. |
| .Ip "\f(CW\*(C`\-ml\*(C'\fR" 4 |
| .IX Item "-ml" |
| Generate ``little endian'' format output. |
| .PP |
| The following options are available when as is configured for the |
| Motorola 68HC11 or 68HC12 series. |
| .Ip "\f(CW\*(C`\-m68hc11 | \-m68hc12\*(C'\fR" 4 |
| .IX Item "-m68hc11 | -m68hc12" |
| Specify what processor is the target. The default is |
| defined by the configuration option when building the assembler. |
| .Ip "\f(CW\*(C`\-\-force\-long\-branchs\*(C'\fR" 4 |
| .IX Item "--force-long-branchs" |
| Relative branches are turned into absolute ones. This concerns |
| conditional branches, unconditional branches and branches to a |
| sub routine. |
| .Ip "\f(CW\*(C`\-S | \-\-short\-branchs\*(C'\fR" 4 |
| .IX Item "-S | --short-branchs" |
| Do not turn relative branchs into absolute ones |
| when the offset is out of range. |
| .Ip "\f(CW\*(C`\-\-strict\-direct\-mode\*(C'\fR" 4 |
| .IX Item "--strict-direct-mode" |
| Do not turn the direct addressing mode into extended addressing mode |
| when the instruction does not support direct addressing mode. |
| .Ip "\f(CW\*(C`\-\-print\-insn\-syntax\*(C'\fR" 4 |
| .IX Item "--print-insn-syntax" |
| Print the syntax of instruction in case of error. |
| .Ip "\f(CW\*(C`\-\-print\-opcodes\*(C'\fR" 4 |
| .IX Item "--print-opcodes" |
| print the list of instructions with syntax and then exit. |
| .Ip "\f(CW\*(C`\-\-generate\-example\*(C'\fR" 4 |
| .IX Item "--generate-example" |
| print an example of instruction for each possible instruction and then exit. |
| This option is only useful for testing \f(CW\*(C`as\*(C'\fR. |
| .PP |
| The following options are available when \f(CW\*(C`as\*(C'\fR is configured |
| for the \s-1SPARC\s0 architecture: |
| .Ip "\f(CW\*(C`\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\*(C'\fR" 4 |
| .IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite" |
| .Ip "\f(CW\*(C`\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\*(C'\fR" 4 |
| .IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a" |
| Explicitly select a variant of the \s-1SPARC\s0 architecture. |
| .Sp |
| \&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment. |
| \&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment. |
| .Sp |
| \&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with |
| UltraSPARC extensions. |
| .Ip "\f(CW\*(C`\-xarch=v8plus | \-xarch=v8plusa\*(C'\fR" 4 |
| .IX Item "-xarch=v8plus | -xarch=v8plusa" |
| For compatibility with the Solaris v9 assembler. These options are |
| equivalent to \-Av8plus and \-Av8plusa, respectively. |
| .Ip "\f(CW\*(C`\-bump\*(C'\fR" 4 |
| .IX Item "-bump" |
| Warn when the assembler switches to another architecture. |
| .PP |
| The following options are available when as is configured for |
| a \s-1MIPS\s0 processor. |
| .Ip "\f(CW\*(C`\-G \f(CInum\f(CW\*(C'\fR" 4 |
| .IX Item "-G num" |
| This option sets the largest size of an object that can be referenced |
| implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that |
| use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8. |
| .Ip "\f(CW\*(C`\-EB\*(C'\fR" 4 |
| .IX Item "-EB" |
| Generate ``big endian'' format output. |
| .Ip "\f(CW\*(C`\-EL\*(C'\fR" 4 |
| .IX Item "-EL" |
| Generate ``little endian'' format output. |
| .Ip "\f(CW\*(C`\-mips1\*(C'\fR" 4 |
| .IX Item "-mips1" |
| .Ip "\f(CW\*(C`\-mips2\*(C'\fR" 4 |
| .IX Item "-mips2" |
| .Ip "\f(CW\*(C`\-mips3\*(C'\fR" 4 |
| .IX Item "-mips3" |
| .Ip "\f(CW\*(C`\-mips4\*(C'\fR" 4 |
| .IX Item "-mips4" |
| .Ip "\f(CW\*(C`\-mips32\*(C'\fR" 4 |
| .IX Item "-mips32" |
| Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. |
| \&\fB\-mips1\fR corresponds to the R2000 and R3000 processors, |
| \&\fB\-mips2\fR to the R6000 processor, and \fB\-mips3\fR to the R4000 |
| processor. |
| \&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond |
| to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, and \s-1MIPS64\s0 \s-1ISA\s0 |
| processors, respectively. |
| .Ip "\f(CW\*(C`\-m4650\*(C'\fR" 4 |
| .IX Item "-m4650" |
| .Ip "\f(CW\*(C`\-no\-m4650\*(C'\fR" 4 |
| .IX Item "-no-m4650" |
| Generate code for the \s-1MIPS\s0 R4650 chip. This tells the assembler to accept |
| the \fBmad\fR and \fBmadu\fR instruction, and to not schedule \fBnop\fR |
| instructions around accesses to the \fB\s-1HI\s0\fR and \fB\s-1LO\s0\fR registers. |
| \&\fB\-no-m4650\fR turns off this option. |
| .Ip "\f(CW\*(C`\-mcpu=\f(CI\s\-1CPU\s0\f(CW\*(C'\fR" 4 |
| .IX Item "-mcpu=CPU" |
| Generate code for a particular \s-1MIPS\s0 cpu. It is exactly equivalent to |
| \&\fB\-m\fR\fIcpu\fR, except that there are more value of \fIcpu\fR |
| understood. |
| .Ip "\f(CW\*(C`\-\-emulation=\f(CIname\f(CW\*(C'\fR" 4 |
| .IX Item "--emulation=name" |
| This option causes \f(CW\*(C`as\*(C'\fR to emulate \f(CW\*(C`as\*(C'\fR configured |
| for some other target, in all respects, including output format (choosing |
| between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate |
| debugging information or store symbol table information, and default |
| endianness. The available configuration names are: \fBmipsecoff\fR, |
| \&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR, |
| \&\fBmipsbelf\fR. The first two do not alter the default endianness from that |
| of the primary target for which the assembler was configured; the others change |
| the default to little- or big-endian as indicated by the \fBb\fR or \fBl\fR |
| in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness |
| selection in any case. |
| .Sp |
| This option is currently supported only when the primary target |
| \&\f(CW\*(C`as\*(C'\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target. |
| Furthermore, the primary target or others specified with |
| \&\fB\*(--enable-targets=...\fR at configuration time must include support for |
| the other format, if both are to be available. For example, the Irix 5 |
| configuration includes support for both. |
| .Sp |
| Eventually, this option will support more configurations, with more |
| fine-grained control over the assembler's behavior, and will be supported for |
| more processors. |
| .Ip "\f(CW\*(C`\-nocpp\*(C'\fR" 4 |
| .IX Item "-nocpp" |
| \&\f(CW\*(C`as\*(C'\fR ignores this option. It is accepted for compatibility with |
| the native tools. |
| .Ip "\f(CW\*(C`\-\-trap\*(C'\fR" 4 |
| .IX Item "--trap" |
| .Ip "\f(CW\*(C`\-\-no\-trap\*(C'\fR" 4 |
| .IX Item "--no-trap" |
| .Ip "\f(CW\*(C`\-\-break\*(C'\fR" 4 |
| .IX Item "--break" |
| .Ip "\f(CW\*(C`\-\-no\-break\*(C'\fR" 4 |
| .IX Item "--no-break" |
| Control how to deal with multiplication overflow and division by zero. |
| \&\fB\*(--trap\fR or \fB\*(--no-break\fR (which are synonyms) take a trap exception |
| (and only work for Instruction Set Architecture level 2 and higher); |
| \&\fB\*(--break\fR or \fB\*(--no-trap\fR (also synonyms, and the default) take a |
| break exception. |
| .Ip "\f(CW\*(C`\-n\*(C'\fR" 4 |
| .IX Item "-n" |
| When this option is used, \f(CW\*(C`as\*(C'\fR will issue a warning every |
| time it generates a nop instruction from a macro. |
| .PP |
| The following options are available when as is configured for |
| an MCore processor. |
| .Ip "\f(CW\*(C`\-jsri2bsr\*(C'\fR" 4 |
| .IX Item "-jsri2bsr" |
| .Ip "\f(CW\*(C`\-nojsri2bsr\*(C'\fR" 4 |
| .IX Item "-nojsri2bsr" |
| Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled. |
| The command line option \fB\-nojsri2bsr\fR can be used to disable it. |
| .Ip "\f(CW\*(C`\-sifilter\*(C'\fR" 4 |
| .IX Item "-sifilter" |
| .Ip "\f(CW\*(C`\-nosifilter\*(C'\fR" 4 |
| .IX Item "-nosifilter" |
| Enable or disable the silicon filter behaviour. By default this is disabled. |
| The default can be overridden by the \fB\-sifilter\fR command line option. |
| .Ip "\f(CW\*(C`\-relax\*(C'\fR" 4 |
| .IX Item "-relax" |
| Alter jump instructions for long displacements. |
| .Ip "\f(CW\*(C`\-mcpu=[210|340]\*(C'\fR" 4 |
| .IX Item "-mcpu=[210|340]" |
| Select the cpu type on the target hardware. This controls which instructions |
| can be assembled. |
| .Ip "\f(CW\*(C`\-EB\*(C'\fR" 4 |
| .IX Item "-EB" |
| Assemble for a big endian target. |
| .Ip "\f(CW\*(C`\-EL\*(C'\fR" 4 |
| .IX Item "-EL" |
| Assemble for a little endian target. |
| .SH "SEE ALSO" |
| .IX Header "SEE ALSO" |
| \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR. |
| .SH "COPYRIGHT" |
| .IX Header "COPYRIGHT" |
| Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free Software Foundation, Inc. |
| .PP |
| Permission is granted to copy, distribute and/or modify this document |
| under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1 |
| or any later version published by the Free Software Foundation; |
| with no Invariant Sections, with no Front-Cover Texts, and with no |
| Back-Cover Texts. A copy of the license is included in the |
| section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R". |