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/* Target-dependent code for GDB, the GNU debugger.
Copyright (C) 1986-2021 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "infrun.h"
#include "symtab.h"
#include "target.h"
#include "gdbcore.h"
#include "gdbcmd.h"
#include "objfiles.h"
#include "arch-utils.h"
#include "regcache.h"
#include "regset.h"
#include "target-float.h"
#include "value.h"
#include "parser-defs.h"
#include "osabi.h"
#include "infcall.h"
#include "sim-regno.h"
#include "gdb/sim-ppc.h"
#include "reggroups.h"
#include "dwarf2/frame.h"
#include "target-descriptions.h"
#include "user-regs.h"
#include "record-full.h"
#include "auxv.h"
#include "coff/internal.h" /* for libcoff.h */
#include "libcoff.h" /* for xcoff_data */
#include "coff/xcoff.h"
#include "libxcoff.h"
#include "elf-bfd.h"
#include "elf/ppc.h"
#include "elf/ppc64.h"
#include "solib-svr4.h"
#include "ppc-tdep.h"
#include "ppc-ravenscar-thread.h"
#include "dis-asm.h"
#include "trad-frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "ax.h"
#include "ax-gdb.h"
#include <algorithm>
#include "features/rs6000/powerpc-32.c"
#include "features/rs6000/powerpc-altivec32.c"
#include "features/rs6000/powerpc-vsx32.c"
#include "features/rs6000/powerpc-403.c"
#include "features/rs6000/powerpc-403gc.c"
#include "features/rs6000/powerpc-405.c"
#include "features/rs6000/powerpc-505.c"
#include "features/rs6000/powerpc-601.c"
#include "features/rs6000/powerpc-602.c"
#include "features/rs6000/powerpc-603.c"
#include "features/rs6000/powerpc-604.c"
#include "features/rs6000/powerpc-64.c"
#include "features/rs6000/powerpc-altivec64.c"
#include "features/rs6000/powerpc-vsx64.c"
#include "features/rs6000/powerpc-7400.c"
#include "features/rs6000/powerpc-750.c"
#include "features/rs6000/powerpc-860.c"
#include "features/rs6000/powerpc-e500.c"
#include "features/rs6000/rs6000.c"
/* Determine if regnum is an SPE pseudo-register. */
#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_ev0_regnum \
&& (regnum) < (tdep)->ppc_ev0_regnum + 32)
/* Determine if regnum is a decimal float pseudo-register. */
#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_dl0_regnum \
&& (regnum) < (tdep)->ppc_dl0_regnum + 16)
/* Determine if regnum is a "vX" alias for the raw "vrX" vector
registers. */
#define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\
(tdep)->ppc_v0_alias_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_v0_alias_regnum \
&& (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs)
/* Determine if regnum is a POWER7 VSX register. */
#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_vsr0_regnum \
&& (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
/* Determine if regnum is a POWER7 Extended FP register. */
#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_efpr0_regnum \
&& (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
/* Determine if regnum is a checkpointed decimal float
pseudo-register. */
#define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_cdl0_regnum \
&& (regnum) < (tdep)->ppc_cdl0_regnum + 16)
/* Determine if regnum is a Checkpointed POWER7 VSX register. */
#define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_cvsr0_regnum \
&& (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
/* Determine if regnum is a Checkpointed POWER7 Extended FP register. */
#define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \
&& (regnum) >= (tdep)->ppc_cefpr0_regnum \
&& (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs)
/* Holds the current set of options to be passed to the disassembler. */
static char *powerpc_disassembler_options;
/* The list of available "set powerpc ..." and "show powerpc ..."
commands. */
static struct cmd_list_element *setpowerpccmdlist = NULL;
static struct cmd_list_element *showpowerpccmdlist = NULL;
static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
static const char *const powerpc_vector_strings[] =
{
"auto",
"generic",
"altivec",
"spe",
NULL
};
/* A variable that can be configured by the user. */
static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
static const char *powerpc_vector_abi_string = "auto";
/* PowerPC-related per-inferior data. */
struct ppc_inferior_data
{
/* This is an optional in case we add more fields to ppc_inferior_data, we
don't want it instantiated as soon as we get the ppc_inferior_data for an
inferior. */
gdb::optional<displaced_step_buffers> disp_step_buf;
};
static inferior_key<ppc_inferior_data> ppc_inferior_data_key;
/* Get the per-inferior PowerPC data for INF. */
static ppc_inferior_data *
get_ppc_per_inferior (inferior *inf)
{
ppc_inferior_data *per_inf = ppc_inferior_data_key.get (inf);
if (per_inf == nullptr)
per_inf = ppc_inferior_data_key.emplace (inf);
return per_inf;
}
/* To be used by skip_prologue. */
struct rs6000_framedata
{
int offset; /* total size of frame --- the distance
by which we decrement sp to allocate
the frame */
int saved_gpr; /* smallest # of saved gpr */
unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
int saved_fpr; /* smallest # of saved fpr */
int saved_vr; /* smallest # of saved vr */
int saved_ev; /* smallest # of saved ev */
int alloca_reg; /* alloca register number (frame ptr) */
char frameless; /* true if frameless functions. */
char nosavedpc; /* true if pc not saved. */
char used_bl; /* true if link register clobbered */
int gpr_offset; /* offset of saved gprs from prev sp */
int fpr_offset; /* offset of saved fprs from prev sp */
int vr_offset; /* offset of saved vrs from prev sp */
int ev_offset; /* offset of saved evs from prev sp */
int lr_offset; /* offset of saved lr */
int lr_register; /* register of saved lr, if trustworthy */
int cr_offset; /* offset of saved cr */
int vrsave_offset; /* offset of saved vrsave register */
};
/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
int
vsx_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->ppc_vsr0_regnum < 0)
return 0;
else
return (regno >= tdep->ppc_vsr0_upper_regnum && regno
<= tdep->ppc_vsr0_upper_regnum + 31);
}
/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
int
altivec_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
return 0;
else
return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
}
/* Return true if REGNO is an SPE register, false otherwise. */
int
spe_register_p (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* Is it a reference to EV0 -- EV31, and do we have those? */
if (IS_SPE_PSEUDOREG (tdep, regno))
return 1;
/* Is it a reference to one of the raw upper GPR halves? */
if (tdep->ppc_ev0_upper_regnum >= 0
&& tdep->ppc_ev0_upper_regnum <= regno
&& regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
return 1;
/* Is it a reference to the 64-bit accumulator, and do we have that? */
if (tdep->ppc_acc_regnum >= 0
&& tdep->ppc_acc_regnum == regno)
return 1;
/* Is it a reference to the SPE floating-point status and control register,
and do we have that? */
if (tdep->ppc_spefscr_regnum >= 0
&& tdep->ppc_spefscr_regnum == regno)
return 1;
return 0;
}
/* Return non-zero if the architecture described by GDBARCH has
floating-point registers (f0 --- f31 and fpscr). */
int
ppc_floating_point_unit_p (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return (tdep->ppc_fp0_regnum >= 0
&& tdep->ppc_fpscr_regnum >= 0);
}
/* Return non-zero if the architecture described by GDBARCH has
Altivec registers (vr0 --- vr31, vrsave and vscr). */
int
ppc_altivec_support_p (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return (tdep->ppc_vr0_regnum >= 0
&& tdep->ppc_vrsave_regnum >= 0);
}
/* Check that TABLE[GDB_REGNO] is not already initialized, and then
set it to SIM_REGNO.
This is a helper function for init_sim_regno_table, constructing
the table mapping GDB register numbers to sim register numbers; we
initialize every element in that table to -1 before we start
filling it in. */
static void
set_sim_regno (int *table, int gdb_regno, int sim_regno)
{
/* Make sure we don't try to assign any given GDB register a sim
register number more than once. */
gdb_assert (table[gdb_regno] == -1);
table[gdb_regno] = sim_regno;
}
/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
numbers to simulator register numbers, based on the values placed
in the ARCH->tdep->ppc_foo_regnum members. */
static void
init_sim_regno_table (struct gdbarch *arch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
int total_regs = gdbarch_num_regs (arch);
int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
int i;
static const char *const segment_regs[] = {
"sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
};
/* Presume that all registers not explicitly mentioned below are
unavailable from the sim. */
for (i = 0; i < total_regs; i++)
sim_regno[i] = -1;
/* General-purpose registers. */
for (i = 0; i < ppc_num_gprs; i++)
set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
/* Floating-point registers. */
if (tdep->ppc_fp0_regnum >= 0)
for (i = 0; i < ppc_num_fprs; i++)
set_sim_regno (sim_regno,
tdep->ppc_fp0_regnum + i,
sim_ppc_f0_regnum + i);
if (tdep->ppc_fpscr_regnum >= 0)
set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
/* Segment registers. */
for (i = 0; i < ppc_num_srs; i++)
{
int gdb_regno;
gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
if (gdb_regno >= 0)
set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
}
/* Altivec registers. */
if (tdep->ppc_vr0_regnum >= 0)
{
for (i = 0; i < ppc_num_vrs; i++)
set_sim_regno (sim_regno,
tdep->ppc_vr0_regnum + i,
sim_ppc_vr0_regnum + i);
/* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
we can treat this more like the other cases. */
set_sim_regno (sim_regno,
tdep->ppc_vr0_regnum + ppc_num_vrs,
sim_ppc_vscr_regnum);
}
/* vsave is a special-purpose register, so the code below handles it. */
/* SPE APU (E500) registers. */
if (tdep->ppc_ev0_upper_regnum >= 0)
for (i = 0; i < ppc_num_gprs; i++)
set_sim_regno (sim_regno,
tdep->ppc_ev0_upper_regnum + i,
sim_ppc_rh0_regnum + i);
if (tdep->ppc_acc_regnum >= 0)
set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
/* spefscr is a special-purpose register, so the code below handles it. */
#ifdef WITH_PPC_SIM
/* Now handle all special-purpose registers. Verify that they
haven't mistakenly been assigned numbers by any of the above
code. */
for (i = 0; i < sim_ppc_num_sprs; i++)
{
const char *spr_name = sim_spr_register_name (i);
int gdb_regno = -1;
if (spr_name != NULL)
gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
if (gdb_regno != -1)
set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
}
#endif
/* Drop the initialized array into place. */
tdep->sim_regno = sim_regno;
}
/* Given a GDB register number REG, return the corresponding SIM
register number. */
static int
rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int sim_regno;
if (tdep->sim_regno == NULL)
init_sim_regno_table (gdbarch);
gdb_assert (0 <= reg && reg <= gdbarch_num_cooked_regs (gdbarch));
sim_regno = tdep->sim_regno[reg];
if (sim_regno >= 0)
return sim_regno;
else
return LEGACY_SIM_REGNO_IGNORE;
}
/* Register set support functions. */
/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
Write the register to REGCACHE. */
void
ppc_supply_reg (struct regcache *regcache, int regnum,
const gdb_byte *regs, size_t offset, int regsize)
{
if (regnum != -1 && offset != -1)
{
if (regsize > 4)
{
struct gdbarch *gdbarch = regcache->arch ();
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize
&& gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset += regsize - gdb_regsize;
}
regcache->raw_supply (regnum, regs + offset);
}
}
/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
in a field REGSIZE wide. Zero pad as necessary. */
void
ppc_collect_reg (const struct regcache *regcache, int regnum,
gdb_byte *regs, size_t offset, int regsize)
{
if (regnum != -1 && offset != -1)
{
if (regsize > 4)
{
struct gdbarch *gdbarch = regcache->arch ();
int gdb_regsize = register_size (gdbarch, regnum);
if (gdb_regsize < regsize)
{
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
memset (regs + offset, 0, regsize - gdb_regsize);
offset += regsize - gdb_regsize;
}
else
memset (regs + offset + regsize - gdb_regsize, 0,
regsize - gdb_regsize);
}
}
regcache->raw_collect (regnum, regs + offset);
}
}
static int
ppc_greg_offset (struct gdbarch *gdbarch,
struct gdbarch_tdep *tdep,
const struct ppc_reg_offsets *offsets,
int regnum,
int *regsize)
{
*regsize = offsets->gpr_size;
if (regnum >= tdep->ppc_gp0_regnum
&& regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
return (offsets->r0_offset
+ (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
if (regnum == gdbarch_pc_regnum (gdbarch))
return offsets->pc_offset;
if (regnum == tdep->ppc_ps_regnum)
return offsets->ps_offset;
if (regnum == tdep->ppc_lr_regnum)
return offsets->lr_offset;
if (regnum == tdep->ppc_ctr_regnum)
return offsets->ctr_offset;
*regsize = offsets->xr_size;
if (regnum == tdep->ppc_cr_regnum)
return offsets->cr_offset;
if (regnum == tdep->ppc_xer_regnum)
return offsets->xer_offset;
if (regnum == tdep->ppc_mq_regnum)
return offsets->mq_offset;
return -1;
}
static int
ppc_fpreg_offset (struct gdbarch_tdep *tdep,
const struct ppc_reg_offsets *offsets,
int regnum)
{
if (regnum >= tdep->ppc_fp0_regnum
&& regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
if (regnum == tdep->ppc_fpscr_regnum)
return offsets->fpscr_offset;
return -1;
}
/* Supply register REGNUM in the general-purpose register set REGSET
from the buffer specified by GREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *gregs, size_t len)
{
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets
= (const struct ppc_reg_offsets *) regset->regmap;
size_t offset;
int regsize;
if (regnum == -1)
{
int i;
int gpr_size = offsets->gpr_size;
for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
i < tdep->ppc_gp0_regnum + ppc_num_gprs;
i++, offset += gpr_size)
ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset,
gpr_size);
ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
(const gdb_byte *) gregs, offsets->pc_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
(const gdb_byte *) gregs, offsets->ps_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
(const gdb_byte *) gregs, offsets->lr_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
(const gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
(const gdb_byte *) gregs, offsets->cr_offset,
offsets->xr_size);
ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
(const gdb_byte *) gregs, offsets->xer_offset,
offsets->xr_size);
ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
(const gdb_byte *) gregs, offsets->mq_offset,
offsets->xr_size);
return;
}
offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize);
}
/* Supply register REGNUM in the floating-point register set REGSET
from the buffer specified by FPREGS and LEN to register cache
REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
void
ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_floating_point_unit_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = (const struct ppc_reg_offsets *) regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
i < tdep->ppc_fp0_regnum + ppc_num_fprs;
i++, offset += 8)
ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8);
ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
(const gdb_byte *) fpregs, offsets->fpscr_offset,
offsets->fpscr_size);
return;
}
offset = ppc_fpreg_offset (tdep, offsets, regnum);
ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset,
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
/* Collect register REGNUM in the general-purpose register set
REGSET from register cache REGCACHE into the buffer specified by
GREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_gregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *gregs, size_t len)
{
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
const struct ppc_reg_offsets *offsets
= (const struct ppc_reg_offsets *) regset->regmap;
size_t offset;
int regsize;
if (regnum == -1)
{
int i;
int gpr_size = offsets->gpr_size;
for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
i < tdep->ppc_gp0_regnum + ppc_num_gprs;
i++, offset += gpr_size)
ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size);
ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
(gdb_byte *) gregs, offsets->pc_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
(gdb_byte *) gregs, offsets->ps_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
(gdb_byte *) gregs, offsets->lr_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
(gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
(gdb_byte *) gregs, offsets->cr_offset,
offsets->xr_size);
ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
(gdb_byte *) gregs, offsets->xer_offset,
offsets->xr_size);
ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
(gdb_byte *) gregs, offsets->mq_offset,
offsets->xr_size);
return;
}
offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize);
}
/* Collect register REGNUM in the floating-point register set
REGSET from register cache REGCACHE into the buffer specified by
FPREGS and LEN. If REGNUM is -1, do this for all registers in
REGSET. */
void
ppc_collect_fpregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep;
const struct ppc_reg_offsets *offsets;
size_t offset;
if (!ppc_floating_point_unit_p (gdbarch))
return;
tdep = gdbarch_tdep (gdbarch);
offsets = (const struct ppc_reg_offsets *) regset->regmap;
if (regnum == -1)
{
int i;
for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
i < tdep->ppc_fp0_regnum + ppc_num_fprs;
i++, offset += 8)
ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8);
ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
(gdb_byte *) fpregs, offsets->fpscr_offset,
offsets->fpscr_size);
return;
}
offset = ppc_fpreg_offset (tdep, offsets, regnum);
ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset,
regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
}
static int
insn_changes_sp_or_jumps (unsigned long insn)
{
int opcode = (insn >> 26) & 0x03f;
int sd = (insn >> 21) & 0x01f;
int a = (insn >> 16) & 0x01f;
int subcode = (insn >> 1) & 0x3ff;
/* Changes the stack pointer. */
/* NOTE: There are many ways to change the value of a given register.
The ways below are those used when the register is R1, the SP,
in a funtion's epilogue. */
if (opcode == 31 && subcode == 444 && a == 1)
return 1; /* mr R1,Rn */
if (opcode == 14 && sd == 1)
return 1; /* addi R1,Rn,simm */
if (opcode == 58 && sd == 1)
return 1; /* ld R1,ds(Rn) */
/* Transfers control. */
if (opcode == 18)
return 1; /* b */
if (opcode == 16)
return 1; /* bc */
if (opcode == 19 && subcode == 16)
return 1; /* bclr */
if (opcode == 19 && subcode == 528)
return 1; /* bcctr */
return 0;
}
/* Return true if we are in the function's epilogue, i.e. after the
instruction that destroyed the function's stack frame.
1) scan forward from the point of execution:
a) If you find an instruction that modifies the stack pointer
or transfers control (except a return), execution is not in
an epilogue, return.
b) Stop scanning if you find a return instruction or reach the
end of the function or reach the hard limit for the size of
an epilogue.
2) scan backward from the point of execution:
a) If you find an instruction that modifies the stack pointer,
execution *is* in an epilogue, return.
b) Stop scanning if you reach an instruction that transfers
control or the beginning of the function or reach the hard
limit for the size of an epilogue. */
static int
rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm,
struct gdbarch *gdbarch, CORE_ADDR pc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
bfd_byte insn_buf[PPC_INSN_SIZE];
CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
unsigned long insn;
/* Find the search limits based on function boundaries and hard limit. */
if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
return 0;
epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
if (epilogue_start < func_start) epilogue_start = func_start;
epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
if (epilogue_end > func_end) epilogue_end = func_end;
/* Scan forward until next 'blr'. */
for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
{
if (!safe_frame_unwind_memory (curfrm, scan_pc,
{insn_buf, PPC_INSN_SIZE}))
return 0;
insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
if (insn == 0x4e800020)
break;
/* Assume a bctr is a tail call unless it points strictly within
this function. */
if (insn == 0x4e800420)
{
CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
tdep->ppc_ctr_regnum);
if (ctr > func_start && ctr < func_end)
return 0;
else
break;
}
if (insn_changes_sp_or_jumps (insn))
return 0;
}
/* Scan backward until adjustment to stack pointer (R1). */
for (scan_pc = pc - PPC_INSN_SIZE;
scan_pc >= epilogue_start;
scan_pc -= PPC_INSN_SIZE)
{
if (!safe_frame_unwind_memory (curfrm, scan_pc,
{insn_buf, PPC_INSN_SIZE}))
return 0;
insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
if (insn_changes_sp_or_jumps (insn))
return 1;
}
return 0;
}
/* Implement the stack_frame_destroyed_p gdbarch method. */
static int
rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
return rs6000_in_function_epilogue_frame_p (get_current_frame (),
gdbarch, pc);
}
/* Get the ith function argument for the current function. */
static CORE_ADDR
rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
struct type *type)
{
return get_frame_register_unsigned (frame, 3 + argi);
}
/* Sequence of bytes for breakpoint instruction. */
constexpr gdb_byte big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
constexpr gdb_byte little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
rs6000_breakpoint;
/* Instruction masks for displaced stepping. */
#define OP_MASK 0xfc000000
#define BP_MASK 0xFC0007FE
#define B_INSN 0x48000000
#define BC_INSN 0x40000000
#define BXL_INSN 0x4c000000
#define BP_INSN 0x7C000008
/* Instruction masks used during single-stepping of atomic
sequences. */
#define LOAD_AND_RESERVE_MASK 0xfc0007fe
#define LWARX_INSTRUCTION 0x7c000028
#define LDARX_INSTRUCTION 0x7c0000A8
#define LBARX_INSTRUCTION 0x7c000068
#define LHARX_INSTRUCTION 0x7c0000e8
#define LQARX_INSTRUCTION 0x7c000228
#define STORE_CONDITIONAL_MASK 0xfc0007ff
#define STWCX_INSTRUCTION 0x7c00012d
#define STDCX_INSTRUCTION 0x7c0001ad
#define STBCX_INSTRUCTION 0x7c00056d
#define STHCX_INSTRUCTION 0x7c0005ad
#define STQCX_INSTRUCTION 0x7c00016d
/* Instruction masks for single-stepping of addpcis/lnia. */
#define ADDPCIS_INSN 0x4c000004
#define ADDPCIS_INSN_MASK 0xfc00003e
#define ADDPCIS_TARGET_REGISTER 0x03F00000
#define ADDPCIS_INSN_REGSHIFT 21
#define PNOP_MASK 0xfff3ffff
#define PNOP_INSN 0x07000000
#define R_MASK 0x00100000
#define R_ZERO 0x00000000
/* Check if insn is one of the Load And Reserve instructions used for atomic
sequences. */
#define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
|| (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
|| (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
|| (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
|| (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
/* Check if insn is one of the Store Conditional instructions used for atomic
sequences. */
#define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
|| (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
|| (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
|| (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
|| (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
typedef buf_displaced_step_copy_insn_closure
ppc_displaced_step_copy_insn_closure;
/* We can't displaced step atomic sequences. */
static displaced_step_copy_insn_closure_up
ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
size_t len = gdbarch_max_insn_length (gdbarch);
std::unique_ptr<ppc_displaced_step_copy_insn_closure> closure
(new ppc_displaced_step_copy_insn_closure (len));
gdb_byte *buf = closure->buf.data ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int insn;
len = target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY, NULL,
buf, from, len);
if ((ssize_t) len < PPC_INSN_SIZE)
memory_error (TARGET_XFER_E_IO, from);
insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
/* Check for PNOP and for prefixed instructions with R=0. Those
instructions are safe to displace. Prefixed instructions with R=1
will read/write data to/from locations relative to the current PC.
We would not be able to fixup after an instruction has written data
into a displaced location, so decline to displace those instructions. */
if ((insn & OP_MASK) == 1 << 26)
{
if (((insn & PNOP_MASK) != PNOP_INSN)
&& ((insn & R_MASK) != R_ZERO))
{
displaced_debug_printf ("Not displacing prefixed instruction %08x at %s",
insn, paddress (gdbarch, from));
return NULL;
}
}
else
/* Non-prefixed instructions.. */
{
/* Set the instruction length to 4 to match the actual instruction
length. */
len = 4;
}
/* Assume all atomic sequences start with a Load and Reserve instruction. */
if (IS_LOAD_AND_RESERVE_INSN (insn))
{
displaced_debug_printf ("can't displaced step atomic sequence at %s",
paddress (gdbarch, from));
return NULL;
}
write_memory (to, buf, len);
displaced_debug_printf ("copy %s->%s: %s",
paddress (gdbarch, from), paddress (gdbarch, to),
displaced_step_dump_bytes (buf, len).c_str ());
/* This is a work around for a problem with g++ 4.8. */
return displaced_step_copy_insn_closure_up (closure.release ());
}
/* Fix up the state of registers and memory after having single-stepped
a displaced instruction. */
static void
ppc_displaced_step_fixup (struct gdbarch *gdbarch,
struct displaced_step_copy_insn_closure *closure_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* Our closure is a copy of the instruction. */
ppc_displaced_step_copy_insn_closure *closure
= (ppc_displaced_step_copy_insn_closure *) closure_;
ULONGEST insn = extract_unsigned_integer (closure->buf.data (),
PPC_INSN_SIZE, byte_order);
ULONGEST opcode;
/* Offset for non PC-relative instructions. */
LONGEST offset;
opcode = insn & OP_MASK;
/* Set offset to 8 if this is an 8-byte (prefixed) instruction. */
if ((opcode) == 1 << 26)
offset = 2 * PPC_INSN_SIZE;
else
offset = PPC_INSN_SIZE;
displaced_debug_printf ("(ppc) fixup (%s, %s)",
paddress (gdbarch, from), paddress (gdbarch, to));
/* Handle the addpcis/lnia instruction. */
if ((insn & ADDPCIS_INSN_MASK) == ADDPCIS_INSN)
{
LONGEST displaced_offset;
ULONGEST current_val;
/* Measure the displacement. */
displaced_offset = from - to;
/* Identify the target register that was updated by the instruction. */
int regnum = (insn & ADDPCIS_TARGET_REGISTER) >> ADDPCIS_INSN_REGSHIFT;
/* Read and update the target value. */
regcache_cooked_read_unsigned (regs, regnum , &current_val);
displaced_debug_printf ("addpcis target regnum %d was %s now %s",
regnum, paddress (gdbarch, current_val),
paddress (gdbarch, current_val
+ displaced_offset));
regcache_cooked_write_unsigned (regs, regnum,
current_val + displaced_offset);
/* point the PC back at the non-displaced instruction. */
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
from + offset);
}
/* Handle PC-relative branch instructions. */
else if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
{
ULONGEST current_pc;
/* Read the current PC value after the instruction has been executed
in a displaced location. Calculate the offset to be applied to the
original PC value before the displaced stepping. */
regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
&current_pc);
offset = current_pc - to;
if (opcode != BXL_INSN)
{
/* Check for AA bit indicating whether this is an absolute
addressing or PC-relative (1: absolute, 0: relative). */
if (!(insn & 0x2))
{
/* PC-relative addressing is being used in the branch. */
displaced_debug_printf ("(ppc) branch instruction: %s",
paddress (gdbarch, insn));
displaced_debug_printf ("(ppc) adjusted PC from %s to %s",
paddress (gdbarch, current_pc),
paddress (gdbarch, from + offset));
regcache_cooked_write_unsigned (regs,
gdbarch_pc_regnum (gdbarch),
from + offset);
}
}
else
{
/* If we're here, it means we have a branch to LR or CTR. If the
branch was taken, the offset is probably greater than 4 (the next
instruction), so it's safe to assume that an offset of 4 means we
did not take the branch. */
if (offset == PPC_INSN_SIZE)
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
from + PPC_INSN_SIZE);
}
/* Check for LK bit indicating whether we should set the link
register to point to the next instruction
(1: Set, 0: Don't set). */
if (insn & 0x1)
{
/* Link register needs to be set to the next instruction's PC. */
regcache_cooked_write_unsigned (regs,
gdbarch_tdep (gdbarch)->ppc_lr_regnum,
from + PPC_INSN_SIZE);
displaced_debug_printf ("(ppc) adjusted LR to %s",
paddress (gdbarch, from + PPC_INSN_SIZE));
}
}
/* Check for breakpoints in the inferior. If we've found one, place the PC
right at the breakpoint instruction. */
else if ((insn & BP_MASK) == BP_INSN)
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
else
{
/* Handle any other instructions that do not fit in the categories
above. */
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
from + offset);
}
}
/* Implementation of gdbarch_displaced_step_prepare. */
static displaced_step_prepare_status
ppc_displaced_step_prepare (gdbarch *arch, thread_info *thread,
CORE_ADDR &displaced_pc)
{
ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf);
if (!per_inferior->disp_step_buf.has_value ())
{
/* Figure out where the displaced step buffer is. */
CORE_ADDR disp_step_buf_addr
= displaced_step_at_entry_point (thread->inf->gdbarch);
per_inferior->disp_step_buf.emplace (disp_step_buf_addr);
}
return per_inferior->disp_step_buf->prepare (thread, displaced_pc);
}
/* Implementation of gdbarch_displaced_step_finish. */
static displaced_step_finish_status
ppc_displaced_step_finish (gdbarch *arch, thread_info *thread,
gdb_signal sig)
{
ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf);
gdb_assert (per_inferior->disp_step_buf.has_value ());
return per_inferior->disp_step_buf->finish (arch, thread, sig);
}
/* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
static void
ppc_displaced_step_restore_all_in_ptid (inferior *parent_inf, ptid_t ptid)
{
ppc_inferior_data *per_inferior = ppc_inferior_data_key.get (parent_inf);
if (per_inferior == nullptr
|| !per_inferior->disp_step_buf.has_value ())
return;
per_inferior->disp_step_buf->restore_in_ptid (ptid);
}
/* Always use hardware single-stepping to execute the
displaced instruction. */
static bool
ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch)
{
return true;
}
/* Checks for an atomic sequence of instructions beginning with a
Load And Reserve instruction and ending with a Store Conditional
instruction. If such a sequence is found, attempt to step through it.
A breakpoint is placed at the end of the sequence. */
std::vector<CORE_ADDR>
ppc_deal_with_atomic_sequence (struct regcache *regcache)
{
struct gdbarch *gdbarch = regcache->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR pc = regcache_read_pc (regcache);
CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
CORE_ADDR loc = pc;
CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
int insn_count;
int index;
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
/* Assume all atomic sequences start with a Load And Reserve instruction. */
if (!IS_LOAD_AND_RESERVE_INSN (insn))
return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
if ((insn & OP_MASK) == 1 << 26)
loc += 2 * PPC_INSN_SIZE;
else
loc += PPC_INSN_SIZE;
insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
/* Assume that there is at most one conditional branch in the atomic
sequence. If a conditional branch is found, put a breakpoint in
its destination address. */
if ((insn & OP_MASK) == BC_INSN)
{
int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
int absolute = insn & 2;
if (bc_insn_count >= 1)
return {}; /* More than one conditional branch found, fallback
to the standard single-step code. */
if (absolute)
breaks[1] = immediate;
else
breaks[1] = loc + immediate;
bc_insn_count++;
last_breakpoint++;
}
if (IS_STORE_CONDITIONAL_INSN (insn))
break;
}
/* Assume that the atomic sequence ends with a Store Conditional
instruction. */
if (!IS_STORE_CONDITIONAL_INSN (insn))
return {};
closing_insn = loc;
loc += PPC_INSN_SIZE;
/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;
/* Check for duplicated breakpoints. Check also for a breakpoint
placed (branch instruction's destination) anywhere in sequence. */
if (last_breakpoint
&& (breaks[1] == breaks[0]
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
std::vector<CORE_ADDR> next_pcs;
for (index = 0; index <= last_breakpoint; index++)
next_pcs.push_back (breaks[index]);
return next_pcs;
}
#define SIGNED_SHORT(x) \
((sizeof (short) == 2) \
? ((int)(short)(x)) \
: ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
/* Limit the number of skipped non-prologue instructions, as the examining
of the prologue is expensive. */
static int max_skip_non_prologue_insns = 10;
/* Return nonzero if the given instruction OP can be part of the prologue
of a function and saves a parameter on the stack. FRAMEP should be
set if one of the previous instructions in the function has set the
Frame Pointer. */
static int
store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
{
/* Move parameters from argument registers to temporary register. */
if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
{
/* Rx must be scratch register r0. */
const int rx_regno = (op >> 16) & 31;
/* Ry: Only r3 - r10 are used for parameter passing. */
const int ry_regno = GET_SRC_REG (op);
if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
{
*r0_contains_arg = 1;
return 1;
}
else
return 0;
}
/* Save a General Purpose Register on stack. */
if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
(op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
{
/* Rx: Only r3 - r10 are used for parameter passing. */
const int rx_regno = GET_SRC_REG (op);
return (rx_regno >= 3 && rx_regno <= 10);
}
/* Save a General Purpose Register on stack via the Frame Pointer. */
if (framep &&
((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
(op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
(op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
{
/* Rx: Usually, only r3 - r10 are used for parameter passing.
However, the compiler sometimes uses r0 to hold an argument. */
const int rx_regno = GET_SRC_REG (op);
return ((rx_regno >= 3 && rx_regno <= 10)
|| (rx_regno == 0 && *r0_contains_arg));
}
if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
{
/* Only f2 - f8 are used for parameter passing. */
const int src_regno = GET_SRC_REG (op);
return (src_regno >= 2 && src_regno <= 8);
}
if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
{
/* Only f2 - f8 are used for parameter passing. */
const int src_regno = GET_SRC_REG (op);
return (src_regno >= 2 && src_regno <= 8);
}
/* Not an insn that saves a parameter on stack. */
return 0;
}
/* Assuming that INSN is a "bl" instruction located at PC, return
nonzero if the destination of the branch is a "blrl" instruction.
This sequence is sometimes found in certain function prologues.
It allows the function to load the LR register with a value that
they can use to access PIC data using PC-relative offsets. */
static int
bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
{
CORE_ADDR dest;
int immediate;
int absolute;
int dest_insn;
absolute = (int) ((insn >> 1) & 1);
immediate = ((insn & ~3) << 6) >> 6;
if (absolute)
dest = immediate;
else
dest = pc + immediate;
dest_insn = read_memory_integer (dest, 4, byte_order);
if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
return 1;
return 0;
}
/* Return true if OP is a stw or std instruction with
register operands RS and RA and any immediate offset.
If WITH_UPDATE is true, also return true if OP is
a stwu or stdu instruction with the same operands.
Return false otherwise.
*/
static bool
store_insn_p (unsigned long op, unsigned long rs,
unsigned long ra, bool with_update)
{
rs = rs << 21;
ra = ra << 16;
if (/* std RS, SIMM(RA) */
((op & 0xffff0003) == (rs | ra | 0xf8000000)) ||
/* stw RS, SIMM(RA) */
((op & 0xffff0000) == (rs | ra | 0x90000000)))
return true;
if (with_update)
{
if (/* stdu RS, SIMM(RA) */
((op & 0xffff0003) == (rs | ra | 0xf8000001)) ||
/* stwu RS, SIMM(RA) */
((op & 0xffff0000) == (rs | ra | 0x94000000)))
return true;
}
return false;
}
/* Masks for decoding a branch-and-link (bl) instruction.
BL_MASK and BL_INSTRUCTION are used in combination with each other.
The former is anded with the opcode in question; if the result of
this masking operation is equal to BL_INSTRUCTION, then the opcode in
question is a ``bl'' instruction.
BL_DISPLACEMENT_MASK is anded with the opcode in order to extract
the branch displacement. */
#define BL_MASK 0xfc000001
#define BL_INSTRUCTION 0x48000001
#define BL_DISPLACEMENT_MASK 0x03fffffc
static unsigned long
rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[4];
unsigned long op;
/* Fetch the instruction and convert it to an integer. */
if (target_read_memory (pc, buf, 4))
return 0;
op = extract_unsigned_integer (buf, 4, byte_order);
return op;
}
/* GCC generates several well-known sequences of instructions at the begining
of each function prologue when compiling with -fstack-check. If one of
such sequences starts at START_PC, then return the address of the
instruction immediately past this sequence. Otherwise, return START_PC. */
static CORE_ADDR
rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
{
CORE_ADDR pc = start_pc;
unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
/* First possible sequence: A small number of probes.
stw 0, -<some immediate>(1)
[repeat this instruction any (small) number of times]. */
if ((op & 0xffff0000) == 0x90010000)
{
while ((op & 0xffff0000) == 0x90010000)
{
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
}
return pc;
}
/* Second sequence: A probing loop.
addi 12,1,-<some immediate>
lis 0,-<some immediate>
[possibly ori 0,0,<some immediate>]
add 0,12,0
cmpw 0,12,0
beq 0,<disp>
addi 12,12,-<some immediate>
stw 0,0(12)
b <disp>
[possibly one last probe: stw 0,<some immediate>(12)]. */
while (1)
{
/* addi 12,1,-<some immediate> */
if ((op & 0xffff0000) != 0x39810000)
break;
/* lis 0,-<some immediate> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) != 0x3c000000)
break;
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
/* [possibly ori 0,0,<some immediate>] */
if ((op & 0xffff0000) == 0x60000000)
{
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
}
/* add 0,12,0 */
if (op != 0x7c0c0214)
break;
/* cmpw 0,12,0 */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if (op != 0x7c0c0000)
break;
/* beq 0,<disp> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xff9f0001) != 0x41820000)
break;
/* addi 12,12,-<some immediate> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) != 0x398c0000)
break;
/* stw 0,0(12) */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if (op != 0x900c0000)
break;
/* b <disp> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xfc000001) != 0x48000000)
break;
/* [possibly one last probe: stw 0,<some immediate>(12)]. */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) == 0x900c0000)
{
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
}
/* We found a valid stack-check sequence, return the new PC. */
return pc;
}
/* Third sequence: No probe; instead, a comparison between the stack size
limit (saved in a run-time global variable) and the current stack
pointer:
addi 0,1,-<some immediate>
lis 12,__gnat_stack_limit@ha
lwz 12,__gnat_stack_limit@l(12)
twllt 0,12
or, with a small variant in the case of a bigger stack frame:
addis 0,1,<some immediate>
addic 0,0,-<some immediate>
lis 12,__gnat_stack_limit@ha
lwz 12,__gnat_stack_limit@l(12)
twllt 0,12
*/
while (1)
{
/* addi 0,1,-<some immediate> */
if ((op & 0xffff0000) != 0x38010000)
{
/* small stack frame variant not recognized; try the
big stack frame variant: */
/* addis 0,1,<some immediate> */
if ((op & 0xffff0000) != 0x3c010000)
break;
/* addic 0,0,-<some immediate> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) != 0x30000000)
break;
}
/* lis 12,<some immediate> */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) != 0x3d800000)
break;
/* lwz 12,<some immediate>(12) */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xffff0000) != 0x818c0000)
break;
/* twllt 0,12 */
pc = pc + 4;
op = rs6000_fetch_instruction (gdbarch, pc);
if ((op & 0xfffffffe) != 0x7c406008)
break;
/* We found a valid stack-check sequence, return the new PC. */
return pc;
}
/* No stack check code in our prologue, return the start_pc. */
return start_pc;
}
/* return pc value after skipping a function prologue and also return
information about a function frame.
in struct rs6000_framedata fdata:
- frameless is TRUE, if function does not have a frame.
- nosavedpc is TRUE, if function does not save %pc value in its frame.
- offset is the initial size of this stack frame --- the amount by
which we decrement the sp to allocate the frame.
- saved_gpr is the number of the first saved gpr.
- saved_fpr is the number of the first saved fpr.
- saved_vr is the number of the first saved vr.
- saved_ev is the number of the first saved ev.
- alloca_reg is the number of the register used for alloca() handling.
Otherwise -1.
- gpr_offset is the offset of the first saved gpr from the previous frame.
- fpr_offset is the offset of the first saved fpr from the previous frame.
- vr_offset is the offset of the first saved vr from the previous frame.
- ev_offset is the offset of the first saved ev from the previous frame.
- lr_offset is the offset of the saved lr
- cr_offset is the offset of the saved cr
- vrsave_offset is the offset of the saved vrsave register. */
static CORE_ADDR
skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
struct rs6000_framedata *fdata)
{
CORE_ADDR orig_pc = pc;
CORE_ADDR last_prologue_pc = pc;
CORE_ADDR li_found_pc = 0;
gdb_byte buf[4];
unsigned long op;
long offset = 0;
long alloca_reg_offset = 0;
long vr_saved_offset = 0;
int lr_reg = -1;
int cr_reg = -1;
int vr_reg = -1;
int ev_reg = -1;
long ev_offset = 0;
int vrsave_reg = -1;
int reg;
int framep = 0;
int minimal_toc_loaded = 0;
int prev_insn_was_prologue_insn = 1;
int num_skip_non_prologue_insns = 0;
int r0_contains_arg = 0;
const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
memset (fdata, 0, sizeof (struct rs6000_framedata));
fdata->saved_gpr = -1;
fdata->saved_fpr = -1;
fdata->saved_vr = -1;
fdata->saved_ev = -1;
fdata->alloca_reg = -1;
fdata->frameless = 1;
fdata->nosavedpc = 1;
fdata->lr_register = -1;
pc = rs6000_skip_stack_check (gdbarch, pc);
if (pc >= lim_pc)
pc = lim_pc;
for (;; pc += 4)
{
/* Sometimes it isn't clear if an instruction is a prologue
instruction or not. When we encounter one of these ambiguous
cases, we'll set prev_insn_was_prologue_insn to 0 (false).
Otherwise, we'll assume that it really is a prologue instruction. */
if (prev_insn_was_prologue_insn)
last_prologue_pc = pc;
/* Stop scanning if we've hit the limit. */
if (pc >= lim_pc)
break;
prev_insn_was_prologue_insn = 1;
/* Fetch the instruction and convert it to an integer. */
if (target_read_memory (pc, buf, 4))
break;
op = extract_unsigned_integer (buf, 4, byte_order);
if ((op & 0xfc1fffff) == 0x7c0802a6)
{ /* mflr Rx */
/* Since shared library / PIC code, which needs to get its
address at runtime, can appear to save more than one link
register vis:
*INDENT-OFF*
stwu r1,-304(r1)
mflr r3
bl 0xff570d0 (blrl)
stw r30,296(r1)
mflr r30
stw r31,300(r1)
stw r3,308(r1);
...
*INDENT-ON*
remember just the first one, but skip over additional
ones. */
if (lr_reg == -1)
lr_reg = (op & 0x03e00000) >> 21;
if (lr_reg == 0)
r0_contains_arg = 0;
continue;
}
else if ((op & 0xfc1fffff) == 0x7c000026)
{ /* mfcr Rx */
cr_reg = (op & 0x03e00000) >> 21;
if (cr_reg == 0)
r0_contains_arg = 0;
continue;
}
else if ((op & 0xfc1f0000) == 0xd8010000)
{ /* stfd Rx,NUM(r1) */
reg = GET_SRC_REG (op);
if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
{
fdata->saved_fpr = reg;
fdata->fpr_offset = SIGNED_SHORT (op) + offset;
}
continue;
}
else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
(((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
(op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
(op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
{
reg = GET_SRC_REG (op);
if ((op & 0xfc1f0000) == 0xbc010000)
fdata->gpr_mask |= ~((1U << reg) - 1);
else
fdata->gpr_mask |= 1U << reg;
if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
{
fdata->saved_gpr = reg;
if ((op & 0xfc1f0003) == 0xf8010000)
op &= ~3UL;
fdata->gpr_offset = SIGNED_SHORT (op) + offset;
}
continue;
}
else if ((op & 0xffff0000) == 0x3c4c0000
|| (op & 0xffff0000) == 0x3c400000
|| (op & 0xffff0000) == 0x38420000)
{
/* . 0: addis 2,12,.TOC.-0b@ha
. addi 2,2,.TOC.-0b@l
or
. lis 2,.TOC.@ha
. addi 2,2,.TOC.@l
used by ELFv2 global entry points to set up r2. */
continue;
}
else if (op == 0x60000000)
{
/* nop */
/* Allow nops in the prologue, but do not consider them to
be part of the prologue unless followed by other prologue
instructions. */
prev_insn_was_prologue_insn = 0;
continue;
}
else if ((op & 0xffff0000) == 0x3c000000)
{ /* addis 0,0,NUM, used for >= 32k frames */
fdata->offset = (op & 0x0000ffff) << 16;
fdata->frameless = 0;
r0_contains_arg = 0;
continue;
}
else if ((op & 0xffff0000) == 0x60000000)
{ /* ori 0,0,NUM, 2nd half of >= 32k frames */
fdata->offset |= (op & 0x0000ffff);
fdata->frameless = 0;
r0_contains_arg = 0;
continue;
}
else if (lr_reg >= 0 &&
((store_insn_p (op, lr_reg, 1, true)) ||
(framep &&
(store_insn_p (op, lr_reg,
fdata->alloca_reg - tdep->ppc_gp0_regnum,
false)))))
{
if (store_insn_p (op, lr_reg, 1, true))
fdata->lr_offset = offset;
else /* LR save through frame pointer. */
fdata->lr_offset = alloca_reg_offset;
fdata->nosavedpc = 0;
/* Invalidate lr_reg, but don't set it to -1.
That would mean that it had never been set. */
lr_reg = -2;
if ((op & 0xfc000003) == 0xf8000000 || /* std */
(op & 0xfc000000) == 0x90000000) /* stw */
{
/* Does not update r1, so add displacement to lr_offset. */
fdata->lr_offset += SIGNED_SHORT (op);
}
continue;
}
else if (cr_reg >= 0 &&
(store_insn_p (op, cr_reg, 1, true)))
{
fdata->cr_offset = offset;
/* Invalidate cr_reg, but don't set it to -1.
That would mean that it had never been set. */
cr_reg = -2;
if ((op & 0xfc000003) == 0xf8000000 ||
(op & 0xfc000000) == 0x90000000)
{
/* Does not update r1, so add displacement to cr_offset. */
fdata->cr_offset += SIGNED_SHORT (op);
}
continue;
}
else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
{
/* bcl 20,xx,.+4 is used to get the current PC, with or without
prediction bits. If the LR has already been saved, we can
skip it. */
continue;
}
else if (op == 0x48000005)
{ /* bl .+4 used in
-mrelocatable */
fdata->used_bl = 1;
continue;
}
else if (op == 0x48000004)
{ /* b .+4 (xlc) */
break;
}
else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
in V.4 -mminimal-toc */
(op & 0xffff0000) == 0x3bde0000)
{ /* addi 30,30,foo@l */
continue;
}
else if ((op & 0xfc000001) == 0x48000001)
{ /* bl foo,
to save fprs??? */
fdata->frameless = 0;
/* If the return address has already been saved, we can skip
calls to blrl (for PIC). */
if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
{
fdata->used_bl = 1;
continue;
}
/* Don't skip over the subroutine call if it is not within
the first three instructions of the prologue and either
we have no line table information or the line info tells
us that the subroutine call is not part of the line
associated with the prologue. */
if ((pc - orig_pc) > 8)
{
struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
struct symtab_and_line this_sal = find_pc_line (pc, 0);
if ((prologue_sal.line == 0)
|| (prologue_sal.line != this_sal.line))
break;
}
op = read_memory_integer (pc + 4, 4, byte_order);
/* At this point, make sure this is not a trampoline
function (a function that simply calls another functions,
and nothing else). If the next is not a nop, this branch
was part of the function prologue. */
if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
break; /* Don't skip over
this branch. */
fdata->used_bl = 1;
continue;
}
/* update stack pointer */
else if ((op & 0xfc1f0000) == 0x94010000)
{ /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
fdata->frameless = 0;
fdata->offset = SIGNED_SHORT (op);
offset = fdata->offset;
continue;
}
else if ((op & 0xfc1f07fa) == 0x7c01016a)
{ /* stwux rX,r1,rY || stdux rX,r1,rY */
/* No way to figure out what r1 is going to be. */
fdata->frameless = 0;
offset = fdata->offset;
continue;
}
else if ((op & 0xfc1f0003) == 0xf8010001)
{ /* stdu rX,NUM(r1) */
fdata->frameless = 0;
fdata->offset = SIGNED_SHORT (op & ~3UL);
offset = fdata->offset;
continue;
}
else if ((op & 0xffff0000) == 0x38210000)
{ /* addi r1,r1,SIMM */
fdata->frameless = 0;
fdata->offset += SIGNED_SHORT (op);
offset = fdata->offset;
continue;
}
/* Load up minimal toc pointer. Do not treat an epilogue restore
of r31 as a minimal TOC load. */
else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
(op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
&& !framep
&& !minimal_toc_loaded)
{
minimal_toc_loaded = 1;
continue;
/* move parameters from argument registers to local variable
registers */
}
else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
(((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
(((op >> 21) & 31) <= 10) &&
((long) ((op >> 16) & 31)
>= fdata->saved_gpr)) /* Rx: local var reg */
{
continue;
/* store parameters in stack */
}
/* Move parameters from argument registers to temporary register. */
else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
{
continue;
/* Set up frame pointer */
}
else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
{
fdata->frameless = 0;
framep = 1;
fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
alloca_reg_offset = offset;
continue;
/* Another way to set up the frame pointer. */
}
else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
|| op == 0x7c3f0b78)
{ /* mr r31, r1 */
fdata->frameless = 0;
framep = 1;
fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
alloca_reg_offset = offset;
continue;
/* Another way to set up the frame pointer. */
}
else if ((op & 0xfc1fffff) == 0x38010000)
{ /* addi rX, r1, 0x0 */
fdata->frameless = 0;
framep = 1;
fdata->alloca_reg = (tdep->ppc_gp0_regnum
+ ((op & ~0x38010000) >> 21));
alloca_reg_offset = offset;
continue;
}
/* AltiVec related instructions. */
/* Store the vrsave register (spr 256) in another register for
later manipulation, or load a register into the vrsave
register. 2 instructions are used: mfvrsave and
mtvrsave. They are shorthand notation for mfspr Rn, SPR256
and mtspr SPR256, Rn. */
/* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
{
vrsave_reg = GET_SRC_REG (op);
continue;
}
else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
{
continue;
}
/* Store the register where vrsave was saved to onto the stack:
rS is the register where vrsave was stored in a previous
instruction. */
/* 100100 sssss 00001 dddddddd dddddddd */
else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
{
if (vrsave_reg == GET_SRC_REG (op))
{
fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
vrsave_reg = -1;
}
continue;
}
/* Compute the new value of vrsave, by modifying the register
where vrsave was saved to. */
else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
|| ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
{
continue;
}
/* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
in a pair of insns to save the vector registers on the
stack. */
/* 001110 00000 00000 iiii iiii iiii iiii */
/* 001110 01110 00000 iiii iiii iiii iiii */
else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
|| (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
{
if ((op & 0xffff0000) == 0x38000000)
r0_contains_arg = 0;
li_found_pc = pc;
vr_saved_offset = SIGNED_SHORT (op);
/* This insn by itself is not part of the prologue, unless
if part of the pair of insns mentioned above. So do not
record this insn as part of the prologue yet. */
prev_insn_was_prologue_insn = 0;
}
/* Store vector register S at (r31+r0) aligned to 16 bytes. */
/* 011111 sssss 11111 00000 00111001110 */
else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
{
if (pc == (li_found_pc + 4))
{
vr_reg = GET_SRC_REG (op);
/* If this is the first vector reg to be saved, or if
it has a lower number than others previously seen,
reupdate the frame info. */
if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
{
fdata->saved_vr = vr_reg;
fdata->vr_offset = vr_saved_offset + offset;
}
vr_saved_offset = -1;
vr_reg = -1;
li_found_pc = 0;
}
}
/* End AltiVec related instructions. */
/* Start BookE related instructions. */
/* Store gen register S at (r31+uimm).
Any register less than r13 is volatile, so we don't care. */
/* 000100 sssss 11111 iiiii 01100100001 */
else if (arch_info->mach == bfd_mach_ppc_e500
&& (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
{
if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
{
unsigned int imm;
ev_reg = GET_SRC_REG (op);
imm = (op >> 11) & 0x1f;
ev_offset = imm * 8;
/* If this is the first vector reg to be saved, or if
it has a lower number than others previously seen,
reupdate the frame info. */
if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
{
fdata->saved_ev = ev_reg;
fdata->ev_offset = ev_offset + offset;
}
}
continue;
}
/* Store gen register rS at (r1+rB). */
/* 000100 sssss 00001 bbbbb 01100100000 */
else if (arch_info->mach == bfd_mach_ppc_e500
&& (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
{
if (pc == (li_found_pc + 4))
{
ev_reg = GET_SRC_REG (op);
/* If this is the first vector reg to be saved, or if
it has a lower number than others previously seen,
reupdate the frame info. */
/* We know the contents of rB from the previous instruction. */
if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
{
fdata->saved_ev = ev_reg;
fdata->ev_offset = vr_saved_offset + offset;
}
vr_saved_offset = -1;
ev_reg = -1;
li_found_pc = 0;
}
continue;
}
/* Store gen register r31 at (rA+uimm). */
/* 000100 11111 aaaaa iiiii 01100100001 */
else if (arch_info->mach == bfd_mach_ppc_e500
&& (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
{
/* Wwe know that the source register is 31 already, but
it can't hurt to compute it. */
ev_reg = GET_SRC_REG (op);
ev_offset = ((op >> 11) & 0x1f) * 8;
/* If this is the first vector reg to be saved, or if
it has a lower number than others previously seen,
reupdate the frame info. */
if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
{
fdata->saved_ev = ev_reg;
fdata->ev_offset = ev_offset + offset;
}
continue;
}
/* Store gen register S at (r31+r0).
Store param on stack when offset from SP bigger than 4 bytes. */
/* 000100 sssss 11111 00000 01100100000 */
else if (arch_info->mach == bfd_mach_ppc_e500
&& (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
{
if (pc == (li_found_pc + 4))
{
if ((op & 0x03e00000) >= 0x01a00000)
{
ev_reg = GET_SRC_REG (op);
/* If this is the first vector reg to be saved, or if
it has a lower number than others previously seen,
reupdate the frame info. */
/* We know the contents of r0 from the previous
instruction. */
if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
{
fdata->saved_ev = ev_reg;
fdata->ev_offset = vr_saved_offset + offset;
}
ev_reg = -1;
}
vr_saved_offset = -1;
li_found_pc = 0;
continue;
}
}
/* End BookE related instructions. */
else
{
/* Not a recognized prologue instruction.
Handle optimizer code motions into the prologue by continuing
the search if we have no valid frame yet or if the return
address is not yet saved in the frame. Also skip instructions
if some of the GPRs expected to be saved are not yet saved. */
if (fdata->frameless == 0 && fdata->nosavedpc == 0
&& fdata->saved_gpr != -1)
{
unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
if ((fdata->gpr_mask & all_mask) == all_mask)
break;
}
if (op == 0x4e800020 /* blr */
|| op == 0x4e800420) /* bctr */
/* Do not scan past epilogue in frameless functions or
trampolines. */
break;
if ((op & 0xf4000000) == 0x40000000) /* bxx */
/* Never skip branches. */
break;
if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
/* Do not scan too many insns, scanning insns is expensive with
remote targets. */
break;
/* Continue scanning. */
prev_insn_was_prologue_insn = 0;
continue;
}
}
#if 0
/* I have problems with skipping over __main() that I need to address
* sometime. Previously, I used to use misc_function_vector which
* didn't work as well as I wanted to be. -MGO */
/* If the first thing after skipping a prolog is a branch to a function,
this might be a call to an initializer in main(), introduced by gcc2.
We'd like to skip over it as well. Fortunately, xlc does some extra
work before calling a function right after a prologue, thus we can
single out such gcc2 behaviour. */
if ((op & 0xfc000001) == 0x48000001)
{ /* bl foo, an initializer function? */
op = read_memory_integer (pc + 4, 4, byte_order);
if (op == 0x4def7b82)
{ /* cror 0xf, 0xf, 0xf (nop) */
/* Check and see if we are in main. If so, skip over this
initializer function as well. */
tmp = find_pc_misc_function (pc);
if (tmp >= 0
&& strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
return pc + 8;
}
}
#endif /* 0 */
if (pc == lim_pc && lr_reg >= 0)
fdata->lr_register = lr_reg;
fdata->offset = -fdata->offset;
return last_prologue_pc;
}
static CORE_ADDR
rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
struct rs6000_framedata frame;
CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
/* See if we can determine the end of the prologue via the symbol table.
If so, then return either PC, or the PC after the prologue, whichever
is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return std::max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. */
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to provide
that bound, then use an arbitrary large number as the upper bound. */
limit_pc = skip_prologue_using_sal (gdbarch, pc);
if (limit_pc == 0)
limit_pc = pc + 100; /* Magic. */
/* Do not allow limit_pc to be past the function end, if we know
where that end is... */
if (func_end_addr && limit_pc > func_end_addr)
limit_pc = func_end_addr;
pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
return pc;
}
/* When compiling for EABI, some versions of GCC emit a call to __eabi
in the prologue of main().
The function below examines the code pointed at by PC and checks to
see if it corresponds to a call to __eabi. If so, it returns the
address of the instruction following that call. Otherwise, it simply
returns PC. */
static CORE_ADDR
rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[4];
unsigned long op;
if (target_read_memory (pc, buf, 4))
return pc;
op = extract_unsigned_integer (buf, 4, byte_order);
if ((op & BL_MASK) == BL_INSTRUCTION)
{
CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
CORE_ADDR call_dest = pc + 4 + displ;
struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
/* We check for ___eabi (three leading underscores) in addition
to __eabi in case the GCC option "-fleading-underscore" was
used to compile the program. */
if (s.minsym != NULL
&& s.minsym->linkage_name () != NULL
&& (strcmp (s.minsym->linkage_name (), "__eabi") == 0
|| strcmp (s.minsym->linkage_name (), "___eabi") == 0))
pc += 4;
}
return pc;
}
/* All the ABI's require 16 byte alignment. */
static CORE_ADDR
rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
{
return (addr & -16);
}
/* Return whether handle_inferior_event() should proceed through code
starting at PC in function NAME when stepping.
The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
handle memory references that are too distant to fit in instructions
generated by the compiler. For example, if 'foo' in the following
instruction:
lwz r9,foo(r2)
is greater than 32767, the linker might replace the lwz with a branch to
somewhere in @FIX1 that does the load in 2 instructions and then branches
back to where execution should continue.
GDB should silently step over @FIX code, just like AIX dbx does.
Unfortunately, the linker uses the "b" instruction for the
branches, meaning that the link register doesn't get set.
Therefore, GDB's usual step_over_function () mechanism won't work.
Instead, use the gdbarch_skip_trampoline_code and
gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
@FIX code. */
static int
rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
CORE_ADDR pc, const char *name)
{
return name && startswith (name, "@FIX");
}
/* Skip code that the user doesn't want to see when stepping:
1. Indirect function calls use a piece of trampoline code to do context
switching, i.e. to set the new TOC table. Skip such code if we are on
its first instruction (as when we have single-stepped to here).
2. Skip shared library trampoline code (which is different from
indirect function call trampolines).
3. Skip bigtoc fixup code.
Result is desired PC to step until, or NULL if we are not in
code that should be skipped. */
static CORE_ADDR
rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned int ii, op;
int rel;
CORE_ADDR solib_target_pc;
struct bound_minimal_symbol msymbol;
static unsigned trampoline_code[] =
{
0x800b0000, /* l r0,0x0(r11) */
0x90410014, /* st r2,0x14(r1) */
0x7c0903a6, /* mtctr r0 */
0x804b0004, /* l r2,0x4(r11) */
0x816b0008, /* l r11,0x8(r11) */
0x4e800420, /* bctr */
0x4e800020, /* br */
0
};
/* Check for bigtoc fixup code. */
msymbol = lookup_minimal_symbol_by_pc (pc);
if (msymbol.minsym
&& rs6000_in_solib_return_trampoline (gdbarch, pc,
msymbol.minsym->linkage_name ()))
{
/* Double-check that the third instruction from PC is relative "b". */
op = read_memory_integer (pc + 8, 4, byte_order);
if ((op & 0xfc000003) == 0x48000000)
{
/* Extract bits 6-29 as a signed 24-bit relative word address and
add it to the containing PC. */
rel = ((int)(op << 6) >> 6);
return pc + 8 + rel;
}
}
/* If pc is in a shared library trampoline, return its target. */
solib_target_pc = find_solib_trampoline_target (frame, pc);
if (solib_target_pc)
return solib_target_pc;
for (ii = 0; trampoline_code[ii]; ++ii)
{
op = read_memory_integer (pc + (ii * 4), 4, byte_order);
if (op != trampoline_code[ii])
return 0;
}
ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
addr. */
pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
return pc;
}
/* ISA-specific vector types. */
static struct type *
rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (!tdep->ppc_builtin_type_vec64)
{
const struct builtin_type *bt = builtin_type (gdbarch);
/* The type we're building is this: */
#if 0
union __gdb_builtin_type_vec64
{
int64_t uint64;
float v2_float[2];
int32_t v2_int32[2];
int16_t v4_int16[4];
int8_t v8_int8[8];
};
#endif
struct type *t;
t = arch_composite_type (gdbarch,
"__ppc_builtin_type_vec64", TYPE_CODE_UNION);
append_composite_type_field (t, "uint64", bt->builtin_int64);
append_composite_type_field (t, "v2_float",
init_vector_type (bt->builtin_float, 2));
append_composite_type_field (t, "v2_int32",
init_vector_type (bt->builtin_int32, 2));
append_composite_type_field (t, "v4_int16",
init_vector_type (bt->builtin_int16, 4));
append_composite_type_field (t, "v8_int8",
init_vector_type (bt->builtin_int8, 8));
t->set_is_vector (true);
t->set_name ("ppc_builtin_type_vec64");
tdep->ppc_builtin_type_vec64 = t;
}
return tdep->ppc_builtin_type_vec64;
}
/* Vector 128 type. */
static struct type *
rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (!tdep->ppc_builtin_type_vec128)
{
const struct builtin_type *bt = builtin_type (gdbarch);
/* The type we're building is this
type = union __ppc_builtin_type_vec128 {
float128_t float128;
uint128_t uint128;
double v2_double[2];
float v4_float[4];
int32_t v4_int32[4];
int16_t v8_int16[8];
int8_t v16_int8[16];
}
*/
/* PPC specific type for IEEE 128-bit float field */
struct type *t_float128
= arch_float_type (gdbarch, 128, "float128_t", floatformats_ia64_quad);
struct type *t;
t = arch_composite_type (gdbarch,
"__ppc_builtin_type_vec128", TYPE_CODE_UNION);
append_composite_type_field (t, "float128", t_float128);
append_composite_type_field (t, "uint128", bt->builtin_uint128);
append_composite_type_field (t, "v2_double",
init_vector_type (bt->builtin_double, 2));
append_composite_type_field (t, "v4_float",
init_vector_type (bt->builtin_float, 4));
append_composite_type_field (t, "v4_int32",
init_vector_type (bt->builtin_int32, 4));
append_composite_type_field (t, "v8_int16",
init_vector_type (bt->builtin_int16, 8));
append_composite_type_field (t, "v16_int8",
init_vector_type (bt->builtin_int8, 16));
t->set_is_vector (true);
t->set_name ("ppc_builtin_type_vec128");
tdep->ppc_builtin_type_vec128 = t;
}
return tdep->ppc_builtin_type_vec128;
}
/* Return the name of register number REGNO, or the empty string if it
is an anonymous register. */
static const char *
rs6000_register_name (struct gdbarch *gdbarch, int regno)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* The upper half "registers" have names in the XML description,
but we present only the low GPRs and the full 64-bit registers
to the user. */
if (tdep->ppc_ev0_upper_regnum >= 0
&& tdep->ppc_ev0_upper_regnum <= regno
&& regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
return "";
/* Hide the upper halves of the vs0~vs31 registers. */
if (tdep->ppc_vsr0_regnum >= 0
&& tdep->ppc_vsr0_upper_regnum <= regno
&& regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
return "";
/* Hide the upper halves of the cvs0~cvs31 registers. */
if (PPC_CVSR0_UPPER_REGNUM <= regno
&& regno < PPC_CVSR0_UPPER_REGNUM + ppc_num_gprs)
return "";
/* Check if the SPE pseudo registers are available. */
if (IS_SPE_PSEUDOREG (tdep, regno))
{
static const char *const spe_regnames[] = {
"ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
"ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
"ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
"ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
};
return spe_regnames[regno - tdep->ppc_ev0_regnum];
}
/* Check if the decimal128 pseudo-registers are available. */
if (IS_DFP_PSEUDOREG (tdep, regno))
{
static const char *const dfp128_regnames[] = {
"dl0", "dl1", "dl2", "dl3",
"dl4", "dl5", "dl6", "dl7",
"dl8", "dl9", "dl10", "dl11",
"dl12", "dl13", "dl14", "dl15"
};
return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
}
/* Check if this is a vX alias for a raw vrX vector register. */
if (IS_V_ALIAS_PSEUDOREG (tdep, regno))
{
static const char *const vector_alias_regnames[] = {
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
};
return vector_alias_regnames[regno - tdep->ppc_v0_alias_regnum];
}
/* Check if this is a VSX pseudo-register. */
if (IS_VSX_PSEUDOREG (tdep, regno))
{
static const char *const vsx_regnames[] = {
"vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
"vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
"vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
"vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
"vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
"vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
"vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
"vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
"vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
};
return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
}
/* Check if the this is a Extended FP pseudo-register. */
if (IS_EFP_PSEUDOREG (tdep, regno))
{
static const char *const efpr_regnames[] = {
"f32", "f33", "f34", "f35", "f36", "f37", "f38",
"f39", "f40", "f41", "f42", "f43", "f44", "f45",
"f46", "f47", "f48", "f49", "f50", "f51",
"f52", "f53", "f54", "f55", "f56", "f57",
"f58", "f59", "f60", "f61", "f62", "f63"
};
return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
}
/* Check if this is a Checkpointed DFP pseudo-register. */
if (IS_CDFP_PSEUDOREG (tdep, regno))
{
static const char *const cdfp128_regnames[] = {
"cdl0", "cdl1", "cdl2", "cdl3",
"cdl4", "cdl5", "cdl6", "cdl7",
"cdl8", "cdl9", "cdl10", "cdl11",
"cdl12", "cdl13", "cdl14", "cdl15"
};
return cdfp128_regnames[regno - tdep->ppc_cdl0_regnum];
}
/* Check if this is a Checkpointed VSX pseudo-register. */
if (IS_CVSX_PSEUDOREG (tdep, regno))
{
static const char *const cvsx_regnames[] = {
"cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
"cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
"cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
"cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
"cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
"cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
"cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
"cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
"cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
};
return cvsx_regnames[regno - tdep->ppc_cvsr0_regnum];
}
/* Check if the this is a Checkpointed Extended FP pseudo-register. */
if (IS_CEFP_PSEUDOREG (tdep, regno))
{
static const char *const cefpr_regnames[] = {
"cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38",
"cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45",
"cf46", "cf47", "cf48", "cf49", "cf50", "cf51",
"cf52", "cf53", "cf54", "cf55", "cf56", "cf57",
"cf58", "cf59", "cf60", "cf61", "cf62", "cf63"
};
return cefpr_regnames[regno - tdep->ppc_cefpr0_regnum];
}
return tdesc_register_name (gdbarch, regno);
}
/* Return the GDB type object for the "standard" data type of data in
register N. */
static struct type *
rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
/* These are the e500 pseudo-registers. */
if (IS_SPE_PSEUDOREG (tdep, regnum))
return rs6000_builtin_type_vec64 (gdbarch);
else if (IS_DFP_PSEUDOREG (tdep, regnum)
|| IS_CDFP_PSEUDOREG (tdep, regnum))
/* PPC decimal128 pseudo-registers. */
return builtin_type (gdbarch)->builtin_declong;
else if (IS_V_ALIAS_PSEUDOREG (tdep, regnum))
return gdbarch_register_type (gdbarch,
tdep->ppc_vr0_regnum
+ (regnum
- tdep->ppc_v0_alias_regnum));
else if (IS_VSX_PSEUDOREG (tdep, regnum)
|| IS_CVSX_PSEUDOREG (tdep, regnum))
/* POWER7 VSX pseudo-registers. */
return rs6000_builtin_type_vec128 (gdbarch);
else if (IS_EFP_PSEUDOREG (tdep, regnum)
|| IS_CEFP_PSEUDOREG (tdep, regnum))
/* POWER7 Extended FP pseudo-registers. */
return builtin_type (gdbarch)->builtin_double;
else
internal_error (__FILE__, __LINE__,
_("rs6000_pseudo_register_type: "
"called on unexpected register '%s' (%d)"),
gdbarch_register_name (gdbarch, regnum), regnum);
}
/* Check if REGNUM is a member of REGGROUP. We only need to handle
the vX aliases for the vector registers by always returning false
to avoid duplicated information in "info register vector/all",
since the raw vrX registers will already show in these cases. For
other pseudo-registers we use the default membership function. */
static int
rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *group)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (IS_V_ALIAS_PSEUDOREG (tdep, regnum))
return 0;
else
return default_register_reggroup_p (gdbarch, regnum, group);
}
/* The register format for RS/6000 floating point registers is always
double, we need a conversion if the memory format is float. */
static int
rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
struct type *type)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
return (tdep->ppc_fp0_regnum >= 0
&& regnum >= tdep->ppc_fp0_regnum
&& regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
&& type->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type)
!= TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
}
static int
rs6000_register_to_value (struct frame_info *frame,
int regnum,
struct type *type,
gdb_byte *to,
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
gdb_byte from[PPC_MAX_REGISTER_SIZE];
gdb_assert (type->code () == TYPE_CODE_FLT);
if (!get_frame_register_bytes (frame, regnum, 0,
gdb::make_array_view (from,
register_size (gdbarch,
regnum)),
optimizedp, unavailablep))
return 0;
target_float_convert (from, builtin_type (gdbarch)->builtin_double,
to, type);
*optimizedp = *unavailablep = 0;
return 1;
}
static void
rs6000_value_to_register (struct frame_info *frame,
int regnum,
struct type *type,
const gdb_byte *from)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
gdb_byte to[PPC_MAX_REGISTER_SIZE];
gdb_assert (type->code () == TYPE_CODE_FLT);
target_float_convert (from, type,
to, builtin_type (gdbarch)->builtin_double);
put_frame_register (frame, regnum, to);
}
/* The type of a function that moves the value of REG between CACHE
or BUF --- in either direction. */
typedef enum register_status (*move_ev_register_func) (struct regcache *,