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/* Instruction printing code for the ARM
Copyright (C) 1994-2021 Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modification by James G. Smith (jsmith@cygnus.co.uk)
This file is part of libopcodes.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include <assert.h>
#include "disassemble.h"
#include "opcode/arm.h"
#include "opintl.h"
#include "safe-ctype.h"
#include "libiberty.h"
#include "floatformat.h"
/* FIXME: This shouldn't be done here. */
#include "coff/internal.h"
#include "libcoff.h"
#include "bfd.h"
#include "elf-bfd.h"
#include "elf/internal.h"
#include "elf/arm.h"
#include "mach-o.h"
/* Cached mapping symbol state. */
enum map_type
{
MAP_ARM,
MAP_THUMB,
MAP_DATA
};
struct arm_private_data
{
/* The features to use when disassembling optional instructions. */
arm_feature_set features;
/* Track the last type (although this doesn't seem to be useful) */
enum map_type last_type;
/* Tracking symbol table information */
int last_mapping_sym;
/* The end range of the current range being disassembled. */
bfd_vma last_stop_offset;
bfd_vma last_mapping_addr;
};
enum mve_instructions
{
MVE_VPST,
MVE_VPT_FP_T1,
MVE_VPT_FP_T2,
MVE_VPT_VEC_T1,
MVE_VPT_VEC_T2,
MVE_VPT_VEC_T3,
MVE_VPT_VEC_T4,
MVE_VPT_VEC_T5,
MVE_VPT_VEC_T6,
MVE_VCMP_FP_T1,
MVE_VCMP_FP_T2,
MVE_VCMP_VEC_T1,
MVE_VCMP_VEC_T2,
MVE_VCMP_VEC_T3,
MVE_VCMP_VEC_T4,
MVE_VCMP_VEC_T5,
MVE_VCMP_VEC_T6,
MVE_VDUP,
MVE_VEOR,
MVE_VFMAS_FP_SCALAR,
MVE_VFMA_FP_SCALAR,
MVE_VFMA_FP,
MVE_VFMS_FP,
MVE_VHADD_T1,
MVE_VHADD_T2,
MVE_VHSUB_T1,
MVE_VHSUB_T2,
MVE_VRHADD,
MVE_VLD2,
MVE_VLD4,
MVE_VST2,
MVE_VST4,
MVE_VLDRB_T1,
MVE_VLDRH_T2,
MVE_VLDRB_T5,
MVE_VLDRH_T6,
MVE_VLDRW_T7,
MVE_VSTRB_T1,
MVE_VSTRH_T2,
MVE_VSTRB_T5,
MVE_VSTRH_T6,
MVE_VSTRW_T7,
MVE_VLDRB_GATHER_T1,
MVE_VLDRH_GATHER_T2,
MVE_VLDRW_GATHER_T3,
MVE_VLDRD_GATHER_T4,
MVE_VLDRW_GATHER_T5,
MVE_VLDRD_GATHER_T6,
MVE_VSTRB_SCATTER_T1,
MVE_VSTRH_SCATTER_T2,
MVE_VSTRW_SCATTER_T3,
MVE_VSTRD_SCATTER_T4,
MVE_VSTRW_SCATTER_T5,
MVE_VSTRD_SCATTER_T6,
MVE_VCVT_FP_FIX_VEC,
MVE_VCVT_BETWEEN_FP_INT,
MVE_VCVT_FP_HALF_FP,
MVE_VCVT_FROM_FP_TO_INT,
MVE_VRINT_FP,
MVE_VMOV_HFP_TO_GP,
MVE_VMOV_GP_TO_VEC_LANE,
MVE_VMOV_IMM_TO_VEC,
MVE_VMOV_VEC_TO_VEC,
MVE_VMOV2_VEC_LANE_TO_GP,
MVE_VMOV2_GP_TO_VEC_LANE,
MVE_VMOV_VEC_LANE_TO_GP,
MVE_VMVN_IMM,
MVE_VMVN_REG,
MVE_VORR_IMM,
MVE_VORR_REG,
MVE_VORN,
MVE_VBIC_IMM,
MVE_VBIC_REG,
MVE_VMOVX,
MVE_VMOVL,
MVE_VMOVN,
MVE_VMULL_INT,
MVE_VMULL_POLY,
MVE_VQDMULL_T1,
MVE_VQDMULL_T2,
MVE_VQMOVN,
MVE_VQMOVUN,
MVE_VADDV,
MVE_VMLADAV_T1,
MVE_VMLADAV_T2,
MVE_VMLALDAV,
MVE_VMLAS,
MVE_VADDLV,
MVE_VMLSDAV_T1,
MVE_VMLSDAV_T2,
MVE_VMLSLDAV,
MVE_VRMLALDAVH,
MVE_VRMLSLDAVH,
MVE_VQDMLADH,
MVE_VQRDMLADH,
MVE_VQDMLAH,
MVE_VQRDMLAH,
MVE_VQDMLASH,
MVE_VQRDMLASH,
MVE_VQDMLSDH,
MVE_VQRDMLSDH,
MVE_VQDMULH_T1,
MVE_VQRDMULH_T2,
MVE_VQDMULH_T3,
MVE_VQRDMULH_T4,
MVE_VDDUP,
MVE_VDWDUP,
MVE_VIWDUP,
MVE_VIDUP,
MVE_VCADD_FP,
MVE_VCADD_VEC,
MVE_VHCADD,
MVE_VCMLA_FP,
MVE_VCMUL_FP,
MVE_VQRSHL_T1,
MVE_VQRSHL_T2,
MVE_VQRSHRN,
MVE_VQRSHRUN,
MVE_VQSHL_T1,
MVE_VQSHL_T2,
MVE_VQSHLU_T3,
MVE_VQSHL_T4,
MVE_VQSHRN,
MVE_VQSHRUN,
MVE_VRSHL_T1,
MVE_VRSHL_T2,
MVE_VRSHR,
MVE_VRSHRN,
MVE_VSHL_T1,
MVE_VSHL_T2,
MVE_VSHL_T3,
MVE_VSHLC,
MVE_VSHLL_T1,
MVE_VSHLL_T2,
MVE_VSHR,
MVE_VSHRN,
MVE_VSLI,
MVE_VSRI,
MVE_VADC,
MVE_VABAV,
MVE_VABD_FP,
MVE_VABD_VEC,
MVE_VABS_FP,
MVE_VABS_VEC,
MVE_VADD_FP_T1,
MVE_VADD_FP_T2,
MVE_VADD_VEC_T1,
MVE_VADD_VEC_T2,
MVE_VSBC,
MVE_VSUB_FP_T1,
MVE_VSUB_FP_T2,
MVE_VSUB_VEC_T1,
MVE_VSUB_VEC_T2,
MVE_VAND,
MVE_VBRSR,
MVE_VCLS,
MVE_VCLZ,
MVE_VCTP,
MVE_VMAX,
MVE_VMAXA,
MVE_VMAXNM_FP,
MVE_VMAXNMA_FP,
MVE_VMAXNMV_FP,
MVE_VMAXNMAV_FP,
MVE_VMAXV,
MVE_VMAXAV,
MVE_VMIN,
MVE_VMINA,
MVE_VMINNM_FP,
MVE_VMINNMA_FP,
MVE_VMINNMV_FP,
MVE_VMINNMAV_FP,
MVE_VMINV,
MVE_VMINAV,
MVE_VMLA,
MVE_VMUL_FP_T1,
MVE_VMUL_FP_T2,
MVE_VMUL_VEC_T1,
MVE_VMUL_VEC_T2,
MVE_VMULH,
MVE_VRMULH,
MVE_VNEG_FP,
MVE_VNEG_VEC,
MVE_VPNOT,
MVE_VPSEL,
MVE_VQABS,
MVE_VQADD_T1,
MVE_VQADD_T2,
MVE_VQSUB_T1,
MVE_VQSUB_T2,
MVE_VQNEG,
MVE_VREV16,
MVE_VREV32,
MVE_VREV64,
MVE_LSLL,
MVE_LSLLI,
MVE_LSRL,
MVE_ASRL,
MVE_ASRLI,
MVE_SQRSHRL,
MVE_SQRSHR,
MVE_UQRSHL,
MVE_UQRSHLL,
MVE_UQSHL,
MVE_UQSHLL,
MVE_URSHRL,
MVE_URSHR,
MVE_SRSHRL,
MVE_SRSHR,
MVE_SQSHLL,
MVE_SQSHL,
MVE_CINC,
MVE_CINV,
MVE_CNEG,
MVE_CSINC,
MVE_CSINV,
MVE_CSET,
MVE_CSETM,
MVE_CSNEG,
MVE_CSEL,
MVE_NONE
};
enum mve_unpredictable
{
UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
*/
UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
fcB = 1 (vpt). */
UNPRED_R13, /* Unpredictable because r13 (sp) or
r15 (sp) used. */
UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
UNPRED_Q_GT_4, /* Unpredictable because
vec reg start > 4 (vld4/st4). */
UNPRED_Q_GT_6, /* Unpredictable because
vec reg start > 6 (vld2/st2). */
UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
and WB bit = 1. */
UNPRED_Q_REGS_EQUAL, /* Unpredictable because vector registers are
equal. */
UNPRED_OS, /* Unpredictable because offset scaled == 1. */
UNPRED_GP_REGS_EQUAL, /* Unpredictable because gp registers are the
same. */
UNPRED_Q_REGS_EQ_AND_SIZE_1, /* Unpredictable because q regs equal and
size = 1. */
UNPRED_Q_REGS_EQ_AND_SIZE_2, /* Unpredictable because q regs equal and
size = 2. */
UNPRED_NONE /* No unpredictable behavior. */
};
enum mve_undefined
{
UNDEF_SIZE, /* undefined size. */
UNDEF_SIZE_0, /* undefined because size == 0. */
UNDEF_SIZE_2, /* undefined because size == 2. */
UNDEF_SIZE_3, /* undefined because size == 3. */
UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
UNDEF_SIZE_NOT_0, /* undefined because size != 0. */
UNDEF_SIZE_NOT_2, /* undefined because size != 2. */
UNDEF_SIZE_NOT_3, /* undefined because size != 3. */
UNDEF_NOT_UNS_SIZE_0, /* undefined because U == 0 and
size == 0. */
UNDEF_NOT_UNS_SIZE_1, /* undefined because U == 0 and
size == 1. */
UNDEF_NOT_UNSIGNED, /* undefined because U == 0. */
UNDEF_VCVT_IMM6, /* imm6 < 32. */
UNDEF_VCVT_FSI_IMM6, /* fsi = 0 and 32 >= imm6 <= 47. */
UNDEF_BAD_OP1_OP2, /* undefined with op2 = 2 and
op1 == (0 or 1). */
UNDEF_BAD_U_OP1_OP2, /* undefined with U = 1 and
op2 == 0 and op1 == (0 or 1). */
UNDEF_OP_0_BAD_CMODE, /* undefined because op == 0 and cmode
in {0xx1, x0x1}. */
UNDEF_XCHG_UNS, /* undefined because X == 1 and U == 1. */
UNDEF_NONE /* no undefined behavior. */
};
struct opcode32
{
arm_feature_set arch; /* Architecture defining this insn. */
unsigned long value; /* If arch is 0 then value is a sentinel. */
unsigned long mask; /* Recognise insn if (op & mask) == value. */
const char * assembler; /* How to disassemble this insn. */
};
struct cdeopcode32
{
arm_feature_set arch; /* Architecture defining this insn. */
uint8_t coproc_shift; /* coproc is this far into op. */
uint16_t coproc_mask; /* Length of coproc field in op. */
unsigned long value; /* If arch is 0 then value is a sentinel. */
unsigned long mask; /* Recognise insn if (op & mask) == value. */
const char * assembler; /* How to disassemble this insn. */
};
/* MVE opcodes. */
struct mopcode32
{
arm_feature_set arch; /* Architecture defining this insn. */
enum mve_instructions mve_op; /* Specific mve instruction for faster
decoding. */
unsigned long value; /* If arch is 0 then value is a sentinel. */
unsigned long mask; /* Recognise insn if (op & mask) == value. */
const char * assembler; /* How to disassemble this insn. */
};
enum isa {
ANY,
T32,
ARM
};
/* Shared (between Arm and Thumb mode) opcode. */
struct sopcode32
{
enum isa isa; /* Execution mode instruction availability. */
arm_feature_set arch; /* Architecture defining this insn. */
unsigned long value; /* If arch is 0 then value is a sentinel. */
unsigned long mask; /* Recognise insn if (op & mask) == value. */
const char * assembler; /* How to disassemble this insn. */
};
struct opcode16
{
arm_feature_set arch; /* Architecture defining this insn. */
unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
const char *assembler; /* How to disassemble this insn. */
};
/* print_insn_coprocessor recognizes the following format control codes:
%% %
%c print condition code (always bits 28-31 in ARM mode)
%b print condition code allowing cp_num == 9
%q print shifter argument
%u print condition code (unconditional in ARM mode,
UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
%C print vscclrm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
%J print register for VLDR instruction
%K print address for VLDR instruction
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitfield>c print as a condition code (for vsel)
%<bitfield>r print as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
%<bitfield>ru as %<>r but each u register must be unique.
%<bitfield>d print the bitfield in decimal
%<bitfield>k print immediate for VFPv3 conversion instruction
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
%<bitfield>f print a floating point constant if >7 else a
floating point register
%<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
%<bitfield>g print as an iWMMXt 64-bit register
%<bitfield>G print as an iWMMXt general purpose or control register
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>V print as a NEON D or Q register
%<bitfield>E print a quarter-float immediate value
%y<code> print a single precision VFP reg.
Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
%z<code> print a double precision VFP reg
Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order
%L print as an iWMMXt N/M width field.
%Z print the Immediate of a WSHUFH instruction.
%l like 'A' except use byte offsets for 'B' & 'H'
versions.
%i print 5-bit immediate in bits 8,3..0
(print "32" when 0)
%r print register offset address for wldt/wstr instruction. */
enum opcode_sentinel_enum
{
SENTINEL_IWMMXT_START = 1,
SENTINEL_IWMMXT_END,
SENTINEL_GENERIC_START
} opcode_sentinels;
#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
#define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
#define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
/* print_insn_cde recognizes the following format control codes:
%% %
%a print 'a' iff bit 28 is 1
%p print bits 8-10 as coprocessor
%<bitfield>d print as decimal
%<bitfield>r print as an ARM register
%<bitfield>n print as an ARM register but r15 is APSR_nzcv
%<bitfield>T print as an ARM register + 1
%<bitfield>R as %r but r13 is UNPREDICTABLE
%<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
%j print immediate taken from bits (16..21,7,0..5)
%k print immediate taken from bits (20..21,7,0..5).
%l print immediate taken from bits (20..22,7,4..5). */
/* At the moment there is only one valid position for the coprocessor number,
and hence that's encoded in the macro below. */
#define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
{ ARCH, 8, 7, VALUE, MASK, ASM }
static const struct cdeopcode32 cde_opcodes[] =
{
/* Custom Datapath Extension instructions. */
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000000, 0xefc00840,
"cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000040, 0xefc00840,
"cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400000, 0xefc00840,
"cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400040, 0xefc00840,
"cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800000, 0xef800840,
"cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800040, 0xef800840,
"cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200000, 0xeeb00840,
"vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200040, 0xeeb00840,
"vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300000, 0xeeb00840,
"vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300040, 0xeeb00840,
"vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800000, 0xee800840,
"vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800040, 0xee800840,
"vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
};
static const struct sopcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
"mia%c\tacc0, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
"miaph%c\tacc0, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800120, 0x0f800ff0,
"wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000a0, 0x0f800ff0,
"wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_CORE_LOW (0),
SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
/* Armv8.1-M Mainline instructions. */
{T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
{T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
/* ARMv8-M Mainline Security Extensions instructions. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
/* Register load/store. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
/* FP v5. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
/* BFloat16 instructions. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
/* Dot Product instructions in the space of coprocessor 13. */
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
/* ARMv8.3 javascript conversion instruction. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
/* Generic coprocessor instructions. These are only matched if a more specific
SIMD or co-processor instruction does not match first. */
static const struct sopcode32 generic_coprocessor_opcodes[] =
{
/* Generic coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
"mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
"cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
"mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
"mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
"mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
"mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
/* V5 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
"cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
"mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
"mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
/* Neon opcode table: This does not encode the top byte -- that is
checked by the print_insn_neon routine, as it depends on whether we are
doing thumb32 or arm32 disassembly. */
/* print_insn_neon recognizes the following format control codes:
%% %
%c print condition code
%u print condition code (unconditional in ARM mode,
UNPREDICTABLE if not AL in Thumb)
%A print v{st,ld}[1234] operands
%B print v{st,ld}[1234] any one operands
%C print v{st,ld}[1234] single->all operands
%D print scalar
%E print vmov, vmvn, vorr, vbic encoded constant
%F print vtbl,vtbx register list
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>e print the 2^N - bitfield in decimal
%<bitfield>D print as a NEON D register
%<bitfield>Q print as a NEON Q register
%<bitfield>R print as a NEON D or Q register
%<bitfield>Sn print byte scaled width limited by n
%<bitfield>Tn print short scaled width limited by n
%<bitfield>Un print long scaled width limited by n
%<bitfield>'c print specified char iff bitfield is all ones
%<bitfield>`c print specified char iff bitfield is all zeroes
%<bitfield>?ab... select from array of values in big endian order. */
static const struct opcode32 neon_opcodes[] =
{
/* Extract. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00840, 0xffb00850,
"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00000, 0xffb00810,
"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
/* Table lookup. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
/* Half-precision conversions. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
/* NEON fused multiply add instructions. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* BFloat16 instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
/* Matrix Multiply instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20300, 0xffb30fd0,
"vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0600, 0xffbf0e10,
"vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3b70600, 0xffbf0e10,
"vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000b00, 0xff800f10,
"vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000b10, 0xff800f10,
"vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3000b00, 0xff800f10,
"vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000000, 0xfe800f10,
"vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000010, 0xfe800f10,
"vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000100, 0xfe800f10,
"vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000200, 0xfe800f10,
"vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000210, 0xfe800f10,
"vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000300, 0xfe800f10,
"vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000310, 0xfe800f10,
"vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000400, 0xfe800f10,
"vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000410, 0xfe800f10,
"vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000500, 0xfe800f10,
"vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000510, 0xfe800f10,
"vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000600, 0xfe800f10,
"vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000610, 0xfe800f10,
"vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000700, 0xfe800f10,
"vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000710, 0xfe800f10,
"vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000910, 0xfe800f10,
"vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000a00, 0xfe800f10,
"vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2000a10, 0xfe800f10,
"vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf3000b10, 0xff800f10,
"vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf3000c10, 0xff800f10,
"vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
/* One register and an immediate value. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
/* Two registers and a shift amount. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880950, 0xfeb80fd0,
"vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900950, 0xfeb00fd0,
"vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00950, 0xfea00fd0,
"vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00e10, 0xfea00e90,
"vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2a00c10, 0xfea00e90,
"vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
/* Three registers of different lengths. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800400, 0xff800f50,
"vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800600, 0xff800f50,
"vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800900, 0xff800f50,
"vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800b00, 0xff800f50,
"vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800d00, 0xff800f50,
"vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800400, 0xff800f50,
"vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800600, 0xff800f50,
"vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800000, 0xfe800f50,
"vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800100, 0xfe800f50,
"vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800200, 0xfe800f50,
"vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800300, 0xfe800f50,
"vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800500, 0xfe800f50,
"vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800700, 0xfe800f50,
"vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800800, 0xfe800f50,
"vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800a00, 0xfe800f50,
"vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800c00, 0xfe800f50,
"vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
/* Two registers and a scalar. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800240, 0xfe800f50,
"vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800640, 0xfe800f50,
"vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2800a40, 0xfe800f50,
"vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf2800e40, 0xff800f50,
"vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf2800f40, 0xff800f50,
"vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf3800e40, 0xff800f50,
"vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
0xf3800f40, 0xff800f50,
"vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
},
/* Element and structure load/store. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
{ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
};
/* mve opcode table. */
/* print_insn_mve recognizes the following format control codes:
%% %
%a print '+' or '-' or imm offset in vldr[bhwd] and
vstr[bhwd]
%c print condition code
%d print addr mode of MVE vldr[bhw] and vstr[bhw]
%u print 'U' (unsigned) or 'S' for various mve instructions
%i print MVE predicate(s) for vpt and vpst
%j print a 5-bit immediate from hw2[14:12,7:6]
%k print 48 if the 7th position bit is set else print 64.
%m print rounding mode for vcvt and vrint
%n print vector comparison code for predicated instruction
%s print size for various vcvt instructions
%v print vector predicate for instruction in predicated
block
%o print offset scaled for vldr[hwd] and vstr[hwd]
%w print writeback mode for MVE v{st,ld}[24]
%B print v{st,ld}[24] any one operands
%E print vmov, vmvn, vorr, vbic encoded constant
%N print generic index for vmov
%T print bottom ('b') or top ('t') of source register
%X print exchange field in vmla* instructions
%<bitfield>r print as an ARM register
%<bitfield>d print the bitfield in decimal
%<bitfield>A print accumulate or not
%<bitfield>c print bitfield as a condition code
%<bitfield>C print bitfield as an inverted condition code
%<bitfield>Q print as a MVE Q register
%<bitfield>F print as a MVE S register
%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
UNPREDICTABLE
%<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
%<bitfield>s print size for vector predicate & non VMOV instructions
%<bitfield>I print carry flag or not
%<bitfield>i print immediate for vstr/vldr reg +/- imm
%<bitfield>h print high half of 64-bit destination reg
%<bitfield>k print immediate for vector conversion instruction
%<bitfield>l print low half of 64-bit destination reg
%<bitfield>o print rotate value for vcmul
%<bitfield>u print immediate value for vddup/vdwdup
%<bitfield>x print the bitfield in hex.
*/
static const struct mopcode32 mve_opcodes[] =
{
/* MVE. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPST,
0xfe310f4d, 0xffbf1fff,
"vpst%i"
},
/* Floating point VPT T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VPT_FP_T1,
0xee310f00, 0xefb10f50,
"vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
/* Floating point VPT T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VPT_FP_T2,
0xee310f40, 0xefb10f50,
"vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T1,
0xfe010f00, 0xff811f51,
"vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T2,
0xfe010f01, 0xff811f51,
"vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T3. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T3,
0xfe011f00, 0xff811f50,
"vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VPT T4. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T4,
0xfe010f40, 0xff811f70,
"vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T5. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T5,
0xfe010f60, 0xff811f70,
"vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VPT T6. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VPT_VEC_T6,
0xfe011f40, 0xff811f50,
"vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VBIC immediate. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VBIC_IMM,
0xef800070, 0xefb81070,
"vbic%v.i%8-11s\t%13-15,22Q, %E"},
/* Vector VBIC register. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VBIC_REG,
0xef100150, 0xffb11f51,
"vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABAV. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABAV,
0xee800f01, 0xefc10f51,
"vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
/* Vector VABD floating point. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VABD_FP,
0xff200d40, 0xffa11f51,
"vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABD_VEC,
0xef000740, 0xef811f51,
"vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VABS floating point. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VABS_FP,
0xFFB10740, 0xFFB31FD1,
"vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VABS. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VABS_VEC,
0xffb10340, 0xffb31fd1,
"vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VADD floating point T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VADD_FP_T1,
0xef000d40, 0xffa11f51,
"vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VADD floating point T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VADD_FP_T2,
0xee300f40, 0xefb11f70,
"vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VADD T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADD_VEC_T1,
0xef000840, 0xff811f51,
"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VADD T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADD_VEC_T2,
0xee010f40, 0xff811f70,
"vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VADDLV. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADDLV,
0xee890f00, 0xef8f1fd1,
"vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
/* Vector VADDV. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADDV,
0xeef10f00, 0xeff31fd1,
"vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
/* Vector VADC. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VADC,
0xee300f00, 0xffb10f51,
"vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VAND. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VAND,
0xef000150, 0xffb11f51,
"vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VBRSR register. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VBRSR,
0xfe011e60, 0xff811f70,
"vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VCADD floating point. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCADD_FP,
0xfc800840, 0xfea11f51,
"vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
/* Vector VCADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCADD_VEC,
0xfe000f00, 0xff810f51,
"vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
/* Vector VCLS. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCLS,
0xffb00440, 0xffb31fd1,
"vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCLZ. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCLZ,
0xffb004c0, 0xffb31fd1,
"vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
/* Vector VCMLA. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMLA_FP,
0xfc200840, 0xfe211f51,
"vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
/* Vector VCMP floating point T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMP_FP_T1,
0xee310f00, 0xeff1ef50,
"vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP floating point T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMP_FP_T2,
0xee310f40, 0xeff1ef50,
"vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T1,
0xfe010f00, 0xffc1ff51,
"vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T2,
0xfe010f01, 0xffc1ff51,
"vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T3. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T3,
0xfe011f00, 0xffc1ff50,
"vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
/* Vector VCMP T4. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T4,
0xfe010f40, 0xffc1ff70,
"vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T5. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T5,
0xfe010f60, 0xffc1ff70,
"vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VCMP T6. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCMP_VEC_T6,
0xfe011f40, 0xffc1ff50,
"vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
/* Vector VDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDUP,
0xeea00b10, 0xffb10f5f,
"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
/* Vector VEOR. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VEOR,
0xff000150, 0xffd11f51,
"veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMA, vector * scalar. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMA_FP_SCALAR,
0xee310e40, 0xefb11f70,
"vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VFMA floating point. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMA_FP,
0xef000c50, 0xffa11f51,
"vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMS floating point. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMS_FP,
0xef200c50, 0xffa11f51,
"vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VFMAS, vector * scalar. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VFMAS_FP_SCALAR,
0xee311e40, 0xefb11f70,
"vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VHADD T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHADD_T1,
0xef000040, 0xef811f51,
"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VHADD T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHADD_T2,
0xee000f40, 0xef811f70,
"vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VHSUB T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHSUB_T1,
0xef000240, 0xef811f51,
"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VHSUB T2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHSUB_T2,
0xee001f40, 0xef811f70,
"vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VCMUL. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMUL_FP,
0xee300e00, 0xefb10f50,
"vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
/* Vector VCTP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCTP,
0xf000e801, 0xffc0ffff,
"vctp%v.%20-21s\t%16-19r"},
/* Vector VDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDUP,
0xeea00b10, 0xffb10f5f,
"vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
/* Vector VRHADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRHADD,
0xef000140, 0xef811f51,
"vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
/* Vector VCVT. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_FIX_VEC,
0xef800c50, 0xef801cd1,
"vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},