blob: db72c039bfd4c322f6a70a53fa3b6f798c35b756 [file] [log] [blame]
/* mips-opc.c -- MIPS opcode list.
Copyright (C) 1993-2021 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
MIPS-3D, MDMX, and MIPS32 Release 2 support added by Broadcom
Corporation (SiByte).
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#include "sysdep.h"
#include <stdio.h>
#include "opcode/mips.h"
#include "mips-formats.h"
/* The 4-bit XYZW mask used in some VU0 instructions. */
const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21 };
static unsigned char reg_0_map[] = { 0 };
/* Return the mips_operand structure for the operand at the beginning of P. */
const struct mips_operand *
decode_mips_operand (const char *p)
{
switch (p[0])
{
case '-':
switch (p[1])
{
case 'a': INT_ADJ (19, 0, 262143, 2, false);
case 'b': INT_ADJ (18, 0, 131071, 3, false);
case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
case 'm': SPECIAL (20, 6, SAVE_RESTORE_LIST);
case 's': SPECIAL (5, 21, NON_ZERO_REG);
case 't': SPECIAL (5, 16, NON_ZERO_REG);
case 'u': PREV_CHECK (5, 16, true, false, false, false);
case 'v': PREV_CHECK (5, 16, true, true, false, false);
case 'w': PREV_CHECK (5, 16, false, true, true, true);
case 'x': PREV_CHECK (5, 21, true, false, false, true);
case 'y': PREV_CHECK (5, 21, false, true, false, false);
case 'A': PCREL (19, 0, true, 2, 2, false, false);
case 'B': PCREL (18, 0, true, 3, 3, false, false);
}
break;
case '+':
switch (p[1])
{
case '1': HINT (5, 6);
case '2': HINT (10, 6);
case '3': HINT (15, 6);
case '4': HINT (20, 6);
case '5': REG (5, 6, VF);
case '6': REG (5, 11, VF);
case '7': REG (5, 16, VF);
case '8': REG (5, 6, VI);
case '9': REG (5, 11, VI);
case '0': REG (5, 16, VI);
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
case 'B': MSB (5, 11, 1, true, 32); /* (1 .. 32), 32-bit op */
case 'C': MSB (5, 11, 1, false, 32); /* (1 .. 32), 32-bit op */
case 'E': BIT (5, 6, 32); /* (32 .. 63) */
case 'F': MSB (5, 11, 33, true, 64); /* (33 .. 64), 64-bit op */
case 'G': MSB (5, 11, 33, false, 64); /* (33 .. 64), 64-bit op */
case 'H': MSB (5, 11, 1, false, 64); /* (1 .. 32), 64-bit op */
case 'I': UINT (2, 6);
case 'J': HINT (10, 11);
case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX);
case 'L': SPECIAL (2, 21, VU0_SUFFIX);
case 'M': SPECIAL (2, 23, VU0_SUFFIX);
case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX);
case 'O': UINT (3, 6);
case 'P': BIT (5, 6, 32); /* (32 .. 63) */
case 'Q': SINT (10, 6);
case 'R': SPECIAL (0, 0, PC);
case 'S': MSB (5, 11, 0, false, 63); /* (0 .. 31), 64-bit op */
case 'T': INT_ADJ (10, 16, 511, 0, false); /* (-512 .. 511) << 0 */
case 'U': INT_ADJ (10, 16, 511, 1, false); /* (-512 .. 511) << 1 */
case 'V': INT_ADJ (10, 16, 511, 2, false); /* (-512 .. 511) << 2 */
case 'W': INT_ADJ (10, 16, 511, 3, false); /* (-512 .. 511) << 3 */
case 'X': BIT (5, 16, 32); /* (32 .. 63) */
case 'Z': REG (5, 0, FP);
case 'a': SINT (8, 6);
case 'b': SINT (8, 3);
case 'c': INT_ADJ (9, 6, 255, 4, false); /* (-256 .. 255) << 4 */
case 'd': REG (5, 6, MSA);
case 'e': REG (5, 11, MSA);
case 'f': INT_ADJ (15, 6, 32767, 3, true);
case 'g': SINT (5, 6);
case 'h': REG (5, 16, MSA);
case 'i': JALX (26, 0, 2);
case 'j': SINT (9, 7);
case 'k': REG (5, 6, GP);
case 'l': REG (5, 6, MSA_CTRL);
case 'm': REG (0, 0, R5900_ACC);
case 'n': REG (5, 11, MSA_CTRL);
case 'o': SPECIAL (4, 16, IMM_INDEX);
case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */
case 'q': REG (0, 0, R5900_Q);
case 'r': REG (0, 0, R5900_R);
case 's': MSB (5, 11, 0, false, 31); /* (0 .. 31) */
case 't': REG (5, 16, COPRO);
case 'u': SPECIAL (3, 16, IMM_INDEX);
case 'v': SPECIAL (2, 16, IMM_INDEX);
case 'w': SPECIAL (1, 16, IMM_INDEX);
case 'x': BIT (5, 16, 0); /* (0 .. 31) */
case 'y': REG (0, 0, R5900_I);
case 'z': REG (5, 0, GP);
case '~': BIT (2, 6, 1); /* (1 .. 4) */
case '!': BIT (3, 16, 0); /* (0 .. 7) */
case '@': BIT (4, 16, 0); /* (0 .. 15) */
case '#': BIT (6, 16, 0); /* (0 .. 63) */
case '$': UINT (5, 16); /* (0 .. 31) */
case '%': SINT (5, 16); /* (-16 .. 15) */
case '^': SINT (10, 11); /* (-512 .. 511) */
case '&': SPECIAL (0, 0, IMM_INDEX);
case '*': SPECIAL (5, 16, REG_INDEX);
case '|': BIT (8, 16, 0); /* (0 .. 255) */
case ':': SINT (11, 0);
case '\'': BRANCH (26, 0, 2);
case '"': BRANCH (21, 0, 2);
case ';': SPECIAL (10, 16, SAME_RS_RT);
case '\\': BIT (2, 8, 0); /* (0 .. 3) */
}
break;
case '<': BIT (5, 6, 0); /* (0 .. 31) */
case '>': BIT (5, 6, 32); /* (32 .. 63) */
case '%': UINT (3, 21);
case ':': SINT (7, 19);
case '\'': HINT (6, 16);
case '@': SINT (10, 16);
case '!': UINT (1, 5);
case '$': UINT (1, 4);
case '*': REG (2, 18, ACC);
case '&': REG (2, 13, ACC);
case '~': SINT (12, 0);
case '\\': BIT (3, 12, 0); /* (0 .. 7) */
case '0': SINT (6, 20);
case '1': HINT (5, 6);
case '2': HINT (2, 11);
case '3': HINT (3, 21);
case '4': HINT (4, 21);
case '5': HINT (8, 16);
case '6': HINT (5, 21);
case '7': REG (2, 11, ACC);
case '8': HINT (6, 11);
case '9': REG (2, 21, ACC);
case 'B': HINT (20, 6);
case 'C': HINT (25, 0);
case 'D': REG (5, 6, FP);
case 'E': REG (5, 16, COPRO);
case 'G': REG (5, 11, COPRO);
case 'H': UINT (3, 0);
case 'J': HINT (19, 6);
case 'K': REG (5, 11, HW);
case 'M': REG (3, 8, CCC);
case 'N': REG (3, 18, CCC);
case 'O': UINT (3, 21);
case 'P': SPECIAL (5, 1, PERF_REG);
case 'Q': SPECIAL (10, 16, MDMX_IMM_REG);
case 'R': REG (5, 21, FP);
case 'S': REG (5, 11, FP);
case 'T': REG (5, 16, FP);
case 'U': SPECIAL (10, 11, CLO_CLZ_DEST);
case 'V': OPTIONAL_REG (5, 11, FP);
case 'W': OPTIONAL_REG (5, 16, FP);
case 'X': REG (5, 6, VEC);
case 'Y': REG (5, 11, VEC);
case 'Z': REG (5, 16, VEC);
case 'a': JUMP (26, 0, 2);
case 'b': REG (5, 21, GP);
case 'c': HINT (10, 16);
case 'd': REG (5, 11, GP);
case 'e': UINT (3, 22)
case 'g': REG (5, 11, CONTROL);
case 'h': HINT (5, 11);
case 'i': HINT (16, 0);
case 'j': SINT (16, 0);
case 'k': HINT (5, 16);
case 'o': SINT (16, 0);
case 'p': BRANCH (16, 0, 2);
case 'q': HINT (10, 6);
case 'r': OPTIONAL_REG (5, 21, GP);
case 's': REG (5, 21, GP);
case 't': REG (5, 16, GP);
case 'u': HINT (16, 0);
case 'v': OPTIONAL_REG (5, 21, GP);
case 'w': OPTIONAL_REG (5, 16, GP);
case 'x': REG (0, 0, GP);
case 'y': REG (5, 16, CONTROL);
case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
}
return 0;
}
/* Short hand so the lines aren't too long. */
#define LC INSN_LOAD_COPROC
#define UBD INSN_UNCOND_BRANCH_DELAY
#define CBD INSN_COND_BRANCH_DELAY
#define CM INSN_COPROC_MOVE
#define CLD (INSN_LOAD_MEMORY|INSN_COPROC_MEMORY_DELAY)
#define CBL INSN_COND_BRANCH_LIKELY
#define NODS INSN_NO_DELAY_SLOT
#define TRAP INSN_NO_DELAY_SLOT
#define LM INSN_LOAD_MEMORY
#define SM INSN_STORE_MEMORY
#define WR_1 INSN_WRITE_1
#define WR_2 INSN_WRITE_2
#define RD_1 INSN_READ_1
#define RD_2 INSN_READ_2
#define RD_3 INSN_READ_3
#define RD_4 INSN_READ_4
#define RD_31 INSN2_READ_GPR_31
#define MOD_1 (WR_1|RD_1)
#define MOD_2 (WR_2|RD_2)
#define WR_31 INSN_WRITE_GPR_31
#define WR_CC INSN_WRITE_COND_CODE
#define RD_CC INSN_READ_COND_CODE
#define RD_C0 INSN_COP
#define RD_C1 INSN_COP
#define RD_C2 INSN_COP
#define RD_C3 INSN_COP
#define WR_C0 INSN_COP
#define WR_C1 INSN_COP
#define WR_C2 INSN_COP
#define WR_C3 INSN_COP
#define UDI INSN_UDI
#define CP INSN_COP
#define WR_HI INSN_WRITE_HI
#define RD_HI INSN_READ_HI
#define MOD_HI WR_HI|RD_HI
#define WR_LO INSN_WRITE_LO
#define RD_LO INSN_READ_LO
#define MOD_LO WR_LO|RD_LO
#define WR_HILO WR_HI|WR_LO
#define RD_HILO RD_HI|RD_LO
#define MOD_HILO WR_HILO|RD_HILO
#define RD_SP INSN2_READ_SP
#define WR_SP INSN2_WRITE_SP
#define MOD_SP (RD_SP|WR_SP)
#define IS_M INSN_MULT
#define WR_MACC INSN2_WRITE_MDMX_ACC
#define RD_MACC INSN2_READ_MDMX_ACC
#define RD_pc INSN2_READ_PC
#define FS INSN2_FORBIDDEN_SLOT
#define I1 INSN_ISA1
#define I2 INSN_ISA2
#define I3 INSN_ISA3
#define I4 INSN_ISA4
#define I5 INSN_ISA5
#define I32 INSN_ISA32
#define I64 INSN_ISA64
#define I33 INSN_ISA32R2
#define I34 INSN_ISA32R3
#define I36 INSN_ISA32R5
#define I37 INSN_ISA32R6
#define I65 INSN_ISA64R2
#define I66 INSN_ISA64R3
#define I68 INSN_ISA64R5
#define I69 INSN_ISA64R6
#define I3_32 INSN_ISA3_32
#define I3_33 INSN_ISA3_32R2
#define I4_32 INSN_ISA4_32
#define I4_33 INSN_ISA4_32R2
#define I5_33 INSN_ISA5_32R2
/* MIPS64 MIPS-3D ASE support. */
#define M3D ASE_MIPS3D
/* MIPS32 SmartMIPS ASE support. */
#define SMT ASE_SMARTMIPS
/* MIPS64 MDMX ASE support. */
#define MX ASE_MDMX
#define IL2E (INSN_LOONGSON_2E)
#define IL2F (INSN_LOONGSON_2F)
#define P3 INSN_4650
#define L1 INSN_4010
#define V1 (INSN_4100 | INSN_4111 | INSN_4120)
#define T3 INSN_3900
/* Emotion Engine MIPS r5900. */
#define EE INSN_5900
#define M1 INSN_10000
#define SB1 INSN_SB1
#define N411 INSN_4111
#define N412 INSN_4120
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
#define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
#define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3)
#define IOCT3 INSN_OCTEON3
#define XLR INSN_XLR
#define IAMR2 INSN_INTERAPTIV_MR2
#define IVIRT ASE_VIRT
#define IVIRT64 ASE_VIRT64
#define G1 (T3 \
|EE \
)
#define G2 (T3 \
)
#define G3 EE
/* 64 bit CPU with 32 bit FPU (single float). */
#define SF EE
/* Support for 128 bit MMI instructions. */
#define MMI EE
/* 64 bit CPU with only 32 bit multiplication/division support. */
#define M32 EE
/* Support for VU0 Coprocessor instructions */
#define VU0 EE
#define VU0CH INSN2_VU0_CHANNEL_SUFFIX
/* MIPS DSP ASE support.
NOTE:
1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
the same structure as $ac0 (HI + LO). For DSP instructions that write or
read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
(RD_HILO) attributes, such that HILO dependencies are maintained
conservatively.
2. For some mul. instructions that use integer registers as destinations
but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
(ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
certain fields of the DSP control register. For simplicity, we decide not
to track dependencies of these fields.
However, "bposge32" is a branch instruction that depends on the "pos"
field. In order to make sure that GAS does not reorder DSP instructions
that writes the "pos" field and "bposge32", we add DSP_VOLA
(INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"
field. */
#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
#define MOD_a WR_a|RD_a
#define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 ASE_DSP
#define D33 ASE_DSPR2
#define D34 ASE_DSPR3
#define D64 ASE_DSP64
/* MIPS MT ASE support. */
#define MT32 ASE_MT
/* MIPS MCU (MicroController) ASE support. */
#define MC ASE_MCU
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
#define EVAR6 ASE_EVA_R6
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
/* MSA support. */
#define MSA ASE_MSA
#define MSA64 ASE_MSA64
/* eXtended Physical Address (XPA) support. */
#define XPA ASE_XPA
#define XPAVZ ASE_XPA_VIRT
/* Cyclic redundancy check instruction (CRC) support. */
#define CRC ASE_CRC
#define CRC64 ASE_CRC64
/* Global INValidate (GINV) support. */
#define GINV ASE_GINV
/* Loongson MultiMedia extensions Instructions (MMI) support. */
#define LMMI ASE_LOONGSON_MMI
/* Loongson Content Address Memory (CAM) support. */
#define LCAM ASE_LOONGSON_CAM
/* Loongson EXTensions (EXT) instructions support. */
#define LEXT ASE_LOONGSON_EXT
/* Loongson EXTensions R2 (EXT2) instructions support. */
#define LEXT2 ASE_LOONGSON_EXT2
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
assembler to pick the right one. In other words, entries with
immediate operands must apear after the same instruction with
registers.
Because of the lookup algorithm used, entries with the same opcode
name must be contiguous.
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
const struct mips_opcode mips_builtin_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
{"pref", "k,+j(b)", 0x7c000035, 0xfc00007f, RD_3, 0, I37, 0, 0 },
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3|LM, 0, I4_32|G3, 0, I37 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 },
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I4_33, 0, I37 },
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
{"li", "t,j", 0x24000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */
{"li", "t,i", 0x34000000, 0xffe00000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 },
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 },
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* addu */
{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */
{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */
{"bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/
{"bc", "+'", 0xc8000000, 0xfc000000, NODS, 0, I37, 0, 0 },
{"balc", "+'", 0xe8000000, 0xfc000000, WR_31|NODS, 0, I37, 0, 0 },
{"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 },
/* Loongson specific instructions. Loongson gs464 (aka loongson3a) redefines the Coprocessor 2
instructions. Put them here so that disassembler will find them first.
The assemblers uses a hash table based on the instruction name anyhow. */
{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 },
{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
{"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
{"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, 0, LEXT, 0 },
{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, LEXT, 0 },
{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, 0, LEXT, 0 },
{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, 0, LEXT, 0 },
{"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
{"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
{"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, 0, LEXT, 0 },
{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, 0, LEXT, 0 },
{"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, 0, LEXT, 0 },
{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
{"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, 0, LEXT, 0 },
{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, 0, LEXT, 0 },
{"cto", "d,s", 0x70000062, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
{"ctz", "d,s", 0x70000022, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
{"dcto", "d,s", 0x700000e2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
{"dctz", "d,s", 0x700000a2, 0xfc1f07ff, WR_1|RD_2, 0, 0, LEXT2, 0 },
/* R5900 VU0 Macromode instructions. */
{"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vadd", "+5+K,+6+K,+7+K", 0x4a000028, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vaddi", "+5+K,+6+K,+y", 0x4a000022, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vaddq", "+5+K,+6+K,+q", 0x4a000020, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vaddw", "+5+K,+6+K,+7+N", 0x4a000003, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vaddx", "+5+K,+6+K,+7+N", 0x4a000000, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vaddy", "+5+K,+6+K,+7+N", 0x4a000001, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vaddz", "+5+K,+6+K,+7+N", 0x4a000002, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vadda", "+m+K,+7+K,+6+K", 0x4a0002bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vaddai", "+m+K,+6+K,+y", 0x4a00023e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vaddaq", "+m+K,+6+K,+q", 0x4a00023c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vaddaw", "+m+K,+6+K,+7+N", 0x4a00003f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vaddax", "+m+K,+6+K,+7+N", 0x4a00003c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vadday", "+m+K,+6+K,+7+N", 0x4a00003d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vaddaz", "+m+K,+6+K,+7+N", 0x4a00003e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vcallms", "+f", 0x4a000038, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"vcallmsr", "+9", 0x4a000039, 0xffff07ff, CP, 0, VU0, 0, 0 },
{"vclipw.xyz", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vclipw", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vdiv", "+q,+6+L,+7+M", 0x4a0003bc, 0xfe0007ff, CP, 0, VU0, 0, 0 },
{"vftoi0", "+7+K,+6+K", 0x4a00017c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vftoi4", "+7+K,+6+K", 0x4a00017d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vftoi12", "+7+K,+6+K", 0x4a00017e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vftoi15", "+7+K,+6+K", 0x4a00017f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"viadd", "+8,+9,+0", 0x4a000030, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"viaddi", "+0,+9,+g", 0x4a000032, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"viand", "+8,+9,+0", 0x4a000034, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"vilwr.w", "+0,(+9)", 0x4a2003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vilwr.x", "+0,(+9)", 0x4b0003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vilwr.y", "+0,(+9)", 0x4a8003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vilwr.z", "+0,(+9)", 0x4a4003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vior", "+8,+9,+0", 0x4a000035, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"viswr.w", "+0,(+9)", 0x4a2003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"viswr.x", "+0,(+9)", 0x4b0003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"viswr.y", "+0,(+9)", 0x4a8003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"viswr.z", "+0,(+9)", 0x4a4003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"visub", "+8,+9,+0", 0x4a000031, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"vitof0", "+7+K,+6+K", 0x4a00013c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vitof4", "+7+K,+6+K", 0x4a00013d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vitof12", "+7+K,+6+K", 0x4a00013e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vitof15", "+7+K,+6+K", 0x4a00013f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vlqd", "+7+K,(#-+9)", 0x4a00037e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vlqi", "+7+K,(+9#+)", 0x4a00037c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmadd", "+5+K,+6+K,+7+K", 0x4a000029, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddi", "+5+K,+6+K,+y", 0x4a000023, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddq", "+5+K,+6+K,+q", 0x4a000021, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddw", "+5+K,+6+K,+7+N", 0x4a00000b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddx", "+5+K,+6+K,+7+N", 0x4a000008, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddy", "+5+K,+6+K,+7+N", 0x4a000009, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaddz", "+5+K,+6+K,+7+N", 0x4a00000a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmadda", "+m+K,+6+K,+7+K", 0x4a0002bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmaddai", "+m+K,+6+K,+y", 0x4a00023f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmaddaq", "+m+K,+6+K,+q", 0x4a00023d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmaddaw", "+m+K,+6+K,+7+N", 0x4a0000bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmaddax", "+m+K,+6+K,+7+N", 0x4a0000bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmadday", "+m+K,+6+K,+7+N", 0x4a0000bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmaddaz", "+m+K,+6+K,+7+N", 0x4a0000be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmax", "+5+K,+6+K,+7+K", 0x4a00002b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaxi", "+5+K,+6+K,+y", 0x4a00001d, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmaxw", "+5+K,+6+K,+7+N", 0x4a000013, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaxx", "+5+K,+6+K,+7+N", 0x4a000010, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaxy", "+5+K,+6+K,+7+N", 0x4a000011, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmaxz", "+5+K,+6+K,+7+N", 0x4a000012, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmfir", "+7+K,+9", 0x4a0003fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmini", "+5+K,+6+K,+7+K", 0x4a00002f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vminii", "+5+K,+6+K,+y", 0x4a00001f, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vminiw", "+5+K,+6+K,+7+N", 0x4a000017, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vminix", "+5+K,+6+K,+7+N", 0x4a000014, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vminiy", "+5+K,+6+K,+7+N", 0x4a000015, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vminiz", "+5+K,+6+K,+7+N", 0x4a000016, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmove", "+7+K,+6+K", 0x4a00033c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmr32", "+7+K,+6+K", 0x4a00033d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmsub", "+5+K,+6+K,+7+K", 0x4a00002d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmsubi", "+5+K,+6+K,+y", 0x4a000027, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmsubq", "+5+K,+6+K,+q", 0x4a000025, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmsubw", "+5+K,+6+K,+7+N", 0x4a00000f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmsubx", "+5+K,+6+K,+7+N", 0x4a00000c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmsuby", "+5+K,+6+K,+7+N", 0x4a00000d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmsubz", "+5+K,+6+K,+7+N", 0x4a00000e, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmsuba", "+m+K,+7+K,+6+K", 0x4a0002fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubai", "+m+K,+6+K,+y", 0x4a00027f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubaq", "+m+K,+6+K,+q", 0x4a00027d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubaw", "+m+K,+6+K,+7+N", 0x4a0000ff, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubax", "+m+K,+6+K,+7+N", 0x4a0000fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubay", "+m+K,+6+K,+7+N", 0x4a0000fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmsubaz", "+m+K,+6+K,+7+N", 0x4a0000fe, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmtir", "+0,+6+L", 0x4a0003fc, 0xff8007ff, CP, 0, VU0, 0, 0 },
{"vmul", "+5+K,+6+K,+7+K", 0x4a00002a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmuli", "+5+K,+6+K,+y", 0x4a00001e, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmulq", "+5+K,+6+K,+q", 0x4a00001c, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vmulw", "+5+K,+6+K,+7+N", 0x4a00001b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmulx", "+5+K,+6+K,+7+N", 0x4a000018, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmuly", "+5+K,+6+K,+7+N", 0x4a000019, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmulz", "+5+K,+6+K,+7+N", 0x4a00001a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vmula", "+m+K,+6+K,+7+K", 0x4a0002be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmulai", "+m+K,+6+K,+y", 0x4a0001fe, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmulaq", "+m+K,+6+K,+q", 0x4a0001fc, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vmulaw", "+m+K,+6+K,+7+N", 0x4a0001bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vnop", "", 0x4a0002ff, 0xffffffff, CP, 0, VU0, 0, 0 },
{"vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
{"vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"vopmsub", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 },
{"vrget", "+7+K,+r", 0x4a00043d, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 },
{"vrinit", "+r,+6+L", 0x4a00043e, 0xff9f07ff, CP, 0, VU0, 0, 0 },
{"vrnext", "+7+K,+r", 0x4a00043c, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 },
{"vrsqrt", "+q,+6+L,+7+M", 0x4a0003be, 0xfe0007ff, CP, 0, VU0, 0, 0 },
{"vrxor", "+r,+6+L", 0x4a00043f, 0xff9f07ff, CP, 0, VU0, 0, 0 },
{"vsqd", "+6+K,(#-+0)", 0x4a00037f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsqi", "+6+K,(+0#+)", 0x4a00037d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsqrt", "+q,+7+M", 0x4a2003bd, 0xfe60ffff, CP, 0, VU0, 0, 0 },
{"vsub", "+5+K,+6+K,+7+K", 0x4a00002c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vsubi", "+5+K,+6+K,+y", 0x4a000026, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vsubq", "+5+K,+6+K,+q", 0x4a000024, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
{"vsubw", "+5+K,+6+K,+7+N", 0x4a000007, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vsubx", "+5+K,+6+K,+7+N", 0x4a000004, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vsuby", "+5+K,+6+K,+7+N", 0x4a000005, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vsubz", "+5+K,+6+K,+7+N", 0x4a000006, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
{"vsuba", "+m+K,+6+K,+7+K", 0x4a0002fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsubai", "+m+K,+6+K,+y", 0x4a00027e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vsubaq", "+m+K,+6+K,+q", 0x4a00027c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
{"vsubaw", "+m+K,+6+K,+7+N", 0x4a00007f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsubax", "+m+K,+6+K,+7+N", 0x4a00007c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsubay", "+m+K,+6+K,+7+N", 0x4a00007d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
{"vwaitq", "", 0x4a0003bf, 0xffffffff, CP, 0, VU0, 0, 0 },
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 },
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 },
{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 },
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 },
{"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
{"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
{"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 },
{"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 },
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 },
{"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 },
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, I37 },
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
{"addiu", "s,+R,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
{"addiupc", "s,-a", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 },
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 },
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 },
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 },
{"addu", "D,S,T", 0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 },
{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, LMMI, 0 },
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 },
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, SB1, MX, 0 },
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, 0, MX, 0 },
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 },
{"and", "D,S,T", 0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"and", "D,S,T", 0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 },
{"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 },
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 },
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 },
{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit032 */
{"bbit0", "s,+x,p", 0xc8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 },
{"bbit132", "s,+x,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 },
{"bbit1", "s,+X,p", 0xf8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 }, /* bbit132 */
{"bbit1", "s,+x,p", 0xe8000000, 0xfc000000, RD_1|CBD, 0, IOCT, 0, 0 },
/* bc0[tf]l? are at the bottom of the table. */
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 },
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 },
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 },
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 },
{"bc1eqz", "T,p", 0x45200000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 },
{"bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
{"bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 },
{"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 },
{"bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 },
{"bc1nez", "T,p", 0x45a00000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 },
{"bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
{"bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 },
{"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 },
{"bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 },
/* bc2* are at the bottom of the table. */
/* bc3* are at the bottom of the table. */
{"beqz", "s,p", 0x10000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"beq", "s,t,p", 0x10000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
{"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 },
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgez", "s,p", 0x04010000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 },
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 },
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"blez", "s,p", 0x18000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"bltz", "s,p", 0x04000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 },
{"nal", "", 0x04100000, 0xffffffff, WR_31|CBD, 0, I1, 0, 0 }, /* bltzal 0,.+4 */
{"bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 },
{"bnez", "s,p", 0x14000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 },
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 },
{"bne", "s,t,p", 0x14000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
{"bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, I37 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 },
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 },
{"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 },
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 },
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 },
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 },
{"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 },
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 },
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 },
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 },
{"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 },
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 },
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 },
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 },
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 },
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 },
{"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 },
{"c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 },
{"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 },
{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.nge.ps", "M,S,T", 0x46c0007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngl.ps", "M,S,T", 0x46c0007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ngle.d", "M,S,T", 0x46200079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngle.ps", "M,S,T", 0x46c00079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngle.s", "M,S,T", 0x46000079, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngt.ps", "M,S,T", 0x46c0007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ole.ps", "M,S,T", 0x46c00076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.olt.ps", "M,S,T", 0x46c00074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.seq.ps", "M,S,T", 0x46c0007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ueq.ps", "M,S,T", 0x46c00073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ule.ps", "M,S,T", 0x46c00077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ult.ps", "M,S,T", 0x46c00075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 },
{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 },
/* CW4010 instructions which are aliases for the cache instruction. */
{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1, 0, 0 },
{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 },
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 },
{"cache", "k,+j(b)", 0x7c000025, 0xfc00007f, RD_3, 0, I37, 0, 0 },
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, I37 },
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0 },
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE },
/* cfc0 is at the bottom of the table. */
{"cfc1", "t,g", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 },
{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LC, 0, I1, 0, 0 },
/* cfc2 is at the bottom of the table. */
/* cfc3 is at the bottom of the table. */
{"cftc1", "d,y", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC, 0, 0, MT32, 0 },
{"cftc2", "d,y", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */
{"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"clo", "d,s", 0x00000051, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
{"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 },
/* ctc0 is at the bottom of the table. */
{"ctc1", "t,g", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 },
/* ctc2 is at the bottom of the table. */
/* ctc3 is at the bottom of the table. */
{"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, 0 },
{"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM, 0, 0, MT32, IOCT|IOCTP|IOCT2 },
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
{"cvt.s.pl", "D,S", 0x46c00028, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 },
{"cvt.s.pu", "D,S", 0x46c00020, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I5_33, 0, 0 },
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF },
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, EE },
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 },
{"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, I37 },
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 },
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 },
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 },
{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
{"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
{"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
{"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
/* dctr and dctw are used on the r5000. */
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 },
{"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 },
{"dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
{"dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */
{"dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
/* For ddiv, see the comments about div. */
{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 },
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32|I69 },
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32|I69 },
/* For ddivu, see the comments about div. */
{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 },
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32|I69 },
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 },
{"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 },
{"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 },
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
{"dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */
{"dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 },
/* The MIPS assembler treats the div opcode with two operands as
though the first operand appeared twice (the first operand is both
a source and a destination). To get the div machine instruction,
you must use an explicit destination of $0. */
{"mod", "d,v,t", 0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"modu", "d,v,t", 0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"div", "d,v,t", 0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, I37 },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, I37 },
{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 },
{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 },
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF },
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 },
/* For divu, see the comments about div. */
{"divu", "d,v,t", 0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, I37 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, I37 },
{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 },
{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* addiu */
{"dli", "t,i", 0x34000000, 0xffe00000, WR_1, 0, I3, 0, 0 }, /* ori */
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 },
{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO, 0, N412, 0, 0 },
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO, 0, N411, 0, 0 },
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, WR_1|RD_C0|LC, 0, I3, 0, EE },
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, WR_1|RD_C0|LC, 0, I64, 0, 0 },
{"dmfgc0", "t,G", 0x40600100, 0xffe007ff, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
{"dmfgc0", "t,G,H", 0x40600100, 0xffe007f8, WR_1|RD_C0|LC, 0, 0, IVIRT64, 0 },
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dmt", "t", 0x41600bc1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, I3, 0, EE },
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, I64, 0, 0 },
{"dmtgc0", "t,G", 0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
{"dmtgc0", "t,G,H", 0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM, 0, 0, IVIRT64, 0 },
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF },
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D, 0, I3, 0, SF },
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF },
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D, 0, I3, 0, SF },
/* dmfc2 is at the bottom of the table. */
/* dmtc2 is at the bottom of the table. */
{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 },
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 },
{"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 },
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0*/
{"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 },
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 },
{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32|I69 },
{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 },
{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32|I69 },
{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 },
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 },
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 },
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 },
{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3, 0, 0 },
{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 },
{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I65, 0, 0 },
{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, N5|I65, 0, 0 },
{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65, 0, 0 },
{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65, 0, 0 },
{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65, 0, 0 },
{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65, 0, 0 },
{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I65, 0, 0 },
{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_1|RD_2, 0, I65, 0, 0 },
{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 },
{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_1|RD_2, 0, I65, 0, 0 },
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsllv */
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsll32 */
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrav */
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsra32 */
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, /* dsrlv */
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 },
{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 },
{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, LMMI, 0 },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dvpe", "t", 0x41600001, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"dvp", "", 0x41600024, 0xffffffff, TRAP, 0, I37, 0, 0 },
{"dvp", "t", 0x41600024, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
{"ei", "", 0x42000038, 0xffffffff, WR_C0, 0, EE, 0, 0 },
{"ei", "", 0x41606020, 0xffffffff, WR_C0, 0, I33, 0, 0 },
{"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 },
{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 },
{"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 },
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 },
{"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */
{"exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 },
{"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 },
{"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 },
{"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 },
{"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 },
{"jr", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */
{"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 },
/* MIPS R6 jic appears before beqzc and jialc appears before bnezc */
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
{"jr.hb", "s", 0x00000409, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr.hb $0 */
{"jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, I37 },
{"j", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */
{"j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, /* jr */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 },
/* This form of j is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1, 0, 0 },
{"jalr", "s", 0x0000f809, 0xfc1fffff, RD_1|WR_31|UBD, 0, I1, 0, 0 },
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I1, 0, 0 },
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
with the same hazard barrier effect. */
{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, RD_1|WR_31|UBD, 0, I32, 0, 0 },
{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, WR_1|RD_2|UBD, 0, I32, 0, 0 },
/* SVR4 PIC code requires special handling for jal, so it must be a
macro. */
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 },
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1, 0, 0 },
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1, 0, 0 },
/* This form of jal is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
{"jal", "a", 0x0c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 },
{"jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 },
{"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 },
{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 },
{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 },
{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 },
{"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 },
{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0},
{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D64, 0},
{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0},
{"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 },
{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0},
{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ldpc", "s,-B", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
/* The macro has to be first to handle o32 correctly. */
{"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 },
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 },
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE },
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE },
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE },
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, I69 },
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I4_33, 0, I37 },
{"lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 },
/* li is at the start of the table. */
{"li.d", "t,F",