blob: afd870e595fa81a3b645caaae85256f54b5d10e4 [file] [log] [blame]
/* Simulation code for the CR16 processor.
Copyright (C) 2008-2021 Free Software Foundation, Inc.
Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This must come before any other includes. */
#include "defs.h"
#include <signal.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/stat.h>
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
#include <string.h>
#include <time.h>
#include <sys/time.h>
#include "sim-main.h"
#include "sim-signal.h"
#include "simops.h"
#include "targ-vals.h"
#ifdef TARGET_SYS_utime
#include <utime.h>
#endif
#ifdef TARGET_SYS_wait
#include <sys/wait.h>
#endif
#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
enum op_types {
OP_VOID,
OP_CONSTANT3,
OP_UCONSTANT3,
OP_CONSTANT4,
OP_CONSTANT4_1,
OP_CONSTANT5,
OP_CONSTANT6,
OP_CONSTANT16,
OP_UCONSTANT16,
OP_CONSTANT20,
OP_UCONSTANT20,
OP_CONSTANT32,
OP_UCONSTANT32,
OP_MEMREF,
OP_MEMREF2,
OP_MEMREF3,
OP_DISP5,
OP_DISP17,
OP_DISP25,
OP_DISPE9,
//OP_ABS20,
OP_ABS20_OUTPUT,
//OP_ABS24,
OP_ABS24_OUTPUT,
OP_R_BASE_DISPS16,
OP_R_BASE_DISP20,
OP_R_BASE_DISPS20,
OP_R_BASE_DISPE20,
OP_RP_BASE_DISPE0,
OP_RP_BASE_DISP4,
OP_RP_BASE_DISPE4,
OP_RP_BASE_DISP14,
OP_RP_BASE_DISP16,
OP_RP_BASE_DISP20,
OP_RP_BASE_DISPS20,
OP_RP_BASE_DISPE20,
OP_R_INDEX7_ABS20,
OP_R_INDEX8_ABS20,
OP_RP_INDEX_DISP0,
OP_RP_INDEX_DISP14,
OP_RP_INDEX_DISP20,
OP_RP_INDEX_DISPS20,
OP_REG,
OP_REGP,
OP_PROC_REG,
OP_PROC_REGP,
OP_COND,
OP_RA
};
enum {
PSR_MASK = (PSR_I_BIT
| PSR_P_BIT
| PSR_E_BIT
| PSR_N_BIT
| PSR_Z_BIT
| PSR_F_BIT
| PSR_U_BIT
| PSR_L_BIT
| PSR_T_BIT
| PSR_C_BIT),
/* The following bits in the PSR _can't_ be set by instructions such
as mvtc. */
PSR_HW_MASK = (PSR_MASK)
};
/* cond Code Condition True State
* EQ Equal Z flag is 1
* NE Not Equal Z flag is 0
* CS Carry Set C flag is 1
* CC Carry Clear C flag is 0
* HI Higher L flag is 1
* LS Lower or Same L flag is 0
* GT Greater Than N flag is 1
* LE Less Than or Equal To N flag is 0
* FS Flag Set F flag is 1
* FC Flag Clear F flag is 0
* LO Lower Z and L flags are 0
* HS Higher or Same Z or L flag is 1
* LT Less Than Z and N flags are 0
* GE Greater Than or Equal To Z or N flag is 1. */
static int cond_stat(int cc)
{
switch (cc)
{
case 0: return PSR_Z; break;
case 1: return !PSR_Z; break;
case 2: return PSR_C; break;
case 3: return !PSR_C; break;
case 4: return PSR_L; break;
case 5: return !PSR_L; break;
case 6: return PSR_N; break;
case 7: return !PSR_N; break;
case 8: return PSR_F; break;
case 9: return !PSR_F; break;
case 10: return !PSR_Z && !PSR_L; break;
case 11: return PSR_Z || PSR_L; break;
case 12: return !PSR_Z && !PSR_N; break;
case 13: return PSR_Z || PSR_N; break;
case 14: return 1; break; /*ALWAYS. */
default:
// case NEVER: return false; break;
//case NO_COND_CODE:
//panic("Shouldn't have NO_COND_CODE in an actual instruction!");
return 0; break;
}
return 0;
}
creg_t
move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
{
/* A MASK bit is set when the corresponding bit in the CR should
be left alone. */
/* This assumes that (VAL & MASK) == 0. */
switch (cr)
{
case PSR_CR:
if (psw_hw_p)
val &= PSR_HW_MASK;
#if 0
else
val &= PSR_MASK;
sim_io_printf
(sd,
"ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
EXCEPTION (SIM_SIGILL);
#endif
/* keep an up-to-date psw around for tracing. */
State.trace.psw = (State.trace.psw & mask) | val;
break;
default:
break;
}
/* only issue an update if the register is being changed. */
if ((State.cregs[cr] & ~mask) != val)
SLOT_PEND_MASK (State.cregs[cr], mask, val);
return val;
}
#ifdef DEBUG
static void trace_input_func (SIM_DESC sd,
const char *name,
enum op_types in1,
enum op_types in2,
enum op_types in3);
#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 8
#endif
#ifndef SIZE_OPERANDS
#define SIZE_OPERANDS 18
#endif
#ifndef SIZE_VALUES
#define SIZE_VALUES 13
#endif
#ifndef SIZE_LOCATION
#define SIZE_LOCATION 20
#endif
#ifndef SIZE_PC
#define SIZE_PC 4
#endif
#ifndef SIZE_LINE_NUMBER
#define SIZE_LINE_NUMBER 2
#endif
static void
trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
{
char *comma;
enum op_types in[3];
int i;
char buf[1024];
char *p;
long tmp;
char *type;
const char *filename;
const char *functionname;
unsigned int linenumber;
bfd_vma byte_pc;
if ((cr16_debug & DEBUG_TRACE) == 0)
return;
switch (State.ins_type)
{
default:
case INS_UNKNOWN: type = " ?"; break;
}
if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
sim_io_printf (sd,
"0x%.*x %s: %-*s ",
SIZE_PC, (unsigned)PC,
type,
SIZE_INSTRUCTION, name);
else
{
buf[0] = '\0';
byte_pc = PC;
if (STATE_TEXT_SECTION (sd)
&& byte_pc >= STATE_TEXT_START (sd)
&& byte_pc < STATE_TEXT_END (sd))
{
filename = (const char *)0;
functionname = (const char *)0;
linenumber = 0;
if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
STATE_TEXT_SECTION (sd),
(struct bfd_symbol **)0,
byte_pc - STATE_TEXT_START (sd),
&filename, &functionname, &linenumber))
{
p = buf;
if (linenumber)
{
sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
p += strlen (p);
}
else
{
sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
p += SIZE_LINE_NUMBER+2;
}
if (functionname)
{
sprintf (p, "%s ", functionname);
p += strlen (p);
}
else if (filename)
{
char *q = strrchr (filename, '/');
sprintf (p, "%s ", (q) ? q+1 : filename);
p += strlen (p);
}
if (*p == ' ')
*p = '\0';
}
}
sim_io_printf (sd,
"0x%.*x %s: %-*.*s %-*s ",
SIZE_PC, (unsigned)PC,
type,
SIZE_LOCATION, SIZE_LOCATION, buf,
SIZE_INSTRUCTION, name);
}
in[0] = in1;
in[1] = in2;
in[2] = in3;
comma = "";
p = buf;
for (i = 0; i < 3; i++)
{
switch (in[i])
{
case OP_VOID:
break;
case OP_REG:
case OP_REGP:
sprintf (p, "%sr%d", comma, OP[i]);
p += strlen (p);
comma = ",";
break;
case OP_PROC_REG:
sprintf (p, "%scr%d", comma, OP[i]);
p += strlen (p);
comma = ",";
break;
case OP_CONSTANT16:
sprintf (p, "%s%d", comma, OP[i]);
p += strlen (p);
comma = ",";
break;
case OP_CONSTANT4:
sprintf (p, "%s%d", comma, SEXT4(OP[i]));
p += strlen (p);
comma = ",";
break;
case OP_CONSTANT3:
sprintf (p, "%s%d", comma, SEXT3(OP[i]));
p += strlen (p);
comma = ",";
break;
case OP_MEMREF:
sprintf (p, "%s@r%d", comma, OP[i]);
p += strlen (p);
comma = ",";
break;
case OP_MEMREF2:
sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
p += strlen (p);
comma = ",";
break;
case OP_MEMREF3:
sprintf (p, "%s@%d", comma, OP[i]);
p += strlen (p);
comma = ",";
break;
}
}
if ((cr16_debug & DEBUG_VALUES) == 0)
{
*p++ = '\n';
*p = '\0';
sim_io_printf (sd, "%s", buf);
}
else
{
*p = '\0';
sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
p = buf;
for (i = 0; i < 3; i++)
{
buf[0] = '\0';
switch (in[i])
{
case OP_VOID:
sim_io_printf (sd, "%*s", SIZE_VALUES, "");
break;
case OP_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) GPR (OP[i]));
break;
case OP_REGP:
tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_PROC_REG:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) CREG (OP[i]));
break;
case OP_CONSTANT16:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
break;
case OP_CONSTANT4:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT4(OP[i]));
break;
case OP_CONSTANT3:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT3(OP[i]));
break;
case OP_MEMREF2:
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)GPR (OP[i + 1]));
i++;
break;
}
}
}
sim_io_flush_stdout (sd);
}
static void
do_trace_output_flush (SIM_DESC sd)
{
sim_io_flush_stdout (sd);
}
static void
do_trace_output_finish (SIM_DESC sd)
{
sim_io_printf (sd,
" F0=%d F1=%d C=%d\n",
(State.trace.psw & PSR_F_BIT) != 0,
(State.trace.psw & PSR_F_BIT) != 0,
(State.trace.psw & PSR_C_BIT) != 0);
sim_io_flush_stdout (sd);
}
#if 0
static void
trace_output_40 (SIM_DESC sd, uint64 val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
sim_io_printf (sd,
" :: %*s0x%.2x%.8lx",
SIZE_VALUES - 12,
"",
((int)(val >> 32) & 0xff),
((unsigned long) val) & 0xffffffff);
do_trace_output_finish ();
}
}
#endif
static void
trace_output_32 (SIM_DESC sd, uint32 val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
sim_io_printf (sd,
" :: %*s0x%.8x",
SIZE_VALUES - 10,
"",
(int) val);
do_trace_output_finish (sd);
}
}
static void
trace_output_16 (SIM_DESC sd, uint16 val)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
sim_io_printf (sd,
" :: %*s0x%.4x",
SIZE_VALUES - 6,
"",
(int) val);
do_trace_output_finish (sd);
}
}
static void
trace_output_void (SIM_DESC sd)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
sim_io_printf (sd, "\n");
do_trace_output_flush (sd);
}
}
static void
trace_output_flag (SIM_DESC sd)
{
if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
sim_io_printf (sd,
" :: %*s",
SIZE_VALUES,
"");
do_trace_output_finish (sd);
}
}
#else
#define trace_input(NAME, IN1, IN2, IN3)
#define trace_output(RESULT)
#endif
/* addub. */
void
OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp;
uint8 a = OP[0] & 0xff;
uint16 b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* addub. */
void
OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = (a + b) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* addub. */
void
OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (GPR (OP[0])) & 0xff;
uint8 b = (GPR (OP[1])) & 0xff;
uint16 tmp = (a + b) & 0xff;
trace_input ("addub", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* adduw. */
void
OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b);
trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* adduw. */
void
OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b);
trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* adduw. */
void
OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b);
trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* addb. */
void
OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0];
uint8 b = (GPR (OP[1]) & 0xff);
uint16 tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addb. */
void
OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint8 b = (GPR (OP[1]) & 0xff);
uint16 tmp = (a + b) & 0xff;
trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addb. */
void
OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (GPR (OP[0]) & 0xff);
uint8 b = (GPR (OP[1]) & 0xff);
uint16 tmp = (a + b) & 0xff;
trace_input ("addb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addw. */
void
OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 a = OP[0];
uint16 tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addw. */
void
OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
{
int16 a = OP[0];
uint16 tmp, b = GPR (OP[1]);
tmp = (a + b);
trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addw. */
void
OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
trace_input ("addw", OP_REG, OP_REG, OP_VOID);
tmp = (a + b);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addcb. */
void
OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
tmp = (a + b + PSR_C) & 0xff;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addcb. */
void
OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
{
int8 a = OP[0] & 0xff;
uint8 b = (GPR (OP[1])) & 0xff;
uint8 tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addcb. */
void
OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (GPR (OP[0])) & 0xff;
uint8 b = (GPR (OP[1])) & 0xff;
uint8 tmp = (a + b + PSR_C) & 0xff;
trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
SET_PSR_C (tmp > 0xFF);
SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
trace_output_16 (sd, tmp);
}
/* addcw. */
void
OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addcw. */
void
OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
{
int16 a = OP[0];
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b + PSR_C);
trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addcw. */
void
OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[1]);
uint16 b = GPR (OP[1]);
uint16 tmp = (a + b + PSR_C);
trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFF);
SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
trace_output_16 (sd, tmp);
}
/* addd. */
void
OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 a = (OP[0]);
uint32 b = GPR32 (OP[1]);
uint32 tmp = (a + b);
trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
trace_output_32 (sd, tmp);
}
/* addd. */
void
OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
{
int32 a = (SEXT16(OP[0]));
uint32 b = GPR32 (OP[1]);
uint32 tmp = (a + b);
trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
trace_output_32 (sd, tmp);
}
/* addd. */
void
OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = GPR32 (OP[0]);
uint32 b = GPR32 (OP[1]);
uint32 tmp = (a + b);
trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
}
/* addd. */
void
OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = OP[0];
uint32 b = GPR32 (OP[1]);
uint32 tmp;
trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
trace_output_32 (sd, tmp);
}
/* addd. */
void
OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
{
int32 a = OP[0];
uint32 b = GPR32 (OP[1]);
uint32 tmp;
trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = (a + b);
SET_GPR32 (OP[1], tmp);
SET_PSR_C (tmp > 0xFFFFFFFF);
SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
trace_output_32 (sd, tmp);
}
/* andb. */
void
OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* andb. */
void
OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* andb. */
void
OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
trace_input ("andb", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
trace_output_16 (sd, tmp);
}
/* andw. */
void
OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* andw. */
void
OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp, a = OP[0], b = GPR (OP[1]);
trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* andw. */
void
OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
trace_input ("andw", OP_REG, OP_REG, OP_VOID);
tmp = a & b;
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* andd. */
void
OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* andd. */
void
OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
tmp = a & b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* ord. */
void
OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* ord. */
void
OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
tmp = a | b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* xord. */
void
OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* xord. */
void
OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
tmp = a ^ b;
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* b. */
void
OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
if (cc)
{
if (sign_flag)
tmp = (PC - (OP[1]));
else
tmp = (PC + (OP[1]));
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_32 (sd, tmp);
}
/* b. */
void
OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
if (cc)
{
if (sign_flag)
tmp = (PC - OP[1]);
else
tmp = (PC + OP[1]);
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_32 (sd, tmp);
}
/* b. */
void
OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0, cc = cond_stat (OP[0]);
trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
if (cc)
{
if (sign_flag)
tmp = (PC - (OP[1]));
else
tmp = (PC + (OP[1]));
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_32 (sd, tmp);
}
/* bal. */
void
OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
SET_GPR32 (14, tmp);
if (sign_flag)
tmp = (PC - (OP[1]));
else
tmp = (PC + (OP[1]));
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap. */
if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
sign_flag = 0; /* Reset sign_flag. */
trace_output_32 (sd, tmp);
}
/* bal. */
void
OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
SET_GPR32 (OP[0], tmp);
if (sign_flag)
tmp = ((PC) - (OP[1]));
else
tmp = ((PC) + (OP[1]));
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
sign_flag = 0; /* Reset sign_flag. */
trace_output_32 (sd, tmp);
}
/* jal. */
void
OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[1]);
tmp = SEXT24(tmp << 1);
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x0) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
trace_output_32 (sd, tmp);
}
/* jal. */
void
OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
tmp = GPR32 (OP[0]);
tmp = SEXT24(tmp << 1);
/* If the resulting PC value is less than 0x00_0000 or greater
than 0xFF_FFFF, this instruction causes an IAD trap.*/
if ((tmp < 0x0) || (tmp > 0xFFFFFF))
{
trace_output_void (sd);
EXCEPTION (SIM_SIGBUS);
}
else
JMP (tmp);
trace_output_32 (sd, tmp);
}
/* beq0b. */
void
OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint8 a = (GPR (OP[0]) & 0xFF);
trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
{
if (sign_flag)
addr = (PC - OP[1]);
else
addr = (PC + OP[1]);
JMP (addr);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_void (sd);
}
/* bne0b. */
void
OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint8 a = (GPR (OP[0]) & 0xFF);
trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
{
if (sign_flag)
addr = (PC - OP[1]);
else
addr = (PC + OP[1]);
JMP (addr);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_void (sd);
}
/* beq0w. */
void
OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint16 a = GPR (OP[0]);
trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a == 0)
{
if (sign_flag)
addr = (PC - OP[1]);
else
addr = (PC + OP[1]);
JMP (addr);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_void (sd);
}
/* bne0w. */
void
OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint16 a = GPR (OP[0]);
trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
addr = OP[1];
if (a != 0)
{
if (sign_flag)
addr = (PC - OP[1]);
else
addr = (PC + OP[1]);
JMP (addr);
}
sign_flag = 0; /* Reset sign_flag. */
trace_output_void (sd);
}
/* jeq. */
void
OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 1)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
}
trace_output_32 (sd, tmp);
}
/* jne. */
void
OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_Z) == 0)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
}
trace_output_32 (sd, tmp);
}
/* jcs. */
void
OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 1)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jcc. */
void
OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_C) == 0)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jhi. */
void
OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 1)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jls. */
void
OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_L) == 0)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jgt. */
void
OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 1)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jle. */
void
OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_N) == 0)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jfs. */
void
OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 1)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jfc. */
void
OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
if ((PSR_F) == 0)
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jlo. */
void
OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_L) == 0))
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jhs. */
void
OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_L) == 1))
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jlt. */
void
OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_N) == 0))
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jge. */
void
OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp = 0;
trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_N) == 1))
{
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
}
trace_output_32 (sd, tmp);
}
/* jump. */
void
OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
trace_output_32 (sd, tmp);
}
/* jusr. */
void
OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
SET_PSR_U(1);
trace_output_32 (sd, tmp);
}
/* seq. */
void
OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
if ((PSR_Z) == 1)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sne. */
void
OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
if ((PSR_Z) == 0)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* scs. */
void
OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
if ((PSR_C) == 1)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* scc. */
void
OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
if ((PSR_C) == 0)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* shi. */
void
OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
if ((PSR_L) == 1)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sls. */
void
OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
if ((PSR_L) == 0)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sgt. */
void
OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
if ((PSR_N) == 1)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sle. */
void
OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
if ((PSR_N) == 0)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sfs. */
void
OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
if ((PSR_F) == 1)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sfc. */
void
OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
if ((PSR_F) == 0)
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* slo. */
void
OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_L) == 0))
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* shs. */
void
OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* slt. */
void
OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
if (((PSR_Z) == 0) & ((PSR_N) == 0))
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* sge. */
void
OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
if (((PSR_Z) == 1) | ((PSR_N) == 1))
SET_GPR (OP[0], 1);
else
SET_GPR (OP[0], 0);
trace_output_void (sd);
}
/* cbitb. */
void
OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* cbitb. */
void
OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* cbitb. */
void
OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitb. */
void
OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SB (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, tmp);
}
/* cbitw. */
void
OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, tmp);
}
/* cbitw. */
void
OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint16 a = (OP[0]), tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
addr = (GPR32 (12)) + OP[2];
else
addr = (GPR32 (13)) + OP[2];
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* cbitw. */
void
OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp & ~(1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitb. */
void
OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitb. */
void
OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SB (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitw. */
void
OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitw. */
void
OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, tmp);
}
/* sbitw. */
void
OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint16 a = (OP[0]), tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
addr = (GPR32 (12)) + OP[2];
else
addr = (GPR32 (13)) + OP[2];
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* sbitw. */
void
OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
tmp = tmp | (1 << a);
SW (addr, tmp);
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, tmp);
}
/* tbitb. */
void
OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = OP[0] & 0xff;
uint32 addr = OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, tmp);
}
/* tbitb. */
void
OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitb. */
void
OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xff;
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RB (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, tmp);
}
/* tbitw. */
void
OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint32 addr = OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, tmp);
}
/* tbitw. */
void
OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 addr;
uint16 a = (OP[0]), tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
if (OP[1] == 0)
addr = (GPR32 (12)) + OP[2];
else
addr = (GPR32 (13)) + OP[2];
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbitw. */
void
OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
tmp = RW (addr);
SET_PSR_F (tmp & (1 << a));
trace_output_32 (sd, addr);
}
/* tbit. */
void
OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = OP[0];
uint16 b = (GPR (OP[1]));
trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
}
/* tbit. */
void
OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = (GPR (OP[1]));
trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
SET_PSR_F (b & (1 << a));
trace_output_16 (sd, b);
}
/* cmpb. */
void
OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xFF;
uint8 b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int8)a > (int8)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpb. */
void
OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (OP[0]) & 0xFF;
uint8 b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int8)a > (int8)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpb. */
void
OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 a = (GPR (OP[0])) & 0xFF;
uint8 b = (GPR (OP[1])) & 0xFF;
trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int8)a > (int8)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpw. */
void
OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint16 b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int16)a > (int16)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpw. */
void
OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = (OP[0]);
uint16 b = GPR (OP[1]);
trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int16)a > (int16)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpw. */
void
OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]) ;
uint16 b = GPR (OP[1]) ;
trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int16)a > (int16)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpd. */
void
OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = (OP[0]);
uint32 b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int32)a > (int32)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpd. */
void
OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = (SEXT16(OP[0]));
uint32 b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int32)a > (int32)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpd. */
void
OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = GPR32 (OP[0]) ;
uint32 b = GPR32 (OP[1]) ;
trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int32)a > (int32)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* cmpd. */
void
OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 a = (OP[0]);
uint32 b = GPR32 (OP[1]);
trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
SET_PSR_Z (a == b);
SET_PSR_N ((int32)a > (int32)b);
SET_PSR_L (a > b);
trace_output_flag (sd);
}
/* movb. */
void
OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp = OP[0] & 0xFF;
uint16 a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
}
/* movb. */
void
OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp = OP[0] & 0xFF;
uint16 a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
}
/* movb. */
void
OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp = (GPR (OP[0])) & 0xFF;
uint16 a = (GPR (OP[1])) & 0xFF00;
trace_input ("movb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], (a | tmp));
trace_output_16 (sd, tmp);
}
/* movw. */
void
OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = OP[0];
trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
}
/* movw. */
void
OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp = OP[0];
trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
SET_GPR (OP[1], (tmp & 0xffff));
trace_output_16 (sd, tmp);
}
/* movw. */
void
OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[0]);
uint32 a = GPR32 (OP[1]);
trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
a = (a & 0xffff0000) | tmp;
SET_GPR32 (OP[1], a);
trace_output_16 (sd, tmp);
}
/* movxb. */
void
OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
trace_output_16 (sd, tmp);
}
/* movzb. */
void
OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 tmp = (GPR (OP[0])) & 0xFF;
trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[1], tmp);
trace_output_16 (sd, tmp);
}
/* movxw. */
void
OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[0]);
trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], SEXT16(tmp));
trace_output_16 (sd, tmp);
}
/* movzw. */
void
OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[0]);
trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
trace_output_16 (sd, tmp);
}
/* movd. */
void
OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp = OP[0];
trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
SET_GPR32 (OP[1], tmp);
trace_output_32 (sd, tmp);
}
/* movd. */
void
OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp = SEXT16(OP[0]);