| 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| |
| * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary |
| register. |
| |
| 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| |
| * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to |
| RISCV_GP_SYMBOL. |
| |
| 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| |
| * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. |
| <c.andi>: Likewise. |
| <c.addiw> Likewise. |
| |
| 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| |
| * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. |
| |
| 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| |
| * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. |
| <srl> Likewise. |
| <srai> Likewise. |
| <sra> Likewise. |
| |
| 2017-03-27 Alan Modra <amodra@gmail.com> |
| |
| PR 21303 |
| * ppc-dis.c (struct ppc_mopt): Comment. |
| (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. |
| |
| 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| |
| Backport from mainline |
| 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| |
| * s390-mkopc.c (main): Remove vx2 check. |
| * s390-opc.txt: Remove vx2 instruction flags. |
| |
| 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| |
| * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; |
| <vsx>: Do not use PPC_OPCODE_VSX3; |
| |
| 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| |
| Apply from master. |
| 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. |
| |
| 2017-03-07 Alan Modra <amodra@gmail.com> |
| |
| Apply from master |
| 2017-03-06 Alan Modra <amodra@gmail.com> |
| PR 21124 |
| * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) |
| (extract_raq, extract_ras, extract_rbx): New functions. |
| (powerpc_operands): Use opposite corresponding insert function. |
| (Q_MASK): Define. |
| (powerpc_opcodes): Apply Q_MASK to all quad insns with even |
| register restriction. |
| |
| 2017-03-02 Tristan Gingold <gingold@adacore.com> |
| |
| * configure: Regenerate. |
| |
| 2017-03-02 Tristan Gingold <gingold@adacore.com> |
| |
| * configure: Regenerate. |
| |
| 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| |
| * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and |
| pseudoinstructions. |
| |
| 2017-02-27 Richard Sandiford <richard.sandiford@arm.com> |
| |
| * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) |
| (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) |
| (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) |
| (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) |
| (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) |
| (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) |
| (OP_SVE_V_HSD): New macros. |
| (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) |
| (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) |
| (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. |
| (aarch64_opcode_table): Add new SVE instructions. |
| (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate |
| for rotation operands. Add new SVE operands. |
| * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. |
| (ins_sve_quad_index): Likewise. |
| (ins_imm_rotate): Split into... |
| (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. |
| * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... |
| (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two |
| functions. |
| (aarch64_ins_sve_addr_ri_s4): New function. |
| (aarch64_ins_sve_quad_index): Likewise. |
| (do_misc_encoding): Handle "MOV Zn.Q, Qm". |
| * aarch64-asm-2.c: Regenerate. |
| * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. |
| (ext_sve_quad_index): Likewise. |
| (ext_imm_rotate): Split into... |
| (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. |
| * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... |
| (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two |
| functions. |
| (aarch64_ext_sve_addr_ri_s4): New function. |
| (aarch64_ext_sve_quad_index): Likewise. |
| (aarch64_ext_sve_index): Allow quad indices. |
| (do_misc_decoding): Likewise. |
| * aarch64-dis-2.c: Regenerate. |
| * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New |
| aarch64_field_kinds. |
| (OPD_F_OD_MASK): Widen by one bit. |
| (OPD_F_NO_ZR): Bump accordingly. |
| (get_operand_field_width): New function. |
| * aarch64-opc.c (fields): Add new SVE fields. |
| (operand_general_constraint_met_p): Handle new SVE operands. |
| (aarch64_print_operand): Likewise. |
| * aarch64-opc-2.c: Regenerate. |
| |
| 2017-02-27 Richard Sandiford <richard.sandiford@arm.com> |
| |
| * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... |
| (aarch64_feature_compnum): ...this. |
| (SIMD_V8_3): Replace with... |
| (COMPNUM): ...this. |
| (CNUM_INSN): New macro. |
| (aarch64_opcode_table): Use it for the complex number instructions. |
| |
| 2017-02-27 Richard Sandiford <richard.sandiford@arm.com> |
| |
| * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. |
| (aarch64_sys_reg_supported_p): Handle them. |
| |
| 2017-02-27 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| |
| * aarch64-tbl.h (RCPC, RCPC_INSN): Define. |
| (aarch64_opcode_table): Use RCPC_INSN. |
| |
| 2017-02-11 Stafford Horne <shorne@gmail.com> |
| Alan Modra <amodra@gmail.com> |
| |
| * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. |
| Use insn_bytes_value and insn_int_value directly instead. Don't |
| free allocated memory until function exit. |
| |
| 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| |
| * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. |
| |
| 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| |
| * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. |
| * i386-dis-evex.h (evex_table): Updated. |
| * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, |
| CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. |
| (cpu_flags): Add CpuAVX512_VPOPCNTDQ. |
| * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. |
| (i386_cpu_flags): Add cpuavx512_vpopcntdq. |
| * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. |
| * i386-init.h: Regenerate. |
| * i386-tbl.h: Ditto. |
| |
| 2017-01-02 Alan Modra <amodra@gmail.com> |
| |
| Update year range in copyright notice of all files. |
| |
| For older changes see ChangeLog-2016 |
| |
| Copyright (C) 2017 Free Software Foundation, Inc. |
| |
| Copying and distribution of this file, with or without modification, |
| are permitted in any medium without royalty provided the copyright |
| notice and this notice are preserved. |
| |
| Local Variables: |
| mode: change-log |
| left-margin: 8 |
| fill-column: 74 |
| version-control: never |
| End: |
