gas/doc/c-riscv.texi

@c Copyright (C) 2016-2018 Free Software Foundation, Inc.
@c This is part of the GAS anual.
@c For copying conditions, see the file as.texinfo
@c man end

@ifset GENERIC
@page
@node RISC-V-Dependent
@chapter RISC-V Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter RISC-V Dependent Features
@end ifclear

@cindex RISC-V support
@menu
* RISC-V-Options::        RISC-V Options
* RISC-V-Directives::     RISC-V Directives
@end menu

@node RISC-V-Options
@section RISC-V Options

The following table lists all available RISC-V specific options.

@c man begin OPTIONS
@table @gcctabopt

@cindex @samp{-fpic} option, RISC-V
@item -fpic
@itemx -fPIC
Generate position-independent code

@cindex @samp{-fno-pic} option, RISC-V
@item -fno-pic
Don't generate position-independent code (default)

@cindex @samp{-march=ISA} option, RISC-V
@item -march=ISA
Select the base isa, as specified by ISA.  For example -march=rv32ima.

@cindex @samp{-mabi=ABI} option, RISC-V
@item -mabi=ABI
Selects the ABI, which is either "ilp32" or "lp64", optionally followed
by "f", "d", or "q" to indicate single-precision, double-precision, or
quad-precision floating-point calling convention, or none to indicate
the soft-float calling convention.

@end table
@c man end

@node RISC-V-Directives
@section RISC-V Directives
@cindex machine directives, RISC-V
@cindex RISC-V machine directives

The following table lists all available RISC-V specific directives.

@table @code

@cindex @code{align} directive
@item .align @var{size-log-2}
Align to the given boundary, with the size given as log2 the number of bytes to
align to.

@cindex Data directives
@item .half @var{value}
@itemx .word @var{value}
@itemx .dword @var{value}
Emits a half-word, word, or double-word value at the current position.

@cindex DTP-relative data directives
@item .dtprelword @var{value}
@itemx .dtpreldword @var{value}
Emits a DTP-relative word (or double-word) at the current position.  This is
meant to be used by the compiler in shared libraries for DWARF debug info for
thread local variables.

@cindex BSS directive
@item .bss
Sets the current section to the BSS section.

@cindex LEB128 directives
@item .uleb128 @var{value}
@itemx .sleb128 @var{value}
Emits a signed or unsigned LEB128 value at the current position.  This only
accepts constant expressions, because symbol addresses can change with
relaxation, and we don't support relocations to modify LEB128 values at link
time.

@cindex Option directive
@cindex @code{option} directive
@item .option @var{argument}
Modifies RISC-V specific assembler options inline with the assembly code.
This is used when particular instruction sequences must be assembled with a
specific set of options.  For example, since we relax addressing sequences to
shorter GP-relative sequences when possible the initial load of GP must not be
relaxed and should be emitted as something like

@smallexample
	.option push
	.option norelax
	la gp, __global_pointer$
	.option pop
@end smallexample

in order to produce after linker relaxation the expected

@smallexample
	auipc gp, %pcrel_hi(__global_pointer$)
	addi gp, gp, %pcrel_lo(__global_pointer$)
@end smallexample

instead of just

@smallexample
	addi gp, gp, 0
@end smallexample

It's not expected that options are changed in this manner during regular use,
but there are a handful of esoteric cases like the one above where users need
to disable particular features of the assembler for particular code sequences.
The complete list of option arguments is shown below:

@table @code
@item push
@itemx pop
Pushes or pops the current option stack.  These should be used whenever
changing an option in line with assembly code in order to ensure the user's
command-line options are respected for the bulk of the file being assembled.

@item rvc
@itemx norvc
Enables or disables the generation of compressed instructions.  Instructions
are opportunistically compressed by the RISC-V assembler when possible, but
sometimes this behavior is not desirable.

@item pic
@itemx nopic
Enables or disables position-independent code generation.  Unless you really
know what you're doing, this should only be at the top of a file.

@item relax
@itemx norelax
Enables or disables relaxation.  The RISC-V assembler and linker
opportunistically relax some code sequences, but sometimes this behavior is not
desirable.
@end table

@end table