gcc/doc/riscv-ext.texi

@c Copyright (C) 2025 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc/doc/include/fdl.texi.

@c This file is generated automatically using
@c  gcc/config/riscv/gen-riscv-ext-texi.cc from:
@c       gcc/config/riscv/riscv-ext.def
@c       gcc/config/riscv/riscv-opts.h

@c Please *DO NOT* edit manually.

@multitable @columnfractions .10 .10 .80
@headitem Extension Name @tab Supported Version @tab Description

@item g
@tab -
@tab General-purpose computing base extension, @samp{g} will expand to
@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
@samp{zifencei}.

@item e
@tab 2.0
@tab Reduced base integer extension

@item i
@tab 2.0 2.1
@tab Base integer extension

@item m
@tab 2.0
@tab Integer multiplication and division extension

@item a
@tab 2.0 2.1
@tab Atomic extension

@item f
@tab 2.0 2.2
@tab Single-precision floating-point extension

@item d
@tab 2.0 2.2
@tab Double-precision floating-point extension

@item c
@tab 2.0
@tab Compressed extension

@item b
@tab 1.0
@tab b extension

@item v
@tab 1.0
@tab Vector extension

@item h
@tab 1.0
@tab Hypervisor extension

@item zic64b
@tab 1.0
@tab Cache block size isf 64 bytes

@item zicbom
@tab 1.0
@tab Cache-block management extension

@item zicbop
@tab 1.0
@tab Cache-block prefetch extension

@item zicboz
@tab 1.0
@tab Cache-block zero extension

@item ziccamoa
@tab 1.0
@tab Main memory supports all atomics in A

@item ziccif
@tab 1.0
@tab Main memory supports instruction fetch with atomicity requirement

@item zicclsm
@tab 1.0
@tab Main memory supports misaligned loads/stores

@item ziccrse
@tab 1.0
@tab Main memory supports forward progress on LR/SC sequences

@item zicfilp
@tab 1.0
@tab zicfilp extension

@item zicfiss
@tab 1.0
@tab zicfiss extension

@item zicntr
@tab 2.0
@tab Standard extension for base counters and timers

@item zicond
@tab 1.0
@tab Integer conditional operations extension

@item zicsr
@tab 2.0
@tab Control and status register access extension

@item zifencei
@tab 2.0
@tab Instruction-fetch fence extension

@item zihintntl
@tab 1.0
@tab Non-temporal locality hints extension

@item zihintpause
@tab 2.0
@tab Pause hint extension

@item zihpm
@tab 2.0
@tab Standard extension for hardware performance counters

@item zimop
@tab 1.0
@tab zimop extension

@item zilsd
@tab 1.0
@tab Load/Store pair instructions extension

@item zmmul
@tab 1.0
@tab Integer multiplication extension

@item za128rs
@tab 1.0
@tab Reservation set size of 128 bytes

@item za64rs
@tab 1.0
@tab Reservation set size of 64 bytes

@item zaamo
@tab 1.0
@tab zaamo extension

@item zabha
@tab 1.0
@tab zabha extension

@item zacas
@tab 1.0
@tab zacas extension

@item zalrsc
@tab 1.0
@tab zalrsc extension

@item zawrs
@tab 1.0
@tab Wait-on-reservation-set extension

@item zama16b
@tab 1.0
@tab Zama16b extension, Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic.

@item zfa
@tab 1.0
@tab Additional floating-point extension

@item zfbfmin
@tab 1.0
@tab zfbfmin extension

@item zfh
@tab 1.0
@tab Half-precision floating-point extension

@item zfhmin
@tab 1.0
@tab Minimal half-precision floating-point extension

@item zfinx
@tab 1.0
@tab Single-precision floating-point in integer registers extension

@item zdinx
@tab 1.0
@tab Double-precision floating-point in integer registers extension

@item zca
@tab 1.0
@tab Integer compressed instruction extension

@item zcb
@tab 1.0
@tab Simple compressed instruction extension

@item zcd
@tab 1.0
@tab Compressed double-precision floating point loads and stores extension

@item zce
@tab 1.0
@tab Compressed instruction extensions for embedded processors

@item zcf
@tab 1.0
@tab Compressed single-precision floating point loads and stores extension

@item zcmop
@tab 1.0
@tab zcmop extension

@item zcmp
@tab 1.0
@tab Compressed push pop extension

@item zcmt
@tab 1.0
@tab Table jump instruction extension

@item zclsd
@tab 1.0
@tab Compressed load/store pair instructions extension

@item zba
@tab 1.0
@tab Address calculation extension

@item zbb
@tab 1.0
@tab Basic bit manipulation extension

@item zbc
@tab 1.0
@tab Carry-less multiplication extension

@item zbkb
@tab 1.0
@tab Cryptography bit-manipulation extension

@item zbkc
@tab 1.0
@tab Cryptography carry-less multiply extension

@item zbkx
@tab 1.0
@tab Cryptography crossbar permutation extension

@item zbs
@tab 1.0
@tab Single-bit operation extension

@item zk
@tab 1.0
@tab Standard scalar cryptography extension

@item zkn
@tab 1.0
@tab NIST algorithm suite extension

@item zknd
@tab 1.0
@tab AES Decryption extension

@item zkne
@tab 1.0
@tab AES Encryption extension

@item zknh
@tab 1.0
@tab Hash function extension

@item zkr
@tab 1.0
@tab Entropy source extension

@item zks
@tab 1.0
@tab ShangMi algorithm suite extension

@item zksed
@tab 1.0
@tab SM4 block cipher extension

@item zksh
@tab 1.0
@tab SM3 hash function extension

@item zkt
@tab 1.0
@tab Data independent execution latency extension

@item ztso
@tab 1.0
@tab Total store ordering extension

@item zvbb
@tab 1.0
@tab Vector basic bit-manipulation extension

@item zvbc
@tab 1.0
@tab Vector carryless multiplication extension

@item zve32f
@tab 1.0
@tab Vector extensions for embedded processors

@item zve32x
@tab 1.0
@tab Vector extensions for embedded processors

@item zve64d
@tab 1.0
@tab Vector extensions for embedded processors

@item zve64f
@tab 1.0
@tab Vector extensions for embedded processors

@item zve64x
@tab 1.0
@tab Vector extensions for embedded processors

@item zvfbfmin
@tab 1.0
@tab Vector BF16 converts extension

@item zvfbfwma
@tab 1.0
@tab zvfbfwma extension

@item zvfh
@tab 1.0
@tab Vector half-precision floating-point extension

@item zvfhmin
@tab 1.0
@tab Vector minimal half-precision floating-point extension

@item zvkb
@tab 1.0
@tab Vector cryptography bit-manipulation extension

@item zvkg
@tab 1.0
@tab Vector GCM/GMAC extension

@item zvkn
@tab 1.0
@tab Vector NIST Algorithm Suite extension, @samp{zvkn} will expand to

@item zvknc
@tab 1.0
@tab Vector NIST Algorithm Suite with carryless multiply extension, @samp{zvknc}

@item zvkned
@tab 1.0
@tab Vector AES block cipher extension

@item zvkng
@tab 1.0
@tab Vector NIST Algorithm Suite with GCM extension, @samp{zvkng} will expand

@item zvknha
@tab 1.0
@tab Vector SHA-2 secure hash extension

@item zvknhb
@tab 1.0
@tab Vector SHA-2 secure hash extension

@item zvks
@tab 1.0
@tab Vector ShangMi algorithm suite extension, @samp{zvks} will expand

@item zvksc
@tab 1.0
@tab Vector ShangMi algorithm suite with carryless multiplication extension,

@item zvksed
@tab 1.0
@tab Vector SM4 Block Cipher extension

@item zvksg
@tab 1.0
@tab Vector ShangMi algorithm suite with GCM extension, @samp{zvksg} will expand

@item zvksh
@tab 1.0
@tab Vector SM3 Secure Hash extension

@item zvkt
@tab 1.0
@tab Vector data independent execution latency extension

@item zvl1024b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl128b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl16384b
@tab 1.0
@tab zvl16384b extension

@item zvl2048b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl256b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl32768b
@tab 1.0
@tab zvl32768b extension

@item zvl32b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl4096b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl512b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl64b
@tab 1.0
@tab Minimum vector length standard extensions

@item zvl65536b
@tab 1.0
@tab zvl65536b extension

@item zvl8192b
@tab 1.0
@tab zvl8192b extension

@item zhinx
@tab 1.0
@tab Half-precision floating-point in integer registers extension

@item zhinxmin
@tab 1.0
@tab Minimal half-precision floating-point in integer registers extension

@item sdtrig
@tab 1.0
@tab sdtrig extension

@item sha
@tab 1.0
@tab The augmented hypervisor extension

@item shcounterenw
@tab 1.0
@tab Support writeable enables for any supported counter

@item shgatpa
@tab 1.0
@tab SvNNx4 mode supported for all modes supported by satp

@item shlcofideleg
@tab 1.0
@tab Delegating LCOFI interrupts to VS-mode

@item shtvala
@tab 1.0
@tab The htval register provides all needed values

@item shvstvala
@tab 1.0
@tab The vstval register provides all needed values

@item shvstvecd
@tab 1.0
@tab The vstvec register supports Direct mode

@item shvsatpa
@tab 1.0
@tab The vsatp register supports all modes supported by satp

@item smaia
@tab 1.0
@tab Advanced interrupt architecture extension

@item smcntrpmf
@tab 1.0
@tab Cycle and instret privilege mode filtering

@item smcsrind
@tab 1.0
@tab Machine-Level Indirect CSR Access

@item smepmp
@tab 1.0
@tab PMP Enhancements for memory access and execution prevention on Machine mode

@item smmpm
@tab 1.0
@tab smmpm extension

@item smnpm
@tab 1.0
@tab smnpm extension

@item smrnmi
@tab 1.0
@tab Resumable non-maskable interrupts

@item smstateen
@tab 1.0
@tab State enable extension

@item smdbltrp
@tab 1.0
@tab Double Trap Extensions

@item ssaia
@tab 1.0
@tab Advanced interrupt architecture extension for supervisor-mode

@item ssccptr
@tab 1.0
@tab Main memory supports page table reads

@item sscofpmf
@tab 1.0
@tab Count overflow & filtering extension

@item sscounterenw
@tab 1.0
@tab Support writeable enables for any supported counter

@item sscsrind
@tab 1.0
@tab Supervisor-Level Indirect CSR Access

@item ssnpm
@tab 1.0
@tab ssnpm extension

@item sspm
@tab 1.0
@tab sspm extension

@item ssstateen
@tab 1.0
@tab State-enable extension for supervisor-mode

@item sstc
@tab 1.0
@tab Supervisor-mode timer interrupts extension

@item sstvala
@tab 1.0
@tab Stval provides all needed values

@item sstvecd
@tab 1.0
@tab Stvec supports Direct mode

@item ssstrict
@tab 1.0
@tab ssstrict extension

@item ssdbltrp
@tab 1.0
@tab Double Trap Extensions

@item ssu64xl
@tab 1.0
@tab UXLEN=64 must be supported

@item supm
@tab 1.0
@tab supm extension

@item svinval
@tab 1.0
@tab Fine-grained address-translation cache invalidation extension

@item svnapot
@tab 1.0
@tab NAPOT translation contiguity extension

@item svpbmt
@tab 1.0
@tab Page-based memory types extension

@item svvptc
@tab 1.0
@tab svvptc extension

@item svadu
@tab 1.0
@tab Hardware Updating of A/D Bits extension

@item svade
@tab 1.0
@tab Cause exception when hardware updating of A/D bits is disabled

@item svbare
@tab 1.0
@tab Satp mode bare is supported

@item xcvalu
@tab 1.0
@tab Core-V miscellaneous ALU extension

@item xcvbi
@tab 1.0
@tab xcvbi extension

@item xcvelw
@tab 1.0
@tab Core-V event load word extension

@item xcvmac
@tab 1.0
@tab Core-V multiply-accumulate extension

@item xcvsimd
@tab 1.0
@tab xcvsimd extension

@item xsfcease
@tab 1.0
@tab xsfcease extension

@item xsfvcp
@tab 1.0
@tab xsfvcp extension

@item xsfvfnrclipxfqf
@tab 1.0
@tab xsfvfnrclipxfqf extension

@item xsfvqmaccdod
@tab 1.0
@tab xsfvqmaccdod extension

@item xsfvqmaccqoq
@tab 1.0
@tab xsfvqmaccqoq extension

@item xtheadba
@tab 1.0
@tab T-head address calculation extension

@item xtheadbb
@tab 1.0
@tab T-head basic bit-manipulation extension

@item xtheadbs
@tab 1.0
@tab T-head single-bit instructions extension

@item xtheadcmo
@tab 1.0
@tab T-head cache management operations extension

@item xtheadcondmov
@tab 1.0
@tab T-head conditional move extension

@item xtheadfmemidx
@tab 1.0
@tab T-head indexed memory operations for floating-point registers extension

@item xtheadfmv
@tab 1.0
@tab T-head double floating-point high-bit data transmission extension

@item xtheadint
@tab 1.0
@tab T-head acceleration interruption extension

@item xtheadmac
@tab 1.0
@tab T-head multiply-accumulate extension

@item xtheadmemidx
@tab 1.0
@tab T-head indexed memory operation extension

@item xtheadmempair
@tab 1.0
@tab T-head two-GPR memory operation extension

@item xtheadsync
@tab 1.0
@tab T-head multi-core synchronization extension

@item xtheadvector
@tab 1.0
@tab xtheadvector extension

@item xventanacondops
@tab 1.0
@tab Ventana integer conditional operations extension

@item xmipscmov
@tab 1.0
@tab Mips conditional move extension

@end multitable