Google GitGoogle Git
Sign in
gnu/gcc.git/refs/heads/master/./gcc/ChangeLog
blob: 986ff820619b88859cfded03ad07a487989bd4eb [file]
2026-10-13 Jakub Jelinek <jakub@redhat.com>
* config/bpf/bpf.opt.urls: Regenerate.
2026-10-13 Tobias Burnus <tburnus@baylibre.com>
* tree-core.h (enum omp_clause_code): Extend comment to
OMP_CLAUSE_MESSAGE.
* tree-pretty-print.cc (dump_omp_clause): Print space before
'severity(fatal)'.
2026-10-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/127858
* tree-ssa-loop-im.cc (gather_mem_refs_stmt): When merging
accesses with differing access path always reset base and
offset to the canonical form by re-using the already canonical
ao_ref.
2026-10-13 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(aarch64_expand_atomic_hints_builtins_fetch): Change require_const_argument.
* config/aarch64/atomics.md: Change values in hint value switch.
2026-10-13 John David Anglin <danglin@gcc.gnu.org>
PR target/127843
* config/pa/pa.cc (pa_emit_move_sequence): Don't check constant
pool address.
(pa_legitimate_constant_p): Likewise.
(pa_legitimate_address_p): Likewise.
2026-10-13 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-expand.cc (ix86_expand_vector_init_insert)
<case E_V16QImode>: We don't need to zero extend var, if the
high bytes will be overwritten.
<case E_V8HImode>: Likewise for V8HImode. Whitespace fix.
(ix86_expand_vector_init_qi4): New helper function to effectively
load a V4QImode vector into an SImode register or constant.
(ix86_expand_vector_init_qi8): Likewise, to effectively load
a V8QImode vector into a DImode register or constant.
(ix86_expand_vector_init_v16qi): Change return type to void,
and never fail. Fallback to V2DI on TARGET64 and V4SI otherwise
using the above helper functions.
(ix86_expand_vector_init_general): Update call to
ix86_expand_vector_init_v16qi now that it can't fail.
2026-10-13 Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com>
* config/riscv/spacemit-x60.md (spacemit_x60_alu0, spacemit_x60_alu1):
((spacemit_x60_alu0|spacemit_x60_alu1)): update ALU reservation
definition.
2026-10-13 Keith Packard <keithp@keithp.com>
* config/picolibc-c.cc: New file.
* config/t-picolibc: New file
* config.gcc: Use new files.
2026-10-13 Jeff Law <jeffreyalaw@gmail.com>
PR target/127778
* config/riscv/riscv.cc (riscv_add_offset): Use synthesize_add
when safe and likely profitable.
2026-10-13 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127809
* jump.cc (delete_related_insns): Ignore debug insns when looking for
a BARRIER before a deleted label.
2026-10-13 Léo Hardt <leom.hardt@inf.ufrgs.br>
* caller-save.cc: Remove unused include directives
* cse.cc: Likewise.
* dwarf2ctf.cc: Likewise.
* function-tests.cc: Likewise.
* gimple-pretty-print.cc: Likewise.
* gimple-range-trace.cc: Likewise.
* gimple-range.cc: Likewise.
* gimple-ssa-store-merging.cc: Likewise.
* ipa-devirt.cc: Likewise.
* ipa-inline-transform.cc: Likewise.
* langhooks.cc: Likewise.
* lto-streamer-in.cc: Likewise.
* print-rtl.cc: Likewise.
* rtl-tests.cc: Likewise.
* sanopt.cc: Likewise.
* stmt.cc: Likewise.
* targhooks.cc: Likewise.
* tree-diagnostic-cfg.cc: Likewise.
* tree-if-conv.cc: Likewise.
* tree-ssa-threadupdate.cc: Likewise.
* tree-vect-patterns.cc: Likewise.
* tree.cc: Likewise.
* varasm.cc: Likewise.
2026-10-13 Vineet Gupta <vineet.gupta@linux.dev>
PR rtl-optimization/127852
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Don't merge two equal operands with side effects in the PLUS and
MINUS coefficient folds and in the (X - 1) * Y + Y and
(X + 1) * Y - Y folds.
2026-10-13 Vineet Gupta <vineet.gupta@linux.dev>
PR tree-optimization/127853
* tree-ssa-forwprop.cc (simplify_count_zeroes): Only pass the
value at zero to .CLZ/.CTZ when the target defines it.
2026-10-13 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127808
* reorg.cc (relax_delay_slots): Ignore debug insns when looking for
a BARRIER before a jump target.
2026-10-13 Jakub Jelinek <jakub@redhat.com>
PR middle-end/127848
* tree-tailcall.cc: Include target.h.
(process_assignment): Punt if one of dest and src_var types
is BITINT_TYPE_P and the other is not. If both are BITINT_TYPE_P,
punt if TYPE_SIZE is different, or for narrowing or same precision
conversions on != bitint_ext_undef targets, or for widening
conversions on != bitint_ext_full targets or if signedness differs.
2026-10-13 xiezhiheng <xiezhiheng@huawei.com>
* config/aarch64/aarch64.md (sve_type): Move to ...
* config/aarch64/aarch64-sched-types.md: ... this new file.
* config/arm/arm.md: Include aarch64-sched-types.md.
* config/arm/cortex-a53.md: Treat SVE as NEON.
* config/arm/cortex-a57.md: Likewise.
2026-10-13 Jakub Jelinek <jakub@redhat.com>
PR target/121688
* config/i386/sse.md (VF4_128_8_256): Only include
V4DF if TARGET_AVX512FP16 && TARGET_AVX512VL.
(VF48H_AVX512VL): Only include V8DF if TARGET_AVX512FP16.
Include V8SF also if TARGET_F16C && !TARGET_AVX512FP16.
(extend<ssePHmodelower><mode>2): Change condition
from TARGET_AVX512FP16 to TARGET_F16C || TARGET_AVX512F.
Expand !TARGET_AVX512FP16 cases differently.
(extendv4hf<mode>2): Change condition from
TARGET_AVX512FP16 && TARGET_AVX512VL to
TARGET_F16C || TARGET_AVX512VL. Expand
!(TARGET_AVX512FP16 && TARGET_AVX512VL) cases differently.
(trunc<mode><ssePHmodelower>2): Change condition
from TARGET_AVX512FP16 to TARGET_F16C || TARGET_AVX512F.
Expand !TARGET_AVX512FP16 cases differently.
(trunc<mode>v4hf2): Change condition from
TARGET_AVX512FP16 && TARGET_AVX512VL to
TARGET_F16C || TARGET_AVX512VL. Expand
!(TARGET_AVX512FP16 && TARGET_AVX512VL) cases differently.
(*vcvtph2ps_load<mask_name>): Rename to ...
(vcvtph2ps_load<mask_name>): ... this.
2026-10-13 Jeff Law <jeffreyalaw@gmail.com>
PR tree-optimization/127813
* config/riscv/zicond.md: Add new define_insn for czero expressed via
logical ops. Add define_splits when related patterns are used by an
IOR to select across two values.
2026-10-12 Iain Sandoe <iain@sandoe.co.uk>
PR target/126723
* config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Handle
C++ source locations.
2026-10-12 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127485
* gimple-range-fold.cc (fur_source::register_outgoing_edges): Don't
require a singleton; only not undefined or varying.
2026-10-12 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/127382
* match.pd (cond_expr_convert_p): Use tree_nop_conversion_p
instead of INTEGRAL_TYPE_P to check the integral selected
operands.
2026-10-12 Alfie Richards <alfie.richards@arm.com>
PR tree-optimization/127805
* tree-vect-loop-manip.cc
(vect_set_loop_condition_partial_vectors_avx512): Use
LOOP_VINFO_MAIN_EXIT instead of exit_edge for final_iv.
(vect_set_loop_condition_normal): Likewise.
2026-10-12 Jørgen Kvalsvik <j@lambda.is>
* path-coverage.cc (find_prime_paths): Call free_graph.
2026-10-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/127811
* tree-vect-slp.cc (vect_schedule_slp_node): Allow extern
last_stmt during transform.
2026-10-12 Robin Dapp <robin.dapp@oss.qualcomm.com>
Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/127443
* lower-subreg.cc (DECOMPOSED_REGISTER_P): New macro.
(decompose_register): Mark decomposed.
(resolve_reg_p): Only resolve decomposed regs.
(resolve_subreg_p): Move.
(simplify_subreg_concatn): Remove assert.
(simplify_gen_subreg_concatn): Use resolve_subreg_p.
(resolve_operand_for_swap_move_operator): Adjust assert.
(resolve_debug): Unmark as decomposed.
* rtl.h (struct GTY): Document usage of volatil in lower-subreg.
2026-10-12 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/127662
* config/riscv/riscv-vector-costs.cc (costs::record_type_sizes):
Add scalar_load and scalar_store.
2026-10-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/nvptx/nvptx.h (CLZ_DEFINED_VALUE_AT_ZERO): Handle
vector modes.
(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
2026-10-12 Josef Melcr <josef.melcr@suse.com>
PR c/127464
* doc/extend.texi (callback_only): Add a sentence about unprototyped
functions to callback_only docs.
2026-10-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-protos.h (aarch64_prepare_sve_int_fma):
Rename to aarch64_prepare_int_fma.
* config/aarch64/aarch64.cc (aarch64_prepare_sve_int_fma): Likewise.
* config/aarch64/aarch64-simd.md (fma<mode>4, fnma<mode>4): New
VDQ_BHSI expanders.
* config/aarch64/aarch64-sve.md (fma<mode>4, fnma<mode>4): Use the
renamed helper.
2026-10-12 Eric Botcazou <ebotcazou@adacore.com>
* dwarf2out.cc (gen_field_die): Change return type to DW_DIE_REF
and add ANONYMOUS parameter. Adjust implementation accordingly.
(analyze_discr_in_predicate): Rename into...
(extract_discr_in_expr): ...this. Also return a sub-field of the
record type when the containing fields are at offset 0.
(analyze_variants_discr): Adjust to above renaming.
(gen_variant_part): If there is no DIE for the discriminant, create
an anonymous DIE for it in the non-variant part of the record type.
2026-10-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/127814
* tree-vect-loop-manip.cc (vect_loop_versioning): Emit
versioning for niter assumption conditions first and
split those to the separate BB together with the cost model
check after rewriting all of it to unconditional defined operations.
2026-10-12 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR analyzer/125265
* params.opt (analyzer-max-macro-alias-depth): Move to...
2026-10-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.md ((x << C1) + C2 splitter): Do not
trigger for Zbkb when C1 is half the word size.
2026-10-11 Jeff Law <jeffreyalaw@gmail.com>
* config/riscv/predicates.md (movcc_operand): Replace
TARGET_ZICOND_LIKE with TARGET_ZICOND.
* config/riscv/riscv.cc (riscv_rtx_costs): Likewise.
(riscv_expand_conditional_move): Likewise.
* config/riscv/riscv-ext-ventana.def: Remove.
* config/riscv/riscv-ext.def: Don't include riscv-ext_ventana.def.
* config/riscv/riscv-ext.opt: Regenerated.
* config/riscv/riscv-opts.h (TARGET_ZICOND_LIKE): Remove.
* config/riscv/riscv.md: Remove references to XVentanacondops. Replace
TARGET_ZICOND_LIKE with TARGET_ZICOND.
* config/riscv/t-riscv (RISCV_EXT_DEFS): Remove riscv-ext-ventana.def.
* config/riscv/zicond.md: Remove references to XVentanaCondOps.
Replace TARGET_ZICOND_LIKE with TARGET_ZICOND throughout. Simplify
where possible.
* doc/riscv-ext.texi: Regenerated.
2026-10-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/vax/vax.h (CTZ_DEFINED_AT_ZERO): Use GET_MODE_UNIT_BITSIZE.
2026-10-11 Dimitar Dimitrov <dimitar@dinux.eu>
* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Use
GET_MODE_UNIT_BITSIZE.
2026-10-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.md (aop<mode>3): New expander.
2026-10-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/bitmanip.md: Add new 3->2 splitter when an outer PLUS
turns on some bits cleared by an inner AND. Adjust the AND mask and
change the outer code to IOR.
2026-10-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/iterators.md (oxp): New code iterator.
* config/riscv/crypto.md (pack patterns and splitters): Accept
oxp in matching RTL. Fix whitespace goofs. Generate the PLUS
forms when possible in splitters.
* config/riscv/riscv.cc (riscv_rtx_cost, case PLUS): Handle
PLUS form of pack instructions.
(riscv_move_integer): Trivial adjustment for crypto.md changes.
2026-10-10 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.cc (pa_emit_move_sequence): Handle SFmode and DFmode
symbolic, constant pool, or CONST memory references on both 32-bit
and 64-bit targets by emitting proper PIC, 14-bit HIGH/LO_SUM, or
1.x fallback move sequences using a scratch register.
(pa_secondary_reload): Strip SUBREG early. Update hard-float memory
displacement checks to account for 5-bit vs 14-bit constraints on
PA 1.x vs PA 2.0. Look through MEM wrappers when evaluating symbolic
address expressions. For symbolic address expressions under flag_pic
or non-readonly conditions, return R1_REGS for SImode and DImode, but
explicitly break out for SFmode and DFmode to let them safely fall
back to GENERAL_REGS. Return GENERAL_REGS instead of NO_REGS for shifted
and coprocessor/SAR reload fallbacks.
(pa_can_change_mode_class): Remove equal-size mode change shortcut.
Prevent cross-class type punning between integer and floating-point
modes within GENERAL_REGS or R1_REGS before reload is completed.
(pa_legitimate_constant_p): Reject out-of-range multi-word constants
in DImode on 32-bit targets. Reject naked symbolic or constant pool
SFmode and DFmode addresses unconditionally on 32-bit targets, while
intentionally allowing fully-formed LO_SUM expressions to preserve
PA 2.0 optimizations.
(pa_legitimate_address_p): Reject naked symbolic, constant pool, or
CONST expressions for SFmode and DFmode unconditionally on 32-bit
targets to force a proper HIGH/LO_SUM split or reload.
2026-10-10 Sam James <sam@gentoo.org>
PR bootstrap/112422
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Drop AC_C_CONST.
2026-10-10 Sam James <sam@gentoo.org>
PR bootstrap/112422
* acinclude.m4 (gcc_AC_C_CHAR_BIT): Don't check HAVE_LIMITS_H.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Don't search for limits.h, locale.h, stdlib.h.
* intl.h (GCC_INTL_H): Always include locale.h.
* system.h: Always include limits.h.
Always include stdlib.h.
2026-10-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* doc/ifn.texi (IFN_CLZ): Document optional second argument.
(IFN_CTZ): Ditto.
* match.pd: Fold zero test for .CLZ/.CTZ over vector modes, too.
2026-10-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/i386/i386.h (CLZ_DEFINED_VALUE_AT_ZERO): Utilize
GET_MODE_UNIT_BITSIZE instead of GET_MODE_BITSIZE in order to
deal with vector modes.
(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
* config/rs6000/rs6000.h (CLZ_DEFINED_VALUE_AT_ZERO): Ditto.
(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
* tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Use
defined zero value for vector modes.
(vect_recog_popcount_clz_ctz_ffs_pattern): Test for a defined
zero value for vector modes.
* tree-vect-stmts.cc (vectorizable_call): Bail out if natural
and final vector mode do not coincide w.r.t. defined-at-zero
value.
2026-10-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.h (CLZ_DEFINED_VALUE_AT_ZERO): Deal with
vector modes.
(CTZ_DEFINED_VALUE_AT_ZERO): Ditto.
* config/s390/s390.md (ctzsi2): Compute 32 for zero value.
* config/s390/vector.md (VIT_VXE3_NO_TI): New mode iterator.
(clzti2): New expander.
(ctzti2): Ditto.
2026-10-09 Roger Sayle <roger@nextmovesoftware.com>
* config/aarch64/aarch64.cc (aarch64_extr_rtx_p): Allow extr
pattern to be represented as either IOR, XOR or PLUS.
* config/aarch64/aarch64.md (*aarch64_bfxil<mode>_extr):
Use any_or_plus iterator.
(*aarch64_bfxilsi_extrdi): Likewise.
(*aarch64_bfxil<mode>): Likewise.
(*aarch64_bfxilsi_uxtw): Likewise.
(aarch64_rev16<mode>2_alt1): Use any_or_plus iterator and
new aop_pref_ior attribute so that the gen function uses IOR.
(*aarch64_rev16<mode>2_alt2): Use any_or_plus iterator.
(*aarch64_rev16si2_alt3): Add "*" prefix to skip gen function.
* config/aarch64/iterators.md (aop_pref_ior): New code attribute to
produce "*" for XOR/PLUS.
2026-10-09 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127781
* value-relation.cc (dom_oracle::start_search): Check if any equiv
set elements are now in the free list.
2026-10-09 Sam James <sam@gentoo.org>
PR bootstrap/112422
* configure: Regenerate.
* configure.ac: AC_HEADER_STDC.
2026-10-09 Igor Shevlyakov <igor@tachyum.com>
PR tree-optimization/127784
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Pass a vector
of 1s as an all-true mask for a VOIDmode mask_mode.
2026-10-09 Christopher Bazley <chris.bazley@arm.com>
* tree-vect-loop.cc (vectorizable_live_operation): Simplify the
calculation of the index of the final result to avoid
generating invalid polynomial offsets relative to the end of
variable-length vector types, which is what happens if the code
for loop vectorization is reused for basic block SLP.
2026-10-09 Jeff Law <jeffreyalaw@gmail.com>
* config/h8300/logical.md (aop<mode>3): New expander.
2026-10-09 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/127723
* omp-simd-clone.cc (simd_clone_clauses_extract): Remove sorry
diagnostic for simdlen with scaled modifier, moved to
c-family/c-omp.cc to ensure it is always active not only when
a target hook exists.
2026-10-09 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127725
* reorg.cc (optimize_skip): Use next_nonnote_nondebug_insn.
(get_label_before): Use prev_nonnote_nondebug_insn.
(fill_slots_from_thread): Use next_nonnote_nondebug_insn.
2026-10-09 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127661
* cfganal.h (compute_idf): Add a bitmap argument, NULL by default.
* cfganal.cc (compute_idf): Add the LIVE argument. If it is not
NULL, only add and follow the blocks in it.
* tree-into-ssa.cc (prune_unused_phi_nodes): Update the comment
about computing liveness.
(compute_livein_region): New function.
(insert_updated_phi_nodes_for): Use it to restrict the IDF of old
virtual names.
2026-10-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (MATCHER_FN_FILE_FRACTION)
(MATCHER_FN_MIN_RUN_FRACTION): New constants.
(ssa_name_group_p, phi_cond_group_p): New functions.
(class fn_splitter): New class.
(fn_splitter::split_out_p, fn_splitter::same_chunk_p)
(fn_splitter::full, fn_splitter::print_params)
(fn_splitter::print_args, fn_splitter::choose_chunk_file)
(fn_splitter::open_chunk, fn_splitter::close_chunk)
(fn_splitter::emit_dispatch, collect_alt_units)
(fn_splitter::emit_alternatives): New functions.
(dt_node::gen_kids): Add an optional fn_splitter argument and use it
at valid function-level boundaries.
(dt_node::gen_kids_1): Add an optional fn_splitter argument and call
the function holding a group in place of its body. Check that the
GENERIC SSA_NAME group and groups with a PHI form stay in the entry
function. Use ssa_name_group_p.
(decision_tree::gen): Set the matcher function budget and use
fn_splitter for large per-operation matchers.
2026-10-09 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127795
* reorg.cc (delete_prior_computation): Ignore debug insns in the
backward scan.
2026-10-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/127521
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Reject
non-constant compares that test the same bit in different ways.
2026-10-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/126563
* tree-ssa-ifcombine.cc (recognize_bits_test): Do not call
get_name_for_bit_test on rhs1.
(ifcombine_ifandif): Check all operands for abnormal PHIs.
Look through conversions via get_name_for_bit_test on the names
only when direct matching fails.
2026-10-09 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126904
* tree-ssa-sccvn.h (class vn_driver): New.
(run_rpo_vn, eliminate_with_rpo_vn, free_rpo_vn): Remove.
* tree-ssa-sccvn.cc (class eliminate_dom_walker): Make the
destructor virtual.
(eliminate_with_rpo_vn): Make static.
(run_rpo_vn): Rename to ...
(assign_value_ids): ... this, static and without the walk.
(free_rpo_vn): Make static.
(do_rpo_vn_1): Take the walker and the RPO map from the caller.
(vn_driver::vn_driver, vn_driver::~vn_driver)
(vn_driver::finalize): New.
(do_rpo_vn, pass_fre::execute): Use a vn_driver.
* tree-ssa-pre.cc (pass_pre::execute): Same.
2026-10-09 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/h8300/h8300.cc (compute_a_shift_length): Do not do any special
length adjustment for H8/SX for SHIFT_SPECIAL.
2026-10-09 Alfie Richards <alfie.richards@arm.com>
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
Use standard_iv_increment_position instead of
vect_iv_increment_position.
(vect_set_loop_condition_partial_vectors_avx512): Likewise
(vect_set_loop_condition_normal): Likewise.
* tree-vect-loop.cc
(vect_update_ivs_after_vectorizer_for_early_breaks):
Likewise.
2026-10-09 Alfie Richards <alfie.richards@arm.com>
Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126301
* tree-vect-loop-manip.cc (vect_use_loop_latch_condition_p):
Remove restriction for avx512 and non-partial vectors.
(vect_reuse_loop_latch): New function.
(vect_set_loop_condition_partial_vectors_avx512):
Add logic for do loop transformation.
(vect_set_loop_condition_normal): Likewise.
2026-10-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/127762
* gimple-fold.cc (decode_field_reference): Change psignbit to
int * and set it to 1 for sign extensions, -1 if all extension
bits are clear, or 0 otherwise.
(fold_truth_andor_for_ifcombine): Change ll_signbit, lr_signbit,
rl_signbit, and rr_signbit to int. Check for signbit > 0 when
including sign bit in test, and signbit < 0 when checking for
zero-extension. Only reject positive lr_signbit and
rr_signbit.
2026-10-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/127447
PR tree-optimization/125444
PR tree-optimization/124937
* gimple-fold.cc (decode_field_reference): Convert exp to
outer_type when decoding an INTEGER_CST right-hand XOR operand.
2026-10-09 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf-protos.h (bpf_check_call_target): New prototype.
* config/bpf/bpf.cc (bpf_check_call_target): New function.
(bpf_output_call): Update comment and error message.
* config/bpf/bpf.md (call): Check the call target with
bpf_check_call_target.
(call_value): Likewise.
2026-10-09 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.opt (mcallx): New option.
* config/bpf/bpf.cc (bpf_option_override): Enable bpf_has_callx
for CPU v1 and above.
(bpf_output_call): Check bpf_has_callx instead of TARGET_XBPF.
(bpf_small_register_classes_for_mode_p): Likewise.
* config/bpf/bpf-c.cc (bpf_target_macros): Define
__BPF_FEATURE_CALLX.
* config/bpf/bpf.md (call_internal): Update comment.
* doc/invoke.texi (eBPF Options): Document -mcallx. Document
that -mxbpf is only passed on to the assembler, and remove the
stale note about callee-saved registers.
2026-10-09 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.md (call_internal): Split the call target
constraint into separate alternatives for a constant address and
for a register, and use the pseudo-C spelling `callx' for the
latter.
(call_value_internal): Likewise.
* config/bpf/bpf.cc (bpf_output_call): Update comment.
2026-10-09 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* ipa-cp.cc (update_profiling_info): Under
-fprofile-partial-training lower the original node's profile to
local instead of also forcing it to global0.
2026-10-09 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* hierarchical_discriminator.cc (assign_discriminators_to_bb):
Handle RTL.
* cfghooks.h (struct copy_bb_data): Add skip_copyid.
* cfghooks.cc (copyid_location_from_bb): New.
(duplicate_block): Assign a fresh copyid unless suppressed.
(copy_bbs): Assign one shared copyid for the duplicated region.
* cfgloopmanip.h (DLTHE_RECORD_HIERARCHICAL_DISCRIMINATOR): Remove.
* cfgloopmanip.cc (duplicate_loop_body_to_header_edge): Remove
manual hierarchical discriminator assignment.
* gimple-loop-versioning.cc (loop_versioning::version_loop): Rely
on copy_bbs for copyids.
* tree-vect-loop-manip.cc (vect_do_peeling, vect_loop_versioning):
Likewise.
* tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely): Drop
DLTHE_RECORD_HIERARCHICAL_DISCRIMINATOR.
* tree-vect-stmts.cc (hoist_defs_of_uses): Assign copyid to
gimple_copy clones.
* value-prof.cc (gimple_ic, gimple_stringop_fixed_value): Likewise.
2026-10-08 Dominic P <gcc@gcc.dp11.uk>
* tree-vect-stmts.cc (vect_truncate_gather_scatter_offset): Do not
lower the element count to the latch iteration count when peeling
for alignment.
2026-10-08 Zhongteng Gui <dragon-archer@outlook.com>
PR target/127137
* config.gcc (i[34567]86-*-mingw* | x86_64-*-mingw*): Remove
handling of i386/crtdll.h.
* config/i386/crtdll.h: Remove file. No longer used.
* doc/install.texi: Remove mingw32crt from the list of targets.
2026-10-08 Alfie Richards <alfie.richards@arm.com>
Alex Coplan <alex.coplan@arm.com>
* config/aarch64/aarch64-acle-builtins.cc
(gimple_folder::fold_contiguous_load): New function.
* config/aarch64/aarch64-acle-builtins.h
(gimple_folder::fold_contiguous_load): New function.
* config/aarch64/aarch64-sve-builtins-base.cc:
(svld1_impl::fold): Change to use fold_contiguous_load.
(svldxf1_extend_impl::fold): Change to use fold_contiguous_load.
* config/aarch64/aarch64-sve.md
(aarch64_ld<fn>f1_<ANY_EXTEND:optab><SVE_HSDI:mode><SVE_PARTIAL_I:mode>):
Add else operand.
2026-10-08 Alfie Richards <alfie.richards@arm.com>
* tree-vect-loop-manip.cc (vect_maybe_permute_loop_masks):
Make the function optional and retargetable.
(vect_maybe_permute_loop_masks):
New overload.
2026-10-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/127693
* tree-ssa-operands.cc (operands_scanner::parse_ssa_operands):
For IFN_ASSUME do not cause address-takens.
* tree-ssa.cc (execute_update_addresses_taken): Likewise, but
still make sure to not rewrite to a register.
* gimple-ssa-pta-constraints.cc (find_func_aliases_for_call): No
side-effects from IFN_ASSUME, so produce no constraints.
2026-10-08 Jørgen Kvalsvik <j@lambda.is>
* prime-paths.cc (scc_exit_prime_paths): Call
insert_with_suffix.
2026-10-08 Jeff Law <jeffreyalaw@gmail.com>
* config/stormy16/stormy16.md (aopqi3, aophi3): New expanders.
2026-10-08 Richard Biener <rguenther@suse.de>
PR target/127769
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Separate MULT_EXPR and MULT_HIGHPART_EXPR handling.
2026-10-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/127758
* pta-andersen.cc (unite): Refuse to merge an artificial
variable into another.
2026-10-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/127758
* pta-andersen.cc (scc_visit): Do not merge when unite fails.
(find_equivalent_node): Likewise.
2026-10-08 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_prologue_setup_frame): Tighten
condition for when prologue_saves is used.
2026-10-08 Georg-Johann Lay <avr@gjlay.de>
PR target/127482
* config/avr/avr.cc (sequent_regs_live): Return 0 for
noreturn functions, OS_task and OS_main.
(avr_prologue_setup_frame, avr_expand_epilogue) <minimize>: Move
OS_task and OS_main tests to sequent_regs_live.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127661
* tree-ssa-dom.cc (names_without_foldable_uses): New variable.
(pass_dominator::execute): Allocate and free it.
(back_propagate_equivalences): Return early for the names in
names_without_foldable_uses unless checking is enabled. Skip PHI
nodes. Record LHS in names_without_foldable_uses if no use can
give an equivalence.
(dom_opt_dom_walker::before_dom_children): After optimize_stmt,
remove the uses of a statement that defines an SSA name from
names_without_foldable_uses.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127483
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case VEC_CONCAT>: Use rtl_hooks.gen_lowpart_no_emit rather than
gen_lowpart, and do not fold if it fails.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127661
* cprop.cc (bypass_block): Substitute SETCC into the source of
JUMP once, before the loop over the incoming edges.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127661
* cprop.cc (struct bypass_set_cache_entry): New.
(bypass_set_cache): New variable.
(find_bypass_set): Use and update it.
(bypass_conditional_jumps): Allocate and free it.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127661
* cprop.cc (bypass_setcc_needed_p): New function.
(bypass_block): Use it to decide whether to copy SETCC onto a
redirected edge.
(bypass_conditional_jumps): Update comment.
2026-10-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (lower_for): Emit a diagnostic and skip replicated
substitutions when no for-level iterator appears in the pattern.
* match.pd: Move the (for lop ...) vec_cond pattern outside the
enclosing (for op ...).
2026-10-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/127764
* ipa-fnsummary.cc (set_switch_stmt_execution_predicate):
Use wi::to_widest to preserve sign when extending min to type.
2026-10-08 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (class back_threader): Add search
and apply; make the destructor virtual.
(back_threader::search): New, split out of thread_blocks.
(back_threader::apply): Same.
(back_threader::thread_blocks): Call them.
2026-10-08 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-path.cc (DEBUG_SOLVER): Move...
(path_range_query::range_defined_in_block): Adjust.
(path_range_query::compute_ranges_in_block): Likewise.
(path_range_query::compute_ranges): Likewise.
* gimple-range-path.h (DEBUG_PATH_RANGER): ...here, renamed.
2026-10-08 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-sccvn.cc (record_unwind_state): New, split out of...
(do_rpo_vn_1): ...here.
2026-10-08 Richard Biener <rguenther@suse.de>
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Also simplify (xor (ior A B) B) to (and (not B) A).
2026-10-08 Richard Biener <rguenther@suse.de>
PR rtl-optimization/127606
* combine.cc (distribute_and_simplify_rtx): Gate the
(and (xor B C) (not A)) to (xor (ior A B) (ior A C))
distribution on A not containing a paradoxical subreg.
2026-10-08 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (legitimate_reload_vector_constant_p):
Move.
(s390_rtx_costs): Add costs for VML and VMAL.
(s390_legitimate_constant_p): Utilize
legitimate_reload_vector_constant_p.
* config/s390/vector.md (*vmal<mode>): New insn pattern.
2026-10-07 Jeff Law <jeffreyalaw@gmail.com>
* config/sh/sh.md (aopsi3): Define and route towards IOR.
2026-10-07 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR analyzer/125265
* doc/params.texi (analyzer-max-macro-alias-depth): Document.
* params.opt (-param=analyzer-max-macro-alias-depth=): New.
2026-10-07 Jason Merrill <jason@redhat.com>
* doc/invoke.texi (-fno-module-include-translate): Document.
2026-10-07 Jason Merrill <jason@redhat.com>
* doc/invoke.texi (C++ Modules): Remove "Textual merging" from
missing pieces.
2026-10-07 Filip Kastl <fkastl@suse.cz>
* gimple-range-cache.h: Add some missing override keywords for
member functions.
* gimple-range-path.h: Ditto.
* gimple-range.h: Ditto.
* range-op.cc: Ditto.
* value-relation.h: Exchange the virtual keyword for the
override keyword where appropriate.
2026-10-07 Filip Kastl <fkastl@suse.cz>
* config/i386/i386.cc: Add a missing override keyword for a
member functions.
2026-10-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/125060
* config/rs6000/vector.md (vcond_mask_<mode><mode>): Change the mode
iterator from VEC_I to VEC_IC to support V1TI.
2026-10-07 Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/108477
* expr.cc (expand_expr_real_2) <case BIT_IOR_EXPR>: Split from
BIT_AND_EXPR path. Use get_nonzero_bits to determine if both
operands a bit-wise disjoint, and if so, expand using the
backend's preferred aop_optab.
<case BIT_XOR_EXPR>: Likewise.
2026-10-07 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/126521
* ifcvt.cc (noce_try_abs): These conversions are unsafe in the
presence of NaNs.
2026-10-07 Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/127544
PR tree-optimization/126562
* tree-ssa-math-opts.cc (gimple_expand_builtin_pow): Use
tree_expr_maybe_signaling_nan_p insted of REAL_VALUE_ISSIGNALING_NAN
to check whether an operand may be a signaling NaN. pow(x,0.5)
also can't be transformed to sqrt(x) if x may be -Inf.
2026-10-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126459
* match.pd (x != CST1 ? x + CST2 : CST3 -> x + CST2): If
CST1 + CST2 overflows and type overflow doesn't wrap,
simplify into corresponding unsigned addition.
2026-10-07 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/127723
* attribs.cc (omp_declare_simd_clauses_equal): Handle
simdlen's type and divisor of the scaled modifier.
* omp-general.cc (resolve_omp_target_device_matches,
omp_construct_simd_compare): Likewise.
* gimplify.cc (gimplify_scan_omp_clauses): Remove
simdlen clause with a sorry when it has a scaled modifier.
* omp-simd-clone.cc (simd_clone_clauses_extract): Likewise.
* tree-core.h (enum omp_clause_code): Update comment for
OMP_CLAUSE_SIMDLEN.
* tree-pretty-print.cc (dump_omp_clause): Handle scaled
modifier to simdlen.
(dump_omp_context_selector): Fix dumping of simd trait.
* tree.cc (omp_clause_num_ops): OMP_CLAUSE_SIMDLEN takes
now three operands.
* tree.h (OMP_CLAUSE_SIMDLEN_TYPE,
OMP_CLAUSE_SIMDLEN_DIVISOR): New defines.
2026-10-06 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (edge_info::derive_equivalences): Remove the
constant-first arms of the PLUS_EXPR and EQ_EXPR cases.
(record_edge_info): Remove the arm for a constant first operand.
2026-10-06 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (dom_opt_dom_walker::simplify_stmt): Rename to...
(dom_opt_dom_walker::fold_cond): ...this. Fold a conditional with
the ranger, do not simplify anything else.
(dom_opt_dom_walker::optimize_stmt): Adjust.
2026-10-06 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
Luis Silva <luis.silva@globalfoundries.com>
PR target/127117
* config/arc/arc.md (*arc_clzsi2): Produce 31 rather than 32 for
a zero operand.
(arc_ctzsi2): Likewise.
2026-10-06 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127719
* tree-ssanames.cc (release_ssa_name_fn): Do not call
reset_range_info.
* value-relation.cc (dom_oracle::nearest_relations): Check the
free list before adding a name to the relation list.
2026-10-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (subtree_has_match_p): New function.
(decision_tree::find_node): Replace unconditional DT_TRUE barrier
with a scan for DT_MATCH descendants in intermediate siblings.
2026-10-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (nodes_overlap_p): Return false when the two
expressions have different is_generic, as they cannot match the
same input.
2026-10-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (contains_id): For c_expr, check CPP_NAME tokens
rather than capture_ids to detect for-iterator references.
(lower_for): Skip result copy in replace_id when the for-iterator
does not appear in the result, to preserve pointer identity and
enable transform sharing.
2026-10-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (capture::gen_transform): Jump to the failure label
rather than return when a comparison needs a sequence and there is
none.
2026-10-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/127705
* tree-vect-slp.cc (vect_schedule_scc): Fixup SCC copy.
2026-10-06 Eric Botcazou <ebotcazou@adacore.com>
* gimple.h (gimple_ior_addresses_taken): Delete.
* gimple.cc (gimple_ior_addresses_taken_1): Move to...
(gimple_ior_addresses_taken): Move to...
* tree-ssa.cc (gimple_ior_addresses_taken_1): ...here and rename
into set_addresses_taken_1.
(gimple_ior_addresses_taken): ...here, swap the parameters and
rename into set_addresses_taken.
(execute_update_addresses_taken): Adjust to above changes and
call set_addresses_taken_1 for the processing of PHI nodes.
2026-10-06 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
* config/i386/i386.cc (ix86_gimplify_va_arg): Always read unnamed
256 and 512-bit vectors from the stack.
2026-10-06 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
* config/i386/i386.cc (ix86_pass_by_reference_abi): New function,
split out of ...
(ix86_pass_by_reference): ... this.
(ix86_gimplify_va_arg): Derive argument indirection from the ABI of
the va_list type. Read indirect MS ABI arguments as pointers.
2026-10-06 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/predicates.md (move_fp_operand): Use CONSTANT_P
instead of CONST_DOUBLE_P.
2026-10-06 Tamar Christina <tamar.christina@arm.com>
PR target/126063
* config/aarch64/aarch64-acle-builtins.cc (function_instance::hash):
Use ptr diff for hash instead of ptr.
(gt_pch_nx): Add the pointers to PCH tracking.
2026-10-06 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127246
* cfgcleanup.cc (try_crossjump_bb): Keep the predecessors of a
computed jump apart under the condition of the gate of
pass_duplicate_computed_gotos.
2026-10-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/53805
* tree-ssa-ifcombine.cc (ifcombine_ifandif): Pass comparisons
in the correct order.
* gimple-fold.cc (and_comparisons_1): Add FIXME comment.
(maybe_fold_and_comparisons): Do not call and_comparisons_1 with
swapped comparisons.
2026-10-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/53805
* fold-const.cc (combine_comparisons): Do not treat COMPCODE_FALSE
or COMPCODE_TRUE as trapping.
2026-10-06 Jakub Jelinek <jakub@redhat.com>
PR target/127720
* config/i386/i386.md (extendhfdf2): Enable also for
TARGET_F16C || TARGET_AVX512VL, in those cases expand as
extendhfsf2 followed by extendsfdf2.
2026-10-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/127452
* config/i386/i386-protos.h (ix86_expand_umulvndi_highpart): Declare.
* config/i386/i386-expand.cc (ix86_expand_umulvndi_highpart):
New function.
* config/i386/sse.md (umul<mode>3_highpart): Add for VI8_AVX2_AVX512F.
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Cost
IFN_MULH as we implement it.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc (vmax, vmaxq, vmin,
vminq, vmaxnm, vmaxnmq, vminnm, vminnmq): New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vmax, vmaxq, vmin,
vminq, vmaxnm, vmaxnmq, vminnm, vminnmq): New function groups.
* config/aarch64/arm_neon.h (vmax_s8, vmax_s16, vmax_s32, vmax_u8,
vmax_u16, vmax_u32, vmaxq_s8, vmaxq_s16, vmaxq_s32, vmaxq_u8,
vmaxq_u16, vmaxq_u32, vmaxnm_f32, vmaxnm_f64, vmaxnmq_f32, vmaxnmq_f64,
vmin_s8, vmin_s16, vmin_s32, vmin_u8, vmin_u16, vmin_u32, vminq_s8,
vminq_s16, vminq_s32, vminq_u8, vminq_u16, vminq_u32, vminnm_f32,
vminnm_f64, vminnmq_f32, vminnmq_f64, vmaxnm_f16, vmaxnmq_f16,
vminnm_f16, vminnmq_f16): Delete functions.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc (vrnd, vrndq, vrnda,
vrndaq, vrndi, vrndiq, vrndm, vrndmq, vrndn, vrndns, vrndnq, vrndp,
vrndpq, vrndx, vrndxq): New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vrnd, vrndq, vrnda,
vrndaq, vrndi, vrndiq, vrndm, vrndmq, vrndn, vrndns, vrndnq, vrndp,
vrndpq, vrndx, vrndxq): New function groups.
* config/aarch64/arm_neon.h (vrnd_f32, vrnd_f64, vrndq_f32, vrndq_f64,
vrnda_f32, vrnda_f64, vrndaq_f32, vrndaq_f64, vrndi_f32, vrndi_f64,
vrndiq_f32, vrndiq_f64, vrndm_f32, vrndm_f64, vrndmq_f32, vrndmq_f64,
vrndns_f32, vrndn_f32, vrndn_f64, vrndnq_f32, vrndnq_f64, vrndp_f32,
vrndp_f64, vrndpq_f32, vrndpq_f64, vrndx_f32, vrndx_f64, vrndxq_f32,
vrndxq_f64, vrnd_f16, vrndq_f16, vrnda_f16, vrndaq_f16, vrndi_f16,
vrndiq_f16, vrndm_f16, vrndmq_f16, vrndn_f16, vrndnq_f16, vrndp_f16,
vrndpq_f16, vrndx_f16, vrndxq_f16): Delete functions.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc (vsqrt, vsqrtq):
New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsqrt, vsqrtq):
New function groups.
* config/aarch64/arm_neon.h (vsqrt_f32, vsqrt_f64, vsqrtq_f32,
vsqrtq_f64, vsqrt_f16, vsqrtq_f16): Delete functions.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc (vhadd, vhaddq, vrhadd,
vrhaddq): New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vhadd, vhaddq, vrhadd,
vrhaddq): New function groups.
* config/aarch64/arm_neon.h (vhadd_s8, vhadd_s16, vhadd_s32, vhadd_u8,
vhadd_u16, vhadd_u32, vhaddq_s8, vhaddq_s16, vhaddq_s32, vhaddq_u8,
vhaddq_u16, vhaddq_u32, vrhadd_s8, vrhadd_s16, vrhadd_s32, vrhadd_u8,
vrhadd_u16, vrhadd_u32, vrhaddq_s8, vrhaddq_s16, vrhaddq_s32,
vrhaddq_u8, vrhaddq_u16, vrhaddq_u32): Delete functions.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-acle-builtins.h (TYPES_s_float_bhs_integer,
TYPES_sd_float_all_integer, s_float_bhs_integer,
sd_float_all_integer): New type lists.
* config/aarch64/aarch64-neon-builtins-base.cc (vaddv, vaddvq, vmaxv,
vmaxvq, vminv, vminvq, vmaxnmv, vmaxnmvq, vminnmv, vminnmvq):
New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vaddv, vaddvq, vmaxv,
vmaxvq, vminv, vminvq, vmaxnmv, vmaxnmvq, vminnmv, vminnmvq):
New function groups.
* config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8,
vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64,
vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32,
vaddvq_f64, vmaxv_s8, vmaxv_s16, vmaxv_s32, vmaxv_u8, vmaxv_u16,
vmaxv_u32, vmaxvq_s8, vmaxvq_s16, vmaxvq_s32, vmaxvq_u8, vmaxvq_u16,
vmaxvq_u32, vmaxnmv_f32, vmaxnmvq_f32, vmaxnmvq_f64, vminv_s8,
vminv_s16, vminv_s32, vminv_u8, vminv_u16, vminv_u32, vminvq_s8,
vminvq_s16, vminvq_s32, vminvq_u8, vminvq_u16, vminvq_u32, vminnmv_f32,
vminnmvq_f32, vminnmvq_f64, vmaxnmv_f16, vmaxnmvq_f16, vminnmv_f16,
vminnmvq_f16): Delete functions.
2026-10-06 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc (vqaddb, vqaddh,
vqadds, vqaddd, vqadd, vqaddq, vqsubb, vqsubh, vqsubs, vqsubd, vqsub,
vqsubq): New function bases.
(one_element_vector_type_p): New function.
(gimple_ifn::fold): Automatically convert arguments with
single-element vector modes to the corresponding XX modes and back.
* config/aarch64/aarch64-neon-builtins-base.def (vqaddb, vqaddh,
vqadds, vqaddd, vqadd, vqaddq, vqsubb, vqsubh, vqsubs, vqsubd, vqsub,
vqsubq): New function groups.
* config/aarch64/arm_neon.h (vqadd_s8, vqadd_s16, vqadd_s32,
vqadd_s64, vqadd_u8, vqadd_u16, vqadd_u32, vqadd_u64, vqaddq_s8,
vqaddq_s16, vqaddq_s32, vqaddq_s64, vqaddq_u8, vqaddq_u16, vqaddq_u32,
vqaddq_u64, vqsub_s8, vqsub_s16, vqsub_s32, vqsub_s64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_s8, vqsubq_s16, vqsubq_s32,
vqsubq_s64, vqsubq_u8, vqsubq_u16, vqsubq_u32, vqsubq_u64, vqaddb_s8,
vqaddh_s16, vqadds_s32, vqaddd_s64, vqaddb_u8, vqaddh_u16, vqadds_u32,
vqaddd_u64, vqsubb_s8, vqsubh_s16, vqsubs_s32, vqsubd_s64, vqsubb_u8,
vqsubh_u16, vqsubs_u32, vqsubd_u64): Delete functions.
2026-10-06 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
Jakub Jelinek <jakub@redhat.com>
PR target/127692
* config/s390/s390.md: Fix bswap:HI reg-reg splitter.
2026-10-06 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-scopedtables.h (expr_hash_elt::expr_hash_elt): Remove
the undefined tree overload.
(initialize_expr_from_cond): Remove declaration.
* tree-ssa-scopedtables.cc (initialize_expr_from_cond): Make
static.
2026-10-05 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127719
* gimple-range-gori.cc (range_def_chain::clear): Do not
recalculate a def chain when it has just been cleared.
* tree-ssanames.cc (release_ssa_name_fn): Clear range info.
2026-10-05 linden <bestxmg@gmail.com>
* text-art/types.h (text_art::array2::set): Add overload taking
element_t &&.
2026-10-05 linden <bestxmg@gmail.com>
* xml.cc (node_with_children::add_text): Remove no-op std::move.
2026-10-05 linden <bestxmg@gmail.com>
* diagnostics/source-printing.cc (to_text::push_html_tag)
(to_text::push_html_tag_with_class, to_text::add_html_tag_with_class)
(to_html::push_html_tag, to_html::push_html_tag_with_class)
(to_html::add_html_tag_with_class): Take tag/class names as
const char * rather than std::string by value.
2026-10-05 linden <bestxmg@gmail.com>
* diagnostics/html-sink.cc (add_labelled_value): std::move 'id' and 'label' into
the xml::printer calls.
2026-10-05 Martin Jambor <mjambor@suse.cz>
* ipa-cp.cc (overall_scaled_runtime): New.
(good_cloning_opportunity_p): Scale PGO evaluations by
overall_scaled_runtime.
(ipcp_propagate_stage): Calculate also overall_scaled_runtime and
print it and unscaled time.
(ipa_cp_cc_finalize): Set overall_scaled_runtime to zero.
* params.opt (ipa-cp-profile-runtime-scaling): New.
* doc/params.texi (ipa-cp-profile-runtime-scaling): New.
2026-10-05 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.cc (hppa_rtx_costs_shadd_p): Strip SUBREG wrappers
from inner operands when checking if X represents a possible
shadd pattern.
2026-10-05 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.cc (aarch64_autovectorize_vector_modes):
All logic to only use aarch64-autovec-mode when specified.
* config/aarch64/aarch64.opt: Add --param=aarch64-autovec-mode.
* doc/params.texi: Document --param=aarch64-autovec-mode.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (single_block_loop_p): Remove.
(record_edge_info): Do not record equivalences on the exit edge of
a single block loop.
2026-10-05 Alex Coplan <alex.coplan@arm.com>
* tree-vect-slp.cc (vect_build_slp_tree_2): In the two_operators
case, avoid setting the code field on the plus/minus nodes.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-scopedtables.cc (build_and_record_new_cond): Remove.
(record_conditions): Do not derive the implied conditions.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (dom_opt_dom_walker::const_or_copy_of_stmt): New.
(dom_opt_dom_walker::eliminate_redundant_computations): Ask it on
a lookup miss.
* tree-ssa-scopedtables.cc (simplify_binary_operation): Remove.
(lookup_avail_expr): Do not call it.
* tree-ssa-scopedtables.h (simplify_binary_operation): Remove.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (record_equivalences_from_incoming_edge): Make a
member of dom_opt_dom_walker and use its tables.
(eliminate_redundant_computations): Same.
(record_equivalences_from_stmt): Same.
(dom_opt_dom_walker::before_dom_children): Adjust the calls.
(dom_opt_dom_walker::optimize_stmt): Same.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (dom_opt_dom_walker::optimize_stmt): Remove the
boolean range special case.
2026-10-05 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-dom.cc (dom_opt_dom_walker::m_dummy_cond): Remove.
(dom_opt_dom_walker::test_for_singularity): Remove.
(dom_opt_dom_walker::fold_cond): Remove.
(dom_opt_dom_walker::simplify_stmt): New.
(dom_opt_dom_walker::optimize_stmt): Call it in place of
test_for_singularity and fold_cond.
2026-10-05 Jonathan Wakely <jwakely@redhat.com>
* doc/extend.texi (Attribute Syntax): Remove stray period.
2026-10-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/127693
* tree-ssa-alias.h (get_continuation_for_phi): Remove
abort_on_visited argument.
* tree-ssa-alias.cc (maybe_skip_until): Likewise. Always
succeed when reaching an already visited region.
(get_continuation_for_phi): Remove abort_on_visited argument.
(walk_non_aliased_vuses): Clear the visited bitmap when
translating the reference instead of tracking whether
we translated.
* ipa-prop.cc (determine_known_aggregate_parts): Adjust.
* tree-ssa-pre.cc (translate_vuse_through_block): Likewise.
2026-10-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/127693
* tree-ssa-alias.cc (cmp_intpair): New qsort helper.
(get_continuation_for_phi): Sort the PHI args and avoid
processing duplicates.
2026-10-05 Andreas Schwab <schwab@suse.de>
* doc/extend.texi (Other Builtins): Fix typo.
2026-10-05 Avinash Jayakar <avinashd@linux.ibm.com>
PR target/127632
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
Initialize size to 0.
2026-10-05 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md
(adddi3): Remove the previous sloppy workaround.
(adddi3_lowpart_0, adddi3_lowpart_1): New insn_and_split patterns.
2026-10-04 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md: Various whitespace and indentation clean-ups.
(aop_name_pfx): New code attribute to
produce "*" for XOR/PLUS.
(x86_64_shld<nf_name>): Use any_or_plus and aop_name_pfx.
(x86_64_shld_ndd<nf_name>): Likewise.
(x86_64_shld_1<nf_name>): Likewise.
(x86_64_shld_ndd_1<nf_name>): Likewise.
(*x86_64_shld_shrd_1_nozext_nf): Use any_or_plus.
(*x86_64_shld_shrd_1_nozext): Likewise.
(*x86_64_shld_2): Likewise.
(*x86_64_shld_ndd_2): Likewise.
(x86_shld<nf_name>): Use any_or_plus and aop_name_pfx.
(x86_shld_1<nf_name>): Likewise.
(x86_shld_ndd_1<nf_name>): Likewise.
(*x86_shld_shrd_1_nozext_nf): Use any_or_plus.
(*x86_shld_shrd_1_nozext): Likewise.
(*x86_shld_2): Likewise.
(*x86_shld_ndd_2): Likewise.
(x86_64_shrd<nf_name>): Use any_or_plus and aop_name_pfx.
(x86_64_shrd_ndd<nf_name>): Likewise.
(x86_64_shrd_1<nf_name>): Likewise.
(x86_64_shrd_ndd_1<nf_name>): Likewise.
(*x86_64_shrd_shld_1_nozext_nf): Use any_or_plus.
(*x86_64_shrd_shld_1_nozext): Likewise.
(*x86_64_shrd_2): Likewise.
(*x86_64_shrd_ndd_2): Likewise. Fix match_dup operand numbering.
(x86_shrd<nf_name>): Use any_or_plus and aop_name_pfx.
(x86_shrd_ndd<nf_name>): Likewise.
(x86_shrd_1<nf_name>): Likewise.
(x86_shrd_ndd_1<nf_name>): Likewise.
(*x86_shrd_shld_1_nozext_nf): Use any_or_plus.
(*x86_shrd_shld_1_nozext): Likewise.
(*x86_shrd_2): Likewise.
(*x86_shrd_ndd_2): Likewise.
* doc/md.texi: Document aop<mode>3 as a named pattern.
2026-10-04 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md (canonicalize_funcptr_for_compare): Check for
SYMBOL_REF targets that are not function addresses early and emit
a direct move instruction to bypass redundant libcall wrappers.
2026-10-04 Aldy Hernandez <aldy@quesejoda.com>
* vr-values.cc (simplify_using_ranges::simplify_compare_using_ranges_1):
Fold a LE or GE test between two names to EQ when the relation
oracle implies it.
2026-10-04 Aldy Hernandez <aldy@quesejoda.com>
* range-op-mixed.h (operator_bitwise_or::lhs_op1_relation): New.
(operator_min::lhs_op1_relation): New.
(operator_min::lhs_op2_relation): New.
(operator_max::lhs_op1_relation): New.
(operator_max::lhs_op2_relation): New.
* range-op.cc (operator_bitwise_and::lhs_op1_relation): Return
VREL_EQ when the operands are equal.
(operator_bitwise_or::lhs_op1_relation): New.
(operator_min::lhs_op1_relation): New.
(operator_min::lhs_op2_relation): New.
(operator_max::lhs_op1_relation): New.
(operator_max::lhs_op2_relation): New.
2026-10-03 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (CORE-V Built-in Functions): Update URL.
2026-10-03 Georg-Johann Lay <avr@gjlay.de>
* doc/install.texi (Tools/packages necessary for modifying GCC):
Note that Texinfo older than 7.1.1 may throw incorrect build
warnings (as opposed to Texinfo older than 7.1).
2026-10-03 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Options): Update documentation of linker
stubs relation to linker relaxation.
2026-10-03 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127689
* match.pd (`(trunc)abs((ext)a)`): Move right
after `abs((ext)a)` pattern. Restrict to
non integral types.
2026-10-02 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::recomputed_relation): Change
implementation.
(dom_oracle::relation_search): Invoke recomputed_relation.
* value-relation.h (recomputed_relation): Adjust prototype.
2026-10-02 Andrew MacLeod <amacleod@redhat.com>
* flag-types.h (RANGER_DEBUG_RELATION): New.
(RANGER_DEBUG_TRACE_RELATION): New.
* params.opt (--param=ranger-debug): Adjusted options.
* tree-vrp.cc (execute_fast_vrp): Remove deprecated param.
* value-query.cc (range_query::create_relation_oracle): Likewise.
* value-query.h (create_relation_oracle): Adjust prototype.
* value-relation.cc (frontier_data::frontier_data): New.
(frontier_data::set_known): New.
(frontier_data::known_relation): New.
(frontier_data::clear_search): New.
(dom_oracle::dom_oracle): Initialize new fields.
(dom_oracle::~dom_oracle): Release new fields.
(dom_oracle::record): Do not register transitives.
(dom_oracle::register_transitives): Delete.
(dom_oracle::find_relation_dom): Do not recompute relations.
(dom_oracle::nearest_relations): New.
(dom_oracle::cache_relation): New.
(dom_oracle::start_search): New.
(dom_oracle::add_to_frontier): New.
(dom_oracle::expand_frontier): New.
(dom_oracle::relation_search): New.
(dom_oracle::query): Use new relation_search routine.
* value-relation.h (dom_oracle::dom_oracle): Adjust prototype.
(dom_oracle::m_do_trans): Remove.
(class frontier_data): New.
(register_transitives): Remove prototype.
(nearest_relations): New prototype.
(relation_search): Likewise.
(cache_relation): Likewise.
(struct related): New.
(m_near): New.
(m_lhs_search, m_rhs_search): New.
(struct frontier_element): New.
(m_worklist): New.
(m_wl_ix): New.
(start_search): New.
(add_to_frontier): New.
(expand_frontier): New.
2026-10-02 Jakub Jelinek <jakub@redhat.com>
* config/avr/avr.opt.urls: Regenerate.
* config/nvptx/nvptx.opt.urls: Regenerate.
2026-10-02 Yongqiang Tian <yqtian668@gmail.com>
PR tree-optimization/127687
* tree-ssa-forwprop.cc (pass_forwprop::execute): Skip debug
statements before assigning UIDs.
2026-10-02 Georg-Johann Lay <avr@gjlay.de>
* configure.ac [target=avr-*.*]: Test linker for --prune-vectab,
and AC_DEFINE HAVE_LD_AVR_PRUNE_VECTAB if supported.
* config.in: Rebuild.
* configure: Rebuild.
* config/avr/avr.opt (-mprune-vectab): New target option.
* config/avr/specs.h (LINK_SPEC): Add %(link_prune_vectab).
* config/avr/gen-avr-mmcu-specs.cc (print_mcu)
[HAVE_LD_AVR_PRUNE_VECTAB]: Emit link_prune_vectab spec.
* config/avr/avr.opt.urls: Rebuild.
* doc/invoke.texi (AVR Options): Document -mprune-vectab.
2026-10-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/127693
* tree-ssa-alias.cc (maybe_skip_until): Stop when reaching
the PHI again.
2026-10-02 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/127635
* simplify-rtx.cc (simplify_context::simplify_subreg): Avoid is_a<..>
with ref param.
2026-10-02 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/127677
* tree-vect-loop-manip.cc (vect_gen_prolog_loop_niters): Generate MIN
expression on niters.
2026-10-02 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc (intersects_p): New.
(class ctor_ref_range): Add SRC.
(ctor_ref_range::accumulate_range_from_array_ref): Load only from
the elements the range of the index reaches, a constant index
included.
(fold_using_range::fold_stmt): Pass the source to
range_from_readonly_var.
(fold_using_range::range_from_readonly_var): Add SRC.
* gimple-range-fold.h (fold_using_range::range_from_readonly_var):
Adjust.
2026-10-01 Guillaume Gomez <contact@guillaume-gomez.fr>
* Makefile.in: Compile new attr-handlers.cc file
* attr-handlers.cc: New file.
* attr-handlers.h: New file.
2026-10-01 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc
(ctor_ref_range::accumulate_range_from_array_ref): Walk the
initializer by index to find the elements it leaves out.
2026-10-01 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-acle-builtins.cc (gimple_folder::fold):
Don't bail out of folding early.
2026-10-01 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc (class ctor_ref_range): New.
(ctor_ref_range::accumulate_range): New, the dispatch of...
(range_from_readonly_load): ...this. Remove.
(ctor_ref_range::accumulate_range_from_scalar,
ctor_ref_range::accumulate_range_from_component_ref,
ctor_ref_range::accumulate_range_from_array_ref): New, its cases.
(range_from_missing_constructor_part): Rename to...
(ctor_ref_range::accumulate_range_from_missing_constructor_elt):
...this.
(fold_using_range::range_from_readonly_var): Collect the component
path from the aggregate out; walk it with ctor_ref_range.
2026-10-01 Richard Biener <rguenther@suse.de>
* fold-const-call.cc (fold_const_call_1): Check the
return type rather than the mode for a scalar integral
type before dispatching to fold_const_call_ss and
fold_const_call_sss.
2026-10-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/127686
* tree-vect-loop.cc (vect_analyze_loop_costing): Do not
require a single vector iteration to be profitable iff
the number of scalar iterations is constant.
2026-10-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/127669
* gimple-lower-bitint.cc (bitint_large_huge::lower_bswap_bitreverse):
Set m_var_msb to true.
2026-10-01 Dominic P <gcc@gcc.dp11.uk>
PR tree-optimization/101179
* tree-ssa-forwprop.cc (simplify_phi_result_movdiv): Reset the
flow-sensitive info of the result when its value changes.
2026-09-30 Dominic P <gcc@gcc.dp11.uk>
* tree-vect-patterns.cc (vect_narrow_unprom_to_range): New function.
(vect_widened_op_tree): Use it for external defs.
2026-09-30 Dominic P <gcc@gcc.dp11.uk>
PR tree-optimization/127103
* match.pd (minmax (a - c, b) + c): Also require that a - c
does not overflow.
2026-09-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-builtins-base.def (vsm3ss1q,
vsm3tt1aq, vsm3tt1bq, vsm3tt2aq, vsm3tt2bq, vsm3partw1q,
vsm3partw2q, vsm4eq, vsm4ekeyq): New function declarations.
* config/aarch64/aarch64-neon-builtins-base.cc (vsm3ss1q,
vsm3tt1aq, vsm3tt1bq, vsm3tt2aq, vsm3tt2bq, vsm3partw1q,
vsm3partw2q, vsm4eq, vsm4ekeyq): New function bases:
* config/aarch64/aarch64-simd-builtins.def (sm3ss1q, sm3tt1aq,
sm3tt1bq, sm3tt2aq, sm3tt2bq, sm3partw1q, sm3partw2q, sm4eq,
sm4ekeyq): Delete builtin functions.
* config/aarch64/arm_neon.h (vsm3ss1q_u32,
vsm3tt1aq_u32, vsm3tt1bq_u32, vsm3tt2aq_u32, vsm3tt2bq_u32,
vsm3partw1q_u32, vsm3partw2q_u32, vsm4eq_u32, vsm4ekeyq_u32):
Delete function definitions.
* config/aarch64/aarch64-builtins.cc
(aarch64_types_quadopu_imm_qualifiers, TYPES_QUADOPUI): Delete
now unused array and macro.
2026-09-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-builtins-base.cc: New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsha512hq,
vsha512h2q, vsha512su0q, vsha512su1q): New function
declarations.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions.
* config/aarch64/arm_neon.h (vsha512hq_u64, vsha512h2q_u64,
vsha512su0q_u64, vsha512su1q_u64): Delete functions.
2026-09-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-builtins-base.cc: New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsha256hq,
vsha256h2q, vsha256su0q, vsha256su1q): New function
definitions.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions
* config/aarch64/arm_neon.h (vsha256hq_u32, vsha256h2q_u32,
vsha256su0q_u32, vsha256su1q_u32): Delete functions.
2026-09-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-builtins-base.cc: New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vsha1cq,
vsha1mq, vsha1pq, vsha1h, vsha1su0q, vsha1su1q): New function
declarations.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions.
* config/aarch64/arm_neon.h (vsha1cq_u32, vsha1mq_u32,
vsha1pq_u32, vsha1h_u32, vsha1su0q_u32, vsha1su1q_u32): Delete
function definitions
2026-09-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.cc
(aarch64_general_gimple_fold_builtin): Delete cases for
`crypto_aese` and `crypto_aesd`.
(aarch64_fold_aes_op): Delete now-unused function.
* config/aarch64/aarch64-neon-builtins-base.cc (struct
gimple_exact_insn): New struct.
* config/aarch64/aarch64-neon-builtins-base.def (vaeseq, vaesdq,
vaesmcq, vaesimcq): New function declarations.
* config/aarch64/aarch64-simd-builtins.def: Delete builtin
functions.
* config/aarch64/arm_neon.h (vaeseq_u8, vaesdq_u8, vaesmcq_u8,
vaesimcq_u8): Delete function definitions.
2026-09-30 Paul-Antoine Arras <parras@baylibre.com>
* gimplify.cc (build_omp_iterators_loops): Clear
OMP_CLAUSE_ITERATORS after sorry.
2026-09-30 Luis Silva <luis.silva@globalfoundries.com>
* config/arc/arc.h (arc_cd_to_as): Declare.
(EXTRA_SPEC_FUNCTIONS): Register cd_to_as.
(ASM_SPEC): Call cd_to_as with the CPU name and code-density
markers from -mcode-density/-mno-code-density.
* config/arc/driver-arc.cc (arc_lookup_cpu): New helper.
(arc_cpu_to_as): Drop code-density handling.
(arc_cd_to_as): New spec function; add -mcode-density only when
appropriate, and omit it for -mno-code-density.
2026-09-30 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127654
* tree-ssa-phiopt.cc (factor_out_conditional_operation): Also
allow NEGATE_EXPR and BIT_NOT_EXPR with a constant in some
cases.
2026-09-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/127670
* tree-vect-stmts.cc (vectorizable_shift): Analyze defs
of the shift operand SLP node instead of the scalar stmt
operands for uniformity.
2026-09-30 Uros Bizjak <ubizjak@gmail.com>
PR target/127650
* config/i386/i386.cc (ix86_gimplify_va_arg): Limit type_align
to arg_boundary.
2026-09-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/60075
* tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Do not
use the type of the FIELD_DECL for COMPONENT_REF ops.
* tree-ssa-pre.cc (create_component_ref_by_pieces_1):
Likewise.
2026-09-30 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (cpu_supports_info): Silence a
warning.
2026-09-30 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc (range_from_missing_constructor_part): Return
void.
(range_from_readonly_load): Adjust.
2026-09-29 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa-forwprop.cc (optimize_agr_copyprop_1): Use the index of
the basic block of USE_STMT instead of STMT to purge EH edges.
2026-09-29 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc (range_from_missing_constructor_part): Add
zero for pointers too. Remove assert.
(range_from_readonly_load): Add a null or a non-null range for a
pointer element.
(fold_using_range::range_from_readonly_var): Return the
accumulated range for pointers too, and fail if it is varying.
2026-09-29 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
PR target/126157
* config/arc/arc.cc (prepare_move_operands): Force the address of
an uncached store into a register when it is not a valid store
destination.
* config/arc/arc.md (stdi<mode>): Use move_dest_operand for the
destination operand.
(*stdidi_split): Use non_mod_move_dest_operand for the destination
operand.
* config/arc/predicates.md (non_mod_move_dest_operand): New
predicate that disallows PRE/POST_INC/DEC.
2026-09-29 Jonathan Wakely <jwakely@redhat.com>
* ginclude/stdalign.h (__alignas_is_defined, __alignof_is_defined):
Note that the macros were removed in C23 and C++26.
* ginclude/stdbool.h (__bool_true_false_are_defined): Note that
the macro is obsolescent since C23 and deprecated since C++23.
2026-09-29 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/2827.md: Remove attributes
zEC12_{cracked,expanded,endgroup,groupalone}.
* config/s390/2964.md: Remove attributes
z13_unit_{fpd,fxa,fxb,fxd,lsu,vfu} and
z13_{cracked,expanded,groupalone,endgroup,groupoftwo}.
* config/s390/3906.md: Remove attributes
z14_unit_{fpd,fxa,fxb,fxd,lsu,vfu} and
z14_{cracked,expanded,groupalone,endgroup,groupoftwo}.
* config/s390/3931.md: Remove attributes
z16_unit_{fpd,fxa,fxb,fxd,lsu,vfu} and
z16_{cracked,expanded,groupalone,endgroup,groupoftwo}.
* config/s390/8561.md: Remove attributes
z15_unit_{fpd,fxa,fxb,fxd,lsu,vfu} and
z15_{cracked,expanded,groupalone,endgroup,groupoftwo}.
* config/s390/9175.md: Remove attributes
z17_unit_{fpd,fxa,fxb,fxd,lsu,vfu} and
z17_{cracked,expanded,groupalone,endgroup,groupoftwo}.
* config/s390/s390.cc (enum s390_sched_unit): New enum
describing the units which should be tracked.
(struct s390_sched_insn_descr): New struct describing an
instruction.
(s390_get_sched_attrmask): Removed.
(s390_get_unit_mask): Removed.
(s390_is_fpd): Removed.
(s390_is_fxd): Removed.
(s390_is_longrunning): Removed.
(get_sched_insn_descr): New function returning the pipeline
description for a particular insn.
(s390_sched_score): Use new insn description.
(PRINT_SCHED_ATTR): Remove.
(s390_sched_variable_issue): Use new insn description.
(s390_sched_init_global): New function, set insn description
according to current tune level.
(TARGET_SCHED_INIT_GLOBAL): Corresponding define.
* config/s390/2827.h: New file.
* config/s390/2964.h: New file.
* config/s390/3906.h: New file.
* config/s390/3931.h: New file.
* config/s390/8561.h: New file.
* config/s390/9175.h: New file.
2026-09-29 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* genattr-common.cc (gen_attr): New preprocessor definition
ATTR_ENUM_MNEMONIC_COUNT.
2026-09-29 Richard Biener <rguenther@suse.de>
PR target/127633
* config/i386/sse.md (movsd/movhpd to movupd): Use
widen_memory_access instead of adjust_address to merge
the MEMs.
* config/i386/i386.cc (ix86_operands_ok_for_move_multiple):
Avoid merging loads from different parameters.
2026-09-29 linden <bestxmg@gmail.com>
* ipa-cp.h (ipcp_bits_lattice::set_to_constant)
(ipcp_bits_lattice::meet_with, ipcp_bits_lattice::meet_with_1):
Take widest_int parameters by const reference.
* ipa-cp.cc (ipcp_bits_lattice::set_to_constant)
(ipcp_bits_lattice::meet_with, ipcp_bits_lattice::meet_with_1):
Likewise.
2026-09-29 Alexey Lapshin <alexey.lapshin@espressif.com>
PR target/107549
* config/xtensa/xtensa.cc (xt_true_regnum): Don't index
reg_renumber before LRA starts.
2026-09-29 Juergen Christ <jchrist@linux.ibm.com>
* config/s390/s390.cc (s390_gimple_fold_builtin): New
function.
2026-09-29 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/126891
* config/rs6000/rs6000.md (rs6000_set_fpscr_drn): Change operand
from DImode to SImode and convert it to DImode before use.
2026-09-29 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-09-28 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/127075
* config/riscv/riscv-vector-costs.cc (compute_estimated_lmul):
Rename...
(estimate_lmul): ...To this.
(compute_lmul_from_conversion_ratio): Remove.
(costs::compute_live_ranges_and_lmul): Remove param.
(costs::compute_conversion_dynamic_lmul): Remove.
(costs::has_unexpected_spills_p): Rename...
(costs::has_spills_p): ...To This.
(costs::record_lmul_spills): Adjust comment.
(costs::record_potential_unexpected_spills): Rename...
(costs::record_potential_spills): ...To this.
(costs::compare_lmul_to): New function.
(costs::better_main_loop_than_p): Call new function.
(costs::record_type_sizes): New function.
(costs::add_stmt_cost): Call new function.
(costs::finish_cost): Compute type ratio for LMUL.
* config/riscv/riscv-vector-costs.h: Declare new function.
2026-09-28 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/127553
* config/riscv/riscv-vector-builtins.cc (validate_instance_type_required_extensions):
Add location param for logging.
(expand_builtin): Pass location.
(check_builtin_call): Likewise.
2026-09-28 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/127484
PR target/127547
* config/riscv/riscv.cc (riscv_subpart): Add parameters and
handle more part sizes.
(spill_subreg_move): Allow subreg bytes != 0.
(riscv_split_quadword_move): Use riscv_subpart for TFmode.
* config/riscv/riscv.md (movtf): Add.
2026-09-28 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Fix moptimize link.
* config/nvptx/nvptx.opt.urls: Same.
2026-09-28 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv-vector-costs.cc (get_pattern_var): New
function.
(costs::compute_local_live_ranges): Replace the argument with
the pattern result when necessary.
2026-09-28 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126531
* gimple-range-cache.cc (ranger_cache::apply_inferred_ranges): Do not
update if there are abnormal edges.
2026-09-28 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127203
* gimple-range-cache.cc (ranger_cache::range_from_dom): Mark both
outgoing edges and inferred ranges as "to calculate".
2026-09-28 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/gcn-devices.def: Add gfx1154.
* config/gcn/gcn-tables.opt: Regenerate.
* doc/invoke.texi (-march=): Add gfx1154.
2026-09-28 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR target/126245
* config/riscv/riscv.md (neg<mode>cc): Add an expansion for
conditional negation of integral values.
2026-09-28 Stian Halseth <stian@itx.no>
PR rtl-optimization/127578
* doc/sourcebuild.texi (cbcond_hw): Document.
* ifcvt.cc (find_cond_trap): Reject a sequence that clobbers a
condition-code register live out of TEST_BB.
2026-09-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/118407
* tree-vect-loop.cc (vect_update_early_break_profiles): New.
(scale_profile_for_vect_loop): Use it and pass loop_vinfo.
(vect_transform_loop): Pass loop_vinfo to scale_profile_for_vect_loop.
2026-09-27 Roger Sayle <roger@nextmovesoftware.com>
PR target/127267
* config/iq2000/iq2000.h (SMALL_INT): Fix trivial parenthesis goof.
* config/iq2000/iq2000.cc (iq2000_move_1word): Eliminate useless
IOR with 0x0 operand.
* config/iq2000/iq2000.md (aopsi3): New expander.
(32 bit integer move splitter): Turn low part IOR into a copy when
the constant is zero.
2026-09-27 Dominic P <gcc@gcc.dp11.uk>
PR target/69374
* doc/install.texi (Microsoft Windows): Remove the Windows CE
subsection.
2026-09-27 wangjue <juewang@linux.alibaba.com>
* tree-vect-patterns.cc (vect_sat_trunc_clip_input_vectype): New.
(vect_recog_sat_trunc_pattern): Look through promotions and check
target support for MAX_EXPR.
2026-09-27 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.cc (machopic_select_section): Do not try to
inspect a typename which has no id.
2026-09-27 Samarth Tandale <samarth.tandale@oss.qualcomm.com>
PR tree-optimization/112094
* match.pd: Add fold for (a != 0) | (popcount(a) == n) and
(a == 0) & (popcount(a) != n).
2026-09-27 James K. Lowden <jklowden@cobolworx.com>
* config/avr/avr.opt.urls: Regenerate.
* config/nvptx/nvptx.opt.urls: Regenerate.
2026-09-27 Jeff Law <jeffreyalaw@gmail.com>
PR tree-optimization/126462
* match.pd (reassociate xor to expose rotate patterns): Rewrite using
wi:: interfaces for the xor constant operand.
2026-09-27 Gerald Pfeifer <gerald@pfeifer.com>
PR target/69374
* doc/install.texi (Specific): No longer mention Windows NT on
Alpha and PowerPC.
2026-09-26 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/127618
* fold-const.cc (test_vec_unpack_folding): Update tests
2026-09-26 Tobias Burnus <tburnus@baylibre.com>
* config/nvptx/nvptx.cc (nvptx_encode_section_info): Handle
'omp groupprivate'.
* varpool.cc (varpool_node::get_create): Print sorry for
'omp groupprivate' variables except for device_type(nohost) and
no offloading or nvptx offloading.
2026-09-26 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
PR debug/119940
* dwarf2codeview.cc (codeview_start_source_file): Open the source file
in binary mode.
2026-09-25 Dominic P <gcc@gcc.dp11.uk>
* config/aarch64/aarch64-simd.md
(aarch64_<sra_op>rsra_n<mode>_insn): Take the shift amount in
<V2XWIDE> mode.
(aarch64_<sra_op>rsra_n<mode>): Build the shift amount vector in
that mode.
(aarch64_<sra_op>rshr_n<mode><vczle><vczbe>_insn): Take the shift
amount in <V2XWIDE> mode.
(aarch64_<sra_op>rshr_n<mode>): Build the shift amount vector in
that mode.
2026-09-25 Dominic P <gcc@gcc.dp11.uk>
* config/aarch64/aarch64-simd.md
(*aarch64_<sra_op>rshrn_n<mode>_insn<vczle><vczbe>): New pattern.
(*aarch64_<sra_op>rshrn2_n<mode>_insn_le): Likewise.
(*aarch64_<sra_op>rshrn2_n<mode>_insn_be): Likewise.
2026-09-25 Dominic P <gcc@gcc.dp11.uk>
* config/aarch64/predicates.md (aarch64_simd_umax_half_mode)
(aarch64_simd_umax_quarter_mode): Remove.
* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>)
(*aarch64_sqmovun<mode>_insn<vczle><vczbe>)
(aarch64_sqxtun2<mode>_le, aarch64_sqxtun2<mode>_be)
(aarch64_sqxtun2<mode>)
(*aarch64_sqshrun_n<mode>_insn<vczle><vczbe>)
(aarch64_sqshrun_n<mode>)
(*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>)
(aarch64_sqrshrun_n<mode>, aarch64_sqshrun2_n<mode>_insn_le)
(aarch64_sqshrun2_n<mode>_insn_be, aarch64_sqshrun2_n<mode>)
(aarch64_sqrshrun2_n<mode>_insn_le)
(aarch64_sqrshrun2_n<mode>_insn_be, aarch64_sqrshrun2_n<mode>):
Match an us_truncate of an smax instead of a truncate of an smin
of an smax.
2026-09-25 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
* config/riscv/arcv-rmx100.md (arcv_rmx100_load_insn):
Update latency.
(arcv_rmx100_fpload_insn): Merge with *_load_insn.
2026-09-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/127602
* except.h (struct eh_catch_d): Add chain_next and chain_prev
GTY.
2026-09-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/127602
* except.h (struct eh_region_d): Add chain_next GTY.
2026-09-25 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/127485
* range-op-mixed.h (class operator_minus): Add op1_op2_relation.
* range-op.cc (operator_minus::op1_op2_relation): New.
* gimple-range-fold.cc (fur_source::register_outgoing_edges):
Derive relations from any integral export, not just booleans.
2026-09-25 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/127326
* lra-constraints.cc (process_alt_operands): Resolve the operand
to memory when it is a winning MEM and the value can be held in a
register.
2026-09-25 Tobias Burnus <tburnus@baylibre.com>
PR lto/127589
* lto-streamer-in.cc (lto_input_mode_table): With ACCEL_COMPILER,
check whether found float and int modes are actually enabled/available
at runtime.
2026-09-25 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_binary_operation_1) <SMUL_HIGHPART>:
Add transformations for multiplications by one and powers to two.
<UMUL_HIGHPART>: Likewise.
2026-09-25 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/112465
* config/aarch64/aarch64.cc (aarch64_override_options_after_change_1):
Turn off outline atomics with -mcmodel=large.
* doc/invoke.texi (-mcmodel=large): Update description.
2026-09-25 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
PR target/54412
* except.cc (sjlj_build_landing_pads): Pass ASLK_REDUCE_ALIGN.
* function.cc (assign_stack_local_2): New function, split from
assign_stack_local_1. Honour an explicit alignment beyond
MAX_SUPPORTED_STACK_ALIGNMENT by overallocating the slot and aligning
its address at run time. Optionally return the address before run-time
alignment.
(assign_stack_local_1): Wrap assign_stack_local_2.
(temp_slot): Add base_addr.
(assign_stack_temp_for_type): Distinguish required and preferred
alignment. Record the address before run-time alignment and recalculate
the aligned address when reusing an over-aligned slot. Do not split an
over-aligned BLKmode slot.
(combine_temp_slots): Do not combine over-aligned slots.
(assign_parm_setup_block): Let assign_stack_local align the slot.
* lra-spills.cc (assign_mem_slot): Pass ASLK_REDUCE_ALIGN.
2026-09-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127588
* tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer):
Use an unsigned type to compute the epilog start value.
2026-09-25 Surya Kumari Jangala <jskumari@linux.ibm.com>
PR rtl-optimization/106770
* config/rs6000/rs6000-p8swap.cc (non_permuting_mem_insn): New function.
(handle_non_permuting_mem_insn): New function.
(rs6000_analyze_swaps): Handle swappable instructions only in certain
webs.
(web_requires_special_handling): New instance variable.
(handle_special_swappables): Remove handling of non-permuting load/store
instructions.
2026-09-25 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-valu.md (mul<mode>3): Remove erroneous hi*hi step.
(mul<mode>3_dup): Likewise.
(mul<mode>3_exec): Likewise.
(mul<mode>3_dup_exec): Likewise.
2026-09-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127601
* tree-vect-stmts.cc (get_load_store_type): Move overrun
flags and final handling to the relevant section, after
determining the step direction and the memory access type.
Only elide overrun with half-vector accesses for the
memory access types supporting that. Do not claim
VMAT_STRIDED_SLP can handle overruns when the step is
negative.
(vectorizable_load): For the last memory access type group
analysis/transform assert what memory access type that covers.
2026-09-25 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Fix moptimize link.
2026-09-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127600
* tree-vect-loop.cc (vect_is_simple_iv_evolution): Explicitly
initialize STMT_VINFO_LOOP_PHI_EVOLUTION_TYPE.
(is_nonwrapping_integer_induction): Bail out for alternate
induction types.
2026-09-25 Jakub Jelinek <jakub@redhat.com>
PR middle-end/127517
* internal-fn.cc (expand_mul_overflow): Revert the 2023-09-06
changes. Instead promote arg0 and/or arg1 to a type with
uns{0,1}_p signedness and mode precision if they have non-mode
precision. Pass the original arg0/arg1 and their type to
ubsan_build_overflow_builtin, instead of passing the promoted
ones.
2026-09-25 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt (-moptimize): New target option.
* config/avr/avr.opt.urls: Add resprective URL.
* common/config/avr/avr-common.cc (avr_enable_optimizations): New
static function.
(avr_handle_option) [OPT_moptimize]: Call it.
* doc/invoke.texi (AVR Options) <-moptimize>: Document it.
2026-09-25 Artemiy Volkov <artemiy.volkov@arm.com>
PR tree-optimization/127552
* match.pd: Fix constant comparison in ((X >> C1) & C2) << C3.
2026-09-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR target/127599
* config/aarch64/aarch64.cc (aarch64_evpc_rev64_ext): Move
the testing_p after the is_bb_in_loop test.
2026-09-24 Jakub Jelinek <jakub@redhat.com>
PR c++/126848
* flag-types.h (enum auto_init_type): Change AUTO_INIT_CXX26
value from 3 to 4.
* gimplify.cc (gimplify_decl_expr): Mask off AUTO_INIT_CXX26 bit
before comparing to AUTO_INIT_PATTERN.
(gimplify_target_expr): Likewise.
* internal-fn.cc (expand_DEFERRED_INIT): Likewise. Formatting fix.
* opts.cc (finish_options): For -fhardened or in AUTO_INIT_CXX26
bit from previous value if it was set. Mask off AUTO_INIT_CXX26 bit
before comparing to AUTO_INIT_ZERO.
* tree-ssa-ccp.cc (likely_value): Return VARYING rather than UNDEFINED
for .DEFERRED_INIT call with AUTO_INIT_CXX26 bit set in the second
argument.
* tree-ssa.cc (ssa_undefined_value_p): Return false rather than true
for .DEFERRED_INIT call with AUTO_INIT_CXX26 bit set in the second
argument.
* tree-ssa-uninit.cc (has_undefined_value_p): Return true for
SSA_NAMEs with .DEFERRED_INIT call as SSA_NAME_DEF_STMT.
2026-09-24 Paul-Antoine Arras <parras@baylibre.com>
* tree-pretty-print.cc (dump_omp_iterators): Print OMP_ITERATOR_BLOCK.
2026-09-24 Andrew Stubbs <ams@baylibre.com>
* gdbhooks.py (Rtx): Decode more things.
(RtxPrinter): Improve output.
(build_pretty_printer): Match more rtx types.
2026-09-24 Andrew Stubbs <ams@baylibre.com>
PR target/127542
* config/gcn/gcn-valu.md (<expander><mode>2<exec>): Add
"popcount_extra_op".
2026-09-24 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/127579
* tree-vect-loop.cc (info_for_reduction): Add assert.
* tree-vect-stmts.cc (vectorizable_operation): Pass SLP node.
2026-09-24 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/i386/i386-features.cc
(rest_of_insert_endbr_and_patchable_area):
Reuse an existing ENDBR.
2026-09-24 Uros Bizjak <ubizjak@gmail.com>
* doc/install.texi (Installing GCC): Change node pointer from
Binaries to Specific.
(Specific): Move to directly follow Installing GCC.
Update node pointers accordingly.
(Binaries): Move to follow Specific.
Update node pointers accordingly.
* doc/include/fdl.texi (GNU Free Documentation License): Under
@ifset gfdlhtml, change node pointer from Specific to Binaries
to match install.texi's chapter order.
2026-09-24 Richard Biener <rguenther@suse.de>
PR target/127268
* config/i386/i386.cc (ix86_default_vector_cost): For
integer mode vec_to_scalar add sse_to_integer cost.
2026-09-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/127571
* tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def):
Re-associate offset computation to avoid overflow.
2026-09-24 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-09-23 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/v850/v850.cc (v850_print_oprerand): Handle operands
like (high (const ...)) by stripping the high and falling into
the (const ...) case.
2026-09-23 Vijay Shankar <vijay@linux.ibm.com>
PR target/27479
* config/rs6000/rs6000.md (tprel_ld_<az>_<HSI:mode>): New pattern.
(tprel_ld_QI_signed): likewise.
(tprel_ld_QI): likewise.
(tprel_ld_DI): likewise.
(tprel_ld_<SFDF:mode>): likewise.
2026-09-23 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_load): Cost non-uniform
invariant loads more appropriately.
2026-09-23 Tamar Christina <tamar.christina@arm.com>
* fold-const.cc (const_unop): Fold VEC_UNPACK_LO_EXPR and
VEC_UNPACK_HI_EXPR for suitable variable-length VECTOR_CSTs.
(selftest::test_vec_unpack_folding): New function.
(selftest::fold_const_cc_tests): Call it.
2026-09-23 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.cc (aarch64_ifn_vect_stmt_p): New function.
(aarch64_adjust_stmt_cost): Account for extra Adv.SIMD SAD and ABD
reduction costs.
(aarch64_vector_costs::count_ops): Likewise.
2026-09-23 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.cc (aarch64_vect_vf_for_cost): New
function.
(aarch64_vector_costs::adjust_body_cost): Use it.
(aarch64_vector_costs::better_main_loop_than_p): Likewise.
2026-09-23 Matthias Kretz <m.kretz@gsi.de>
* config/i386/sse.md (roundeven<mode>2): New.
2026-09-22 Chung-Lin Tang <cltang@baylibre.com>
* omp-offload.cc (omp_discover_implicit_declare_target):
For self_maps/unified_shared_memory case, adjust to not convert
'omp declare target local' variables to 'link'.
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_LOCAL.
* tree.cc (omp_clause_num_ops): Add entry for OMP_CLAUSE_LOCAL.
(omp_clause_code_name): Likewise.
* varpool.cc (varpool_node::get_create): Do not add variable to
offload_vars if "local" argument is present in "omp declare target".
2026-09-22 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/127326
* lra-constraints.cc (process_alt_operands): Ignore register if
constraint describes memory and register which can not hold the
mode value.
2026-09-22 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
PR target/114544
* config/i386/constraints.md (YD): New constraint, like Yd but
allows SSE_REGS on TARGET_SSE2.
* config/i386/i386.cc (inline_secondary_memory_needed): Update
that TImode moves to GENERAL_REGS don't need to use memory.
* config/i386/i386.md (*movti_internal): Change Yd constraint to YD.
(define_split): On TARGET_64BIT && TARGET_SSE2 && !TARGET_SSE4_1,
split *movti_internal into movq+shufpd+movq+shufpd.
2026-09-22 Richard Earnshaw <rearnsha@arm.com>
PR target/127393
* config/aarch64/predicates.md (pure_register_operand): New predicate.
* config/aarch64/aarch64.md (negvti3): Use it.
2026-09-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/127492
* builtins.cc (expand_builtin_atomic_fetch_op): Force val into a
pseudo if updates to mem could change its value.
(expand_ifn_atomic_bit_test_and): Likewise.
2026-09-22 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vectorizable_live_operation): Cost
the lane extract in vect_body for BB vectorization and
in vect_epilog for loop vectorization.
2026-09-22 Richard Biener <rguenther@suse.de>
* doc/invoke.texi (fwrapv-pointer): Add disclaimer.
(fno-strict-overflow): Discourage, suggest fwrapv.
2026-09-22 Andrew Stubbs <ams@baylibre.com>
* target.def (base_reg_class): New target hook.
* targhooks.h (default_base_reg_class): Declare.
* targhooks.cc (default_base_reg_class): New function, implementing
the previous BASE_REG_CLASS/MODE_BASE_REG_CLASS/
MODE_BASE_REG_REG_CLASS/MODE_CODE_BASE_REG_CLASS macro fallback
chain as the hook's default.
* addresses.h (base_reg_class): Rewrite to call the
TARGET_BASE_REG_CLASS hook instead of dispatching through
INSN_BASE_REG_CLASS and the other macros by hand; add a MEM
parameter.
* rtl.h (address_info): Add mem field.
* rtlanal.cc (decompose_mem_address): Set it.
* lra-constraints.cc (simplify_operand_subreg, process_alt_operands,
base_to_reg, base_plus_disp_to_reg, process_address_1,
curr_insn_transform): Pass the enclosing MEM, and INSN where
previously omitted, to base_reg_class.
* reload.cc (find_reloads, find_reloads_address,
find_reloads_address_1, find_reloads_subreg_address): Likewise.
* reload1.cc (maybe_fix_stack_asms): Likewise.
* regcprop.cc: Include target.h.
(replace_oldest_value_addr, replace_oldest_value_mem): Pass MEM to
base_reg_class.
* regrename.cc (base_reg_class_for_rename): Add a MEM parameter.
(scan_rtx_address, scan_rtx): Pass it.
* caller-save.cc: Include target.h.
* config/i386/i386.h (INSN_BASE_REG_CLASS): Delete.
* config/i386/i386-protos.h (ix86_insn_base_reg_class): Delete
declaration.
* config/i386/i386.cc (ix86_insn_base_reg_class): Rename to...
(ix86_base_reg_class): ...this, adjust the signature, and implement
TARGET_BASE_REG_CLASS instead of INSN_BASE_REG_CLASS.
(TARGET_BASE_REG_CLASS): Define.
* doc/tm.texi.in: Add TARGET_BASE_REG_CLASS. Mark BASE_REG_CLASS,
MODE_BASE_REG_CLASS, MODE_BASE_REG_REG_CLASS and
MODE_CODE_BASE_REG_CLASS as obsolete in favor of the new hook, and
remove the now-unused INSN_BASE_REG_CLASS.
* doc/tm.texi: Regenerate.
2026-09-22 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/atomics.md (atomic_store<mode>): Use aarch64_reg_or_zero.
2026-09-22 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/126486
* tree-affine.cc: Include vr-values.h.
(aff_combination_convert): Accept and propagate range context.
(expr_to_aff_combination): Likewise. Fold sign-changing conversions
and negative unsigned offsets.
(tree_to_aff_combination): Accept and propagate range context.
* tree-affine.h (aff_combination_convert): Update declaration.
(tree_to_aff_combination): Likewise.
* tree-ssa-loop-ivopts.cc: Include gimple-range.h.
(get_computation_aff_1): Pass the use statement.
(tree_ssa_iv_optimize): Enable ranger.
2026-09-22 liuhongt <hongtao.liu@intel.com>
PR target/127500
* config/i386/i386.cc (ix86_split_stlf_stall_load): Don't split
the load when the address adjusted by 8 is not a valid memory
address.
2026-09-22 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/112626
* match.pd: Fold comparisons between abs (x) and x including
unsigned conversions of both operands.
2026-09-22 Pan Li <pan2.li@intel.com>
PR target/127269
* config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return
false instead of assertion when the nregs of the dest is less
than that of the src.
2026-09-22 Pan Li <pan2.li@intel.com>
* config/riscv/constraints.md (Wn4): New constraint for the
vector register which doesn't overlap the register group of
the operand 4.
* config/riscv/vector.md: Take the Wn4 constraint for the
operand 3 and the Wvr constraint for the operand 4 of the
vfwadd.wv.
2026-09-21 Eric Botcazou <ebotcazou@adacore.com>
* config/riscv/riscv.cc (riscv_flatten_aggregate_field) <ARRAY_TYPE>:
Perform the computation of the number of elements using the precision
of the index type instead of using HOST_WIDE_INT.
2026-09-21 Eric Botcazou <ebotcazou@adacore.com>
* tree-loop-distribution.cc (loop_distribution::classify_partition):
Disqualify the partition for builtins it it contains nonaddressable
data references.
2026-09-21 Eric Botcazou <ebotcazou@adacore.com>
* dwarf2out.h (struct array_descr_info): Add reverse_storage_order.
* dwarf2out.cc (gen_descr_array_type_die): Pass it in the call to
add_type_attribute instead of using TYPE_REVERSE_STORAGE_ORDER.
2026-09-21 Ancheng.Qiao <ancheng.qiao@corelabtech.com>
* config/riscv/riscv.cc (riscv_expand_prologue): Fold into the
cm.push reserve only as many callee-saved FPRs as it can hold by
dividing the additional reserve by UNITS_PER_FP_REG.
(riscv_expand_epilogue): Likewise.
2026-09-21 Matt Turner <mattst88@gmail.com>
PR middle-end/66462
* builtins.cc (fold_builtin_fpclassify): Expand using the
classification built-ins when their optabs are available.
2026-09-21 Matt Turner <mattst88@gmail.com>
PR middle-end/66462
* config/aarch64/aarch64.md (cmp_swp_<shift>_reg<mode>): Add a
parameterized name.
(isinf<mode>2): Use GPF_HF_BF and handle the 16-bit formats.
(isfinite<mode>2): Likewise.
(isnan<mode>2): Likewise.
2026-09-21 Matt Turner <mattst88@gmail.com>
PR middle-end/66462
* config/aarch64/aarch64.md (isnormal<mode>2): Add new expander.
* config/aarch64/iterators.md (GPF_HF_BF): New mode iterator.
(mantissa_bits): Add HF and BF.
(V_INT_EQUIV): Add BF.
2026-09-21 Matt Turner <mattst88@gmail.com>
* config/aarch64/aarch64.md (*extend<SHORT:mode><GPI:mode>2_aarch64):
Guard the smov alternative with base_simd rather than fp.
(*zero_extend<SHORT:mode><GPI:mode>2_aarch64): Likewise for umov.
2026-09-21 Matt Turner <mattst88@gmail.com>
PR middle-end/66462
* config/alpha/alpha-protos.h (enum alpha_fp_class): New.
(alpha_expand_fp_classify): Declare.
* config/alpha/alpha.cc (alpha_expand_fp_classify): New function.
* config/alpha/alpha.md (isfinite<mode>2, isinf<mode>2)
(isnan<mode>2, isnormal<mode>2): New expanders.
2026-09-21 Richard Biener <rguenther@suse.de>
Claude Opus 5 <noreply@anthropic.com>
PR tree-optimization/113703
PR tree-optimization/127515
* tree-ssa-loop-ivopts.cc (iv_elimination_compare_lt): Also record
A + 1 when matching the number of iterations. Convert it to OFF_TYPE
as a whole, compute B + 1 in OFF_TYPE and require both to be
non-negative scaled offsets that do not overflow. Build the bound
out of them instead of A and B.
2026-09-21 Alfie Richards <alfie.richards@arm.com>
PR target/127494
* config/riscv/riscv-v.cc (autovectorize_vector_modes):
Restore previous behaviour.
2026-09-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/127475
* tree-vect-loop.cc (vectorizable_induction): Use
signed_or_unsigned_type_for to get the step vectype.
2026-09-21 Richard Biener <rguenther@suse.de>
PR ipa/127479
* lto-streamer-out.cc (output_cfg): Output predecessor edges.
* lto-streamer-in.cc (input_cfg): Input predecessor edges.
2026-09-21 Josef Melcr <josef.melcr@suse.com>
PR ipa/127104
* internal-fn.def (ASSUME): Downgrade from const to pure.
2026-09-21 Kyrylo Tkachov <ktkachov@nvidia.com>
* genextract.cc (locstr): Make it a string of bytes.
(UPPER_OFFSET, MISSING_OPERAND_CHAR): Remove.
(ENCODE_PATH_STEP, MISSING_OPERAND_STEP, MAX_PATH_INDEX): New macros.
(accum_extract::pathstr): Hold bytes.
(push_pathstr_operand): Encode the step as a number and check that
the index fits.
(VEC_safe_set_locstr, VEC_char_to_string, add_path, gen_insn): Update
for the byte paths.
(print_string_literal): Remove.
(print_extractions): Emit the paths as an array of numbers and walk
them without the character ranges.
2026-09-21 Christophe Lyon <christophe.lyon@arm.com>
* configure.ac: Replace 'ret' with '$insn'.
* configure: Regenerate.
2026-09-21 Uros Bizjak <ubizjak@gmail.com>
PR target/127461
* config/i386/mmx.md (negv2qi2): Use optimize_size instead of
optimize_function_for_size_p (cfun) in the enabled attribute.
(<plusminus:insn>v2qi3): Ditto.
2026-09-21 Artemiy Volkov <artemiy.volkov@arm.com>
* match.pd: New rule to fold ((X >> C1) & C2) << C3.
2026-09-21 Jakub Jelinek <jakub@redhat.com>
PR target/127498
* config/i386/sse.md (<insn><mode>3 any_rotate:VI1_AVX512_3264): Add
TARGET_AVX2 to condition.
2026-09-21 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127445
* function.cc (gen_call_used_regs_seq): Return whether a zeroing
sequence was emitted. Do not update the exit block uses here.
(pass_zero_call_used_regs::execute): Call
df_update_entry_exit_and_calls once when a sequence was emitted.
2026-09-21 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/98984
* match.pd: Fold integer-float-integer conversions when the
intermediate floating-point significand covers the final integer
precision under -fno-trapping-math.
2026-09-20 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.cc (alpha_expand_movmisalign): Derive the
access size from MODE rather than assuming 8 bytes.
* config/alpha/alpha.md (MISALIGN): New mode iterator.
(movmisalign<mode>): Use it in place of VEC.
2026-09-20 Samarth Tandale <samarth.tandale@oss.qualcomm.com>
PR tree-optimization/125700
* match.pd: Fold type-bound guarded min/max expressions.
2026-09-20 Iain Sandoe <iain@sandoe.co.uk>
* common/config/i386/cpuinfo.h (darwin_get_kernel_bool): New.
(get_available_features): Query kernel for avx512 availability
on Darwin.
2026-09-20 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127423
* ifcvt.cc (noce_get_alt_condition): Ignore debug instructions when
checking whether if_info->x is mentioned in the interval.
2026-09-20 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* tree-ssa-math-opts.cc (build_long_mul_partial_operand): New
function.
(build_long_mul_partials): Use it.
2026-09-20 Philipp Tomsich <philipp.tomsich@vrull.eu>
Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/127042
* tree-ssa-math-opts.cc (build_long_mul_partials): Emit zero
high-half partial products, and skip the high-half split and
the low-half mask, for an operand that provably fits the half
width.
2026-09-20 Dominic P <gcc@gcc.dp11.uk>
* gimple-fold.h (gimple_needing_rewrite_undefined): Add a
SHIFT_COUNT parameter defaulting to false.
* gimple-fold.cc (gimple_needing_rewrite_undefined): Return true
for a shift or rotate whose count may be out of range, only when
SHIFT_COUNT.
(rewrite_to_defined_unconditional): Reduce such a count into range.
* tree-ssa-loop-im.cc (shift_needs_mask_p): New function.
(determine_max_movement): Cost a shift whose count would need
masking as cheap.
(movement_possibility_1): Require preserved execution for a
possibly out-of-range count only when the rewrite cannot reduce it
or the loop is optimized for size.
2026-09-20 Filip Kastl <fkastl@suse.cz>
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests):
State that the bit test algorithm is optimal.
2026-09-20 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (`((VCE (a cmp b ? -1 : 0)) < 0) ? c : d`): Remove
`(a cmp b)` match part.
2026-09-20 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (`CMP * a`): Use tcc_comparison directly.
(`(type)CMP * a`): Likewise.
2026-09-20 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (maybe_cmp): Use tcc_comparison directly instead
of for loop.
2026-09-20 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/126412
* fold-mem-offsets.cc (change_in_vec_p): Move before fold_groups.
(changes_map_t): New type.
(class fold_groups): New class.
(struct regno_changes): Remove.
(sort_pairs): Likewise.
(cancel_changes_for_group): Take the fold group to cancel.
(find_groups_to_cancel): Rename from find_keys_to_remove.
(update_insns): Group the changes by fold group instead of by the
register defined by the last fold insn of the def-chain.
(fold_mem_offsets_1): Use fold_groups and commit all groups in a
single change_insns call.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_narrow_clip): Add the complement
form.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (signed_integer_sat_trunc): Add the constant-clamp
form.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (integer_constant_clamp): New match.
(unsigned_integer_narrow_clip): Add the constant-clamp form.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (signed_integer_sat_val): Recognize an arithmetic
sign shift.
(signed_integer_sat_trunc): Use signed_integer_sat_val in the existing
form. Recognize a shifted value with an equivalent pre-shift sign
source.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_add): Accept a compare
against MAX - 1 in the widened form.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (signed_integer_sat_add): Add the two sided
clamp on a wider intermediate, in both nesting orders.
(signed_integer_sat_sub): Likewise.
* tree-ssa-math-opts.cc (match_unsigned_saturation_sub): Rename
to ...
(match_saturation_sub_with_assign): ... this, and ask the signed
predicate as well.
(math_opts_dom_walker::after_dom_children): Update the callers,
and call it for NOP_EXPR.
2026-09-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (signed_integer_sat_trunc): Allow a wider lossless
unsigned range type. Continue to require a narrowing result. Construct
the expected constants at the range precision.
2026-09-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR middle-end/127474
* expmed.cc (expand_mult): Look through vector mode.
2026-09-19 Jørgen Kvalsvik <j@lambda.is>
* gcov.cc (add_path_counts): Read the right field paths.size.
(function_summary): Add missing else.
2026-09-19 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127053
* tree-ssa-phiopt.cc (trailing_store_in_bb): Rename vphi to
vuse_only.
(cond_if_else_store_replacement_limited): Add case if
cond_if_else_store_replacement_1 failed, allowing
for skipping one store on each side.
(trailing_store_in_bb): Require the store stmt
to be a gimple simple assign.
2026-09-19 Yongqiang Tian <yqtian668@gmail.com>
PR target/127460
* config/pru/pru.cc (pru_insert_loop_label_last): Ignore debug
instructions while counting final loop opcodes.
2026-09-19 panciyan <panciyan@eswincomputing.com>
* function.cc (assign_parm_find_stack_rtl): When data->partial is
nonzero, limit the stack slot alignment to the largest power of
two dividing the partial size.
2026-09-19 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
PR target/127374
* config/riscv/iterators.md (leu): Map gt to le
* config/riscv/zicond.md: Add define_split patterns
2026-09-19 Dominic P <gcc@gcc.dp11.uk>
* postreload.cc (reload_cse_regs_1): Find the condition of the
predecessor's conditional branch with get_condition, so a comparison
held in the condition-code register is seen. Reject a jump whose
target is not a label. Record the implicit set only where the block
sets the register to that value.
2026-09-19 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
PR target/126074
* config/riscv/riscv.cc (riscv_build_integer_1): Add logic to
synthesize constants using shNadd.uw.
(riscv_move_integer): Handle FMA with use_uw for RTL emission.
2026-09-18 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125945
* tree-ssa-phiopt.cc (induction_based): New function.
(factor_out_conditional_load): Allow some factoring out
with early and/or before_vect.
(factor_out_all): Set before_vect to false when not vectorizing.
(pass_phiopt::execute): Initialize scev in some cases.
2026-09-18 Michiel Derhaeg <michiel@derhaeg.be>
* config/riscv/riscv.cc (synthesize_add): Do not form shNadd
when the base register is a virtual register.
2026-09-18 Zhongyao Chen <chenzhongyao.hit@gmail.com>
PR rtl-optimization/127367
* ext-dce.cc: Include regs.h.
(ext_dce_process_uses): Handle multi-register hard regs.
2026-09-18 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p):
Compare VLA costs under -mrvv-max-lmul=dynamic.
2026-09-18 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): Add new builtins.
(aarch64_init_atomic_hints_builtins): Likewise.
(aarch64_expand_atomic_hints_builtins_fetch): Handle Fetch intrinsics.
(aarch64_general_expand_builtin): Add call for new builtins.
(aarch64_resolve_overloaded_builtin_atomic_hint_fetch): Handle Fetch intrinsics.
(aarch64_resolve_overloaded_builtin_general): Add new call.
* config/aarch64/arm_acle.h
(enum atomic_fetch): Store different Fetch types.
(__arm_atomic_fetch_add_with_hint): Add new builtin.
(__arm_atomic_fetch_sub_with_hint): Likewise.
(__arm_atomic_fetch_and_with_hint): Likewise.
(__arm_atomic_fetch_xor_with_hint): Likewise.
(__arm_atomic_fetch_or_with_hint): Likewise.
* config/aarch64/atomics.md
(aarch64_atomic_fetch_<atomic_ldoptab><mode>_atomic_hint): New pattern for atomic_fetch.
(@aarch64_atomic_hints_fetch<mode>): Likewise.
* config/aarch64/iterators.md: New unspecs.
2026-09-18 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): Change Function/Builtin names.
(aarch64_init_pcdphint_builtins): Likewise.
(aarch64_init_atomic_hints_builtins): Likewise.
(aarch64_general_init_builtins): Likewise.
(aarch64_expand_stshh_builtin): Likewise.
(aarch64_expand_atomic_hints_builtins): Likewise.
(aarch64_general_expand_builtin): Likewise.
(aarch64_resolve_overloaded_builtin_stshh): Likewise.
(aarch64_resolve_overloaded_builtin_atomic_hint_store): Likewise
(aarch64_resolve_overloaded_builtin_general): Likewise.
* config/aarch64/arm_acle.h
(__atomic_store_with_stshh): Likewise.
(__arm_atomic_store_with_hint): Likewise.
* config/aarch64/atomics.md
(@aarch64_atomic_store_stshh<mode>): Add new hints to pattern
(@aarch64_atomic_hints_store<mode>): Likewise.
* config/aarch64/iterators.md: Add Unspec for new hints.
2026-09-18 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree): Assert successful
discovered nodes do not require splitting.
2026-09-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/127473
* tree-vect-slp.cc (vect_build_slp_tree_3): Duplicate the BB
case of rejecting a not grouped load early to avoid assiging
the first_match to it.
2026-09-18 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-valu.md (mov<mode>_exec): Add xnack alternatives.
(@mov<mode>_sgprbase): Likewise.
2026-09-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/127468
* tree-vect-slp.cc (vect_build_slp_tree_3): Print the correct
trapping stmt.
2026-09-18 Léo Hardt <leom.hardt@inf.ufrgs.br>
* asan.cc: Remove include that already came from ssa.h.
* gimple-ssa-pta-constraints.cc: Remove unused include.
* tree-ssa-loop-unswitch.cc: Likewise.
* ubsan.cc: Change an include to a more specific file.
* value-query.cc: Remove unused import.
* value-range-storage.cc: Likewise.
* value-range.cc: Change an include to a more specific file.
2026-09-18 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/127406
* match.pd: Restrict (X {+,-} M*N) / N optimization.
2026-09-18 Alfie Richards <alfie.richards@arm.com>
* machmode.h (parse_machine_mode): New function.
* read-rtl.cc (find_mode): Use parse_machine_mode.
* config/riscv/riscv-v.cc (autovectorize_vector_modes): Likewise.
2026-09-18 Jakub Jelinek <jakub@redhat.com>
Manjunath Matti <mmatti@linux.ibm.com>
PR middle-end/127378
* gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt): On
big endian, compare idx_next in separate_ext loop against
bo_idx + total - 1 - end, and if that wraps around, compare idx
against 0 instead.
2026-09-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/126306
* tree-vect-slp.cc (vect_build_slp_tree_1): Remove soft-failing.
(vect_build_slp_tree_2): Add soft-failing here, delayed
to after vect_get_and_check_slp_defs.
(vect_get_and_check_slp_defs): When we'll soft-fail do not
fall back to vect_external_def on mismatches.
2026-09-18 Pan Li <pan2.li@intel.com>
* config/riscv/constraints.md (Wn3): New constraint for the
vector register which doesn't overlap the register group of
the operand 3.
* config/riscv/riscv-protos.h (riscv_v_widen_non_overlap_constraint_ok):
New function declaration.
* config/riscv/riscv-v.cc (riscv_v_reg_group_overlap_p): New
function to tell if two vector register groups overlap.
(riscv_v_widen_constraint_ok): Leverage the above function for
the register group overlap check.
(riscv_v_widen_non_overlap_constraint_ok): New function to tell
if the register doesn't overlap the reference register group.
* config/riscv/vector.md: Take the Wn3 constraint for the
operand 4 of the widening integer reduction.
2026-09-18 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127421
* reorg.cc (redundant_insn): Use NONDEBUG_INSN_P in both bounded
backward walks. Remove redundant debug-instruction checks.
2026-09-18 Yongqiang Tian <yqtian668@gmail.com>
PR rtl-optimization/127422
* combine.cc (can_combine_p): Ignore debug instructions when scanning
for intervening volatile references.
2026-09-18 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md (bitreverseqi2): Disable on
LA32R.
2026-09-17 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::query): Prefer a normal
relation over a partial equivalency.
(path_oracle::record): Do not record partial equivalences, nor
intersect one with the relation being recorded.
2026-09-17 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::record): Do not record
VREL_UNDEFINED.
(dom_oracle::search_and_merge_relation): Likewise.
(path_oracle::record): Likewise.
2026-09-17 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (rr_negate_table): Fill PE slots.
(rr_swap_table): Likewise.
(rr_intersect_table): Likewise.
(rr_union_table): Likewise.
(rr_transitive_table): Likewise.
(relation_tests): Also confirm partial equivalency entries.
2026-09-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/127405
* tree-ssa-loop-manip.cc (tree_transform_and_unroll_loop): Only
set nb_iterations_upper_bound of the epilogue loop and scale its
profile when the control IV is known not to wrap.
2026-09-17 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_instance): Pick the
largest isomorphic subset when vectorizing a BB reduction.
2026-09-17 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (match_elt_t): New.
(_slp_tree::failed): Make a match_elt_t *.
* tree-vect-slp.cc (vect_build_slp_tree_3): Make
re-startable at start_i, change representation of
matches[] to match_elt_t[].
(vect_build_slp_tree_1): Iteratively resolve not matched lanes.
Retain isomorphism of BB unrolling failed tail.
(vect_build_slp_tree_2): Adjust for s/bool/match_elt_t/
(vect_build_slp_tree): Likewise.
(optimize_load_redistribution_1): Likewise.
(vect_build_slp_instance): Likewise.
(vect_analyze_slp_reduc_chain): Likewise.
(vect_analyze_slp_reduction): Likewise.
(vect_analyze_slp_reduction_group): Likewise.
(vect_analyze_slp_reductions): Likewise.
(vect_analyze_slp_instance): Likewise.
(vect_lower_load_permutations): Likewise.
2026-09-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/127407
* tree-vect-data-refs.cc (vect_analyze_data_ref_dependence):
Also call vect_preserves_scalar_order_p for negative dependence
distance.
2026-09-17 Uros Bizjak <ubizjak@gmail.com>
* config.gcc (i[34567]86-*-* | x86_64-*-*): Set
default_md_generator_partitions target default to 6:6:1.
2026-09-17 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn.cc (gcn_spill_class): Spill scalars in VGPRs to
SCALAR_SPILL_REGS.
(gcn_memory_move_cost): Handle SCALAR_SPILL_REGS.
* config/gcn/gcn.h (enum reg_class): Add SCALAR_SPILL_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
2026-09-17 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
PR target/127191
* config/arc/arc.md (doloop_end): Clobber CC.
(loop_end): Likewise.
(dbnz): Likewise.
(flag): Likewise.
(kflag): Likewise.
2026-09-17 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
* config/arc/arc.cc (arc_init_reg_tables): Set the mode class of
CC_Vmode to C_MODE.
2026-09-17 Michiel Derhaeg <michiel.derhaeg@globalfoundries.com>
PR target/126243
* config/arc/simdext.md (<voptab>v2si3): Require TARGET_PLUS_QMACW.
2026-09-17 Claudiu Zissulescu <claziss@gmail.com>
* config/arc/arc.md: Remove the "cond" attribute definition, all
its uses and the comments describing it.
* config/arc/fpu.md: Likewise.
* config/arc/fpx.md: Likewise.
* config/arc/simdext.md: Likewise.
2026-09-17 Longjun Luo <luolongjuna@gmail.com>
PR lto/126841
* doc/invoke.texi (-ffunction-sections): Document implicit function
section names under LTO.
* ipa-strub.cc (pass_ipa_strub::execute): Let cfgexpand resolve the
GIMPLE wrapper section.
* symtab-thunks.cc (expand_thunk): Likewise for generic GIMPLE thunks.
Clarify the direct-assembler case.
2026-09-17 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127103
* match.pd (`minmax (a - c, b) + c`): New pattern.
2026-09-17 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127103
* match.pd (`x+umax(x,1)`): New pattern.
2026-09-17 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/126174
* doc/gm2.texi (Using GNU Modula-2): Move Unbounded by reference after
Exception handling in the menu.
2026-09-16 Kyrylo Tkachov <ktkachov@nvidia.com>
* lto-wrapper.cc (run_gcc): Make saved parallel LTRANS outputs phony.
2026-09-16 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
* ipa-inline.cc (report_inline_failed_reason): Check for NULL
before calling cl_target_option_print_diff.
2026-09-16 Léo Hardt <leom.hardt@inf.ufrgs.br>
* asan.cc: Remove duplicate stringpool includes.
* builtins.cc: Likewise.
* calls.cc: Likewise.
* cgraphunit.cc: Likewise.
* dwarf2out.cc: Likewise.
* fold-const.cc: Likewise.
* function.cc: Likewise.
* gimple-expr.cc: Likewise.
* internal-fn.cc: Likewise.
* ipa.cc: Likewise.
* lto-cgraph.cc: Likewise.
* pointer-query.cc: Likewise.
* tree-streamer-in.cc: Likewise.
* varasm.cc: Likewise.
2026-09-16 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_conversion): Prevent
conversions from non-mode-precision _BitInt.
2026-09-16 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-sve-builtins-sme.def (DEF_SME_FUNCTION_GS): Undef
at end.
2026-09-16 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* ira-lives.cc (single_reg_class): Compute regno in case of
single reg class constraint or hard register constraint, and
rename to ...
(single_reg_class_regno): ... this.
(single_reg_operand_class): Similarly as before and rename
to ...
(single_reg_operand_class_regno): ... this.
(process_single_reg_class_operands): Utilize
single_reg_operand_class_regno() and deal with regnos directly
instead of single reg classes.
(process_single_reg_class_operands): Rename to ...
(process_single_reg_constrained_operands): ... this.
(process_bb_node_lives): Refer to renamed function.
2026-09-15 Gerald Pfeifer <gerald@pfeifer.com>
* doc/libgdiagnostics/topics/sarif.rst: Update SARIF website URL.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_valid_move):
Remove code that rejects non-register sources when the destination
is the stack pointer.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h
(GP_REG_NUM, BR_REG_NUM, FP_REG_NUM, ACC_REG_NUM): Remove.
(GP_REG_P, BR_REG_P, FP_REG_P, ACC_REG_P):
Change to use the IN_RANGE() macro.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h (xt_true_regnum): Remove.
* config/xtensa/xtensa.cc (xt_true_regnum):
Specify as a static function.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h (xtensa_regno_to_class):
Remove.
* config/xtensa/xtensa.h (xtensa_regno_to_class):
Declaration of a new global array.
(REGNO_REG_CLASS):
Change to reference the xtensa_regno_to_class array.
* config/xtensa/xtensa.cc (xtensa_regno_to_class):
Remove the original function definition and define it as a new global
array.
(xtensa_conditional_register_usage):
Append code to the end that records a map in xtensa_regno_to_class
showing which of the current regclass definitions each hardware
register belongs to.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_adjust_reg_alloc_order):
Reformat the "reg_call0_alloc_order" array.
* config/xtensa/xtensa.h (REG_ALLOC_ORDER): Reformat.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_conditional_register_usage):
Clear the bit corresponding to the A0 register from the
HARD_REG_SET associated with RL_REGS, if TARGET_WINDOWED_ABI
is enabled.
2026-09-15 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h (EPILOGUE_USES): Remove.
* config/xtensa/xtensa.md (return):
Resurrect '(use (reg:SI A0_REG))' to the template description.
(sibcall_epilogue): Revive emitting '(use (reg:SI A0_REG))'.
2026-09-15 Jørgen Kvalsvik <j@lambda.is>
PR gcov-profile/127408
* gcov.cc (function_summary): Check calls_suppressed, not calls.
2026-09-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/127390
* tree-vect-stmts.cc (vectorizable_comparison_1): Reject
bit-precision integer comparisons.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* Makefile.in (NUM_INSNRECOG_SPLITS): New variable.
(INSNRECOG_SPLITS_SEQ): Use it.
(NUM_INSNATTRTAB_SPLITS): New variable.
(INSNATTRTAB_SPLITS_SEQ): Use it.
(MOSTLYCLEANFILES): Remove all numbered generator sources.
(s-tmp-emit, s-tmp-recog): Stop when an output move fails.
(s-tmp-emit, s-tmp-recog, s-attrtab): Depend on Makefile.
* config.gcc (default_md_generator_partitions): New variable.
Document its scalar and tuple forms.
(aarch64*-*-*): Set the target default.
* configure.ac (--with-md-generator-partitions): New option.
(--with-insnemit-partitions): Keep as a deprecated alias.
Use the target default when no option is specified. Validate and
substitute all three counts.
* configure: Regenerate.
* doc/install.texi (--with-md-generator-partitions): Document.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* Makefile.in (INSNATTRTAB_SPLITS_SEQ, INSNATTRTAB_SEQ_SRC)
(INSNATTRTAB_SEQ_TMP, INSNATTRTAB_SEQ_O): New variables.
(OBJS): Replace insn-attrtab.o with $(INSNATTRTAB_SEQ_O).
(MOSTLYCLEANFILES): Add $(INSNATTRTAB_SEQ_SRC), retaining the legacy
unnumbered source for cleanup.
(.PRECIOUS): Use $(INSNATTRTAB_SEQ_SRC).
(s-attrtab): Generate and move numbered attribute files. Stop when a
move fails.
* configure.ac (--with-insnemit-partitions): Document all generators
which use the option.
* configure: Regenerate.
* genattrtab.cc (attr_file_name, attr_file, open_outfile): Remove.
(output_files): New variable.
(dfa_file_name, latency_file_name): Retain output names.
(make_automaton_attrs): Write to the first attribute partition.
(handle_arg): Register repeatable attribute outputs.
(attr_output_size, cmp_attr_output_size): New functions.
(main): Register fixed outputs and use the common output helpers.
Distribute attribute, delay, and length functions, largest first.
* final.cc (length_unit_log): Update comment for partitioned output.
* config/arc/arc-protos.h (regno_clobbered_p): Likewise.
* config/ia64/ia64.cc (bundling): Likewise.
* config/ia64/t-ia64 (insn-attrtab.o-warn): Replace with per-partition
warning variables.
* config/sh/sh.h (code_for_indirect_jump_scratch): Update comment for
partitioned output.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* gensupport.h (generator_output): New structure.
(add_generator_output, open_generator_outputs): Declare.
(close_generator_outputs): Likewise.
(choose_output): Accept generator_output records. Remove the output
index parameter.
* gensupport.cc (add_generator_output): New function.
(open_generator_outputs, close_generator_outputs): Likewise.
(choose_output): Select only partition records. Remove the output index
and disabled round-robin implementation.
(SIZED_BASED_CHUNKS): Remove.
* genemit.cc (output_files): Use generator_output records.
(handle_arg): Register output names.
(main): Use the common open, selection, and close helpers.
* genrecog.cc (print_subroutine_group): Accept generator_output records.
(header_name): Change to a pointer.
(header): Remove global variable.
(output_files): Use generator_output records.
(handle_arg): Register output names and validate -H.
(main): Validate and register the header output. Use the common open,
selection, and close helpers. Remove an unused output selection.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* genattrtab.cc (attr_value): Add enum_index.
(attr_desc): Add num_values, derived_from and derived_table.
(get_attr_value, add_attr_value, find_attr): Maintain them.
(attr_value_index, eq_attr_value_set, simple_enum_attr_p)
(sole_tested_attr, find_derived_attrs, write_derived_attr_get): New
functions.
(write_attr_get): Use write_derived_attr_get where it applies.
(main): Call find_derived_attrs before optimize_attrs.
2026-09-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/126760
PR tree-optimization/127391
* tree-if-conv.cc (if_convertible_stmt_p): Delay switch
validation to ...
(if_convertible_loop_p_1): ... the loop iterating over
PHIs.
2026-09-15 Jakub Jelinek <jakub@redhat.com>
PR target/127352
* config/i386/i386-expand.cc (split_double_mode): For high halves of
paradoxical subregs after RA use CONST0_RTX (half_mode) instead of
ICE.
2026-09-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/113703
* tree-ssa-loop-ivopts.cc: Include gimple-range.h.
(nonneg_scaled_offset_p): New function.
(iv_elimination_compare_lt): Add USE and BOUND_P parameters. Bail
out if the exit test does not come after the increment of the
candidate, if the comparison in the number of iterations is signed
or if the offsets are not known to be non-negative and to not
overflow. Recompute the bound and store it in BOUND_P.
(may_eliminate_iv): Adjust the call to iv_elimination_compare_lt
and move the expensiveness check on the bound after it.
2026-09-15 Tamar Christina <tamar.christina@arm.com>
PR target/126629
* config/aarch64/aarch64-sve-builtins-base.cc
(emit_ldf1_ffr_update): New.
(svldff1_gather_impl, svldff1_gather_extend, svldxf1_impl,
svldxf1_extend_impl): Use it.
* config/aarch64/aarch64-sve.md (aarch64_update_ffr<mode>): Update insn.
2026-09-15 Haochen Jiang <haochen.jiang@intel.com>
PR target/127264
* config/i386/i386-expand.cc (ix86_expand_ace_builtin):
Revise logic to avoid INTVAL check for non-constant
operands.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/127185
* builtins.cc (expand_builtin_strub_update): Use a separate MEM with
load trap semantics for each watermark load.
(expand_builtin_strub_leave): Use load trap semantics for watermark
MEMs.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/127185
* cfgexpand.cc (expand_asm_stmt): Restore load MEM_NOTRAP for memory
inputs.
* internal-fn.cc: Include tree-eh.h.
(expand_partial_load_optab_fn): Expand the source as memory and
restore load MEM_NOTRAP.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/127185
* builtins.cc (get_memory_rtx): Add STORE_P. Pass it to
set_mem_attributes.
(expand_builtin_memory_copy_args): Mark the destination as a store
and the source as a load.
(expand_movstr): Likewise.
(expand_builtin_strncpy): Mark the destination as a store.
(expand_builtin_memset_args): Likewise.
(expand_builtin_memcmp): Mark both memory operands as loads.
(expand_builtin_strcmp): Likewise.
(expand_builtin_strncmp): Likewise.
(inline_string_cmp): Mark the memory operand as a load.
* builtins.h (get_memory_rtx): Add STORE_P.
* internal-fn.cc (expand_RAWMEMCHR): Mark the memory operand as a
load.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/127185
* emit-rtl.cc (set_mem_attributes_minus_bitpos): Add MAY_STORE_P.
Use lhs_could_trap_p when it is true.
(set_mem_attributes): Add MAY_STORE_P and pass it through.
* emit-rtl.h (set_mem_attributes): Add MAY_STORE_P with a
conservative default.
(set_mem_attributes_minus_bitpos): Likewise.
* expr.cc (expand_assignment): Mark the destination as a store.
(expand_expr_real_1): Treat only EXPAND_NORMAL as a known load.
Set MEM_NOTRAP from the access direction.
2026-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/127184
* gimple.cc (gimple_could_trap_p_1): Check a memory LHS with
lhs_could_trap_p. Do not inspect an LHS as an rvalue.
(test_could_trap): New self-test.
(gimple_cc_tests): Run it.
* tree-eh.cc (stmt_could_throw_p): Check a nothrow call's memory LHS.
2026-09-15 Naveen <naveen.siddegowda@oss.qualcomm.com>
* config/aarch64/aarch64-simd.md: Add define_expand <su>sadv8qi
guarded by TARGET_DOTPROD.
2026-09-15 Hongyu Wang <hongyu.wang@intel.com>
PR target/127177
* config/i386/i386-expand.cc (ix86_fp_cmp_code_to_pcmp_immediate):
Return the _UQ predicate immediates for UNLE, UNLT, UNGE, UNGT and
UNEQ.
* config/i386/i386.cc (ix86_print_operand):Likewise to print the
_uq suffixed AVX predicates for these codes.
* config/i386/predicates.md (ix86_fp_vec_cmp_operator): New
predicate.
* config/i386/sse.md (vec_cmp<mode><sseintvecmodelower>): Use the
new predicate for the VF_128 compare.
* config/i386/mmx.md (vec_cmpv2sfv2si): Likewise.
2026-09-14 Jean-Didier Pailleux <jean-didier.pailleux@sipearl.com>
* config/aarch64/aarch64-sve-builtins-sme.def (REQUIRED_EXTENSIONS): Add
missing #undef.
2026-09-14 Dominic P <gcc@gcc.dp11.uk>
PR tree-optimization/127379
* match.pd (ior_range_test_0): Require an integral type.
2026-09-14 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.h (TARGET_SVE_PREFER_ZEROING_MOVIMM): New
define.
* config/aarch64/aarch64-sve.md (*vcond_mask_<mode><vpred>): Add a
split condition for zero predicate.
* config/aarch64/aarch64-tuning-flags.def: Add AVOID_MOVIMM_Z tune.
* config/aarch64/tuning_models/neoversev1.h (tune_flags): Update.
* config/aarch64/tuning_models/neoversev2.h (tune_flags): Update.
2026-09-14 xiezhiheng <xiezhiheng@huawei.com>
* haifa-sched.cc (max_issue): Cap max_lookahead_tries
2026-09-14 Jakub Jelinek <jakub@redhat.com>
PR middle-end/127336
* optabs.cc (maybe_emit_compare_and_swap_exchange_loop,
expand_atomic_fetch_op_no_fallback, expand_atomic_fetch_op): Force
val into a pseduo if it updates to mem could change its value
and when using val after the atomic op or inside of a loop.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* genemit.cc (main): Choose an output file for each overloaded name.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* rtl.h (note_split): Declare.
* emit-rtl.cc (note_split): New function.
* genemit.cc (gen_split): Call it rather than emitting the test and
the fprintf.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* genrecog.cc (md_conditions, md_condition_ids): New variables.
(md_condition_id, print_md_conditions): New functions.
(print_test): Call a helper for a C test rather than emitting the
condition.
(main): Write the helpers to the header.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* genextract.cc (MISSING_OPERAND_CHAR): New macro.
(pathpool, dupnums): New variables.
(add_path, print_string_literal, print_extractions): New functions.
(print_path): Remove.
(print_header): Only emit the prologue.
(main): Call print_extractions.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_sub): Accept commuted
comparison operand orders and the arm order from a two-return source.
2026-09-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_sub): Add the
X - MIN (X, Y) form.
* tree-ssa-math-opts.cc
(build_saturation_binary_arith_call_and_replace): Return whether a
replacement was made.
(match_saturation_add_with_assign): Likewise.
(match_unsigned_saturation_sub): Likewise.
(math_opts_dom_walker::after_dom_children): Check MINUS_EXPR for
saturation, and use the assign recognizer results.
2026-09-14 Claudio Bantaloukas <claudio.bantaloukas@arm.com>
* config/aarch64/aarch64-acle-builtins.cc:
(function_resolver::resolve_to): Fix documentation comment.
* config/aarch64/aarch64-acle-builtins.h: (TYPES_tmop_base,
TYPES_tmop_h_bfloat, TYPES_tmop_h_float, TYPES_tmop_h_mf8,
TYPES_tmop_s_mf8): Add new DEF_SVE_TYPES_ARRAYs.
* config/aarch64/aarch64-c.cc: (__ARM_FEATURE_SME_TMOP): Add define.
* config/aarch64/aarch64-sme.md:
(@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SVE_FULL_BHI:mode>): Add
new insn.
(@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><VNx16QI_ONLY:mode>):
Likewise.
(@aarch64_sme_lane_<optab><mode><mode>):
Likewise.
(@aarch64_sme_lane_<optab><VNx4SI_ONLY:mode><SVE_FULL_HF:mode>):
Likewise.
(@aarch64_sme_lane_<optab><SME_TMOPA_FP8:mode><VNx16QI_ONLY:mode>):
Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc:
(ternary_za_uint_dual_single): Add new shape.
* config/aarch64/aarch64-sve-builtins-shapes.h: Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc: (svtmopa_lane_za_impl):
Add new function impl class.
(svtmopa_lane_za): Add new FUNCTION.
* config/aarch64/aarch64-sve-builtins-sme.def: (svtmopa_lane): Add new
DEF_SME_ZA_FUNCTION_GS entries.
* config/aarch64/aarch64-sve-builtins-sme.h: (svtmopa_lane_za): Add new.
* config/aarch64/aarch64.h: (TARGET_STREAMING_SME_TMOP): Add new define.
* config/aarch64/constraints.md (Uwo): Add new constraint for Control
Vector Register in TMOP operations.
* config/aarch64/iterators.md: (SME_TMOPA_BHSF, SME_TMOPA_FP8): Add new mode
iterators.
(UNSPEC_SME_FTMOPA, UNSPEC_SME_FTMOPA_FP8, UNSPEC_SME_STMOPA,
UNSPEC_SME_SUTMOPA, UNSPEC_SME_USTMOPA, UNSPEC_SME_UTMOPA): Add new
unspecs.
(SME_TMOP_INT, SME_TMOP_INT_CROSS, SME_TMOP_FP, SME_TMOP_FP8): Add new
iterators.
(za_imm_bits): Add new mode_attr.
(optab): Update with new unspecs.
* config/aarch64/predicates.md: (aarch64_imm1, aarch64_imm4): Add new
predicates.
2026-09-14 Claudio Bantaloukas <claudio.bantaloukas@arm.com>
* config/aarch64/aarch64.md: Rename aarch64_imm3 as aarch64_shift_imm3.
* config/aarch64/aarch64-simd.md: Rename aarch64_lane_imm3 as aarch64_imm3.
* config/aarch64/predicates.md: Rename aarch64_imm3 as aarch64_shift_imm3
and aarch64_lane_imm3 to aarch64_imm3.
2026-09-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/127377
* tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def):
Properly consider the padding before the object when
pruning the size.
2026-09-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/127363
* tree-vect-stmts.cc (vectorizable_assignment): Properly
code-generate PAREN_EXPRs.
2026-09-14 Artemiy Volkov <artemiy.volkov@arm.com>
PR target/126983
* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>):
Split into VS32_I_SUB64_F_CONDFP16 and HFBF variants. Change
uxtw to uxt<extsize>.
(*aarch64_combinez_be<mode>): Likewise.
* config/aarch64/iterators.md (VSSUB64_F): Remove iterator.
(VS32_I_SUB64_F): Amend by explicitly listing all modes.
(VS32_I_SUB64_F_CONDFP16): New iterator.
2026-09-14 Rohith Kapelli <kapellirohith@gmail.com>
PR ipa/123227
* ipa-icf.cc (sem_function::equals_wpa): Compare TYPE_ATTRIBUTES
as a list rather than through comp_type_attributes. Reject a
METHOD_TYPE compared against a FUNCTION_TYPE.
2026-09-13 Dominic P <gcc@gcc.dp11.uk>
* generic-match-head.cc (gimple_match_no_overflow_p): New.
* gimple-match-head.cc (gimple_match_no_overflow_p): New.
* match.pd (Y + MIN (X - Y, 0), X - MIN (X - Y, 0), Y + MAX (X - Y, 0),
X - MAX (X - Y, 0), MIN (X + Y, Y) - Y, MAX (X + Y, Y) - Y): New
patterns.
2026-09-13 Dominic P <gcc@gcc.dp11.uk>
* match.pd (A - MIN (B, C), A - MAX (B, C)): New patterns.
2026-09-13 Jeff Law <jeffreyalaw@gmail.com>
Sun Yuechi <sunyuechi@iscas.ac.cn
* config/riscv/riscv-bclr-lowest-set-bit.cc
(pass_bclr_lowest_set_bit::execute): Do not handle addiw forms.
2026-09-13 Dominic P <gcc@gcc.dp11.uk>
* match.pd (ior_range_test, ior_range_test_1, ior_range_test_0):
New matchers.
(((X + C1) | (C2 - X)) < 0): New simplification.
((unsigned) ((X + C1) | (C2 - X)) >> (prec - 1)): Likewise.
(ABS_EXPR <X> > C): Likewise.
2026-09-13 Michiel Derhaeg <michiel@derhaeg.be>
* config/riscv/bitmanip.md (crc_rev<ANYI1:mode><ANYI:mode>4):
Use the clmul expansion for a word-sized crc on rv32 with Zbc.
* config/riscv/riscv.cc (expand_reversed_crc_using_clmul): Use
clmulr with the unshifted reflected polynomial when the crc is
word-sized.
(riscv_optab_supported_p): Allow crc_rev for a word-sized result
on rv32 with Zbc when optimizing for size.
2026-09-13 Marek Polacek <polacek@redhat.com>
PR c++/125820
PR c++/124249
PR c++/124414
* expr.cc (count_type_elements) <case LANG_TYPE>: Return 1.
* tree.cc (wide_int_to_tree_1) <case LANG_TYPE>: New.
(cache_integer_cst) <case LANG_TYPE>: New.
2026-09-13 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/127318
* config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): Attach
REG_CFA_DEF_CFA note to the copy from the stack pointer.
2026-09-13 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127358
* match.pd (two_value cond): Prefer unsigned types.
2026-09-13 Xi Ruoyao <xry111@xry111.site>
PR target/127153
* config/loongarch/loongarch.md (both_non_zero): Defer the split
post reload and add constraint to ensure operands[0] and
operands[2] are in different hard registers.
(both_non_zero_subreg): Likewise.
2026-09-12 Shivam Gupta <shivam98.tkg@gmail.com>
* tree-ssa-loop-niter.cc (number_of_iterations_cltz): Reject
undefined ranges returned by Ranger.
(number_of_iterations_cltz_complement): Likewise.
2026-09-12 Georg-Johann Lay <avr@gjlay.de>
* common/config/avr/avr-common.cc
(avr_option_optimization_table) [OPT_LEVELS_1_PLUS]: Set
-mdemote-switch.
* config/avr/avr-passes.cc (avr_pass_casesi::gate):
Require avropt_demote_switch to be on.
* config/avr/avr.opt (mdemote-switch): New option.
* config/avr/avr.opt.urls (mdemote-switch): Add UrlSuffix.
* doc/invoke.texi (AVR Options): Document -mdemote-switch.
2026-09-12 Gerald Pfeifer <gerald@pfeifer.com>
PR target/69374
* doc/install.texi (Downloading the source): Drop note on
more finely grained source code archives.
2026-09-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* genoutput.cc (data): Add output_code.
(output_def): New structure.
(output_codes): New variable.
(process_template): Determine the output format before emitting
anything and test that rather than the template. Reuse an identical
definition emitted earlier, recording output_code, and check the
number of alternatives against the count recorded with it.
(output_insn_data): Use output_code.
2026-09-12 Pan Li <pan2.li@intel.com>
PR target/127269
* config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return
false instead of assertion when the nregs of dest and src are
the same but greater than 1.
2026-09-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/127306
* config/riscv/riscv-bclr-lowest-set-bit.cc (find_later_ctz): Fix
off-by-one error for scan to verify ctz input isn't modified.
(pass_bclr_lowest_bit_set::execute): Remove original AND in case
where the CTZ is found after the AND.
2026-09-11 Dominic P <gcc@gcc.dp11.uk>
* tree-vect-stmts.cc (has_consecutive_load_permutation): Remove
the group_size parameter and the requirement that the permutation
length divides the group size. Make static.
(get_load_store_type): Adjust caller.
2026-09-11 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/127244
* lra-constraints.cc (inheritance_pseudo_p): New function.
(undo_optional_reloads): Keep optional reload for output
operand if it is inherited.
2026-09-11 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_slow_unaligned_access):
Return the same as riscv_support_vector_misalignment.
2026-09-11 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR middle-end/127323
* expmed.cc (extract_integral_bit_field): Use store_bit_field if
operand_subword fails.
2026-09-11 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (rr_transitive_table): Update.
2026-09-11 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/riscv-protos.h (riscv_expand_block_clear):
Remove.
(expand_vec_setmem): Add testing param.
(riscv_expand_setmem): Likewise.
* config/riscv/riscv-string.cc (riscv_expand_block_clear_zicboz_zic64b):
Likewise.
(riscv_expand_block_clear): Make static.
(expand_scalar_setmem): New function.
(riscv_expand_setmem): New function.
(expand_vec_setmem): Add testing param.
* config/riscv/riscv.cc (riscv_use_by_pieces_infrastructure_p):
Query riscv_expand_setmem for support.
* config/riscv/riscv.md: Use riscv_expand_setmem.
2026-09-11 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/riscv-protos.h (riscv_expand_block_move):
Declare.
* config/riscv/riscv-string.cc (riscv_block_move_straight):
Handle overlap.
(riscv_block_move_loop): Pass "no overlap" to
riscv_block_move_straight.
(riscv_expand_block_move_scalar): Add overlap param.
(riscv_expand_block_move): Likewise.
(expand_block_move): Likewise.
* config/riscv/riscv.md: Use riscv_expand_block_move.
2026-09-11 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/aarch64/aarch64.cc (aarch64_regmode_natural_size):
Set REGMODE_NATURAL_SIZE to the size of one vector.
2026-09-11 Kyrylo Tkachov <ktkachov@nvidia.com>
* doc/generic.texi (REFERENCE_TYPE): Document the object contract
for reference parameters.
(METHOD_TYPE): Document the object contract for the this parameter.
* tree-eh.cc (parm_decl_from_ptr): New function.
(whole_object_param_size): New function.
(tree_could_trap_1): Use whole-object parameter bounds for loads.
2026-09-11 Manjunath Matti <mmatti@linux.ibm.com>
Jakub Jelinek <jakub@redhat.com>
PR target/117584
* config/rs6000/rs6000-call.cc (rs6000_bitint_large_p): New
function.
(rs6000_return_in_memory): Return large _BitInt values, and enums
backed by _BitInt, via a hidden pointer.
(rs6000_pass_by_reference): Pass large _BitInt values, and enums
backed by _BitInt, by reference.
* config/rs6000/rs6000.cc (TARGET_C_BITINT_TYPE_INFO): Define.
(init_float128_ibm): Set bitinttofp_optab and bitintfromfp_optab
libfuncs to __floatbitinttf and __fixtfbitint.
(init_float128_ieee): Set bitinttofp_optab and bitintfromfp_optab
libfuncs to __floatbitintkf and __fixkfbitint.
(rs6000_function_value): Exclude BITINT_TYPE from sub-word integer
return value promotion.
(rs6000_bitint_type_info): New function.
2026-09-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/127310
* tree-vect-loop.cc (vectorizable_lane_reducing): Apply
costing after registering loop masks.
2026-09-11 Richard Sandiford <rdsandiford@googlemail.com>
PR middle-end/127330
* recog.h (recog_state_saver::recog_state_saver): Initialize
m_tmp_recog_data.insn.
2026-09-11 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadupdate.cc (jt_path_registry::remove_path): New,
and an overload taking the path's first edge.
(jt_path_registry::add_first_edge): New.
(jt_path_registry::drop_first_edge): New.
(jt_path_registry::first_edge_count): New.
(back_jt_path_registry::adjust_one_path): Move the candidate's
count when its first edge changes; remove before cancelling.
(back_jt_path_registry::adjust_paths_after_duplication): Return
early when no other path starts on the same edge.
(fwd_jt_path_registry::mark_threaded_blocks): Use remove_path.
(back_jt_path_registry::update_cfg): Remove the threaded path by
the edge it started on.
(fwd_jt_path_registry::update_cfg): Use remove_path.
(jt_path_registry::register_jump_thread): Count the new first edge.
* tree-ssa-threadupdate.h (jt_path_registry::m_first_edge_counts): New.
(jt_path_registry::remove_path, add_first_edge, drop_first_edge)
(jt_path_registry::first_edge_count): Declare.
2026-09-11 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadupdate.cc (back_jt_path_registry::adjust_one_path):
Fix the dump messages.
2026-09-11 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadupdate.cc (back_jt_path_registry::adjust_one_path):
New, split out of ...
(back_jt_path_registry::adjust_paths_after_duplication): ... here.
* tree-ssa-threadupdate.h (back_jt_path_registry::adjust_one_path):
Declare.
2026-09-11 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-eh.cc (tree_could_trap_1, tree_could_trap_p): Clarify the
function comments.
(lhs_could_trap_p): Correct the function comment.
2026-09-11 Richard Biener <rguenther@suse.de>
* tree-pretty-print.cc (dump_generic_node): Adjust -gimple
dumping for clobbers.
2026-09-11 H.J. Lu <hjl.tools@gmail.com>
PR target/127020
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Add gain of
COSTS_N_INSNS (1) for pand/pior/pxor loads.
2026-09-10 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/127308
* genmatch.cc (operator==): Move earlier.
(c_code_id::gen_checking): Correct the check for CONVERT_EXPR/NOP_EXPR.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/pdp11/pdp11.cc (pdp11_rtx_costs): Move src assignment
into the blocks that need it.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/nds32/nds32-cost.cc (nds32_rtx_costs_speed_prefer): Fix
two places that returned a cost directly so that they now store
the cost in *total and return true.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/mmix/mmix-protos.h (mmix_eh_return_data_regno): Return
unsigned int rather than int.
* config/mmix/mmix.cc (mmix_eh_return_data_regno): Likewise.
(mmix_initial_elimination_offset): Limit regno variables to
their for loops and use unsigned regnos for EH data queries.
(mmix_use_simple_return): Likewise.
(mmix_expand_prologue): Likewise.
(mmix_expand_epilogue): Likewise.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/gcn/gcn.cc (gcn_init_cumulative_args): Start the
inform message with a lowercase letter. Quote the option name.
2026-09-10 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (back_threader_profitability):
Remove the note on bb_insns.
(back_threader_profitability::possibly_profitable_path_p): Dump
each block's insn count.
2026-09-10 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (back_threader_profitability): Add
push_bb, pop_bb, m_loop, unwind_state and m_unwind; add n_insns
to path_stats; replace m_n_insns with a net_insns accessor.
(back_threader_profitability::back_threader_profitability):
Initialize m_loop and m_stats.
(back_threader_profitability::account_bb): Return the number of
insns in the block.
(back_threader_profitability::push_bb): New.
(back_threader_profitability::pop_bb): New.
(back_threader_profitability::possibly_profitable_path_p): Use
the accumulated stats.
(back_threader_profitability::profitable_path_p): Likewise.
(back_threader::find_paths_to_names): Call push_bb/pop_bb.
2026-09-10 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (back_threader_profitability): Add
path_stats and m_stats; move m_threaded_through_latch,
m_multiway_branch_in_path, m_contains_hot_bb and
m_unprofitable_bb into it.
(back_threader_profitability::account_bb): Adjust.
(back_threader_profitability::possibly_profitable_path_p):
Adjust.
(back_threader_profitability::profitable_path_p): Adjust.
2026-09-10 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (back_threader_profitability): Add
account_bb and m_unprofitable_bb.
(back_threader_profitability::account_bb): New.
(back_threader_profitability::possibly_profitable_path_p): Use it.
2026-09-10 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc
(back_threader_profitability::possibly_profitable_path_p): Dump
the path after counting it instead of from within the loop.
2026-09-10 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* config/aarch64/aarch64-json-tunings-parser.cc (test_json_integers): Initialize params.
(test_json_boolean): Likewise.
(test_json_strings): Likewise.
(test_json_enums): Likewise.
2026-09-10 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127052
* tree-ssa-phiopt.cc (cond_store_replacement_limited): Reject clobbers
for the middle bb store. And Remove the check on ssa name for the rhs
of the middle bb store.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* genopinit.cc (struct pattern_info): New.
(patterns): Use it.
(gen_insn): Record the pattern's C test.
(pattern_cmp): Use pattern_info.
(narrowest_uint_type): New function.
(main): Emit a condition-number table and a loop instead of one
assignment per pattern, and drop the split into 1000-pattern
functions.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/rx/rx.cc (rx_gen_move_template): Fix GET_MODE/GET_CODE typo.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/nds32/nds32.cc (nds32_dwarf_register_span): Remove
unused dwarf_single variable.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/lm32/lm32.cc (lm32_builtin_va_start): Remove unused
variable.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* config/c6x/c6x.cc (reorg_split_calls): Remove unused uid
and reservation_mask variables.
(hwloop_optimize): Remove unused delayed_splits variable.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((type) MAX ((wide_type) a - (wide_type) b, 0)): New
simplification.
((type) MIN ((wide_type) a + (wide_type) b, MAX)): Likewise.
2026-09-10 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/predicates.md (insertps_parallel): New predicate.
* config/i386/sse.md (sse4_1_insertps_<mode>_perm): New
define_insn to implement V4SI or V4SF permute using insertps.
(*sse2_insertps_<mode>_perm): Emulate the above insn on SSE2
by splitting to one or two of pslldq, psrldq and pshufd.
2026-09-10 Richard Sandiford <rdsandiford@googlemail.com>
* recog.h (recog_data_d): Delete copy and move constructors.
(recog_data_ptr): New variable.
(recog_data): Turn into a macro.
(recog_data_saver): Rename to...
(recog_state_saver): ...this and move into the !GENERATOR_FILE block.
Save and restore which_alternative. Save and restore recog_data_ptr
rather than doing a full recog_data_d copy.
* varasm.cc (assemble_asm): Explicitly initialize n_dups,
n_alternatives, and is_operator.
* recog.cc (recog_data): Replace with...
(main_recog_data, recog_data_ptr): ...these new variables.
* emit-rtl.cc (address_reload_context::emit_autoinc): Update
after the rename.
* reload.cc (can_reload_into): Use recog_state_saver rather than
manually saving and restoring recog_data.
* config/i386/i386.cc (ix86_memory_address_reg_class): Likewise.
(ix86_lea_outperforms): Likewise.
* config/i386/i386-expand.cc (ix86_vector_duplicate_value): Likewise.
* config/sh/sh.cc (sh_recog_treg_set_expr): Likewise.
(sh_split_treg_set_expr): Likewise.
* config/sh/sh.md: Likewise in two peephole2s.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_add): Recognise comparisons
against the complement of an operand. Also recognise ADD_OVERFLOW
with a separate addition.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* genmatch.cc (case_convert_id_p): New function.
(same_case_p): Likewise.
(operation_has_case_p): Likewise.
(operations_overlap_p): Likewise.
(function_operation_p): Likewise.
(operand_cases_overlap_p): Likewise.
(cmp_operand): Handle conversion cases and function iterators.
(nodes_overlap_p): New function.
(decision_tree::find_node): Do not merge across an overlapping node.
(decision_tree::insert_operand): Assert the recursive lookup result.
(fns_cmp): Remove.
(dt_operand_group): New structure.
(add_operation_cases): New function.
(find_group): Likewise.
(collect_operand_groups): Likewise.
(operation_covers_group_p): Likewise.
(emit_operation_test): Likewise.
(emit_group_labels): Likewise.
(emit_expr_group): Likewise.
(emit_fn_group): Likewise.
(dt_node::gen_kids): Do not sort function nodes.
(dt_node::gen_kids_1): Emit groups with unique case labels.
2026-09-10 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn.md (one_cmpldi2): Use s_not_b64.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc: Spell noce_if_info without the struct keyword throughout.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (count_bb_insns, cheap_bb_rtx_cost_p, first_active_insn,
last_active_insn, find_active_insn_before, find_active_insn_after,
block_fallthru, cond_exec_get_condition, noce_get_condition,
find_if_header, block_jumps_and_fallthru, noce_find_if_block,
noce_emit_move_insn, noce_emit_store_flag, noce_try_move,
noce_try_ifelse_collapse, noce_try_store_flag, noce_try_addcc,
noce_try_store_flag_constants, noce_try_shifted_store_flag,
noce_try_store_flag_mask, noce_try_cmove, noce_try_cmove_arith,
noce_get_alt_condition, noce_try_minmax, noce_try_abs,
noce_try_sign_mask): Remove the unused forward declarations.
(noce_emit_cmove): Likewise, and give the definition the default
arguments.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_can_force_operand): Return a bool rather than an
insn_code.
(noce_emit_cmove): Remove ATTRIBUTE_UNUSED from local variables.
(bbs_ok_for_cmove_arith): Drop braces around single statements.
(noce_find_if_block): Value-initialize if_info instead of memsetting it.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_original_region_cost): New function.
(noce_process_if_block): Use it for the multiple-set and the
single-set estimate. Rename old_cost to base_cost and compute
speed_p once.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (cond_move_process_if_block): Make then_regs and else_regs
auto_vec and return directly instead of jumping to a cleanup label.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_seq_clobbers_cc_cmp_p): New function.
(noce_convert_multiple_sets_1): Use it for both candidate sequences.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (MAX_CONDITIONAL_EXECUTE): Add a comment.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (cond_exec_changed_p): Rename to...
(ifcvt_changed_p): ...this, and correct its comment. Adjust all uses.
(noce_finish_if_conversion): Bump num_updated_if_blocks.
(noce_convert_multiple_sets, noce_process_if_block,
cond_move_process_if_block): Drop the bump the helper now does.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_try_store_flag_logical): Pass 0, not false, for the
normalize argument.
(noce_convert_multiple_sets): Use a range-for over insn_info.
(merge_if_block, cond_exec_find_if_block): Drop the elaborated struct
type.
(block_jumps_and_fallthru): Test the insn pointer directly.
(cond_exec_find_if_block): Drop a redundant last_test_bb store.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_splat_to_const): New function.
(noce_try_sign_bit_splat): Use it for both orientations.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (merge_block_into_combo): New function.
(merge_if_block): Use it for the THEN and the ELSE block.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_representable_diff_p): New function.
(noce_try_store_flag_constants): Use it.
(noce_try_cmove): Likewise.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_reversed_cond): New function.
(noce_reversed_cond_code): Use it.
(noce_try_addcc, noce_try_cmove_arith, noce_try_cond_arith): Likewise.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.h (struct ce_if_block): Make and_and_p a bool.
(struct noce_multiple_sets_info): Correct the unmodified_insn and
need_cmov comments.
(struct noce_if_info): Correct the insn_a/insn_b, speed_p and
original_cost comments.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_process_if_block): Remove a redundant else_bb test.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (IFCVT_MULTIPLE_DUMPS): Remove.
(if_convert): Remove its now-vacuous #ifdef guards.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (first_active_insn, find_active_insn_after, block_fallthru,
noce_try_move, noce_try_sign_bit_splat, noce_try_store_flag_mask,
noce_emit_cmove, noce_try_cmove, get_base_reg_or_constant,
noce_try_cond_arith, try_emit_cmove_seq,
noce_convert_multiple_sets_1, init_noce_multiple_sets_info,
check_cond_move_block, find_if_header, block_jumps_and_fallthru,
find_if_case_2, dead_or_predicable): Fix comments.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (dead_or_predicable): Make merge_set, live and return_regs
auto_bitmap and drop the manual BITMAP_FREE calls.
(bbs_ok_for_cmove_arith): Make bba_sets an auto_bitmap.
(bb_valid_for_noce_process_p): Make test_bb_temps an auto_bitmap and
return directly instead of jumping to a cleanup label.
(noce_convert_multiple_sets): Make set_targets an auto_bitmap.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_convert_multiple_sets_1): Take the condition as a
parameter instead of re-decoding it. Remove the unused cond_earliest
local.
(noce_convert_multiple_sets): Pass the decoded condition down.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (enum ifcvt_phase): New.
(ifcvt_pass_phase): New, replacing...
(ifcvt_after_combine): ...this.
(cheap_bb_rtx_cost_p): Test ifcvt_pass_phase.
(if_convert): Take an ifcvt_phase instead of a bool.
(rest_of_handle_if_conversion): Adjust caller.
(pass_if_after_combine, pass_if_after_reload): Remove, folding both
into...
(pass_rtl_ifcvt): ...this, now parameterised on the phase.
(make_pass_rtl_ifcvt, make_pass_if_after_combine,
make_pass_if_after_reload): Construct it with the matching phase.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_commit_sequence): New function.
(noce_try_ifelse_collapse, noce_try_store_flag,
noce_try_sign_bit_splat, noce_try_inverse_constants,
noce_try_shifted_store_flag, noce_try_store_flag_constants,
noce_try_store_flag_logical, noce_try_addcc,
noce_try_store_flag_mask, noce_try_cmove, noce_try_cmove_arith,
noce_try_cond_arith, noce_try_sign_mask): Use it.
2026-09-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_finish_if_conversion): New function.
(noce_convert_multiple_sets): Use it. Remove now-unused locals.
(noce_process_if_block): Likewise.
(cond_move_process_if_block): Likewise.
2026-09-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Restrict the condition
to accept only CONST0_RTX as operand 2 when operand 1 is MEM.
(*vec_concatv2si_sse4_1): Ditto.
(*vec_concatv2sf_sse): Disable the pattern when SSE4.1 is enabled.
(*vec_concatv2si_sse): Rename from *vec_concatv2si.
2026-09-10 Shivam Gupta <shivam98.tkg@gmail.com>
PR tree-optimization/125734
* tree-ssa-loop-niter.cc (is_rshift_by_1): Remove TYPE_UNSIGNED restriction.
(number_of_iterations_cltz): Use range_on_edge to check non-negativity of
signed preheader input.
(number_of_iterations_cltz_complement): Likewise.
2026-09-10 Zhongyao Chen <chen.zhongyao@zte.com.cn>
* config/riscv/riscv-protos.h (get_vector_units): New.
(get_scalar_units): New.
* config/riscv/generic-ooo.md: Update comments for vector issue width.
* config/riscv/generic-vector-ooo.md (vxu_ooo_issue): Change to reservation over 2 units.
(vxu_ooo_alu): Likewise.
(vxu_ooo_multicycle): Likewise.
* config/riscv/riscv-vector-costs.cc (costs::scale_vector_cost): New.
(costs::add_stmt_cost): Call it.
* config/riscv/riscv-vector-costs.h (costs::scale_vector_cost): New.
* config/riscv/riscv.cc (riscv_tune_param): Add scalar_units and
vector_units.
(generic_ooo_tune_info): Set scalar_units to 4 and vector_units to 2.
2026-09-09 John David Anglin <danglin@gcc.gnu.org>
PR rtl-optimization/127142
* config/pa/pa.md: Add alternatives using ldil/addl
sequence to various insns to load the high part of
a symbolic operand.
2026-09-09 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127261
* tree-ssa-sccvn.cc (insert_predicates_for_cond): Canonicalize
the comparison before testing for recusion.
2026-09-09 Léo Hardt <leom.hardt@inf.ufrgs.br>
* expr.cc (gen_common_operation_to_reflect): Remove.
(reflect_64_bit_value): Remove.
(reflect_32_bit_value): Remove.
(reflect_16_bit_value): Remove.
(reflect_8_bit_value): Remove.
(generate_reflecting_code_standard): Remove.
* expr.h (generate_reflecting_code_standard): Remove.
2026-09-09 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.cc (pa_spill_class): Declare.
(pa_legitimize_address_displacement): Declare.
(TARGET_SPILL_CLASS): Define.
(TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT): Define.
(pa_secondary_reload): Handle 32 and 64-bit
float/integer type puns. We need a secondary
reload for SImode/DImode REG+D moves to general
and float registers.
(pa_legitimate_address_p): Allow 14-bit displacements
when lra_in_progress is true.
(pa_spill_class): Implement.
(pa_legitimize_address_displacement): Implement.
2026-09-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (if_case_blocks_ok_p): New function.
(find_if_case_1, find_if_case_2): Use it.
2026-09-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_try_shifted_store_flag): Drop the vacuous null test
on common.
(noce_try_store_flag_mask): Match the two forms without assigning
inside the condition.
(noce_convert_multiple_sets): Drop the redundant set_used_flags calls
and the locals they were the only use of.
2026-09-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_try_cond_arith): Assert that the conditional move
exists after the subreg fallback and drop the four dead tests for it.
2026-09-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* system.h (HAVE_DESIGNATED_UNION_INITIALIZERS): Remove and poison.
* recog.h (insn_data_d::insn_output_u): New union, replacing the
anonymous one and its non-designated fallback. Add a constructor
per member.
* genoutput.cc (output_operand_data): Emit one row per line.
(output_insn_data): Likewise, and initialise the output member
directly rather than through a designated initialiser.
2026-09-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-ssa-loop-im.cc (can_sm_ref_p): Reject a trapping store when
non-call exceptions are enabled.
2026-09-09 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-phiopt.cc (hoist_adjacent_loads): Clear the range
info of the hoisted loads.
2026-09-09 Aldy Hernandez <aldy@quesejoda.com>
* tree-ssa-threadbackward.cc (back_threader::m_visited_bbs):
Replace with...
(back_threader::m_visited_flag): ...this.
(back_threader::back_threader): Initialize it.
(back_threader::find_paths_to_names): Adjust.
(back_threader::maybe_thread_block): Drop the reset.
2026-09-09 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.cc (range_from_missing_constructor_part):
Allow float types.
(range_from_readonly_load): Add the range of a REAL_CST.
(fold_using_range::range_from_readonly_var): Allow float types.
2026-09-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/127262
* gimple-predicate-analysis.cc (predicate::init_from_control_deps):
Convert switch label values to the type of the switch index.
2026-09-09 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-niter.cc (nowrap_type_p): Honor
-fwrapv-pointer.
2026-09-09 Sun, Qin <qin.sun@intel.com>
* config/i386/sse.md (vec_concatv2df): Restrict the condition
to accept only CONST0_RTX as operand 2 when operand 1 is MEM.
2026-09-09 Richard Biener <rguenther@suse.de>
PR ipa/126153
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Only
reinterpret a known aggregate value into the type of the
condition if both types have the same precision.
2026-09-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/126153
* tree-ssa-sccvn.cc (reverse_storage_order_for_component_p): Take
the operands by const reference.
(vn_reference_lookup_3): Punt when translating a reference through
an aggregate copy consumes all of its operands and either access
has reverse storage order.
2026-09-09 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-neon-builtins-base.cc: Merge NEON_FUNCTION
macro instances having the same CLASS and ARGS arguments.
* config/aarch64/aarch64-neon-builtins-functions.h
(NEON_FUNCTION): Convert to a variadic macro and rename from this ...
(NEON_FUNCTION_IMPL): ... to this.
(NEON_FUNCTION_COUNT_IMPL): New macro.
(NEON_FUNCTION_COUNT): Likewise.
(NEON_FUNCTION_N_3): Likewise.
(NEON_FUNCTION_N_4): Likewise.
(NEON_FUNCTION_N_5): Likewise.
(NEON_FUNCTION_N_6): Likewise.
(NEON_FUNCTION_N_7): Likewise.
(NEON_FUNCTION_N_8): Likewise.
(NEON_FUNCTION_N_9): Likewise.
(NEON_FUNCTION_N_10): Likewise.
(NEON_FUNCTION_N_11): Likewise.
(NEON_FUNCTION_N_12): Likewise.
(NEON_FUNCTION_2): Likewise.
(NEON_FUNCTION_1): Likewise.
2026-09-09 liuhongt <hongtao.liu@intel.com>
PR target/127225
* config/i386/i386-expand.cc (ix86_expand_vector_init_v4sf): Use
emit_move_insn rather than a bare SET to materialize the V2SFmode
zero half, as movv2sf may not be available.
2026-09-08 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/126622
* config/alpha/alpha.cc (alpha_va_start): Use
build_int_cst (integer_type_node, cst).
* config/i386/i386-options.cc (ix86_handle_tm_regparm_attribute): Ditto.
* config/mips/mips.cc (mips_build_builtin_va_list): Ditto.
(mips_gimplify_va_arg_expr): Ditto.
* config/rs6000/rs6000-call.cc (rs6000_va_start): Ditto.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Ditto.
(resolve_vec_step): Ditto.
* config/s390/s390.cc (s390_va_start): Ditto.
* config/s390/s390-c.cc (s390_expand_overloaded_builtin): Ditto.
(s390_resolve_overloaded_builtin): Ditto.
* config/stormy16/stormy16.cc (xstormy16_expand_builtin_va_start): Ditto.
* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Ditto.
* omp-simd-clone.cc (simd_clone_adjust): Ditto.
* trans-mem.cc (ipa_tm_insert_irr_call): Ditto.
* tree-data-ref.cc (compute_overlap_steps_for_affine_univar): Ditto.
(analyze_subscript_affine_affine): Ditto.
* tsan.cc (instrument_builtin_call): Ditto.
* omp-expand.cc (expand_omp_atomic_fetch_op): Ditto.
(expand_omp_atomic_cas): Ditto.
(expand_omp_atomic_pipeline): Ditto.
* tree-vect-generic.cc (add_shift): Ditto.
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Ditto.
* expr.cc (maybe_optimize_mod_cmp): Ditto.
* gimple-ssa-store-merging.cc (bswap_replace): Ditto.
(imm_store_chain_info::output_merged_store): Ditto.
* omp-low.cc (lower_omp_ordered): Ditto.
2026-09-08 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* tree-pretty-print.h (pp_double_int): Remove.
* tree-pretty-print.cc (pp_double_int): Ditto.
2026-09-08 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-path.h (path_range_query::m_pointer_exit_dependencies):
New.
* gimple-range-path.cc (path_range_query::adjust_for_non_null_uses):
Walk m_pointer_exit_dependencies, and return early for a block with no
inferred ranges.
(path_range_query::compute_ranges): Fill in m_pointer_exit_dependencies.
2026-09-08 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-path.cc (path_range_query::reset_path): Splice
into the existing path vector.
(path_range_query::compute_ranges): Reset the path oracle
unconditionally.
* tree-ssa-threadbackward.cc (back_threader::m_solver): New.
(back_threader::back_threader): Allocate it.
(back_threader::~back_threader): Free it.
(back_threader::find_taken_edge_goto): Use it.
(back_threader::find_taken_edge_switch): Same.
(back_threader::find_taken_edge_cond): Same.
2026-09-08 Rohith Kapelli <kapellirohith@gmail.com>
PR ipa/119006
* ipa-icf-gimple.cc (func_checker::compare_operand): Pass
OEP_ADDRESS_OF_SAME_FIELD to operand_equal_p.
2026-09-08 Dominic P <gcc@gcc.dp11.uk>
* match.pd (((x >> 1) + (y >> 1)) + ((x | y) & 1)): New pattern.
2026-09-08 Zhongyao Chen <chenzhongyao.hit@gmail.com>
PR target/126932
* config/riscv/autovec.md: Rewrite vector FMA patterns.
* config/riscv/autovec-opt.md: Likewise and add new patterns.
2026-09-08 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/117193
* fold-const.cc (combine_comparisons): Add support
for LT, GT, LE, and GE.
* match.pd (`(a CMP0 b) OP (a OP1 b)`): Change to use simple_comparison
instead of eq/ne.
2026-09-08 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/107881
* fold-const.cc (enum comparison_code): Mark underlying type as
unsigned char. Wrap in an anonymous namespace.
(operator~): New function.
(operator|): New function.
(operator&): New function.
(operator^): New function.
(combine_comparisons): Add support for NE/XOR and EQ.
* match.pd (`(a CMP1 b) OP (a CMP2 b)`): Move
above others and add NE, XOR and EQ to the list of OPs.
(`(a CMP1 b) ^ (a CMP2 b)`): Remove.
(`(a CMP1 b) == (a CMP2 b)`): Remove.
2026-09-08 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/126912
* doc/match-and-simplify.texi: Document new
with optional operands.
* genmatch.cc (fprint_indent): New function.
(class c_code_id): New class.
(c_code_id::gen_checking): New mthod.
(get_operator): For c_code_id, mark it as used too.
(lower_for): Treat c_code_id like a function.
(get_operand_type): Handle c_code_id with cmps
set as a comparison.
(expr::gen_transform): Likewise.
Call gen_checking for c_code_id and handle
c_code_id for generic for function and tree code case.
(dt_simplify::gen_1): Handle c_code_id.
(parser::parse_c_with_ids): New method.
(parser::parse_result): Handle optional part of with.
* match.pd (`(a CMP1 b) bitop (a CMP2 b)`): Remove rcmp
loop and update for the new syntax.
(other comparison loops): Update for the new syntax.
2026-09-08 Joel Sherrill <joel@rtems.org>
* config/microblaze/rtems.h: RTEMS needs this defined to
select the proper procedure for executing the
global constructors.
2026-09-08 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-vector-costs.cc (costs::add_stmt_cost): Skip
statement cost adjustments for scalar costing.
2026-09-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/127245
* tree-vect-slp.cc (vect_slp_analyze_node_operations): Check
whether child passes vect_get_num_copies_for_invariant.
2026-09-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (cond_exec_process_insns): Document the parameters in the
function comment instead of between them.
(cond_exec_process_if_block): Likewise.
2026-09-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* ifcvt.cc (noce_try_cond_arith): Return bool instead of int.
(block_jumps_and_fallthru): Use a logical test on the bool flags.
2026-09-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-ssa-math-opts.cc (match_arith_overflow): Canonicalize the
operands of commutative overflow internal functions.
2026-09-08 Chung-Lin Tang <cltang@baylibre.com>
PR middle-end/122205
* omp-offload.cc (omp_discover_implicit_declare_target): For variables,
under 'OMP_REQUIRES_SELF_MAPS | OMP_REQUIRES_UNIFIED_SHARED_MEMORY',
remove "omp declare target" attribute and add "omp declare target link".
2026-09-08 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64.md
(*extend<SHORT:mode><GPI:mode>2_aarch64): Use extsize instead of
size.
(*adds_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*add_<optab><SHORT:mode>_si_uxtw): Likewise.
(*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*add_<optab><SHORT:mode>_shft_si_uxtw): Likewise.
(*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*sub_<optab><SHORT:mode>_si_uxtw): Likewise.
(*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*sub_<optab><SHORT:mode>_shft_si_uxtw): Likewise.
(*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise.
(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>):
Likewise.
(*aarch64_combinez_be<mode>): Likewise.
* config/aarch64/atomics.md
(*aarch64_atomic_load<ALLX:mode>_rcpc_sext): Likewise.
* config/aarch64/iterators.md (size): Yield empty string for SI.
(extsize): New iterator.
2026-09-08 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (movsf_internal):
Prefix register constraints with '*' for hardware FP register load
and store alternatives.
2026-09-08 Jack O'Donohue <jackodonohue41@gmail.com>
* config/sh/sh.cc (sh1_builtin_p): Rename to sh_fpu_p.
(sh_fpu_p): Check TARGET_FPU_ANY instead of TARGET_SH1.
(bdesc): Update sh1_builtin_p to sh_fpu_p.
2026-09-07 Roger Sayle <roger@nextmovesoftware.com>
* expmed.cc (store_fixed_bit_field_1): Use new aop_optab when
writing a value into a fixed size bitfield of a structure.
* optabs.cc (expand_binop): If target doesn't provide a suitable
aop<mode>3 instruction, intelligently use PLUS or IOR instead.
(expand_binop): For rotations, use aop_optab to select AOP
implementation instead of hard-coding add_optab.
(expand_bitreverse): Likwise, Use aop_optab instead of ior_optab
when composing swapped bits and nibbles (allows use of shift_add).
* optabs.def (aop_optab): New named optab for any_or_plus.
* rtl.def (AOP): New RTX code to capture any_or_plus semantics.
* config/avr/avr.md (aop<mode>3): New define_expand to specify
that IOR should always be used to implement any_or_plus (AOP).
2026-09-07 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn.cc (gcn_spill_class): Spill scalars to SGPRs.
2026-09-07 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-valu.md (vnhi): New mode attribute.
(VnHI): Likewise.
(<u>mul<mode><vnsi>3<exec>): New.
(<u>mul<mode><vnhi>3<exec>): New.
* config/gcn/gcn.md (<u>mulqihi3_scalar): Rename this ...
(<u>mulqihi3): ... to this.
2026-09-07 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-opts.h (TARGET_RDNA3_PLUS): New.
* config/gcn/gcn-valu.md (<expander><mode>2<exec>): New.
(<expander><mode>2): New.
(<expander><mode>2_natural): New.
* config/gcn/gcn.md (rnda): Add n3 and 3p values.
(enabled): Handle rdna n3 and 3p.
(mnemonic): Add clz and ctz.
(rdna_mnemonic): New code attribute.
2026-09-07 Kyrylo Tkachov <ktkachov@nvidia.com>
Cui Lili <lili.cui@intel.com>
PR tree-optimization/125557
* ifcvt.cc (noce_convert_multiple_sets): Build metadata for both arms.
Append entries for else-only live-out destinations, enforce the final
output limit, and preserve the then-arm source location.
(noce_convert_multiple_sets_1): Consume the unified output metadata.
Select incoming values for destinations defined by only one arm.
(init_noce_multiple_sets_info): Initialize stable metadata fields.
(bb_ok_for_noce_convert_multiple_sets): Remove final-source
classification.
(noce_process_if_block): Form the union of the arm live-outs, accept
arm-only destinations and one-set arms without a shared-source gate, and
keep the CFG arm order.
2026-09-07 Jakub Jelinek <jakub@redhat.com>
* optabs.def (bitinttofp_optab, bitintfromfp_optab): New optabs.
* optabs-libfuncs.h (gen_bitint_fp_libfunc): Declare.
* optabs-libfuncs.cc (gen_interclass_conv_libfunc): Move most of
the function into ...
(gen_interclass_conv_libfunc_name_name): New helper function.
(gen_bitint_fp_libfunc): New function.
* internal-fn.cc (expand_FLOATTOBITINT): Use
optab_libfunc (bitintfromfp_optab, mode) instead of constructing
libcall name manually.
(expand_BITINTTOFLOAT): Similarly with
optab_libfunc (bitinttofp_optab, mode).
2026-09-06 Iain Sandoe <iain@sandoe.co.uk>
* config/i386/i386-expand.cc (ix86_expand_call): User setting of
no_caller_saved_registers overrides lazy symbol stub reservations.
2026-09-06 wangjue <juewang@linux.alibaba.com>
* config/m68k/m68k.cc (m68k_sched_issue_rate): Return one for CPUs
without a scheduling model.
2026-09-05 Jin Ma <jinma@linux.alibaba.com>
PR target/126196
* config/riscv/vector-crypto.md (vv_ins_con): New int attribute.
(vv_ins1_con): Likewise.
(vi_ins1_con): Likewise.
(@pred_v<vv_ins1_name><mode>): Use vv_ins1_con.
(@pred_crypto_vv<vv_ins_name><ins_type><mode>): Use vv_ins_con.
(@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar): Use vi_ins1_con.
(@pred_vsm3me<mode>): Mark the destination as early-clobber.
2026-09-05 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_add): Add the
X + MIN (~X, Y) form.
2026-09-05 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_sat_sub): Add the four
forms that compare the difference with the minuend.
2026-09-05 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/127201
* tree-data-ref.cc (dr_may_alias_p): Consult DR_PTR_INFO of both
data references before falling back to base-object analysis.
2026-09-05 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_zero_call_used_regs):
Change to assign 0 to the A9 register and then use it to clear
other non-GP registers, instead of triggering a gcc_assert()
failure when the address register is not zeroed out at all.
2026-09-04 Jakub Jelinek <jakub@redhat.com>
PR target/126671
* config/riscv/bitmanip.md (bswaphi2): Use
TARGET_ZBB || TARGET_ZBKB condition instead of just
TARGET_ZBB.
(bitreverse<mode>2): New expander.
2026-09-04 Richard Earnshaw <rearnsha@arm.com>
PR target/126463
* config/aarch64/aarch64.cc (aarch64_select_cc_mode): Correctly
match overflow detection idioms using MINUS and NEG.
* config/aarch64/aarch64.md (subv<GPI:mode>4): Re-order the
compare into canonical form.
(subv<GPI:mode>4_insn): Likewise.
(negv<GPI:mode>4): Likewise.
(negv<GPI:mode>_insn): Likewise. Fix typo in output template.
2026-09-04 Yongqiang Tian <yqtian668@gmail.com>
PR debug/108784
* ira.cc (ira): Use get_max_insn_count instead of get_max_uid when
selecting simple LRA.
2026-09-04 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/125507
* gengtype-lex.l: Remove ENUM_BITFIELD.
* real.h (struct real_value): Ditto.
2026-09-04 Dominic P <gcc@gcc.dp11.uk>
Richard Earnshaw <rearnsha@arm.com>
PR target/111609
* config/arm/neon.md (neon_vshll<sup>_n<mode>): Emit vmovl for a
shift of zero. Use signless form when the shift amount == element
size.
2026-09-04 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126942
* gimple-range-fold.cc (fold_using_range::fold_stmt): Use
set_range_query.
* gimple-range-path.h (path_ranger::active_query_compatible_p): New.
* gimple-range.cc (enable_ranger): Use set_range_query.
(disable_ranger): Likewise.
* tree-vrp.cc (execute_fast_vrp): Likewise.
* value-query.cc (set_range_query): New.
* value-query.h (range_query::active_query_compatible_p): New.
(set_range_query): Declare.
2026-09-04 Georg-Johann Lay <avr@gjlay.de>
PR target/127188
* config/avr/avr-passes.cc (avr_pass_2moves) <optimize_2moves_bb>:
Use next_nondebug_insn_bb to traverse the insns.
<optimize_2moves>: Ignore degug insns when traversing
DF_REG_USE_CHAIN.
2026-09-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/127206
* tree-vect-slp.cc (vect_schedule_slp): If scc_info is already
present, use its failure state.
2026-09-04 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-09-03 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR middle-end/125390
* config/riscv/riscv-v.cc (shuffle_even_odd_patterns): Adjust
check and clarify comment.
* config/riscv/riscv.cc (riscv_can_change_mode_class): Allow
same-sized vectors.
(riscv_regmode_natural_size): Set to "one vector" for VLS modes.
2026-09-03 Robin Dapp <rdapp.gcc@gmail.com>
Richard Sandiford <rdsandiford@googlemail.com>
PR target/124996
PR middle-end/125390
* doc/tm.texi: Document int move requirements for
REGMODE_NATURAL_SIZE.
* doc/tm.texi.in: Likewise.
* expmed.cc (store_bit_field_1): Spill unsplittable modes to
memory.
(store_integral_bit_field): Defer unsplittable modes to
extract_bit_field.
(extract_bit_field_1): Spill if necessary.
* expr.cc (read_complex_part): Adjust assert.
* lower-subreg.cc (interesting_mode_p): Don't consider
unsplittable modes as interesting.
(simple_move_operand): Don't split subregs whose outer mode
can be split but the inner mode cannot.
(simplify_subreg_concatn): Don't insist the outer mode is
interesting but rather check that its size is constant.
2026-09-03 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/riscv-protos.h (riscv_split_quadword_move):
Declare.
* config/riscv/riscv.cc (riscv_subpart): New function to get
TImode sub-parts from OImode regs.
(subreg_word_splittable_p): New function to check if a subreg
(spill_subreg_move): New function.
(riscv_split_doubleword_move): Add unsplittable-subreg handling.
(riscv_split_quadword_move): New function to split OImode.
* config/riscv/riscv.md (movti): New expander.
(movoi): Likewise.
2026-09-03 Alfie Richards <alfie.richards@arm.com>
PR target/126629
* config/aarch64/aarch64-sve-builtins-base.cc
(svldff1_gather_impl::expand): Change ffr update.
(svldff1_gather_extend::expand): Likewise.
(svldxf1_impl::expand): Likewise.
(svldxf1_extend_impl::expand): Likewise.
* config/aarch64/aarch64-sve.md (aarch64_update_ffr_for_load):
Change to...
(@aarch64_update_ffr<mode>): ...this.
2026-09-03 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127183
* tree-eh.cc (lower_eh_constructs_2): Use lhs_could_trap_p for lhs.
(stmt_could_throw_1_p): Use tree_could_throw_1 for lhs.
(tree_could_throw_p): Likewise.
2026-09-03 Dominic P <gcc@gcc.dp11.uk>
PR target/96056
* config/arm/arm.cc (arm_expand_compare_and_swap): Always promote
mod_s to ACQ_REL for the RELEASE/ACQUIRE combination.
2026-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/iterators.md (vn_mode): Add the SVE modes whose
elements halve without changing the number of lanes.
* config/aarch64/aarch64-sve2.md
(*aarch64_sve_<shrn_op>shrnb<mode>): New pattern.
2026-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/iterators.md (VNARROWQ, Vnarrowq): Add the SVE
modes whose elements halve without changing the number of lanes.
(Ventype): Add the unpacked SVE modes.
* config/aarch64/aarch64-sve2.md
(<sat_trunc_op>trunc<mode><Vnarrowq>2): New pattern.
2026-09-03 Josef Melcr <josef.melcr@suse.com>
* doc/extend.texi: Reformat callback_only attrbute docs.
2026-09-03 Josef Melcr <josef.melcr@suse.com>
* doc/extend.texi: Add a line saying variadic functions are
unsupported to the callback_only description.
2026-09-03 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Move gpr<->xmm move cost ...
(ix86_vector_costs::add_slp_cost): ... here, to new overload
of add_slp_cost.
* tree-vect-slp.cc (vect_prologue_cost_for_slp): Consistently
set SLP node for all cost components to make grouping for
the add_slp_cost hook work.
(add_slp_costs): Avoid calling vector_costs::add_slp_cost
with NULL SLP node.
2026-09-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/127195
* tree-vect-slp.cc (vect_create_constant_vectors):
Properly compute number_of_copies, assert we end up
on a vector boundary.
2026-09-03 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/gcc-auto-profile: Replace explicit perf.data
with perf_file variable. Add parsing for "--perf" flag.
* config/i386/gcc-auto-profile: Likewise.
2026-09-03 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/89007
* tree-vect-patterns.cc (vect_recog_average_pattern): Allow signed
types in the fallback. Check whether the fallback operations are
supported.
2026-09-03 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_vectorization_profitable_p):
Prefer the computed SLP schedule location to determine
the containing loop. Make sure to make lock-step
progress when iterating regions with missing vector/scalar
part. Delay individual assessment of profitability for
the region containing the entry and require profitability
based on total costs.
2026-09-03 Julio Sotoriva De Bastiani <Julio.SotorivaDeBastiani@arm.com>
PR target/126096
* config/aarch64/aarch64-acle-builtins.cc
(gimple_folder::fold_to_pfalse): Handle svcount_t.
* config/aarch64/aarch64-sve-builtins-base.cc
(svpfalse_impl::fold): Handle svcount_t.
(svwhilelx_impl::fold_type): Punt for non-pfalse svcount_t.
2026-09-03 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/driver-riscv.cc (struct riscv_cpuid): New.
(riscv_cpuid::valid_p, riscv_cpuid::match): New member functions.
(struct riscv_core_id): New.
(riscv_core_ids): New.
(riscv_core_from_cpuid): New function.
(riscv_hwprobe_cpus, riscv_hwprobe_affinity, riscv_hwprobe_this_core):
New functions.
(struct riscv_cpuinfo): Add the identification registers.
(riscv_read_cpuinfo): Read them.
(riscv_cpuid_from_pairs, riscv_cpuid_from_hwprobe)
(riscv_cpuid_from_cpuinfo): New functions.
(riscv_native_tune): New function.
(host_detect_local_cpu): Handle "tune".
* config/riscv/riscv.h (RISCV_NATIVE_SPECS): Handle -mtune=native
and -mcpu=native.
(OPTION_DEFAULT_SPECS): Leave -mcpu=native to RISCV_NATIVE_SPECS.
* config/riscv/x-riscv: Update the dependencies.
* doc/invoke.texi (RISC-V Options): Document -mtune=native and
-mcpu=native.
2026-09-03 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-cores.def (RISCV_CORE): Fill in MVENDORID,
MARCHID and MIMPID for sifive-u74, sifive-p550, sifive-p870-d,
spacemit-x60, spacemit-x100 and spacemit-a100.
2026-09-03 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-hwprobe.h (riscv_core_id_t): New typedef.
* config/riscv/riscv-cores.def (UNKNOWN_ID): New macro.
(RISCV_CORE): Take MVENDORID, MARCHID and MIMPID; pass UNKNOWN_ID
for every core.
* common/config/riscv/riscv-common.cc (RISCV_CORE): Update for the
new arguments.
* config/riscv/gen-riscv-mcpu-texi.cc (RISCV_CORE): Likewise.
2026-09-02 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127092
* range-op.cc (operator_div::op1_op2_relation_effect): Only
handle TRUNC_DIV_EXPR, EXACT_DIV_EXPR and FLOOR_DIV_EXPR
for the `a < b` case.
2026-09-02 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/125557
* ifcvt.cc: Include "explow.h".
(noce_simple_cmove_operand_p): New function.
(noce_try_cmove): Use it.
(noce_convert_multiple_sets): Handle diamond CFG cleanup.
(noce_convert_multiple_sets_1): Evaluate secondary-arm values in fresh
pseudos, preserve their source locations, and use their final values
as conditional-move inputs. Use copy_to_mode_reg. Reject secondary
sequences that modify condition inputs and handle condition-code
clobbers.
(bb_ok_for_noce_convert_multiple_sets): Add REQUIRE_MULTIPLE,
LIVE_OUT_DESTS, HAS_NON_SIMPLE_SRC, NONREG_LIVE_OUT_DESTS, and
INSN_COUNT. Record distinct live-out destinations, non-simple sources,
the raw source class of each final live-out definition, and the number
of active sets.
(noce_process_if_block): Recognize and cost multi-set diamonds. Choose
the compatible primary arm from the validated live-out destinations.
Require a shared destination with a non-register final source in at least
one arm. Limit unconditional secondary-arm evaluation with
MAX_CONDITIONAL_EXECUTE. Defer all-simple diamonds to existing
conditional-move handling.
(check_cond_move_block): Use noce_simple_cmove_operand_p.
2026-09-02 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_unary_operation_1) <case BSWAP>:
Canonicalize (BSWAP (BITREVERSE x)) as (BITREVERSE (BSWAP x)).
2026-09-02 Roger Sayle <roger@nextmovesoftware.com>
* config/aarch64/aarch64.md (*aarch_movk<mode>): Prepend asterisk.
Use any_or_plus iterator to also recognize PLUS and XOR forms.
2026-09-02 wangjue <juewang@linux.alibaba.com>
* ifcvt.cc (noce_parallel_cost_node): New.
(noce_parallel_costed_insn_p): New.
(noce_dependency_level): New.
(noce_parallel_seq_cost): New.
(default_noce_conversion_profitable_p): Use it.
2026-09-02 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_register_move_cost): Check
secondary memory necessity before early return.
2026-09-02 Richard Biener <rguenther@suse.de>
PR ipa/126153
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Do not
look up an aggregate value for a condition whose offset is not
byte aligned.
2026-09-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/127190
* tree-vect-loop.cc (vectorizable_lane_reducing): Fail
when vect_get_num_copies_for_invariant does.
2026-09-02 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/127149
* tree-vect-patterns.cc (vect_recog_popcount_clz_ctz_ffs_pattern):
Handle lhs_type without mode precision by adding casts.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config/i386/acev1intrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new builtin type.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_ace_builtin):
Handle new builtin type.
* config/i386/sse.md (UNSPECV_TOP2BF16PS): New.
(UNSPECV_TOP4BSSD): Ditto.
(UNSPECV_TOP4BSUD): Ditto.
(UNSPECV_TOP4BUSD): Ditto.
(UNSPECV_TOP4BUUD): Ditto.
(UNSPECV_TOP4MXBF8PS): Ditto.
(UNSPECV_TOP4MXBHF8PS): Ditto.
(UNSPECV_TOP4MXHBF8PS): Ditto.
(UNSPECV_TOP4MXHF8PS): Ditto.
(UNSPECV_TOP4MXBSSPS): Ditto.
(top2bf16ps): Ditto.
(top4<top4bdtype>): Ditto.
(top4<top4mxfp8type>ps): Ditto.
(top4mxbssps): Ditto.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config/i386/acev1intrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new builtin types.
* config/i386/i386-builtin.def (BDESC): Handle new builtins.
* config/i386/i386-expand.cc
(ix86_expand_ace_builtin): Handle new builtin type.
* config/i386/sse.md (UNSPEC_TCVTROWD2PS) New.
(UNSPEC_TCVTROWPS2FP16H): Ditto.
(UNSPEC_TCVTROWPS2FP16L): Ditto.
(UNSPEC_TILEMOVROWEXTRACT): Ditto.
(UNSPECV_TILEMOVROWINSERT): Ditto.
(UNSPECV_TILEMOVCOLINSERT): Ditto.
(VHFBF_512): Ditto.
(tcvtrowd2ps): Ditto.
(tcvtrowps2<bf16_ph><highlowsuffix>): Ditto.
(tilemovrow_extract): Ditto.
(tilemov<rowcol>_insert): Ditto.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config/i386/acev1intrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new function types.
* config/i386/i386-builtins.cc
(ix86_init_mmx_sse_builtins): Add new builtins.
* config/i386/i386-builtins.h (enum ix86_builtins): Ditto.
* config/i386/i386-expand.cc (ix86_expand_builtin):
Handle new builtins.
* config/i386/sse.md (UNSPEC_BSRMOVH_STORE): New.
(UNSPEC_BSRMOVL_STORE): Ditto.
(UNSPECV_BSRINIT): Ditto.
(UNSPECV_BSRMOVH_LOAD): Ditto.
(UNSPECV_BSRMOVL_LOAD): Ditto.
(bsrinit): Ditto.
(bsrmovf): Ditto.
(bsrmovh_load): Ditto.
(bsrmovl_load): Ditto.
(bsrmovh_store): Ditto.
(bsrmovl_store): Ditto.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config.gcc: Include acev1intrin.h.
* config/i386/i386-builtin-types.def: Add new function type.
* config/i386/i386-builtin.def (BDESC): Reuse AMX-TILE builtins
and handle ACEV1 new builtins.
* config/i386/i386-builtins.cc
(BDESC_VERIFYS): Add BDESC_ACE.
(def_builtin): Share builtin between AMX-TILE and ACEv1.
(ix86_init_mmx_sse_builtins): Handle BDESC_ACE.
* config/i386/i386-expand.cc
(ix86_expand_ace_builtin): New.
(ix86_check_builtin_isa_match): Share builtin between AMX-TILE
and ACEv1.
(ix86_expand_builtin): Handle BDESC_ACE.
* config/i386/i386.md (ldtilecfg): Add TARGET_ACEV1.
(sttilecfg): Ditto.
* config/i386/immintrin.h: Include acev1intrin.h.
* config/i386/sse.md (UNSPECV_TILEZERO): New.
(tilezero): Ditto.
* config/i386/acev1intrin.h: New intrin file.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config/i386/i386.cc (regclass_map): Add BSR_REGS.
(debugger_register_map): Add bsr.
(debugger64_register_map): Add bsr.
(svr_debugger_register_map): Add bsr.
(ix86_conditional_register_usage): Enable bsr when ACE exists.
(print_reg): Handle bsr.
* config/i386/i386.h (FIXED_REGISTERS): Add bsr0.
(CALL_USED_REGISTERS): Ditto.
(REG_ALLOC_ORDER): Ditto.
(HI_REGISTER_NAMES): Add bsr0.
* config/i386/i386.md: Add BSR0_REG.
* config/i386/predicates.md (bsr0_operand): New.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* config/i386/i386.cc (regclass_map): Add tmm.
(debugger64_register_map): Ditto.
(debugger_register_map): Ditto. Also fix for APX r16-31.
(svr4_debugger_register_map): Ditto.
(ix86_conditional_register_usage): Enable tmm only when AMX
or ACE exists.
* config/i386/i386.h (FIXED_REGISTERS): Ditto.
(CALL_USED_REGISTERS): Ditto.
(REG_ALLOC_ORDER): Ditto.
(HI_REGISTER_NAMES): Ditto.
* config/i386/i386.md: Ditto.
2026-09-02 Haochen Jiang <haochen.jiang@intel.com>
Dipesh Sharma <Dipesh.Sharma@amd.com>
* common/config/i386/cpuinfo.h
(get_available_features): Add ACEV1.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_ACEV1_SET): New.
(OPTION_MASK_ISA2_AVX10V2AUX_UNSET): Disable ACEV1.
(OPTION_MASK_ISA2_ACEV1_UNSET): New.
(ix86_handle_option): Handle ACEV1.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Add FEATURE_ACEV1.
* common/config/i386/i386-isas.h: Handle acev1.
* config/i386/cpuid.h (bit_ACE): New.
* config/i386/i386-c.cc (ix86_target_macros_internal):
Handle acev1.
* config/i386/i386-isa.def (ACEV1): Add DEF_PTA.
* config/i386/i386-options.cc (isa2_opts): Handle acev1.
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.opt: Add macev1.
* config/i386/i386.opt.urls: Regenerated.
* doc/extend.texi: Add acev1 documentation.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
2026-09-02 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/127166
* match.pd: Canonicalize conditional signed narrow clips before loop
if-conversion.
2026-09-02 Kyrylo Tkachov <ktkachov@nvidia.com>
* match-sat-alu.pd (unsigned_integer_narrow_clip): Require an
unsigned comparison and a signed right shift.
2026-09-02 Hongyu Wang <hongyu.wang@intel.com>
PR target/127114
* config/i386/i386.cc (ix86_optab_supported_p): Return true for
round_optab in HFmode.
2026-09-02 Peter Bergner <bergner@gcc.gnu.org>
* doc/install.texi: Remove incorrect mention of --with-long-double-64.
Co-authored-by: Kishan Parmar <kishan@linux.ibm.com>
2026-09-02 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/127133
PR tree-optimization/127134
* tree-eh.cc (tree_could_trap_p): Split into ...
(tree_could_trap_1): This. Take into account lhs
in some cases.
(lhs_could_trap_p): Just call tree_could_trap_1.
2026-09-02 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-loop-im.cc (can_sm_ref_p): Use lhs_could_trap_p.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.
2026-09-02 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-09-01 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/aarch64/aarch64-builtins.cc (enum aarch64_builtins): Add
AARCH64_BUILTIN_YIELD, AARCH64_BUILTIN_WFE, AARCH64_BUILTIN_WFI,
AARCH64_BUILTIN_SEV and AARCH64_BUILTIN_SEVL.
(aarch64_init_syshintop_builtins): New function.
(handle_arm_acle_h): Call aarch64_init_syshintop_builtins.
(aarch64_general_expand_builtin): Expand the system hint builtins.
* config/aarch64/aarch64.md (unspecv): Add UNSPECV_YIELD, UNSPECV_WFE,
UNSPECV_WFI, UNSPECV_SEV and UNSPECV_SEVL.
(aarch64_yield): New insn pattern.
(aarch64_wfe): Likewise.
(aarch64_wfi): Likewise.
(aarch64_sev): Likewise.
(aarch64_sevl): Likewise.
2026-09-01 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/126977
* gimple-match-exports.cc (fn_arg_must_be_const_p): New function.
(all_ssa_names_p): New function.
(factor_operation_ok): New exported function.
* gimple-match.h (factor_operation_ok): New declaration.
* tree-if-conv.cc (factor_out_operators): Use factor_operation_ok.
* tree-ssa-phiopt.cc (factor_out_conditional_operation): Use
factor_operation_ok.
* tree-ssa-tail-merge.cc (merge_stmts_p): Use factor_operation_ok
instead of just looking at specific internal functions.
2026-09-01 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-vector-costs.cc (costs::adjust_stmt_cost):
Restrict LMUL scaling to vector types.
(costs::add_stmt_cost): Recover the scalar type for scalar costing.
2026-09-01 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/127039
* fold-const-call.cc (fold_const_reduction): Explain the handling of
singleton sNaN encodings.
2026-09-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/127130
* tree-scalar-evolution.cc (simplify_peeled_chrec):
Guard against signed integer overflow UB.
2026-09-01 Christopher Bazley <chris.bazley@arm.com>
* tree-vect-slp.cc (vect_create_constant_vectors):
Add an assertion to guard against the outer loop never
terminating because the inner loop is never entered.
2026-09-01 Shreesh Adiga <16567adigashreesh@gmail.com>
* fold-const-call.cc (fold_const_crc): new function to fold crc
(fold_const_call): invoke fold_const_crc to fold builtin crc
2026-09-01 Shreesh Adiga <16567adigashreesh@gmail.com>
* expr.cc (calculate_crc): Moved to hwint.cc file.
(assemble_crc_table): Updated function call.
(calculate_reversed_crc): Moved to hwint.cc file.
(assemble_reversed_crc_table): Updated function call.
* hwint.cc (calculate_crc): Moved from expr.cc and made public.
(calculate_reversed_crc): Moved from expr.cc and made public.
* hwint.h (calculate_crc): Added function prototype.
(calculate_reversed_crc): Added function prototype.
2026-09-01 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127154
* value-range-storage.cc (prange_storage::set_prange) Access
bitmask and points to fields only for kinds those that use them
2026-09-01 Jørgen Kvalsvik <j@lambda.is>
* profile.cc (coverage_instrumentation_p): Put return type on
separate line.
2026-09-01 Jørgen Kvalsvik <j@lambda.is>
* gcov.cc (find_prime_paths): Remove comment.
2026-09-01 Jørgen Kvalsvik <j@lambda.is>
PR gcov-profile/127038
* gcov.cc (tombstone_subsequence_p): Guard iterator
dereference.
2026-09-01 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* auto-profile.cc (function_instance::match): Do not insert a null
entry into counts.
2026-09-01 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_get_num_copies_for_invariant):
Refactor to avoid accessing rem when we will return false.
2026-08-31 Dipesh Sharma <Dipesh.Sharma@amd.com>
PR tree-optimization/126690
* match.pd: Add patterns to fold CPROJ when nested inside CPROJ or CABS.
2026-08-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/127163
* tree-ssa-forwprop.cc (simplify_phi_result_movdiv): check if
the div/mod is using INTEGRAL_TYPE_P operands.
2026-08-31 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126906
* cfghooks.h (can_copy_bbs_p): Add prevailing_exit argument.
(copy_bbs): Likewise.
* cfghooks.cc (can_copy_bbs_p): Exempt prevailing_exit->src
from the abnormal successor edge refusal; refuse a
prevailing_exit->dest inside the region.
(copy_bbs): Prune the non-prevailing edges of
prevailing_exit->src's copy instead of redirecting them.
Assert the prevailing exit leaves the region.
* tree-ssa-threadupdate.cc
(back_jt_path_registry::duplicate_thread_path): Pass EXIT to
can_copy_bbs_p and copy_bbs when the path ends in abnormal
edges. Assert the region ends in EXIT's source. Remove
write-only exit_copy.
2026-08-31 Léo Hardt <leom.hardt@inf.ufrgs.br>
* tree-into-ssa.cc (struct mark_def_sites_global_data): Remove.
* tree-ssa-propagate.cc (ssa_propagation_engine::ssa_propagate):
Remove.
* tree-ssa-tail-merge.cc (struct aux_bb_info): Remove
(BB_VOP_AT_EXIT): Remove.
* tree-vectorizer.h (vect_detect_hybrid_slp): Remove.
2026-08-31 wangjue <juewang@linux.alibaba.com>
* ifcvt.cc (noce_cond_arith_operation): New function.
(noce_operand_known_extended_p): New function.
(noce_try_cond_arith): Handle arithmetic operations wrapped in an
extension.
2026-08-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/126998
* tree-vectorizer.h (vect_get_num_copies_for_invariant):
Adjust API.
* tree-vect-slp.cc (vect_get_num_copies_for_invariant): Also
compute and output the constant number of excess lanes produced.
(vect_create_constant_vectors): Adjust.
(vect_slp_analyze_node_operations): Likewise.
* tree-vect-loop.cc (vectorizable_lane_reducing): Likewise.
2026-08-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/127152
* tree-vect-loop.cc (vect_transform_reduction): Restore
vectype_in computation, compute vec_in_num from unaltered
vec_oprnds.
2026-08-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/101179
* tree-ssa-forwprop.cc (simplify_phi_result_movdiv): New
forwprop step where MOD/DIV ops with pow2 divisors can be
simplified to BIT_AND/RSHIFT.
(pass_forwprop::execute): Call simplify_phi_result_movdiv.
2026-08-31 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/bitmanip.md: Split masked bit-test branches into
BEXT.
2026-08-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/127116
* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Pass rhs1_type as scalar type to build_mask_conversion.
(vect_init_pattern_stmt): Dump mask-precision used for the stmt.
(append_pattern_def_seq): Likewise.
2026-08-31 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/126982
* match-sat-alu.pd (signed_integer_sat_trunc): Require the
conversion to keep the precision of the operand, and the result
to be narrower than it.
2026-08-31 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/126981
* match-sat-alu.pd (unsigned_integer_narrow_clip): Require the
operand to be known different from the minimum of its type.
2026-08-31 Lunex <imlunex2011@gmail.com>
PR tree-optimization/126994
* tree-scalar-evolution.cc (final_value_replacement_loop): Guard
analyze_and_compute_bitop_with_inv_effect on
integer_zerop (niter_desc.may_be_zero).
2026-08-31 Matthias Kretz <m.kretz@gsi.de>
PR target/127055
* config/i386/sse.md (floor<mode>2): Drop !flag_trapping_math.
(lfloor<mode><sseintvecmodelower>2): Likewise.
(ceil<mode>2): Likewise.
(lceil<mode><sseintvecmodelower>2): Likewise.
(btrunc<mode>2): Likewise.
2026-08-31 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/constraints.md (Gz, Gc): New FP constant constraint.
* config/xtensa/predicates.md (move_operand):
Remove to replace the role with the following two new predicates, in
order to make it easier for both humans and compilers to understand.
(move_int_operand): New predicate for the second operand of
"mov[dshq]i_internal" MD patterns.
(move_fp_operand): New predicate for the second operand of
"mov[ds]f_internal" MD patterns.
(const_float_1_operand): Remove as it is not being used.
* config/xtensa/xtensa-protos.h (xtensa_fp_const):
New function prototype.
* config/xtensa/xtensa.cc (xtensa_fp_const):
New function that returns the corresponding non-negative index number
for FP constant values supported by the CONST.S instruction.
(print_operand): Add a new format specifier "G" that outputs the index
for the FP constant value handled by the "CONST.S" instruction.
(xtensa_legitimate_constant_p): Add the non-negative zero set by the
"MOVI" instruction and the floating-point constant supported by the
"CONST.S" instruction to the evaluation range.
* config/xtensa/xtensa.h (TARGET_HARD_FLOAT_CONST_S):
A new macro indicating the conditions under which the "CONST.S"
instruction is available.
* config/xtensa/xtensa.md
(movdi_internal, movsi_internal, movhi_internal, movqi_internal):
Replace the "move_operand" predicate with "move_int_operand".
(movsf): Modify the preparation statement used during RTL generation
to prevent constant immediates that satisfy "Gz" or "Gc" constraints
from being placed in literal pool.
(movsf_internal): Replace the "move_operand" predicate with
"move_fp_operand", and Add the "MOVI" instruction using the "Gz"
constraint and the "CONST.S" instruction using the "Gs" constraint to
the alternatives.
(movdf_internal): Replace the "move_operand" predicate with
"move_fp_operand".
2026-08-31 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/127102
* match.pd: Add pattern to simplify MIN(A,B) == 0 to A == 0 and
MIN(A,B) != 0 to A != 0 when B is known positive.
2026-08-31 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-31 Sun, Qin <qin.sun@intel.com>
PR target/119300
* config/i386/i386-options.cc (ix86_option_override_internal):
Warn and use SSE arithmetics when -mfpmath=387 is set, 387 is turned
off but SSE is available.
2026-08-29 Jeff Law <jeffrey.law@oss.qualcomm.com>
* tree-ssa-loop-ivopts.cc (ivopts_estimate_reg_pressure): Remove
stray semi-colon and fix formatting.
2026-08-29 Mark Wielaard <mark@klomp.org>
* common.opt.urls: Regenerate.
2026-08-29 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Configuration): Update SARIF website.
2026-08-29 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.md (UNSPEC_SSP_SET, UNSPEC_SSP_TEST): New
unspecs.
(stack_protect_set, stack_protect_setdi): New patterns.
(stack_protect_test, stack_protect_testdi): Likewise.
2026-08-29 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.h (FRAME_GROWS_DOWNWARD): Define.
* config/alpha/alpha.cc (alpha_initial_elimination_offset): Resolve
FRAME_POINTER_REGNUM to the high end of the local variables when
FRAME_GROWS_DOWNWARD.
(alpha_vms_initial_elimination_offset): Likewise.
2026-08-29 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.cc (alpha_expand_unaligned_load): Use
copy_addr_to_reg to compute the byte address.
(alpha_expand_unaligned_store_safe_partial): Likewise.
2026-08-29 Jovan Dmitrovic <jovan.dmitrovic@htecgroup.com>
Radosav Krunić <radosav.krunic@htecgroup.com>
* tree-ssa-loop-ivopts.cc (ivopts_estimate_reg_pressure):
Change register pressure estimate in order to respect
the impact of spilling induction variables, compared
to spilling loop invariants.
2026-08-29 Jovan Dmitrovic <jovan.dmitrovic@htecgroup.com>
* tree-ssa-loop-ivopts.cc (ivopts_estimate_reg_pressure):
Remove target_reg_cost from the computation of register pressure
and target_res_regs from the computation of available registers.
2026-08-29 Jovan Dmitrovic <jovan.dmitrovic@htecgroup.com>
Radosav Krunić <radosav.krunic@htecgroup.com>
* tree-ssa-loop-ivopts.cc (ivopts_estimate_reg_pressure):
Remove n_cands bias from reg pressure cost calculation.
2026-08-29 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.h (FRAME_ADDR_RTX): Define.
2026-08-29 Matt Turner <mattst88@gmail.com>
* builtins.cc (expand_builtin_return_addr): Pass COUNT to
FRAME_ADDR_RTX.
* defaults.h (FRAME_ADDR_RTX): Add COUNT argument.
* config/epiphany/epiphany.h (FRAME_ADDR_RTX): Likewise.
* config/s390/s390.h (FRAME_ADDR_RTX): Likewise.
* config/sparc/sparc.h (FRAME_ADDR_RTX): Likewise.
* doc/tm.texi.in (FRAME_ADDR_RTX): Document COUNT and the
NULL_RTX return value.
* doc/tm.texi: Regenerate.
2026-08-29 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (ARM ARMv8-M Security Extensions): Update URL.
* doc/invoke.texi (ARM Options): Ditto.
2026-08-29 Georg-Johann Lay <avr@gjlay.de>
PR middle-end/127098
* config/avr/avr.md (MPUSH): Add TImode to mode iterator.
* config/avr/avr.h (PUSH_ROUNDING): Adjust comment.
2026-08-29 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126896
* tree-ssa-phiopt.cc (pass_phiopt::execute): Run
replicate_conds_over_phis in early phiopt too.
2026-08-28 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/127039
* fold-const-call.cc (fold_const_reduction): Fold non-stepped constants
when the available lane-count information determines the result.
* match.pd (reduction of a vector duplicate): New simplifications to
the duplicated element or zero.
2026-08-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/127105
* tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Access
scalar_stmts[0] only after we determined it exists.
2026-08-28 Richard Biener <rguenther@suse.de>
* common.opt (ftree-loop-if-convert): Mark as ignored.
* doc/invoke.texi (ftree-loop-if-convert): Remove.
* tree-ssa-phiopt.cc (cond_if_else_store_replacement):
Do not check !flag_tree_loop_if_convert.
* tree-if-conv.cc (pass_if_conversion::gate): Only
run when loop vectorization is enabled on any loop.
(pass_if_conversion::execute): Adjust.
(tree_if_conversion): Likewise. Simplify as we now
always version.
(convert_scalar_cond_reduction): Remove loop_versioned
argument which is now always true.
(predicate_scalar_phi): Likewise.
(predicate_all_scalar_phis): Likewise.
(combine_blocks): Likewise.
2026-08-28 Richard Biener <rguenther@suse.de>
* tree-ssa-operands.cc (operands_scanner::verify_ssa_operands):
Verify there are no operands that need renaming.
2026-08-28 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127094
* gimple-range-phi.cc (phi_analyzer::process_phi): Do not process
the same name multiple times.
2026-08-28 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127082
* range-op.cc (operator_trunc_mod::same_quotient): New.
(operator_trunc_mod::wi_fold): Call same_quotient.
2026-08-28 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-27 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR target/102055
* config/aarch64/aarch64.cc (is_bb_in_loop): New.
(aarch64_evpc_rev64_ext): New.
(aarch64_expand_vec_perm_const_1): Call aarch64_evpc_rev64_ext.
2026-08-27 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/127100
* doc/md.texi (vec_mask_len_load_lanes@var{m}@var{n}): Use
operand4 - operand5 rather than operand4 + operand5.
(vec_mask_len_store_lanes@var{m}@var{n}): Use
operand3 - operand4 rather than operand3 + operand4.
(mask_len_gather_load@var{m}@var{n}): Use operand 7 - operand 8
rather than operand 7 + operand 8.
(mask_len_strided_load@var{m}): Use operand 4 - operand 5 rather
than operand 4 + operand 5.
(mask_len_scatter_store@var{m}@var{n}): Use operand 6 - operand 7
rather than operand 6 + operand 7.
(mask_len_strided_store@var{m}): Use operand 4 - operand 5 rather
than operand 4 + operand 5.
(len_load_@var{m}): Use operand 3 - operand 4 rather than
operand 3 + operand 4.
(len_store_@var{m}): Use operand 2 - operand 3 rather than
operand 2 + operand 3.
(mask_len_load@var{m}@var{n}): Use operand 4 - operand 5 rather
than operand 3 + operand 4 or operand 4 + operand 5. Use
Operand 5 rather than Operand 4 when talking about bias QI mode.
(mask_len_store@var{m}@var{n}): Use operand 3 - operand 4 rather
than operand 3 + operand 4 or operand 2 + operand 4.
(cond_len_neg@var{mode}): Use operand 4 - operand 5 rather than
operand 4 + operand 5. Use ops[4] - ops[5] rather than
ops[4] + ops[5].
(cond_len_add@var{mode}): Use operand 5 - operand 6 rather than
operand 5 + operand 6. Use ops[5] - ops[6] rather than
ops[5] + ops[6].
(cond_len_fma@var{mode}): Use ops[6] - ops[7] rather than
ops[6] + ops[7].
* gimple-fold.cc (partial_load_store_mask_state): Compute wlen
as wi::to_poly_widest (len) - wi::to_widest (bias) rather than
wi::to_poly_widest (len) + wi::to_widest (bias).
2026-08-27 Jakub Jelinek <jakub@redhat.com>
* common.opt (Wunsafe-loop-optimizations): Use 2 spaces instead of
1 between sentences in the description.
(Wunreachable-code, fargument-alias, fargument-noalias,
fargument-noalias-global, fargument-noalias-anything,
floop-flatten, fipa-matrix-reorg, fipa-struct-reorg,
foptimize-register-move, fregmove, ftree-vect-loop-version):
Likewise.
* config/alpha/alpha.opt (mgas): Use 2 spaces instead of 1 between
sentences in the description.
2026-08-27 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
PR target/120192
* cfgexpand.cc (defer_stack_allocation): Use align_local_variable
to compute the alignment, matching expand_one_stack_var_1.
2026-08-27 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree_3): Move stmt-local
checks first. Check unsupported BIT_FIELD_REFs for all stmts.
2026-08-27 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree_3): New function,
split out from ...
(vect_build_slp_tree_1): ... here.
2026-08-27 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/127085
* tree-ssa-phiopt.cc (preserves_loop_structure_p): Remove.
(replicate_cond_into_pred): Do not call it.
(replicate_conds_over_phis): Never duplicate loop headers; do
not mark back edges; set LOOPS_NEED_FIXUP when the CFG changed.
2026-08-27 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/9175.md: Complete list of instructions which are
utilizing the LSU/FXA/FXB.
2026-08-27 Manjunath Matti <mmatti@linux.ibm.com>
PR target/126512
* config/rs6000/rs6000-builtins.def (__builtin_altivec_vperm_1ti,
__builtin_altivec_vperm_1ti_uns, __builtin_altivec_vsel_1ti,
__builtin_altivec_vsel_1ti_uns, __builtin_altivec_vsldoi_v1ti): Move
from the [altivec] stanza to the [vsx] stanza.
2026-08-27 Vijay Shankar <vijay@linux.ibm.com>
PR target/116004
* config/rs6000/vsx.md (first_mismatch_or_eos_index): Remove redundant
emit_insns.
2026-08-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/126998
* tree-vectorizer.h (vect_get_num_copies_for_invariant):
Declare.
* tree-vect-slp.cc (vect_get_num_copies_for_invariant): Export.
* tree-vect-loop.cc (vectorizable_lane_reducing): Use
vect_get_num_copies_for_invariant on the SLP input.
2026-08-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/126998
* tree-vect-loop.cc (vect_reduction_update_partial_vector_usage):
Return a bool, defer vect_record_loop_{len,mask} to the caller.
(vectorizable_lane_reducing): Adjust.
(vectorizable_reduction): Likewise.
2026-08-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/126998
* tree-vect-loop.cc (vect_transform_reduction): Remove
redundant effec_reduc_ncopies, compute vec_num based on
the actual vector inputs and rename to vec_in_num.
2026-08-27 Roger Sayle <roger@nextmovesoftware.com>
* config/cris/cris.md (*bswapsi2_not<setcc><setnz><setnzvc>):
New define_insn.
(cris_swap_bits): Rename to...
(<acc><anz><anzvc>bitreversesi2<setcc><setnz><setnzvc>): Renamed
from cris_swap_bits.
(*bitreversesi2_not<setcc><setnz><setnzvc>): New define_insn.
(*rotsi2_16<setcc><setnz><setnzvc>): Likewise.
(*rotsi2_16_not<setcc><setnz><setnzvc>): Likewise.
2026-08-27 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md ("*cstore<mode>4_btstqb0_<CC>"): New
define_insn_and_split.
2026-08-27 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md ("*btst<mode>): Simplify; iterate only over
ZnNNZSET and compare only to a zero_extract result of SImode.
Just add sanity checks for the mode of operand 0 in the condition.
("*cbranch<mode>4_btstrq1_<CC>", "*cbranch<mode>4_btstqb0_<CC>"):
Generate a zero_extract in SImode.
2026-08-27 Sammy Al Hashemi <sammy@salh.xyz>
* doc/invoke.texi (-Wstrict-aliasing): Document that the
front-end type-based checking runs without -fstrict-aliasing
when the warning is requested explicitly.
(-Wstrict-aliasing=n): Likewise.
2026-08-27 Shreesh Adiga <16567adigashreesh@gmail.com>
* config/aarch64/aarch64.md: allow usage of zero reg for CRC32
instructions
2026-08-26 Iain Sandoe <iain@sandoe.co.uk>
* config.gcc: Default the 64b arch to core2.
2026-08-26 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64.cc (aarch64_gen_ccmp_next): Reject a
comparison that would lose an observable exception.
* target.def (gen_ccmp_next): Document the rule.
* doc/tm.texi: Regenerate.
2026-08-26 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64.cc (aarch64_fp_cc_mode): New function.
Use CCFPmode when the FCMPE exception is not observable.
(aarch64_select_cc_mode): Use it.
2026-08-26 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/127039
* match.pd (REDUC (@0 op VECTOR_CST)): Require FMAX and FMIN
constant reductions to simplify.
2026-08-26 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/125138
* config/rs6000/vsx.md (xxpermx): Use a temporary register for the
negated control vector.
2026-08-26 Léo Hardt <leom.hardt@inf.ufrgs.br>
* cgraph.cc (cgraph_nodes_queue): Removed.
(cgraph_cc_finalize): Removed cgraph_nodes_queue
initialization.
2026-08-25 Eric Botcazou <ebotcazou@adacore.com>
PR ada/125984
* tree-dfa.cc (get_ref_base_and_extent) <ARRAY_REF>: Use the range
of the difference between the index expression and the low bound,
instead of that of the index expression itself, to constrain the
maximum size of the access.
2026-08-25 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/127056
* lra-constraints.cc (process_address_1): Canonicalize a complete
address reload.
2026-08-25 Dimitar Dimitrov <dimitar@dinux.eu>
PR target/125746
* config/i386/i386.cc (ix86_hard_regno_mode_ok): For SSEv1,
reject 16-bit modes.
2026-08-25 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126999
* tree-vrp.cc (remove_unreachable::m_list): Change from a std::pair
to an edge vector.
(remove_unreachable::maybe_register): Save edge.
(remove_unreachable::remove): Use the edge.
(remove_unreachable::remove_and_update_globals): Likewise.
2026-08-25 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/127027
* gimple-range-infer.cc (exit_range::bbi): Change from stmt.
(infer_range_manager::add_range): Update block index not stmt.
(infer_range_manager::clear): Remove from specified block list.
2026-08-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127049
* tree-vect-data-refs.cc (vect_analyze_data_refs): Build
a MEM_REF of the DR_REF type for analyzing the innermost
loop behavior for outer loop vectorization.
2026-08-25 Roger Sayle <roger@nextmovesoftware.com>
Richard Sandiford <rdsandiford@googlemail.com>
PR target/48609
* rtl.cc (rtvec_series_p): Enhance to allow START to be a
poly_int64 instead of just an int.
* rtl.h (rtvec_series_p): Update function prototype.
* rtlanal.cc (vec_series_highpart_p): Now that rtxvec_series_p
can handle poly_int64, we handle modes that aren't constant size.
(vec_series_lowpart_p): Likewise.
(get_ref_base_and_offset): New function to determine the base RTX
and byte offset of an arbitrary expression, typically a SUBREG.
* rtlanal.h (get_ref_base_and_offset): Prototype here.
* simplify-rtx.cc (simplify_binary_operation_1) <case VEC_CONCAT>:
Generalize the existing (vec_concat (first_half) (second_half))
optimization using the new get_ref_base_and_offset function.
2026-08-25 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
PR target/126619
* config/i386/i386-expand.cc
(ix86_expand_vector_init_one_nonzero) <case E_V4SFmode>:
Improved initialization of one non-zero element V4SF vectors.
(ix86_expand_vector_init_v4sf): Reuse the above function
ix86_expand_vector_init_one_nonzero where possible. Various
improvements. Fall back to using (the original)
ix86_expand_vector_init_concat in the general case, when
SSE 4.1 instructions aren't available.
* config/i386/sse.md (vec_set<mode>_0): Prefer to avoid
inter-unit moves to general purpose registers in reload.
(vec_setv4sf_sse4_1): Remove asterisk to expose to i386-expand.
(sse4_1_insertps_v4sf_init): Variant of insertps that clears
all the other elements of the destination to zero.
(sse2_insertps_v4sf_3): Implementation of the above instruction
available on SSE2 by using the pslldq instruction.
2026-08-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127058
PR tree-optimization/127051
* tree-vect-slp.cc (vect_create_constant_vectors): Zero-pad
excess elements.
* tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts):
Change 'half' parameter to indicate optional fixed number
of vectors to produce.
(vectorizable_conversion): Adjust.
2026-08-25 Georg-Johann Lay <avr@gjlay.de>
PR target/127032
* config/avr/avr.md (Tag_GNU_AVR_BITS_LONG_DOUBLE)
(Tag_GNU_AVR_BITS_DOUBLE): New define_constants.
* config/avr/avr.cc (avr_uses_long_double_p)
(avr_uses_double_p): New static variables.
(avr_find_double): New function.
(avr_file_end) [HAVE_AS_AVR_GNU_ATTRIBUTE]: Run avr_find_double
on each varpool node. Output .gnu_attribute according to
avr_uses_long_double_p and avr_uses_double_p.
* config/avr/avr-passes.cc (gimple-walk.h): Include.
(avr_pass_has) <op_callback>: New static method.
<scan_bb>: Use it in walk_gimple_op.
<execute>: Set up walk_stmt_info and pass it to scan_bb.
* config/avr/avr-passes.def (avr_pass_has): Adjust comment.
* config/avr/avr-protos.h (avr_find_double): New proto.
2026-08-25 Georg-Johann Lay <avr@gjlay.de>
* configure.ac [avr] <HAVE_AS_AVR_GNU_ATTRIBUTE>: Set
according to gcc_GAS_CHECK_FEATURE for .gnu_attribute.
* configure: Rebuild.
* config.in: Rebuild.
* config/avr/avr.h (avr_addrspace_t) <gnu_attr_val>: New field.
* config/avr/avr.cc (avr_addrspace): Adjust initializer.
(avr_uses_vtable_p): New global variable.
(avr_file_end): Update avr_uses_vtable_p according to varpool,
then output .gnu_attribute 4 according to avr_uses_vtable_p.
* config/avr/avr-passes.cc (gimple.h): Include.
(gimple-iterator.h): Include.
(avr_pass_data_has): New pass data.
(avr_pass_has): New gimple pass.
(make_avr_pass_has): New function.
* config/avr/avr-passes.def (avr_pass_has): Insert pass.
* config/avr/avr-protos.h (avr_uses_vtable_p): New global var.
(class gimple_opt_pass): Declare.
(make_avr_pass_has): New proto.
* config/avr/avr.md (Tag_GNU_AVR_VTABLE_AS)
(Val_GNU_AVR_VTABLE_NONE, Val_GNU_AVR_VTABLE_RAM)
(Val_GNU_AVR_VTABLE_FLASH, Val_GNU_AVR_VTABLE_FLASH1)
(Val_GNU_AVR_VTABLE_FLASH2, Val_GNU_AVR_VTABLE_FLASH3)
(Val_GNU_AVR_VTABLE_FLASH4, Val_GNU_AVR_VTABLE_FLASH5)
(Val_GNU_AVR_VTABLE_FLASHX): Define constants.
2026-08-25 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt (-mfuse-ifelse): New option.
* config/avr/avr-passes.cc (avr_pass_ifelse::gate): Don't
return true when avropt_fuse_ifelse is false.
* config/avr/avr.opt.urls (mfuse-ifelse): Add URL.
* common/config/avr/avr-common.cc (avr_option_optimization_table)
[OPT_LEVELS_1_PLUS]: Set OPT_mfuse_ifelse to 1.
* doc/invoke.texi (AVR Options): Document it.
2026-08-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/126995
* tree-vect-slp.cc (vect_schedule_slp_node): When we cannot
place according to constraints for possibly trapping stmts,
fail.
2026-08-25 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR middle-end/127031
* expmed.h (struct algorithm): Add one slot to the op and log
arrays for the operation synth_mult appends to a full
sub-algorithm before discarding it.
2026-08-25 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-ssa-math-opts.cc (convert_plusminus_to_widen): Require the
result of an intervening conversion to be single-use.
2026-08-25 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64.cc (aarch64_gen_ccmp_first): Handle HFmode.
(aarch64_gen_ccmp_next): Likewise. Reject unsupported HFmode early.
* config/aarch64/aarch64.md
(@ccmp<CCFP_CCFPE:mode><GPF_F16:mode>): Use GPF_F16 and stype.
(@ccmp<CCFP_CCFPE:mode><GPF_F16:mode>_rev): Likewise.
2026-08-25 Dipesh Sharma <Dipesh.Sharma@amd.com>
* common/config/i386/cpuinfo.h (get_available_features): Detect AVX512BMM from
extended features instead of standard leaf.
* config/i386/cpuid.h (bit_AVX512BMM): Move to extended features
section.
2026-08-25 Josef Melcr <josef.melcr@suse.com>
PR ipa/127023
* multiple_target.cc (create_dispatcher_calls): Use the call
statement variant of create_reference.
2026-08-25 Josef Melcr <josef.melcr@suse.com>
PR plugins/126882
* plugin.cc (struct callback_info): Put the struct into an
anonymous namespace.
2026-08-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/127000
* match.pd ((T *)(ptr - ptr_cst)): Canonicalize directly
to (T *)ptr p+ cst.
2026-08-25 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126896
* tree-ssa-phiopt.cc: Include tree-ssa-threadedge.h.
(preserves_loop_structure_p): New.
(replicate_cond_into_pred): New.
(replicate_conds_over_phis): New.
(pass_phiopt::execute): Call replicate_conds_over_phis.
2026-08-25 H.J. Lu <hjl.tools@gmail.com>
PR target/127045
* config/i386/i386.md (*fix_trunc<mode>si_sse_zext): Removed.
(*fix_trunc<mode>si_sse_2_zext): Likewise.
2026-08-25 H.J. Lu <hjl.tools@gmail.com>
PR target/127020
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Check TARGET_SSE4_1
instead of TARGET_AVX for pinsrq and pextrq.
2026-08-25 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-24 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/126991
* genmatch.cc (dt_node::gen_kids): New in_gcond argument.
(dt_node::gen_kids_1): New in_gcond argument.
Disable SSA_NAME generation when in_gcond is true.
(dt_operand::gen): Pass false to gen_kids.
(decision_tree::gen): Likewise.
(write_predicate): Likewise.
(dt_operand::gen_phi_on_cond): Pass true to gen_kids.
2026-08-24 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/126745
* range-op.cc (operator_div::op1_op2_relation_effect): add
VREL_EQ range equal one for op1/op2 and op1%op2 if op1 == op2.
2026-08-24 Kishan Parmar <kishan@linux.ibm.com>
PR target/126738
* config/rs6000/rs6000.opt: Fix formatting of the -mfuture warning.
Co-authored-by: Göran Uddeborg <goeran@uddeborg.se>
2026-08-24 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/127039
* match.pd (REDUC (@0 op VECTOR_CST)): Require the constant reduction
to simplify.
2026-08-24 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vect_get_vector_types_for_stmt): Remove
nunits_vectype_out parameter and code computing it.
* tree-vectorizer.h (vect_get_vector_types_for_stmt): Adjust.
(vect_get_smallest_scalar_type): Remove.
* tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Likewise.
(simd_clone_call_p): Likewise.
* tree-vect-slp.cc (vect_build_slp_tree_1): Adjust.
2026-08-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_record_vectype): Inline ...
(vect_build_slp_tree_2): ... here.
(vect_build_slp_tree_1): ... and here. Use vectype to
guide splitting for BB vectorization.
2026-08-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree_1): Hard-fail early
due to BB SLP unrolling.
2026-08-24 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126896
* tree-ssa-threadedge.cc
(edge_forwards_cmp_to_conditional_jump_through_empty_bb_p): Make
static. Split into...
(cond_on_phi_p): ...this...
(phi_arg_from_cmp_p): ...and this.
* tree-ssa-threadedge.h (cond_on_phi_p): Declare.
(phi_arg_from_cmp_p): Declare.
2026-08-24 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126896
* cfghooks.cc (can_duplicate_block_on_edge_p): New.
* cfghooks.h (can_duplicate_block_on_edge_p): Declare.
* tree-ssa-threadedge.cc: Include cfghooks.h.
(jump_threader::thread_across_edge): Use
can_duplicate_block_on_edge_p.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/127018
* tree-vect-slp.cc (vect_schedule_scc): For SCCs of
multiple components update the scheduling state and
propagate it to all nodes.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/127018
* tree-vect-slp.cc (slp_scc_info::res): New member.
(vect_schedule_scc): Initialize res for invariants
and when pushing to the stack. Record result for
singletons and look it up for already visited entries.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/127000
* match.pd ((T *)(ptr - ptr_cst)): Use build1 to build
an ADDR_EXPR.
* tree-ssa-sccvn.cc (vn_nary_build_or_lookup_1): Avoid
creating GIMPLE_SINGLE_RHS to insert stmts.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/126984
* tree-vect-slp-patterns.cc (complex_pattern::build):
Rename to ...
(complex_pattern::build_common): ... this.
(complex_pattern::build): Likewise and adjust.
(complex_pattern::m_rep): New.
(complex_pattern::complex_pattern): Initialize m_rep.
(complex_add_pattern::build): Call build_common instead
of complex_pattern::build.
(complex_mul_pattern::build): Likewise.
(complex_fms_pattern::build): Likewise.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/126995
* tree-vect-slp.cc (vect_schedule_slp_node): Keep
schedule when we schedule to a point dominated by the
trapping stmt.
2026-08-24 H.J. Lu <hjl.tools@gmail.com>
PR target/126933
* config/i386/i386-expand.cc (ix86_expand_truncsfbf2): New.
* config/i386/i386-protos.h (ix86_expand_truncsfbf2): Likewise.
* config/i386/i386.md (truncsfbf2): Changed to define_expand
and update comments.
(truncsfbf2_vcvtneps2bf16): New.
2026-08-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/126997
* tree-ssa-loop-unswitch.cc (tree_ssa_unswitch_loops):
Perform invariant motion when we unswitched a loop.
2026-08-24 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/driver-riscv.cc (riscv_arch_from_hwprobe): Use
RISCV_HWPROBE_EXT_V rather than the removed RISCV_HWPROBE_IMA_V.
2026-08-24 Kyrylo Tkachov <ktkachov@nvidia.com>
* Makefile.in (check_p_min_slots, check_p_jobs, check_p_slots): New
variables.
(check_p_subdirs): Use check_p_slots.
2026-08-24 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* ipa-cp.cc (adjust_clone_incoming_counts): Adjust counts only when
ipa quality.
2026-08-24 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Add sifive-p550 and
sifive-p870-d.
(RISCV_CORE): Add sifive-p550 and sifive-p870-d.
* config/riscv/riscv.cc (sifive_p550_tune_info): New.
(sifive_p870_tune_info): New.
* doc/riscv-mcpu.texi: Regenerate.
* doc/riscv-mtune.texi: Regenerate.
2026-08-24 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc (standard_extensions_p):
Rename to...
(riscv_ext_is_known_p): ...this, and export.
(riscv_subset_list::parse_single_std_ext): Update the callers.
(riscv_subset_list::parse_single_multiletter_ext): Likewise.
* config/riscv/riscv-subset.h (riscv_ext_is_known_p): Declare.
* config/riscv/driver-riscv.cc: Include riscv-subset.h.
(riscv_native_arch): Split the hwprobe half out into...
(riscv_arch_from_hwprobe): ...this new function.
(struct riscv_cpuinfo): New.
(riscv_cpuinfo_file, riscv_cpuinfo_forced, riscv_cpuinfo_cpu)
(riscv_cpuinfo_field, riscv_read_cpuinfo, riscv_cpuinfo)
(riscv_filter_isa, riscv_arch_from_cpuinfo): New functions.
* config/riscv/x-riscv: Update the dependencies.
2026-08-24 Kito Cheng <kito.cheng@sifive.com>
* config.host: Build driver-riscv.o for riscv*-*-linux* hosts.
* config/riscv/driver-riscv.cc: New file.
* config/riscv/x-riscv: New file.
* config/riscv/riscv.h (host_detect_local_cpu): Declare.
(HAVE_LOCAL_CPU_DETECT): Define.
(RISCV_NATIVE_SPEC_FUNCTIONS): Define.
(RISCV_NATIVE_SPECS): Define.
(EXTRA_SPEC_FUNCTIONS): Add RISCV_NATIVE_SPEC_FUNCTIONS.
(DRIVER_SELF_SPECS): Add RISCV_NATIVE_SPECS.
* doc/invoke.texi (RISC-V Options): Document -march=native.
2026-08-24 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-hwprobe.def: New file.
* common/config/riscv/riscv-hwprobe.h: New file.
2026-08-24 vekumar <Venkataramanan.Kumar@amd.com>
* config/i386/x86-tune-costs.h (znver4_cost): Increase branch
mispredict scale from COSTS_N_INSNS (2) to COSTS_N_INSNS (2) + 3.
(znver5_cost): Likewise.
2026-08-23 Georg-Johann Lay <avr@gjlay.de>
PR target/127004
* config/avr/avr-passes.cc (rtl-iter.h): Include.
(insninfo_t::scratch_mask): New method.
(optimize_data_t::try_split_ldi): Use it for ignore_mask.
(optimize_data_t::try_split_any): Same.
(optimize_data_t::emit_sequence): Dump ignore_mask prior to
calling fatal_insn.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (struct long_mul_summand): Add
constructors and methods and operator bool.
(long_mul_set_summand): Rename to ...
(long_mul_summand::set): This. Remove the info argument.
(long_mul_classify_carry): Rename to ...
(long_mul_summand::classify_carry): This. Remove the
info argument.
(long_mul_classify_plus_kinds): Rename to ...
(long_mul_summand::classify_plus_kinds): This. Remove the
info argument.
(long_mul_classify_hi_extract): Rename to ...
(long_mul_summand::classify_hi_extract): This. Remove the
info argument.
(long_mul_classify_lo_extract): Rename to ...
(long_mul_summand::classify_lo_extract): This. Remove the
info argument.
(long_mul_classify_shl_extract): Rename to ...
(long_mul_summand::classify_shl_extract): This. Remove the
info argument.
(long_mul_classify_bare): Rename to ...
(long_mul_summand::classify_bare): This. Remove the
info argument.
(long_mul_classify_summand): Rename to ...
(long_mul_summand::long_mul_summand): This. Remove the
info argument.
(long_mul_classify_chain): Update for the long_mul_summand
constructor.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (enum long_mul_kind): Add LMK_INVALID.
(long_mul_set_summand): Add default case to switch.
(long_mul_summand_compare): Add checking to make sure
the kinds are not LMK_INVALID.
(long_mul_find_summand): Likewise.
(long_mul_classify_chain): Add checking right before
the push to check for LMK_INVALID.
(match_long_mul_phi): Simpilify stynx for initializing carry.
2026-08-23 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/59429
* match.pd: Combine four loops into one loop for spaceship.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (enum long_mul_kind): Fix to unsigned char.
(enum long_mul_extract): Likewise.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (enum long_mul_kind): Put in an anonymous namespace.
(enum long_mul_extract): Likewise.
(struct long_mul_summand): Likewise.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (long_mul_set_summand): Update
comment on the shift.
2026-08-23 Kyrylo Tkachov <ktkachov@nvidia.com>
* combine.cc (combine_simplify_rtx): Handle PREFETCH like MEM when
simplifying the address.
2026-08-23 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/126501
PR rtl-optimization/126747
* ifcvt.cc (noce_cc_reg_set): New struct.
(noce_record_cc_reg_set): New function.
(noce_clobbers_live_cc_p): New function.
(end_ifcvt_sequence): Use it to reject sequences that clobber a
condition-code register that is live out of the test block.
(noce_convert_multiple_sets): Likewise.
2026-08-23 Kyrylo Tkachov <ktkachov@nvidia.com>
* compare-elim.cc (find_comparisons_in_bb): Test the live-in set
of the successor block rather than of the current block.
2026-08-23 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv.cc (struct riscv_tune_param): New member.
(xt_c9501_tune_info): Set autoprefetcher model to weak.
(riscv_override_options_internal): Set
param_sched_autopref_queue_depth based on autoprefetcher model.
2026-08-23 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126827
* gimple-range-op.cc (class cfn_fp_nonnegative): New class.
(class cfn_fp_nonnegative_arg0): New class.
(gimple_range_op_handler::maybe_builtin_call): Handle some
functions which were handled in nonnegative.
2026-08-23 Dominic P <gcc@gcc.dp11.uk>
PR target/71048
* expmed.cc (store_fixed_bit_field_1): When OP0 is a memory
reference that the field fills entirely, store VALUE directly
instead of doing a read-modify-write, so that no read of OP0 is
emitted.
2026-08-23 Dominic P <gcc@gcc.dp11.uk>
* expmed.cc (last_div_const): New variable, moved out of...
(expand_divmod): ...here.
* expmed.h (last_div_const): Declare.
* function.cc (prepare_function_start): Reset last_div_const.
2026-08-23 Dominic P <gcc@gcc.dp11.uk>
PR tree-optimization/111000
* tree-ssa-loop-im.cc (movement_possibility_1): Require
MOVE_PRESERVE_EXECUTION for an out-of-range constant shift
count, not an in-range one.
2026-08-23 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-22 Luke Zhuang <luke.zhuang@linux.alibaba.com>
* config/riscv/riscv.md: Restrict slliw shifted bitfield split
to extractions starting at bit 0, and require the outer mask to
match slliw sign-extension.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (struct long_mul_summand): Change
hilo{0,1,2} into an array.
(long_mul_set_summand): Use a copy loop instead of written out.
(long_mul_check_consistency): Use the array directly instead
of a local copy of the loop for the range for loop.
(match_long_mul_phi): Replace `hilo0` with `hilo[0]`.
Replace `hilo1` with `hilo[1]`. Replace `hilo2` with `hilo[2]`.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (mul_carry_low_sum): Remove @1 from
the result captures. Rename @0 to @shift0.
(mul_low_accum): Likewise.
(mul_ladder_sum1): Likewise.
(mul_ladder_sum2): Likewise.
(mul_ladder_sum3): Likewise.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (mul_carry_cross_sum): Use wi::to_wide instead
of tree_to_uhwi.
(long_mul_high_chain): Likewise and use `% 4`.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (mul_hilo): Remove INTEGER_CST check on the operands.
(mul_lolo): Likewise.
(mul_hihi): Likewise.
(mul_low_accum): Likewise.
(mul_ladder_sum1): Likewise.
(mul_ladder_sum2): Likewise.
(mul_ladder_sum3): Likewise.
(mul_carry_low_sum): Likewise.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (mul_cross_sum): Remove the `:c` from the plus.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-forwprop.cc (match_long_mul_phi): Swap the shift
amount check with gimple_mul_low_sum/gimple_mul_cross_sum
checks.
2026-08-22 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (cond_carry_add_neg): Rename to
cond_carry_add.
* tree-ssa-forwprop.cc (gimple_cond_carry_add_neg): Remove.
(match_long_mul_phi): Don't call gimple_cond_carry_add_neg.
2026-08-21 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126958
* match.pd (mul_hi): Use wi::to_wide instead of
tree_fits_uhwi_p/tree_to_uhwi.
(mul_lo): Likewise.
2026-08-21 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126957
* match.pd (mul_carry_low_sum): Remove `?` from convert.
(mul_carry_cross_sum): Likewise.
2026-08-21 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126956
* match.pd (cond_carry_add): Use `:c` instead of manually
swapping the comparison and operands.
(cond_carry_add_neg): Likewise.
2026-08-21 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/126955
* match.pd: Remove extra `#if GIMPLE`/`#endif` pair.
2026-08-21 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126954
* match.pd (mul_ladder_sum1): Change over to match syntax
instead of doing it manually.
2026-08-21 Tamar Christina <tamar.christina@arm.com>
* value-query.cc (range_query::get_tree_range): Add bitmask back to
VARYING case.
2026-08-21 Jin Ma <jinma@linux.alibaba.com>
PR target/126873
* config/riscv/autovec.md (vec_set<mode>): Zero-extend a
sub-Pmode index to Pmode.
(vec_extract<mode><vel>): Likewise.
2026-08-21 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.cc (aarch64_poly_int_indeterminate_bound): New.
(TARGET_POLY_INT_INDETERMINATE_BOUND): Implement hook using it.
2026-08-21 Tamar Christina <tamar.christina@arm.com>
* target.def (poly_int_indeterminate_bound): New.
* doc/tm.texi.in: Document it.
* doc/tm.texi: Regenerate.
* value-query.cc (range_query::get_tree_range): Use it.
2026-08-21 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/iterators.md (vnarrowq): Delete.
* config/aarch64/aarch64-simd.md
(<sat_trunc_op>trunc<mode><vnarrowq>2): Rename to...
(<sat_trunc_op>trunc<mode><Vnarrowq>2): ... this.
2026-08-21 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64.cc (aarch64_hard_regno_nregs,
aarch64_class_max_nregs): Handle `FP_HI_REGS`.
* config/aarch64/aarch64-acle-builtins.h (mop4_base,
mop4_b16b16, mop4_f8f16, mop4_f8f32, mop4_f64f64,
mop4_i16i64): New type arrays.
* config/aarch64/aarch64.h (reg_class::FP_HI_REGS): New enum member.
* config/aarch64/aarch64-sve-builtins-shapes.cc (struct mop4_def): New function shape.
* config/aarch64/aarch64-sve-builtins-shapes.h: New function shape.
* config/aarch64/aarch64-sve-builtins-sme.def (DEF_SME_FUNCTION):
Unconditionally define in terms of `DEF_SME_FUNCTION_GS`.
(DEF_SME_ZA_FUNCTION_GS): Unconditionally define in terms of `DEF_SME_ZA_FUNCTION_GS_FPM`.
(DEF_SME_ZA_FUNCTION): Unconditionally define in terms of `DEF_SME_ZA_FUNCTION_GS`.
(svmop4a, svmop4s): New function groups.
(DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION_GS_FPM): New
macros.
* config/aarch64/aarch64-sve-builtins.def (1x1, 1x2, 2x1, 2x2):
New SVE function modes.
* config/aarch64/constraints.md (z, Ux2, Uxz): New register
constraints.
* config/aarch64/aarch64-sme.md (@aarch64_mop4_): New insns.
* config/aarch64/aarch64-sve-builtins-functions.h (class sme_mop4): New function base.
* config/aarch64/aarch64-sve-builtins-sme.cc (svmop4a_za,
svmop4s_za): New functions.
* config/aarch64/aarch64-sve-builtins-sme.h (svmop4a_za,
svmop4s_za): New function bases.
* config/aarch64/iterators.md: New mode iterators.
(UNSPEC_SME_FMOP4A, UNSPEC_SME_FMOP4S, UNSPEC_SME_UMOP4A,
UNSPEC_SME_UMOP4S, UNSPEC_SME_SMOP4A, UNSPEC_SME_SMOP4S,
UNSPEC_SME_SUMOP4A, UNSPEC_SME_SUMOP4S, UNSPEC_SME_USMOP4A,
UNSPEC_SME_USMOP4S): New unspecs.
(SME_FP_MOP4, SME_FP8_MOP4, SME_INT_MOP4): New int iterators.
2026-08-21 Karl Meakin <karl.meakin@arm.com>
* doc/invoke.texi: Document new extension flags.
* config/aarch64/aarch64.h (TARGET_SME_MOP4): New target macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
`__ARM_FEATURE_SME_MOP4` macros when the relevant extension is enabled.
2026-08-21 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/constraints.md: Fix comments.
2026-08-21 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126856
* value-relation.cc (dom_oracle::dom_oracle): Create m_block_list.
(dom_oracle::~dom_oracle): Free m_block_list.
(relation_chain_head::clear): Decrease the number of relations.
(dom_oracle::clear): Walk the block_list looking for relations.
(dom_oracle::record_relation_block): New.
(dom_oracle::create_relation_in_bb): call record_relation_block.
* value-relation.h (dom_oracle::m_block_list): New.
(record_relation_block): Declare.
2026-08-21 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126856
* value-relation.cc (equiv_oracle::equiv_oracle): Adjust for
rename from m_self_equiv to m_name_info.
(equiv_oracle::~equiv_oracle): Likewise.
(equiv_oracle::register_equiv_block): New.
(equiv_oracle::equiv_set): Adjust for rename.
(equiv_oracle::register_equiv): Call register_equiv_block.
(equiv_oracle::clear): Process just the required blocks.
(equiv_oracle::add_equiv_to_block): Call register_equiv_block.
* value-relation.h (class name_info): New.
(equiv_oracle::m_self_equiv): Change type and Rename to m_name_info.
(register_equiv_block): Declare.
2026-08-21 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126856
* gimple-range-infer.cc (exit_range::name_link): New.
(infer_range_manager::infer_range_manager): Adjust for rename
from m_nonzero to m_name_info.
(infer_range_manager::~infer_range_manager): Likewise.
(infer_range_manager::get_nonzero): Likewise
(infer_range_manager::add_range): Add to name_link list.
(infer_range_manager::clear): Walk name_link list.
* gimple-range-infer.h (class ssa_name_link): New vec.
(infer_range_manager::m_nonzero): Retype and rename to m_name_info.
2026-08-21 Kyrylo Tkachov <ktkachov@nvidia.com>
* gimple-fold.cc (gimple_fold_builtin_fwrite): New function.
(gimple_fold_builtin): Call it for BUILT_IN_FWRITE and
BUILT_IN_FWRITE_UNLOCKED.
2026-08-21 Kyrylo Tkachov <ktkachov@nvidia.com>
PR sanitizer/88109
* tree.h (TYPE_OVERFLOW_SANITIZED): Use ANY_INTEGRAL_TYPE_P.
2026-08-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/126979
* tree-vect-slp-patterns.cc (compatible_complex_nodes_p):
Special case VEC_PERM nodes.
2026-08-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/126965
* tree-ssa-pre.cc (find_or_generate_expression): Limit
recursion depth.
2026-08-21 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_slp_tree::max_nunits): Remove.
(vect_update_max_nunits): Likewise.
* tree-vect-slp.cc (_slp_tree::_slp_tree): Adjust.
(vect_record_max_nunits): Rename to ...
(vect_record_vectype): ... this and adjust.
(vect_build_slp_tree_1): Drop max_nunits argument and adjust.
(vect_build_slp_tree_2): Likewise.
(vect_build_slp_tree): Likewise.
(vect_build_slp_store_interleaving): Likewise.
(vect_print_slp_tree): Adjust.
(optimize_load_redistribution_1): Likewise.
(vect_build_slp_instance): Likewise.
(vect_analyze_slp_reduc_chain): Likewise.
(vect_analyze_slp_reduction): Likewise.
(vect_analyze_slp_reduction_group): Likewise.
(vect_analyze_slp_instance): Likewise.
(vect_lower_load_permutations): Likewise.
2026-08-21 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_update_slp_vf_for_node): Compute
VF based on SLP_TREE_VECTYPE only.
(vect_get_num_copies_for_invariant): New.
(vect_prologue_cost_for_slp): Take nvectors as argument.
(vect_slp_analyze_node_operations): Verify that we can
div_away_from_zero for vect_prologue_cost_for_slp.
(vect_create_constant_vectors): Use vect_get_num_copies_for_invariant.
* tree-vect-stmts.cc (vect_create_vectorized_promotion_stmts):
Support creating half of the promoted results.
(vectorizable_conversion): When we have excess input elements
request half of the promoted results.
2026-08-21 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/126686
* avoid-store-forwarding.cc
(store_forwarding_analyzer::avoid_store_forwarding): Reject
BLKmode stores and loads as forwarding candidates.
2026-08-21 Richard Biener <rguenther@suse.de>
* tree-ssa-pre.cc (get_or_alloc_expr_for_nary): Assert we
do not try to encode a SSA name or a constant as NARY.
(phi_translate_1): Save the translated NARY so we can
restore it if we want to reject a simplification to a
SSA name.
2026-08-21 H.J. Lu <hjl.tools@gmail.com>
PR target/126959
* config/i386/i386.cc (ix86_preferred_reload_class): Allow
minus ones for MASK register and standard SSE constants for
SSE register.
2026-08-21 Jojo R <rjiejie@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_optab_supported_p): New function.
(TARGET_OPTAB_SUPPORTED_P): Define.
2026-08-21 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.cc (riscv_pass_aggregate_in_vr): Return
NULL_RTX for an aggregate with no field.
2026-08-21 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_slp_node_weight): Add comment
indicating bbs[0] fallback is imprecise.
(vect_optimize_slp_pass::containing_loop): Likewise.
2026-08-21 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-fusion.cc (riscv_fuse_cache_aligned_std):
Remove.
(riscv_fusion_table): Remove its entry.
* config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Remove
RISCV_FUSE_CACHE_ALIGNED_STD.
2026-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
* tree-profile.cc (split_update_decision_counter): New.
(instrument_decisions): Use counter_update to determine which
atomic operations are available. Use
split_update_decision_counter() if 64-bit atomic operations can
be split up into two 32-bit atomic operations.
2026-08-21 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* cgraph.cc (cgraph_node::scale_profile_to): Apply the computed scale.
2026-08-21 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* auto-profile.cc (afdo_calculate_branch_prob): Set a zero entry
block count to half a scaled sample after adjusting guessed profiles.
2026-08-20 Egas Ribeiro <egas.g.ribeiro@gmail.com>
* doc/analyzer.texi (Region Model): Use malloc (n) in the
example to match the dump; fix the frame for the result_4
cluster; correct the heap region number; note that heap region
numbering depends on traversal order.
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64.cc (aarch64_evpc_splice): New function.
(aarch64_expand_vec_perm_const_1): Use it.
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/122069
* tree-vect-patterns.cc (vect_recog_widen_sum_pattern): Try wider
intermediate input types.
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
Revert:
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/122069
* tree-vect-patterns.cc (vect_recog_widen_sum_pattern): Try wider
intermediate input types.
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/122069
* tree-vect-patterns.cc (vect_recog_widen_sum_pattern): Try wider
intermediate input types.
2026-08-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-simd.md (bitreverse<mode>2): New expander
for VDQHS.
(ctz<mode>2): Replace the VB and VS expanders with one for
VDQ_BHSI.
2026-08-20 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126961
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Fix remainder use
and add signedness check.
2026-08-20 Jakub Jelinek <jakub@redhat.com>
PR debug/126801
* opts.cc (finish_options): Don't set flag_var_tracking_uninit to
flag_var_tracking by default. Instead, set flag_var_tracking to
flag_var_tracking_uninit if the latter was explicitly set.
* config/darwin.cc (darwin_override_options): Only set
flag_var_tracking_uninit if it wasn't explicitly set and set it to
1 rather than flag_var_tracking. Formatting fix.
2026-08-20 Paul-Antoine Arras <parras@baylibre.com>
* common.opt (fopenmp-ompt): Turn into an alias for
-fopenmp-ompt=basic.
(fopenmp-ompt=): New option, replacing fopenmp-ompt{,-detailed}.
* common.opt.urls: Regenerate.
* doc/invoke.texi (-fopenmp-ompt): Document the new levels and
drop -fopenmp-ompt-detailed.
* flag-types.h (enum omp_ompt_level): New.
* omp-expand.cc (expand_omp_for_static_nochunk,
expand_omp_for_static_chunk): Check flag_openmp_ompt against
OMP_OMPT_LEVEL_EXTENDED instead of flag_openmp_ompt_detailed.
* opts.cc (finish_options): Adjust diagnostic for the removal of
-fopenmp-ompt-detailed.
2026-08-20 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-log.cc (INCLUDE_ALGORITHM): Define for std::min.
(avr_log_operands, avr_log_operand): New static functions.
(avr_log_node): Support ADDR_EXPR, POINTER_PLUS_EXPR,
POINTER_DIFF_EXPR, ADDR_SPACE_CONVERT_EXPR, CONVERT_EXPR,
NOP_EXPR, MEM_REF, CONSTRUCTOR.
2026-08-20 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/126775
* match.pd (0.0 - x -> -x): Use new real_negzerop function.
* tree.cc (real_negzerop): New predicate function to test if
a tree expression is -0.0 or equivalent (like real_zerop).
* tree.h (real_negzerop): Prototype here.
2026-08-20 Shivam Gupta <shivam98.tkg@gmail.com>
* match.pd: Add simplifications for XORs and boolean
comparisons of zero_one_valued comparisons against zero.
2026-08-20 Richard Biener <rguenther@suse.de>
* tree.cc (tree_nop_conversion_p): Special case two BLKmode
types.
2026-08-20 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/112104
* tree-scalar-evolution.cc (analyze_and_compute_bitop_with_inv_effect):
Handle BIT_XOR_EXPR with a variable trip count.
2026-08-20 Manjunath Matti <mmatti@linux.ibm.com>
PR middle-end/126939
* gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
Take the address of the memmove source operand.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/107090
PR tree-optimization/126642
* match.pd (long_mul_high_chain): New atom for the emitted high-part chain.
* tree-ssa-forwprop.cc (long_mul_classify_match): Gate the
HIGH_PART wide-chain emit on optimize_widening_mul_active_p
rather than on the target having a 2N multiply.
* tree-ssa-math-opts.cc (can_widen_to_narrow_p): New.
(build_long_mul_partials): New; emits the four partial products
using widening or plain multiplies.
(emit_long_mul_highpart): New; the high N bits of an N-bit
product, as a longhand over (N/2)-bit partials.
(combine_long_mul_halves): New; the high N bits of a product of
two 2N-bit values given as N-bit halves.
(long_mul_op_fits_p): New; true when an operand is provably
representable in narrow_prec unsigned bits.
(long_mul_split_operand): New; splits an operand into N-bit
halves using only N-bit operations.
(struct long_mul_halves): New; the halves an operand PHI was
split into.
(struct long_mul_arg_split): New; an argument of an operand PHI
with the statements that split it.
(long_mul_split_phi): New; splits an operand PHI by splitting its
arguments and merging the halves with two new PHIs. Record the
halves and reuse them for the next consumer of the same PHI.
(long_mul_high_half_uses): New; collects the `>> N' uses forming
a product's high half.
(long_mul_only_low_half_used_p): New.
(unexpandable_long_mul_p): New; true for a 2N multiply in a mode
the target cannot multiply.
(narrow_long_mul_low_half): New; narrow a 2N low-half-only mult
the target cannot expand to an N-bit mult.
(narrow_long_mul_operands): New; recurse into chained wide
products after a narrowing/lowering.
(finish_long_mul_low_half): New; narrows or removes a 2N mult
whose high half is synthesized elsewhere.
(narrow_long_mul_halves): New; rewrites a 2N multiply into the
N-bit halves its uses read.
(gimple_long_mul_high_chain): Declare.
(lower_long_mul_high_chain): New; lowers the high-part chain to a
longhand at narrow precision. Split each operand into N-bit
halves and combine, handling an operand wider than narrow_prec
instead of rejecting it. Narrow or drop the residual 2N mult via
the helpers and recurse into its operands.
(optimize_widening_mul_active_p): New; shared gate used by
pass_optimize_widening_mul::gate and by the forwprop long-multiply
recognizer. Return false when optimize_debug.
(math_opts_dom_walker::after_dom_children): Dispatch to
lower_long_mul_high_chain on the outer convert. Run
narrow_long_mul_low_half on MULT_EXPR before the widen/fma
conversion attempts.
(pass_optimize_widening_mul::execute): Sweep the function for
multiplies left in a mode the target cannot expand. Scope the
record of split operand PHIs to one run of the pass.
* tree-ssa-math-opts.h (optimize_widening_mul_active_p): Declare.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/107090
* match.pd: Add cond_carry_add and cond_carry_add_neg match
recognizers for the 2-arg PHI form PHI<base + pow2, base>,
one per gcond polarity.
* tree-ssa-forwprop.cc (gimple_cond_carry_add): Declare.
(gimple_cond_carry_add_neg): Likewise.
(long_mul_check_low_plus_defer): Note that the PHI entry commits
only to HIGH_PART rows.
(long_mul_classify_match): Take the candidate statement for the
per-row checks.
(long_mul_classify_chain): Take an optional pre-classified extra
summand, for the carry the PHI entry synthesizes.
(match_long_mul): Adjust.
(match_long_mul_phi): New PHI-driven entry; recognizes a
cond_carry_add(_neg) PHI and folds the long-multiply
when the rest of the high-part chain matches.
(pass_forwprop::execute): Call match_long_mul_phi on each
PHI in the degenerate-PHI walk.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/107090
* tree-ssa-forwprop.cc (long_mul_check_low_plus_defer): New
helper, defers the fold when any GT/LT/GE/LE use shares an
operand with the PLUS; gates the LOW_PART PLUS_EXPR row added
to long_mul_table.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/107090
* match.pd: Add mul_ladder_sum1, mul_ladder_sum2,
mul_ladder_sum3 and mul_ladder_part_sum atom recognizers.
* tree-ssa-forwprop.cc (gimple_mul_ladder_sum1): Declare.
(gimple_mul_ladder_sum2): Likewise.
(gimple_mul_ladder_sum3): Likewise.
(gimple_mul_ladder_part_sum): Likewise.
(enum long_mul_kind): Add LMK_LADDER_SUM1 / LMK_LADDER_SUM2
/ LMK_LADDER_SUM3 / LMK_LADDER_PART_SUM, with the
long_mul_table HIGH_PART and LOW_PART rows for each ladder
form.
(long_mul_set_summand): Handle the new kinds.
(long_mul_classify_carry): Update the specificity note above
long_mul_classify_plus_kinds.
(long_mul_classify_plus_kinds): Try mul_ladder_sum3 and
mul_ladder_sum1 before mul_low_sum (more-constrained
first); add mul_ladder_sum2.
(long_mul_classify_hi_extract): Add mul_ladder_part_sum
branch.
(long_mul_classify_lo_extract): Adjust.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/107090
* match.pd: Add mul_carry_low atom recognizer.
* tree-ssa-forwprop.cc (gimple_mul_carry_low): Declare.
(enum long_mul_kind): Add LMK_CARRY_LOW.
(struct long_mul_summand): Add carry_a / carry_b for the
LMK_CARRY_LOW summand's two operands.
(long_mul_set_summand): Handle LMK_CARRY_LOW.
(long_mul_classify_carry): Try mul_carry_low after the
more-constrained mul_carry_low_sum / mul_carry_cross_sum.
(long_mul_find_summand): New helper, find the first summand
with a given kind.
(long_mul_check_two_carries): New extra check, validates the
LMK_CARRY_LOW summand's operands against the canonical
(op0, op1); gates the two-carry HIGH_PART row added to
long_mul_table.
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/107090
* match.pd: Add mul_low_sum and mul_carry_low_sum atom
recognizers.
* tree-ssa-forwprop.cc (gimple_mul_low_sum): Declare.
(gimple_mul_carry_low_sum): Likewise.
(create_mul_low_seq): Update the widest-atom note above
LONG_MUL_MAX_CAPTURES to mul_carry_low_sum (7 captures).
(enum long_mul_kind): Add LMK_LOW_SUM and LMK_CARRY_LOW_SUM,
with the long_mul_table HIGH_PART and LOW_PART rows that
consume them.
(long_mul_set_summand): Handle the new kinds.
(long_mul_classify_carry): Try mul_carry_low_sum before
mul_carry_cross_sum (most-specific first).
(long_mul_classify_plus_kinds): Try mul_low_sum after
mul_low_accum (mul_low_sum's first arm is any plus and
mul_low_accum constrains both arms).
2026-08-19 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/107090
* match.pd: Add atom match recognizers for long-multiply
(mul_hi, mul_lo, mul_hilo, mul_lolo, mul_hihi, mul_cross_sum,
mul_low_accum, mul_carry_cross_sum).
* tree-ssa-forwprop.cc (gimple_mul_hi): Declare.
(gimple_mul_lo): Likewise.
(gimple_mul_hilo): Likewise.
(gimple_mul_lolo): Likewise.
(gimple_mul_hihi): Likewise.
(gimple_mul_cross_sum): Likewise.
(gimple_mul_low_accum): Likewise.
(gimple_mul_carry_cross_sum): Likewise.
(build_mul_high_seq): New, emits (N)(((2N) op1 * (2N) op2) >> N)
into a caller-supplied destination.
(long_mul_apply_extras): New, combines the preserved addends back
on top of the folded multiply.
(create_mul_high_seq): New, replaces the statement with the
high-part multiply plus any extras.
(create_mul_low_seq): New, likewise for the low part.
(enum long_mul_kind): New.
(enum long_mul_extract): New.
(struct long_mul_summand): New.
(long_mul_linearize_chain): New, walks the outer add/ior chain
into a multiset of leaves.
(long_mul_is_lshift_def): New.
(long_mul_set_summand): New.
(long_mul_classify_carry): New.
(long_mul_classify_plus_kinds): New.
(long_mul_classify_hi_extract): New.
(long_mul_classify_lo_extract): New.
(long_mul_classify_shl_extract): New.
(long_mul_classify_bare): New.
(long_mul_classify_summand): New, classify each summand via the
match.pd atoms.
(long_mul_summand_compare): New.
(struct long_mul_row): New.
(long_mul_same_ops): New.
(long_mul_is_cross_half): New.
(long_mul_hilo_orientation): New, orientation of a mul_hilo
capture relative to (op0, op1).
(long_mul_canonical_ops): New.
(long_mul_check_consistency): New, cross-summand consistency
check (operand pairing, half-width shifts, hilo cross-half).
(long_mul_signature_matches): New.
(long_mul_hint_shared_intermediate): New, dump-file hint
pointing at a shared inner addition.
(long_mul_classify_match): New, looks a summand multiset up in
long_mul_table and runs the per-row checks.
(long_mul_classify_chain): New, linearize plus classify plus
table lookup; sets aside leaves that classify as no summand.
(match_long_mul): New, top-level entry: starts only at a chain
end, classifies the chain, and dispatches to create_mul_high_seq
/ create_mul_low_seq with any preserved addends.
(pass_forwprop::execute): Call match_long_mul on PLUS_EXPR and
BIT_IOR_EXPR statements.
2026-08-19 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126934
* range-op.cc (operator_div::op1_op2_relation_effect): Fix
for ops range being negative with VREL_LT.
2026-08-19 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/iterators.md (vnarrowq): New mode attribute.
(sat_trunc_op): New code attribute.
* config/aarch64/aarch64-simd.md (<sat_trunc_op>trunc<mode><vnarrowq>2):
New expander.
2026-08-19 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sys-regs.def: Sync from Binutils.
2026-08-19 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.h (LINK_COMMAND_SPEC_A): Synchronise the
options for coverage with gcc/gcc.cc.
2026-08-19 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-simd.md (aarch64_cm<optab>di): Accept a
zero second operand in the general register alternative.
2026-08-19 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/125557
* ifcvt.cc (average_cost): Scale a nonnegative cost difference using
the probability of the more expensive arm.
2026-08-19 Kyrylo Tkachov <ktkachov@nvidia.com>
* profile-count.h (profile_probability::apply): Scale an unsigned
magnitude with safe_scale_64bit.
* profile-count.cc (test_profile_probability_apply): New.
(profile_count_cc_tests): New.
* selftest.h (profile_count_cc_tests): Declare.
* selftest-run-tests.cc (selftest::run_tests): Run it.
2026-08-19 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_instance): Remove dead code.
(vect_analyze_slp_instance): Likewise.
2026-08-19 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_print_slp_tree): Dump the scheduling
point, if set.
2026-08-19 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_optimize_slp_pass::containing_loop):
For nodes w/o representative use the region entry block
to indicate the containing loop.
2026-08-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/126936
* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Exclude
use_stmt from dominance check.
(vect_schedule_slp): Likewise for root.
2026-08-19 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_slp_build_two_operator_nodes):
Set SLP_TREE_REPRESENTATIVE to NULL for the permute nodes.
(vect_build_slp_tree_2): Likewise.
(vect_build_slp_store_interleaving): Likewise.
(vect_lower_load_permutations): Likewise.
(vect_optimize_slp_pass::get_result_with_layout): Likewise.
(vect_cse_slp_node_parts): Deal with NULL SLP_TREE_REPRESENTATIVE
for VEC_PERM nodes.
(vect_slp_analyze_node_operations_1): Assert permute nodes
do not have SLP_TREE_REPRESENTATIVE set.
* tree-vect-slp-patterns.cc (complex_pattern::build): Adjust.
(vect_build_swap_evenodd_node): Do not set SLP_TREE_REPRESENTATIVE.
(vect_build_combine_node): Likewise.
2026-08-19 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_slp_node_weight): Get vinfo as
context. For nodes without representative use the
region entry block.
(vect_optimize_slp_pass::start_choosing_layouts): Always
assign vertex weight.
2026-08-19 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/126597
* config/aarch64/aarch64.cc (aarch64_expand_vec_perm_const_1): Swap
zero_op0_p and zero_op1_p along with the operands.
2026-08-19 Richard Biener <rguenther@suse.de>
PR ipa/126930
* tree-ssa-alias.cc (ptr_deref_may_alias_global_p): Guard
against non-pointers.
(ptr_deref_may_alias_auto_p): Likewise.
2026-08-18 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126856
* gimple-range-cache.cc (block_range_cache::clear): New.
(ranger_cache::reset_range_info): New.
* gimple-range-cache.h (block_range_cache::clear): Declare.
(ranger_cache::reset_range_info): Declare.
* gimple-range-gori.cc (range_def_chain::clear): New.
* gimple-range-gori.h (range_def_chain::clear): Declare.
* gimple-range-infer.cc (infer_range_manager::clear): New.
* gimple-range-infer.h (infer_oracle::clear): New virtual function.
(infer_range_manager::clear): Override.
* gimple-range.cc (gimple_ranger::reset_range_info): New.
* gimple-range.h (gimple_ranger::reset_range_info): Declare.
* tree-ssa-dce.cc (simple_dce_from_worklist): Reset flow-sensitive
information when replacing a definition.
* tree-ssanames.cc (reset_flow_sensitive_info): Reset information
maintained by the current range query.
* value-query.cc (range_query::reset_range_info): New.
* value-query.h (range_query::reset_range_info): Declare.
* value-relation.cc (equiv_oracle::clear): New.
(relation_chain_head::clear): New.
(dom_oracle::clear): New.
(path_oracle::clear): New.
* value-relation.h (relation_oracle::clear): New virtual function.
(equiv_oracle::clear): Override.
(relation_chain_head::clear): Declare.
(dom_oracle::clear): Override.
(path_oracle::clear): Override.
2026-08-18 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* auto-profile.cc (function_instance::match): Walk predecessor edges
for PHI arguments.
2026-08-18 Dylan Rees <dylan.rees@arm.com>
* config/aarch64/aarch64-sve-builtins-base.cc: fold method
created for 'svbrk_unary_impl'. Cases added for folding into
'ptrue' and 'pfalse' where appropriate and not folding where
unnecessary. Expand method of 'svpfirst_svpnext_impl' extended
to handle specific case where 'ptrue' should be emitted but in
a form where it can be recognised as a flag setting operation.
2026-08-18 Léo Hardt <leom.hardt@inf.ufrgs.br>
* final.cc (notice_source_line): Remove dead condition
for override_filename.
2026-08-18 Georg-Johann Lay <avr@gjlay.de>
* doc/extend.texi (Coverage Pragmas): Fix a typo.
(Size of an asm): Fix a typo.
2026-08-18 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.cc (alpha_option_override): Set alpha_fprm to
ALPHA_FPRM_DYN when flag_rounding_math is set, -mfp-rounding-mode
was not given explicitly and -mfloat-vax is not in effect.
* doc/invoke.texi (Alpha Options): Document the default rounding
mode and its interaction with -frounding-math.
2026-08-18 Kyrylo Tkachov <ktkachov@nvidia.com>
* Makefile.in ($(lang_checks_parallelized)): Only merge summaries
from instances that produced one, and warn about the others. Write
the merged files through a temporary and fail if the merge fails.
2026-08-18 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/iterators.md (optab): Map UNSPEC_COND_FRINTN to
roundeven.
2026-08-18 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Options): Sort alphabetically.
2026-08-18 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (struct _slp_tree): Amend documentation.
2026-08-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/126926
* tree-vect-slp.cc (vectorize_slp_instance_root_stmt): Only
replace the RHS of the vector constructing scalar stmt.
2026-08-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/126925
* tree-ssa-loop-ivopts.cc (create_new_iv): Avoid crashing
if the use IV is invariant.
2026-08-18 Dominic P <gcc@gcc.dp11.uk>
* match.pd ((X & C1) cmp 0 op (X & C2) cmp 0): Combine pairs of
single-bit tests of the same operand into a single compare of
the union mask.
2026-08-18 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126876
* gimple-range-path.cc
(path_range_query::internal_range_of_expr): Only call
range_defined_in_block at the current path position.
(path_range_query::range_defined_in_block): Assert the current
path position.
2026-08-18 H.J. Lu <hjl.tools@gmail.com>
PR middle-end/126784
* match.pd ((type) minmax ((wide_type) a, (wide_type) b)): Changed
to ...
(minmax ((wide_type) a, (wide_type) b)): This.
2026-08-18 Dominic P <gcc@gcc.dp11.uk>
* match.pd ((t * u) % u -> 0): New simplification.
2026-08-18 Shivam Gupta <shivam98.tkg@gmail.com>
PR tree-optimization/112533
* match.pd: Canonicalize boolean comparisons of masked pow2
bits into xor-mask tests.
2026-08-18 Josef Melcr <josef.melcr@suse.com>
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Remove
dead if statement checking for internal calls.
2026-08-18 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126906
* tree-ssa-threadupdate.h
(back_jt_path_registry::duplicate_thread_path): Add failure_reason
argument.
* tree-ssa-threadupdate.cc
(back_jt_path_registry::duplicate_thread_path): Set
FAILURE_REASON on the two failing exits.
(back_jt_path_registry::update_cfg): Cancel the path with the
reason when duplicate_thread_path fails.
2026-08-17 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Add mstrict-addr-space-subsets.
2026-08-17 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt (-mstrict-addr-space-subsets): New
target option.
* config/avr/avr.cc (avr_addr_space_subset_p): Use it.
* doc/invoke.texi (AVR Options): Document it.
2026-08-17 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h (_mm_cvtss_epi32_epi8): New intrin.
(_mm_mask_cvtss_epi32_epi8): Ditto.
(_mm_maskz_cvtss_epi32_epi8): Ditto.
(_mm_mask_cvtss_epi32_storeu_epi8): Ditto.
(_mm256_cvtss_epi32_epi8): Ditto.
(_mm256_mask_cvtss_epi32_epi8): Ditto.
(_mm256_maskz_cvtss_epi32_epi8): Ditto.
(_mm256_mask_cvtss_epi32_storeu_epi8): Ditto.
(_mm512_cvtss_epi32_epi8): Ditto.
(_mm512_mask_cvtss_epi32_epi8): Ditto.
(_mm512_maskz_cvtss_epi32_epi8): Ditto.
(_mm512_mask_cvtss_epi32_storeu_epi8): Ditto.
(_mm_unpack_epi8): Ditto.
(_mm_mask_unpack_epi8): Ditto.
(_mm_maskz_unpack_epi8): Ditto.
(_mm256_unpack_epi8): Ditto.
(_mm256_mask_unpack_epi8): Ditto.
(_mm256_maskz_unpack_epi8): Ditto.
(_mm512_unpack_epi8): Ditto.
(_mm512_mask_unpack_epi8): Ditto.
(_mm512_maskz_unpack_epi8): Ditto.
* config/i386/i386-builtin-types.def: New function types.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new function types
and reserved immediate check.
* config/i386/sse.md (vunpackb<mode><mask_name>): New.
(avx10v2aux_sym_truncatev4siv4qi2): Ditto.
(*avx10v2aux_sym_truncatev4siv4qi2): Ditto.
(avx10v2aux_sym_truncatev8siv8qi2): Ditto.
(*avx10v2aux_sym_truncatev8siv8qi2): Ditto.
(avx10v2aux_sym_truncatev4siv4qi2_mask): Ditto.
(*avx10v2aux_sym_truncatev4siv4qi2_mask): Ditto.
(avx10v2aux_sym_truncatev8siv8qi2_mask): Ditto.
(*avx10v2aux_sym_truncatev8siv8qi2_mask): Ditto.
(*avx10v2aux_sym_truncatev16siv16qi2): Ditto.
(avx10v2aux_sym_truncatev16siv16qi2_mask): Ditto.
(avx10v2aux_sym_truncatev16siv16qi2_mask_store): Ditto.
(*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_1): Ditto.
(*avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_store_2): Ditto.
(avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_1): Ditto.
(avx10v2aux_sym_truncate<mode>v<ssescalarnum>qi2_mask_store_2): Ditto.
2026-08-17 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/86937
* fold-const-call.cc (fold_const_call): fold
CFN_BUILT_IN_STRNLEN calls.
2026-08-17 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/126743
* range-op-mixed.h: declare.
* range-op.cc (operator_bitwise_or::op1_op2_relation_effect):
add op1 NE op2 relation range for op1 | op2 as nonzero.
2026-08-17 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/126748
* range-op.cc (class operator_div): declarations.
(operator_div::op1_op2_relation_effect): add op1/op2 relation
range equal zero for op1/op2 if op1 < op2 and both op1 and op2
are positives.
2026-08-17 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/124667
* match.pd(`(A & BIT) EQ|NE 0 ? A | BIT : A`): New
pattern.
(`(A & BIT) EQ|NE 0 ? A : A | BIT`): New pattern.
(`(A & MASK) EQ|NE MASK ? A : A | MASK`): New pattern.
(`(A & MASK) EQ|NE MASK ? A | MASK : A`): New pattern.
(`A | (((A >> N) & 1) << N)`): New pattern.
2026-08-17 Richard Biener <rguenther@suse.de>
PR middle-end/126788
* optabs-tree.cc (supportable_convert_operation): For same
modes allow NOP_EXPR and VIEW_CONVERT_EXPR.
* tree-ssa-forwprop.cc (simplify_vector_constructor): Avoid
converting the vector to be used for blending into the
result to the type of the permutation.
* tree-vect-stmts.cc (vectorizable_conversion): Leave
nop-conversions to vectorizable_assignment.
2026-08-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/126887
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Allow to search past a loop header in case we are threading a
loop exit test.
* tree-ssa-threadupdate.cc
(back_jt_path_registry::duplicate_thread_path): Properly
detect when a entered subloop is dissolved by threading,
but avoid creating new entries into the original loop.
(jt_path_registry::cancel_invalid_paths): Do not allow
peeling loops.
2026-08-17 Abhishek Kaushik <abhishek.kaushik@arm.com>
* config/aarch64/aarch64-sve-builtins-sve2.cc (svabal): Define.
* config/aarch64/aarch64-sve-builtins-sve2.def (svabal): New
function.
* config/aarch64/aarch64-sve-builtins-sve2.h (svabal): Declare.
* config/aarch64/iterators.md (UNSPEC_SABAL, UNSPEC_UABAL): New
unspecs.
(SVE2_INT_BINARY_LONG, SVE2_INT_ADD_BINARY_LONG): Add
UNSPEC_SABAL and UNSPEC_UABAL.
(sve_int_op, sve_int_add_op, sve_type_unspec): Handle them.
2026-08-17 Josef Melcr <josef.melcr@suse.com>
* gimple-low.cc (lower_assumption): Unset stdarg after
determining the body function's arguments.
2026-08-17 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-16 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc: Fix typos in comments.
* config/avr/avr.md: Same.
* config/avr/avr-passes.cc: Same.
* config/avr/genmultilib.awk: Same.
2026-08-16 Léo Hardt <leom.hardt@inf.ufrgs.br>
* sel-sched-ir.cc (copy_data_sets): Removed dead code.
* sel-sched-ir.h (_XLIST_X): Likewise.
(_XLIST_NEXT): Likewise.
(_xlist_add): Likewise.
(_xlist_remove): Likewise.
(_xlist_clear): Likewise.
(_xlist_is_in_p): Likewise.
(_list_iter_cond_x): Likewise.
(_xlist_iter_remove): Likewise.
(_FOR_EACH_X): Likewise.
(_FOR_EACH_X_1): Likewise.
(sel_save_haifa_priorities): Likewise.
(insn_eligible_for_subst_p): Likewise.
(sel_init_invalid_data_sets): Likewise.
(insn_at_boundary_p): Likewise.
(copy_data_sets): Likewise.
2026-08-15 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_out_perm_compare_eqne): New static func.
(avr_out_compare): Use it.
2026-08-15 Pietro Monteiro <pietro@sociotechnical.xyz>
* config/t-openbsd (USER_H): Add $(srcdir)/ginclude/stdatomic.h.
2026-08-15 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-fixed.md: Use constants like REG_24
instead of magic numbers like 24.
2026-08-14 Odysseas Georgoudis <odygrd@hotmail.com>
PR middle-end/122715
* config/i386/i386.cc: Include "internal-fn.h".
(ix86_gimple_fold_builtin): Canonicalize PAVG builtins to
IFN_AVG_CEIL.
2026-08-14 Shreya Munnangi <smunnang@qti.qualcomm.com>
PR rtl-optimization/125731
* ifcvt.cc (get_base_reg_or_const): Renamed from get_base_reg.
Handle CONST_INTs too.
(noce_try_cond_arith): Use get_base_reg_or_const. Handle case where
get_base_reg_or_const returns a CONST_INT.
2026-08-14 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126845
* value-relation.cc (dom_oracle::search_and_merge_relation): Create
relation immediately and update it later.
2026-08-14 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126814
* gimple-range-fold.cc (fold_using_range::fold_stmt): Temporarily
replace the current range query with the specified one.
2026-08-14 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126533
* gimple-range-gori.cc (gori_name_helper): Add depth counter.
2026-08-14 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126538
* gimple-range-phi.cc (phi_group::calculate_using_modifier): Limit the
iteration upper bound to MAX_FIXED_MODE_SIZE.
2026-08-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (x / y * y == x): Extend to inequality.
2026-08-14 LIU Hao <lh_mouse@126.com>
* config/i386/sym-mingw32.cc: Add `extern "C"` and `visibility("hidden")`.
2026-08-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/126865
* tree-vect-slp.cc (vect_build_slp_tree_1): Track common
BB and whether there's any trapping stmt in the matching set
and verify the same BB constraint after we've seen all stmts.
2026-08-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/126862
* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): For PHI
uses verify dominance to the PHI use edge source.
2026-08-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/126861
* tree-vect-slp.cc (vect_schedule_slp_node): Use NULL for
scheduling at region start.
2026-08-14 Reshma Roy <Reshma.Roy@amd.com>
PR tree-optimization/126646
* match.pd: Fold umin(a, 1) | umin(b, 1) into umin(a | b, 1).
2026-08-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/126852
* tree-vect-slp.cc (vect_schedule_slp_node): Verify schedule
for PHIs.
2026-08-14 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (nop_convert): Use vector_nop_conversion_p.
((A == 0) & (B == 0), (A != 0) | (B != 0)): Extend the
existing simplifications to vector operands.
((A == -1) & (B == -1), (A != -1) | (B != -1)): Likewise.
* tree.cc (vector_nop_conversion_p): New function.
* tree.h (vector_nop_conversion_p): Declare.
2026-08-14 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/107765
* match.pd (`(cast)-(cast)a`): Expand to
use expr_not_equal_to of INT_MIN.
2026-08-14 Longjun Luo <luolongjuna@gmail.com>
PR debug/126355
* cgraphunit.cc (cgraph_node::create_wrapper): Preserve
DECL_IGNORED_P across forced GIMPLE thunk expansion.
2026-08-14 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/98602
* match.pd (vec_cond (cmp @0 VECTOR_CST@1) @0 VECTOR_CST@2):
New simplification.
(vec_cond (cmp @0 VECTOR_CST@1) VECTOR_CST@2 @0): Likewise.
* tree.cc (record_uniform_integer_difference): New helper.
(uniform_vector_difference_p): New function.
* tree.h (uniform_vector_difference_p): Declare.
2026-08-14 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/108031
* config/riscv/riscv.cc (riscv_rtx_costs): Bump the cost of a LO_SUM
by one unit to encourage use of related values instead of the symbolic
form.
2026-08-14 H.J. Lu <hjl.tools@gmail.com>
PR testsuite/126697
* config/i386/cpuid.h (__get_cpuid_max): Rename the first
argument to __leaf and apply 0xC0000000 mask before passing
it to CPUID.
(__get_cpuid): Pass __leaf to __get_cpuid_max.
(__get_cpuid_count): Likewise.
2026-08-14 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/126426
* ext-dce.cc (carry_backpropagate): Return a conservatively
correct mask when presented with vector modes.
(ext_dce_process_uses): Don't use GET_MODE_INNER, we need to
know the full extent of the bits for vector and complex modes.
2026-08-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/120582
* tree-ssa-forwprop.cc (simplify_builtin_call): Remove dead code.
2026-08-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR sanitizer/120581
* sancov.cc (sancov_pass): Remove dead code.
2026-08-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/120580
* gimple-ssa-nonnull-compare.cc (do_warn_nonnull_compare):
Remove dead code.
2026-08-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/120579
* gimple.cc (gimple_could_trap_p_1): Remove dead code.
2026-08-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/120477
* tree-ssa-math-opts.cc (arith_overflow_check_p): Remove dead code.
2026-08-13 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126103
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Follow abnormal PHIs.
2026-08-13 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-fold.h (gimple_range_ssa_p): Remove the
SSA_NAME_OCCURS_IN_ABNORMAL_PHI check.
* gimple-range-path.cc (path_range_query::ssa_range_in_phi):
Assert the incoming path edge is not abnormal.
2026-08-13 Jim Lin <jim@andestech.com>
* common/config/riscv/riscv-common.cc
(riscv_multi_lib_info_t::parse): Skip a multilib that is exactly
equivalent to the default march/mabi.
2026-08-13 Peter Bergner <bergner@tenstorrent.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-xg.
(RISCV_CORE): Likewise.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add tt_ascalon_xg.
* config/riscv/riscv.md (tune): Likewise.
* config/riscv/tt-ascalon-d8.md (asc-xg-fp64-vec0, asc-xg-fp64-vec1):
New define_cpu_unit.
(tt_ascalon_xg_fp64_vec): New define_reservation.
(tt_ascalon_d8_int_load, tt_ascalon_d8_alu, tt_ascalon_d8_sfb,
tt_ascalon_d8_branch, tt_ascalon_d8_float_move, tt_ascalon_d8_fcvt,
tt_ascalon_d8_fcmp, tt_ascalon_d8_imul, tt_ascalon_d8_idiv,
tt_ascalon_d8_fadd, tt_ascalon_d8_mul, tt_ascalon_d8_float_fma,
tt_ascalon_d8_float_div_half, tt_ascalon_d8_float_div_single,
tt_ascalon_d8_float_div_double, tt_ascalon_d8_popcount,
tt_ascalon_d8_vec_load, tt_ascalon_d8_vec_store,
tt_ascalon_d8_vec_load_strided, tt_ascalon_d8_vec_store_strided,
tt_ascalon_d8_vec_load_indexed, tt_ascalon_d8_vec_store_indexed,
tt_ascalon_d8_vec_loadstore_seg, tt_ascalon_d8_vec_alu_1,
tt_ascalon_d8_vec_alu_2, tt_ascalon_d8_vec_alu_3,
tt_ascalon_d8_vec_alu_4, tt_ascalon_d8_vec_imul, tt_ascalon_d8_vec_pop,
tt_ascalon_d8_vec_crypto_aes, tt_ascalon_d8_vec_crypto_sha,
tt_ascalon_d8_vec_perm_1, tt_ascalon_d8_vec_perm_3,
tt_ascalon_d8_vec_perm_4, tt_ascalon_d8_vec_reduction,
tt_ascalon_d8_vec_ordered_reduction, tt_ascalon_d8_vec_idiv_byte,
tt_ascalon_d8_vec_idiv_half, tt_ascalon_d8_vec_idiv_single,
tt_ascalon_d8_vec_idiv_double, tt_ascalon_d8_vec_float_divsqrt_half,
tt_ascalon_d8_vec_float_divsqrt_single,
tt_ascalon_d8_vec_float_divsqrt_double, tt_ascalon_d8_vec_mask,
tt_ascalon_d8_vec_vesetvl, tt_ascalon_d8_vec_setrm,
tt_ascalon_d8_vec_readlen, tt_ascalon_d8_vec_unknown):
Use tt_ascalon_xg.
(tt_ascalon_d8_vec_fcmp, tt_ascalon_d8_vec_fadd,
tt_ascalon_d8_vec_fmul): Disable vector instructions that produce FP64
output values when tuning for tt_ascalon_xg.
(tt_ascalon_xg_fp64_vec_insns): New define_insn_reservation.
* doc/riscv-mcpu.texi: Regenerate.
* doc/riscv-mtune.texi: Likewise.
2026-08-13 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/126315
* combine.cc (simplify_comparison) <case AND>: Delete
transformation that changed (AND (SUBREG x) C) into the
non-canonical (SUBREG (AND x C)).
2026-08-13 Richard Biener <rguenther@suse.de>
H.J. Lu <hjl.tools@gmail.com>
* match.pd ((convert (convert @0))): Allow integer vector
types, unify {inside,intrer,final}_vec, guard patterns that
are not correct for vectors and those that are with
checks the resulting conversion is supported by the target.
* optabs-tree.h (supportable_convert_operation): Remove
useless last argument.
* optabs-tree.cc (supportable_convert_operation): Likewise.
(supportable_half_widening_operation): Adjust.
* tree-vect-stmts.cc (vectorizable_conversion): Likewise.
(supportable_indirect_convert_operation): Likewise.
* tree-vect-generic.cc (expand_vector_conversion): Likewise.
* tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Likewise.
* tree-ssa-forwprop.cc (simplify_vector_constructor): Likewise.
2026-08-13 Josef Melcr <josef.melcr@suse.com>
* Makefile.in: Add callback-info.o to OBJS.
* attr-callback.cc (callback_fetch_attr_by_edge): Use fn_idx
from the summary.
(callback_get_arg_mapping): Replaced by
callback_get_arg_mapping_from_attr and the summary field.
(callback_get_arg_mapping_from_attr): New function, parses the
attr and returns the computed argument mapping.
(callback_fetch_fn_position): Delete, obsoleted by the summary.
(callback_edge_useful_p): Check for the redirected flag in the
summary instead of cgraph_node fields.
* attr-callback.h (enum callback_position): Add comment.
(enum arg_mapping_constants): New enum, defines the identifier
for -1 in the arg_mapping vector.
(callback_get_arg_mapping): Delete.
(callback_fetch_fn_position): Delete.
(callback_get_arg_mapping_from_attr): Add decl.
* cgraph.cc (symbol_table::create_edge): Remove callback_id initializer.
(cgraph_edge::make_callback): Initialize the callback_info
summary, add necessary arguments.
(cgraph_edge::redirect_callee): Set the redirected flag when
redirecting a callback edge.
(cgraph_edge::redirect_call_stmt_to_callee): Use the summary.
(cgraph_node::verify_node): Remove callback_id checks.
(cgraph_cc_finalize): Free the summaries.
* cgraph.h: Remove callback_id from cgraph_edge, adjust decl of
cgraph_edge::make_callback.
* cgraphclones.cc (cgraph_edge::clone): Remove callback_id.
* ipa-cp.cc (ipcp_driver): Initialize the summary sum.
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Remove
callback_id, adjust call to make_callback, use the summary.
(ipa_analyze_node): Initialize the summary sum.
(ipa_register_cgraph_hooks): Likewise.
* lto-cgraph.cc (lto_output_edge): Remove callback_id, stream
out the summary.
(output_symtab): Initialize the summary sum.
(input_edge): Remove callback_id, stream in the summary.
(input_cgraph_1): Initialize the summary sum.
* callback-info.cc: New file.
* callback-info.h: New file.
2026-08-13 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-dce.cc (simple_dce_from_worklist): Fix conditional
for no_delete with a call.
2026-08-13 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126815
* tree-ssa-dce.cc (simple_dce_from_worklist): Just don't
remove the lhs for no_delete case rather than adding a
new stmt.
2026-08-13 Rohith Kapelli <kapellirohith@gmail.com>
PR rtl-optimization/125683
* simplify-rtx.cc (simplify_context::simplify_ternary_operation):
When folding an IF_THEN_ELSE of two equal MEM operands with
different memory attributes, return a copy whose attributes are
widened to what both operands allow.
2026-08-13 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-12 Iain Sandoe <iain@sandoe.co.uk>
PR target/126723
* config/darwin.cc (darwin_encode_section_info): Make all
string constant labels linker-visible. Likewise const
section anchors.
2026-08-12 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (range_operator::fold_range): Fold each pair
of sub-ranges, or the diagonal when the operands are equal.
(range_op_float_tests): New test.
2026-08-12 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*bt<mode>): Change operand 1 constraint
from "q<S>,<S>" to "r<S>,<S>".
(*bt<SWI48:mode>_mask): Remove constraints from operand 0.
2026-08-12 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-fixed.md (*round<mode>3.libgcc_split)
(*round<mode>3.libgcc): Use the ALL12QA mode iterator instead
of ALL1Q and ALL2QA separately.
2026-08-12 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-fixed.md (ALL12QA): New mode iterator.
(sat_ashl): New code iterator.
(usashluqq3, ssashlqq3, usashluhq3, ssashlhq3, usashluha3)
(ssashlha3, usashlusq3, ssashlsq3, usashlusa3, ssashlsa3)
(*usashluqq3, *ssashlqq3, *usashluhq3, *ssashlhq3)
(*usashluha3, *ssashlha3, *usashlusq3, *ssashlsq3, *usashlusa3)
(*ssashlsa3): New insns.
* config/avr/avr.md (code_stdname): Also map ss_ashift, us_ashift.
2026-08-12 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (RISC-V Vector Intrinsics): Update link to
specification.
2026-08-12 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126418
* match.pd (`(A ^ -cmp) + cmp`): Cast to unsigned type
before taking the negative.
2026-08-12 Matt Turner <mattst88@gmail.com>
* configure.ac (gcc_cv_irelative_reloc): New variable, set for
riscv*-*-linux* and alpha*-*-linux*. Perform the linker
IRELATIVE check once, driven by it.
* configure: Regenerate.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-simd.md (reduc_widen_<su>sum<mode><vsi2qi>3):
Expand through aarch64_expand_reduc_widen_sum.
* config/aarch64/aarch64.cc (aarch64_expand_reduc_widen_sum): Use
[SU]DOT for a step from byte to word elements.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-protos.h (aarch64_expand_reduc_widen_sum):
Declare.
* config/aarch64/aarch64.cc (aarch64_expand_reduc_widen_sum): New
function.
* config/aarch64/aarch64-simd.md (aarch64_<su>adalp<mode>): Rename
to ...
(@aarch64_<su>adalp<mode>): ... this.
(reduc_widen_ssum<Vdblw><mode>3, reduc_widen_usum<Vdblw><mode>3):
Replace by ...
(reduc_widen_<su>sum<Vdblw><mode>3): ... this. Expand to [SU]ADALP.
(reduc_widen_ssum<mode><vsi2qi>3, reduc_widen_usum<mode><vsi2qi>3):
Replace by ...
(reduc_widen_<su>sum<mode><vsi2qi>3): ... this. Handle
!TARGET_DOTPROD.
(reduc_widen_<su>sumv2di<mode>3): New expander.
* config/aarch64/iterators.md (VQ_BH): New mode iterator.
2026-08-12 H.J. Lu <hjl.tools@gmail.com>
PR target/94649
PR target/126293
* common/config/i386/i386-cpuinfo.h (ix86_decode_cpu_info): New
function.
* config/i386/i386-options.cc
(ix86_option_override_internal): Issue an error for -m128bit-atomic
in 32-bit mode. Turn on -mcx16 if -m128bit-atomic is enabled.
Enable -m128bit-atomic in 64-bit mode by default if supported by
the targeting processor.
* config/i386/i386.h (TARGET_128BIT_ATOMIC_ENABLED): New.
* config/i386/i386.opt (m128bit-atomic): New option.
* config/i386/i386.opt.urls: Regenerated.
* config/i386/sync.md: Update comments for 128-bit aligned vector
loads and stores.
(atomic_loadti): New pattern.
(atomic_loadti_sse): Likewise.
(atomic_storeti): Likewise.
(atomic_storeti_sse): Likewise.
* doc/invoke.texi: Remove __atomic Builtins reference from -mcx16.
Document -m128bit-atomic.
2026-08-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126589
* tree-vect-slp-patterns.cc (vect_validate_multiplication): Cleanup
comment.
(vect_validate_multiplication_commutative): Remove last 4 orders.
2026-08-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126589
* tree-vect-slp-patterns.cc (complex_fms_pattern::matches): Check
another form of FMS.
2026-08-12 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/125129
* doc/gm2.texi (-fdump-builtins): New switch.
2026-08-12 Abhishek Kaushik <abhishek.kaushik@arm.com>
* config/aarch64/aarch64-acle-builtins.h
(TYPES_qshr_x2): New macro.
(TYPES_qrshr_x2_8): Likewise.
(TYPES_qshru_x2): Likewise.
(TYPES_qrshrun_x2): Likewise.
(DEF_SVE_TYPES_ARRAY): Add qshr_x2, qrshr_x2_8, qrshrun_x2
and qshru_x2.
* config/aarch64/aarch64-sve-builtins-sve2.cc (svqshrn): New
function.
(svqshrun): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def (svqrshrn): Add
SVE2p3/SME2p3 x2 form.
(svqrshrun): Likewise.
(svqshrn): Add SVE2p3/SME2p3 x2 form.
(svqshrun): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h (svqshrn): Declare.
(svqshrun): Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve_<sve_int_op><mode>): New define_insn.
* config/aarch64/iterators.md (SVE_FULL_HIx2): New mode iterator.
(UNSPEC_SQSHRN, UNSPEC_SQSHRUN, UNSPEC_UQSHRN): New unspecs.
(VNARROW): Add VNx16HI mapping.
(Ventype): Likewise.
(SVE2_INT_SHIFT_IMM_NARROWxN): Add UNSPEC_SQSHRN,
UNSPEC_SQSHRUN and UNSPEC_UQSHRN.
(sve_int_op): Add sqshrn, sqshrun and uqshrn.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (((X - 1) | C) + 1): New simplification.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* doc/md.texi (reduc_widen_ssum@var{n}@var{m}3)
(reduc_widen_usum@var{n}@var{m}3): Document that the assignment of
input elements to accumulator elements is unconstrained, that
intermediate sums must not overflow, and that the widen_[us]sum
names are reserved. Fix a typo.
* tree.def (WIDEN_SUM_EXPR): Document that the assignment of elements
of the first argument to elements of the second is unconstrained.
(DOT_PROD_EXPR, SAD_EXPR): Note the same freedom.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* optabs.def (ssum_widen_optab): Rename to ...
(reduc_widen_ssum_optab): ... this. Rename the pattern from
widen_ssum$a$b3 to reduc_widen_ssum$a$b3.
(usum_widen_optab): Rename to ...
(reduc_widen_usum_optab): ... this. Rename the pattern from
widen_usum$a$b3 to reduc_widen_usum$a$b3.
* optabs-tree.cc (optab_for_tree_code): Update for the renamed
optabs.
* doc/md.texi (widen_ssum@var{n}@var{m}3): Rename to ...
(reduc_widen_ssum@var{n}@var{m}3): ... this.
(widen_usum@var{n}@var{m}3): Rename to ...
(reduc_widen_usum@var{n}@var{m}3): ... this.
* config/aarch64/aarch64-simd.md (widen_ssum<Vdblw><mode>3): Rename
to ...
(reduc_widen_ssum<Vdblw><mode>3): ... this.
(widen_ssum<Vwide><mode>3): Rename to ...
(reduc_widen_ssum<Vwide><mode>3): ... this.
(widen_usum<Vdblw><mode>3): Rename to ...
(reduc_widen_usum<Vdblw><mode>3): ... this.
(widen_usum<Vwide><mode>3): Rename to ...
(reduc_widen_usum<Vwide><mode>3): ... this.
(widen_ssum<mode><vsi2qi>3): Rename to ...
(reduc_widen_ssum<mode><vsi2qi>3): ... this.
(widen_usum<mode><vsi2qi>3): Rename to ...
(reduc_widen_usum<mode><vsi2qi>3): ... this.
* config/aarch64/aarch64-sve.md (widen_<sur>sum<mode><vsi2qi>3):
Rename to ...
(reduc_widen_<sur>sum<mode><vsi2qi>3): ... this.
* config/aarch64/aarch64-sve2.md (widen_ssum<mode><Vnarrow>3): Rename
to ...
(reduc_widen_ssum<mode><Vnarrow>3): ... this.
(widen_usum<mode><Vnarrow>3): Rename to ...
(reduc_widen_usum<mode><Vnarrow>3): ... this.
* config/arm/neon.md (widen_ssum<v_double_width><mode>3): Rename
to ...
(reduc_widen_ssum<v_double_width><mode>3): ... this.
(widen_ssum<V_widen_l><mode>3): Rename to ...
(reduc_widen_ssum<V_widen_l><mode>3): ... this.
(widen_usum<v_double_width><mode>3): Rename to ...
(reduc_widen_usum<v_double_width><mode>3): ... this.
(widen_usum<V_widen_l><mode>3): Rename to ...
(reduc_widen_usum<V_widen_l><mode>3): ... this.
* config/ia64/vect.md (widen_usumv4hiv8qi3): Rename to ...
(reduc_widen_usumv4hiv8qi3): ... this.
(widen_usumv2siv4hi3): Rename to ...
(reduc_widen_usumv2siv4hi3): ... this.
(widen_ssumv4hiv8qi3): Rename to ...
(reduc_widen_ssumv4hiv8qi3): ... this.
(widen_ssumv2siv4hi3): Rename to ...
(reduc_widen_ssumv2siv4hi3): ... this.
* config/rs6000/altivec.md (widen_usumv4si<mode>3): Rename to ...
(reduc_widen_usumv4si<mode>3): ... this.
(widen_ssumv4siv16qi3): Rename to ...
(reduc_widen_ssumv4siv16qi3): ... this.
(widen_ssumv4siv8hi3): Rename to ...
(reduc_widen_ssumv4siv8hi3): ... this.
2026-08-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/126099
PR tree-optimization/126053
* tree-vect-slp.cc (vect_cse_gather_part_starts): New function.
(vect_cse_slp_node_parts): Likewise.
(vect_optimize_slp): For BB SLP CSE to low/highparts of
other nodes.
2026-08-12 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_schedule_slp): Adjust prototype.
* tree-vect-slp.cc (vect_slp_analyze_bb_1): When scheduling
fails, fail vectorization.
(vect_schedule_slp_node): Return whether we can schedule
the node.
(vect_schedule_scc): Likewise.
(vect_schedule_slp): When asked, elide SLP graph entries
that cannot be scheduled.
2026-08-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/126028
* tree-vectorizer.h (_slp_tree::si): New member.
(vect_schedule_slp): Adjust prototype.
* tree-vect-loop.cc (vect_transform_loop): Adjust.
* tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize si.
(vect_bb_slp_mark_live_stmts): Use vector stmt placement
constraint computed by pre-scheduling of SLP nodes.
(vect_slp_analyze_bb_1): Pre-schedule SLP nodes before
computing live lane extraction points.
(vect_slp_region): Adjust.
(vect_schedule_slp_node): Add parameter indicating to whether
we should perform pre-scehduling or not. Compute the
insertion place suitable for dominance checks when
pre-scheduling.
(vect_schedule_scc): Adjust.
(vect_schedule_slp): Likewise.
2026-08-12 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vect_is_simple_cond): Simplify and
inline ...
(vectorizable_condition): ... here. Simplify.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/predicates.md (aarch64_general_reg): Test the
register number rather than REGNO_REG_CLASS, which reports the
W8_W11_REGS and W12_W15_REGS subclasses for x8-x15.
2026-08-12 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_CSSC for TARGET_CSSC.
2026-08-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/126789
* config/i386/mmx.md (mmxxmmmode): Add V2SF and V2SI.
(mmxxmmmodelower): Likewise.
(vcond_mask_<mode>qi): New expander for V2SF and V2SI.
* tree-vect-stmts.cc (vectorizable_conversion): Handle
conversion via VEC_COND_EXPR.
(supportable_indirect_convert_operation): For mask vector
conversions to vector integer mode try using a VEC_COND_EXPR.
2026-08-12 Jørgen Kvalsvik <j@lambda.is>
* cfg-flags.def (COVERAGE_SUPPRESSED): New flag.
* doc/extend.texi: Add sections on suppress_coverage.
* doc/gcov.texi: Add sections on suppress_coverage.
* gcov-dump.cc (tag_suppress): New function.
* gcov-io.h (GCOV_TAG_SUPPRESS): New.
(GCOV_TAG_SUPPRESS_LENGTH): New.
(GCOV_TAG_SUPPRESS_NUM): New.
* gcov.cc (struct arc_info): Add field suppressed.
(block_info::block_info): Initialize suppressed.
(line_info::line_info): Initialize suppressed.
(struct coverage_info): Add fields lines_suppressed,
(struct path_info): Add fields residual_paths,
residual_covered.
(executed_summary): Add suppressed argument.
(tombstone_p): New function.
(remove_tombstones): New function.
(tombstone_subsequence_p): New function.
(subsumed_by_any_p): New function.
(path_info::suppress_blocks): New function.
(path_info::get_paths): New function.
(path_info::count): New function.
(path_info::suppressed_count): New function.
(path_info::suppressed_p): New function.
(find_arc): Return NULL if arc cannot be found.
(main): Pass total_suppressed to executed_summary.
(output_intermediate_json_line): Skip suppressed.
(json_set_prime_path_coverage): Include suppressed counts.
(output_json_intermediate_file): Likewise.
(process_all_functions): Record block, arc suppressed status.
(generate_results): Count total suppressed.
(read_graph_file): Read SUPPRESS tag.
(add_branch_counts): Count suppressed.
(add_condition_counts): Likewise.
(add_path_counts): Likewise.
(function_summary): Print info on suppressed blocks.
(file_summary): Count suppressed.
(add_line_counts): Likewise.
(accumulate_line_info): Likewise.
(accumulate_line_counts): Likewise.
(output_conditions): Skip suppressed.
(output_branch_count): Likewise.
(print_prime_path_lines): Annotate suppressed arcs.
(print_prime_path_source): Likewise, and widen the annotation
column.
(output_path_coverage): Print info on suppressed paths.
(output_line_beginning): Prefix suppressed lines with '#'.
(output_line_details): Pass suppressed.
(output_lines): Likewise.
* profile.cc (suppress_coverage): New function.
(suppress_coverage_unset): New function.
(coverage_suppressed_p): New function.
(any_block_coverage_suppressed_p): New function.
(suppress_coverage_begin): New function.
(suppress_coverage_end): New function.
(in_pragma_suppress_coverage_p): New function.
(location_in_pragma_suppress_coverage_p): New function.
(fn_in_pragma_suppress_coverage_p): New function.
(branch_prob): Write SUPPRESS record, skip MC/DC and path
coverage when the entire function is suppressed.
* profile.h (in_pragma_suppress_coverage_p): New forward
declaration.
(location_in_pragma_suppress_coverage_p): Ditto.
(coverage_suppressd_p): Ditto.
(suppress_coverage): Ditto.
(suppress_coverage_unset): Ditto.
* tree-cfg.cc (gimple_empty_block_p): New forward declaration.
(make_blocks_1): Set coverage-suppresesed on blocks.
(make_blocks): Sometimes insert NOP to help coverage
suppression on blocks.
(gimple_can_merge_blocks_p): Don't merge coverage-suppressed
block with non-suppressed blocks.
(gimple_merge_blocks): Likewise.
(gimple_split_edge): Propagate coverage-suppressed on block
splits.
(gimple_split_block): Likewise.
(gimple_duplicate_bb): Likewise.
(insert_cond_bb): Likewise.
2026-08-12 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126103
* tree-ssa-threadbackward.cc (class back_threader): Add
find_taken_edge_goto.
(back_threader::find_taken_edge): Handle GIMPLE_GOTO.
(back_threader::find_taken_edge_goto): New.
(back_threader::maybe_thread_block): Handle GIMPLE_GOTO.
2026-08-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126778
* tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge): Move it.
(vect_set_loop_condition_partial_vectors): Use it to update edge.
2026-08-12 Hongyu Wang <hongyu.wang@intel.com>
PR target/126787
* config/i386/sse.md (*fma_fmadd_<mode>): Use the "jm" to replace
"m" constraint and set addr attribute to "gpr16" for vex only
alternatives.
(*fma_fmsub_<mode>): Likewise.
(*fma_fnmadd_<mode>): Likewise.
(*fma_fnmsub_<mode>): Likewise.
(*fma_fmaddsub_<mode>): Likewise.
(*fma_fmsubadd_<mode>): Likewise.
(xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise.
(xop_p<macs>dql): Likewise.
(xop_p<macs>dqh): Likewise.
(xop_p<macs>wd): Likewise.
(xop_p<madcs>wd): Likewise.
(xop_pcmov_<mode><avxsizesuffix>): Likewise.
(xop_phadd<u>bw): Likewise.
(xop_phadd<u>bd): Likewise.
(xop_phadd<u>bq): Likewise.
(xop_phadd<u>wd): Likewise.
(xop_phadd<u>wq): Likewise.
(xop_phadd<u>dq): Likewise.
(xop_phsubbw): Likewise.
(xop_phsubwd): Likewise.
(xop_phsubdq): Likewise.
(xop_pperm): Likewise.
(xop_pperm_pack_v2di_v4si): Likewise.
(xop_pperm_pack_v4si_v8hi): Likewise.
(xop_pperm_pack_v8hi_v16qi): Likewise.
(xop_rotl<mode>3): Likewise.
(xop_rotr<mode>3): Likewise.
(xop_vrotl<mode>3): Likewise.
(xop_sha<mode>3): Likewise.
(xop_shl<mode>3): Likewise.
(xop_frcz<mode>2): Likewise.
(*xop_vmfrcz<mode>2): Likewise.
(xop_maskcmp<mode>3): Likewise.
(xop_maskcmp_uns<mode>3): Likewise.
(xop_maskcmp_uns2<mode>3): Likewise.
(xop_pcom_tf<mode>3): Likewise.
(xop_vpermil2<mode>3): Likewise.
2026-08-12 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-protos.h (enum riscv_fusion_pairs): Use
HOST_WIDE_INT_1U for bit masks.
(riscv_get_fusible_ops): Return unsigned HOST_WIDE_INT.
* config/riscv/riscv.cc (struct riscv_tune_param): Change
fusible_ops to unsigned HOST_WIDE_INT.
(riscv_get_fusible_ops): Likewise.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::create_relation_in_bb): Adjust
to use ssa_name instead of version.
(dom_oracle::search_and_merge_relation): Likewise.
(dom_oracle::find_relation_block): Likewise.
(dom_oracle::find_relation_dom): Likewise.
(dom_oracle::query): Likewise.
* value-relation.h (find_relation_block): Use trees not unsigned.
(find_relation_dom): Likewise.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::record): Use search_and_merge_relation.
(dom_oracle::create_relation_in_bb): New.
(dom_oracle::search_and_merge_relation): Rename from set_one_relation
and extract create_relation code.
(dom_oracle::register_transitives): Use search_and_merge_relation.
* value-relation.h (set_one_relation): Delete.
(create_relation_in_bb): New.
(search_and_merge_relation): Rename from set_one_relation.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126536
* gimple-range-edge.cc (calc_switch_ranges): Check that invert worked.
* gimple-range-op.cc (cfn_toupper_tolower::fold_range): Likewise.
* range-op-ptr.cc (operator_equal::op1_range): Likewise.
(operator_not_equal::op1_range): Likewise.
* range-op.cc (operator_equal::op1_range): Likewise.
(operator_not_equal::op1_range): Likewise.
(operator_rshift::op1_range): Likewise.
(operator_logical_not::fold_range): Likewise.
* tree-ssa-loop-unswitch.cc (unswitch_predicate): Likewise.
* value-range.cc (irange_bitmask::range_from_mask): Likewise.
(prange::invert): Return bool for success/fail.
(irange::invert): Likewise.
(irange::snap_subranges): Check that invert worked.
(range_tests_int_range_max): Confirm failed invert works.
(range_tests_misc): Check invert return value.
* value-range.h (irange::invert): Add boolean return value.
(prange::invert): Add boolean return value.
* vr-values.cc (simplify_switch_using_ranges): Check invert result.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126531
* gimple-range-cache.cc (ranger_cache::range_from_dom): Track
abnormal edges throughout the dom search.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126329
* tree-ssa-dce.cc (simple_dce_from_worklist): Add no-delete option.
* tree-ssa-dce.h (simple_dce_from_worklist): Add no delete param.
* tree-vrp.cc (remove_unreachable::handle_early): Use no delete option.
2026-08-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126648
* range-op.cc (operator_lshift::op1_range): Handle undefined.
2026-08-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/126789
* tree-vect-patterns.cc (build_mask_conversion): Add
scalar_type_for_mask parameter and pass it along.
(vect_convert_mask_for_vectype): Likewise.
(vect_recog_bool_pattern): Adjust.
(vect_recog_mask_conversion_pattern): Likewise.
2026-08-11 Dipesh Sharma <Dipesh.Sharma@amd.com>
PR tree-optimization/126693
* match.pd: Fold abs(x) * abs(y) into abs(x * y).
2026-08-11 Georg-Johann Lay <avr@gjlay.de>
PR target/121343
* config/avr/avr-fixed.md: Rewrite insns and expanders to
use hard-register constraints.
* config/avr/avr.md (*umulqihi3.call_split): Add comment.
2026-08-11 Rohith Kapelli <kapellirohith@gmail.com>
PR tree-optimization/123951
* config/aarch64/aarch64-simd.md
(*aarch64_simd_vec_set_lane0<mode>): New pattern.
(*aarch64_simd_vec_copy_lane_same<mode>): New pattern.
2026-08-11 Hu, Lin1 <lin1.hu@intel.com>
PR target/126676
* config/i386/i386-expand.cc (ix86_expand_fp_compare): Only use
UNSPEC_OPTCOMX for the modes VCOMX exists for.
2026-08-10 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* wide-int.cc (canonize): Use return 1 instead of return len.
2026-08-10 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*movbehi2): New insn, split from the
movbe alternatives of *bswaphi2_movbe.
(*bswaphi2_movbe): Convert to define_insn_and_split. Split
the MOVBE alternatives (mem<->reg) post-reload into *movbehi2
to drop the now-unneeded flags clobber.
2026-08-10 Tudor-Stefan Magirescu <tudor.magirescu@gmail.com>
* match.pd (((X CMP1 Y) - (X CMP2 Y)) REL 0): New pattern.
2026-08-10 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
* config/mingw/winnt.cc (i386_pe_drectve_name): New.
(i386_pe_assemble_visibility): Emit -exclude-symbols
directives into .drectve for VISIBILITY_HIDDEN and
VISIBILITY_INTERNAL instead of warning. Use the external
symbol spelling for 32-bit PE names.
2026-08-10 Paul-Antoine Arras <parras@baylibre.com>
* omp-expand.cc (expand_omp_for_static_nochunk,
expand_omp_for_static_chunk): Adjust calls to OMPT variants with
GOMP_loop_end.
2026-08-10 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126103
* doc/params.texi (dom-jump-threading): Document.
* params.opt (-param=dom-jump-threading=): New.
* tree-ssa-dom.cc (dom_opt_dom_walker::after_dom_children): Honor
param_dom_jump_threading.
2026-08-10 Gerald Pfeifer <gerald@pfeifer.com>
PR target/69374
* doc/install.texi (Binaries): Remove reference to OpenPKG.
2026-08-10 Alice Carlotti <alice.carlotti@arm.com>
PR target/124629
* config/aarch64/driver-aarch64.cc (AARCH64_ARCH):
Don't skip first character of #ARCH_IDENT.
2026-08-10 Alice Carlotti <alice.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(aarch64_get_extension_string_for_isa_flags): Check isa_flags.
* config/aarch64/aarch64-option-extensions.def
(CRYPTO, SVE2_AES, SVE2_BITPERM, SVE2_SHA3, SVE2_SM4): Remove
cpuinfo feature string.
2026-08-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Check that the
two arms of the pair are one access size apart.
2026-08-10 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/126701
* cfgexpand.cc (verify_partition_mem_exprs): Document when it may
be called.
(pass_expand::execute): Call it after the RTL of PARM_DECL and
RESULT_DECL default definitions is restored.
* tree-outof-ssa.cc (split_overlapping_partition_decls): Note the
variable a partition of a parameter or result default definition
ends up with.
2026-08-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/126658
* gimple.cc (check_loadstore): Restrict TARGET_MEM_REF
handling.
* gimple-ssa-isolate-paths.cc (check_loadstore): Likewise.
* gimple-range-infer.cc (non_null_loadstore): Likewise.
2026-08-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((X | Y) >> C, (X ^ Y) >> C): New simplification.
2026-08-10 Avinash Jayakar <avinashd@linux.ibm.com>
PR target/126513
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Allocate reg
if target is null or const0_rtx.
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): Add
error handling for c1, c2 and c3 described in this commit.
2026-08-10 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-fusion.cc (riscv_fuse_zext_common): New function.
(riscv_fuse_zextw): Likewise.
(riscv_fuse_zextws): Use riscv_fuse_zext_common and document RTL
relationships and constraints.
(riscv_fuse_zexth): Use riscv_fuse_zext_common.
(riscv_fuse_ldindexed): Document RTL relationships and constraints.
(riscv_fuse_expanded_ld): Likewise.
(riscv_fuse_ldpreincrement): Likewise.
(riscv_fuse_lui_addi): Likewise.
(riscv_fuse_auipc_addi): Likewise.
(riscv_fuse_lui_ld): Likewise.
(riscv_fuse_auipc_ld): Likewise.
(riscv_fuse_cache_aligned_std): Likewise.
(riscv_fuse_aligned_std): Likewise.
(riscv_fuse_bfext): Likewise.
(riscv_fuse_b_alui): Likewise.
(riscv_fusion_entry::op): Rename from op_flags and use an enum.
(riscv_fusion_table): Split ZEXTW and ZEXTWS entries.
(riscv_macro_fusion_pair_p): Use riscv_fusion_enabled_p and print
instruction UIDs.
2026-08-10 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/125735
* match.pd: 1 / X -> X == 1 for positive X.
2026-08-09 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/111959
* fold-const.cc (tree_single_nonnegative_p): Use the range to see
if the SSA_NAME was nonnegative.
2026-08-09 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126729
* tree-ssa-phiopt.cc (factor_out_conditional_load): Handle
REF_REVERSE_STORAGE_ORDER being set correctly.
2026-08-09 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
* tree-pretty-print.cc (dump_mem_ref): Dump REF_REVERSE_STORAGE_ORDER
if it was set.
2026-08-09 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* hwint.h (add_hwi, mul_hwi): Combine return result.
2026-08-09 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.md (trunctfsf2): Adjust sequence to avoid
conversion step landing at a halfway value.
2026-08-09 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/126742
* match.pd: Fix wrong code.
2026-08-09 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/126625
* hwint.cc (reflect_hwi): Use STAGE0_CXX_HAS_BUILTIN
for __builtin_bitreverse64.
* ira-color.cc (HAS_SMUL_OVERFLOW): Remove
and use STAGE0_CXX_HAS_BUILTIN instead.
* system.h (STAGE0_CXX_HAS_BUILTIN): New macro.
2026-08-09 Aldy Hernandez <aldy@quesejoda.com>
* data-streamer-out.cc (streamer_write_vrange): Stream each frange
sub-range.
* data-streamer-in.cc (streamer_read_value_range): Read them.
2026-08-09 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (float_binary_op_range_finish): Use
contains_zero_p on lhs instead of inspecting the hull endpoints.
2026-08-09 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Configuration): Spell CPU in uppercase letters.
(Specific): Ditto.
2026-08-09 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((A / B) * (C / D)): New simplification.
2026-08-09 Roger Sayle <roger@nextmovesofware.com>
Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126467
* match.pd (0.0 - x -> -x): Update the conditions under which
the transformation is performed, disallowing x = +0.0 when we
honor signed zeros. This is still disallowed if x is a NaN.
2026-08-08 Kevin Stefanov <kevinstefanov15@gmail.com>
PR middle-end/111856
* omp-simd-clone.cc (simd_clone_adjust_return_type): Use VOID_TYPE_P
when checking for void return type in adjusted functions.
(simd_clone_adjust): Likewise.
2026-08-08 Alexander Monakov <amonakov@ispras.ru>
* gcc.cc (execute) [default]: Use the same wording as above.
2026-08-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (REDUC (a) op REDUC (b)): New simplifications combining
two reductions into one.
2026-08-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((type) minmax ((wide_type) a, (wide_type) b)): Accept
vector types, using element_precision and requiring the narrow
operation to be supported.
2026-08-08 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((x + y) - minmax (x, y)): New simplification.
2026-08-08 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (operator_cast::fold_range): Convert each
sub-range and union the results.
(range_op_float_tests): New test.
2026-08-08 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (operator_cast::fold_range): Convert each
sub-range and union the results.
(range_op_float_tests): New test.
2026-08-07 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126714
* range-op-float.cc (range_op_float_tests): Guard the signed-zero
== op1_range self-test with HONOR_SIGNED_ZEROS.
2026-08-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126534
* gimple-range-op.cc (cfn_sqrt::op1_range): Widen lb or ub
by further 0.5ulp or 1ulp before squaring it.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
PR target/120681
* config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Allow large
code model as well as medium code model.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Likewise.
(rs6000_elf_declare_function_name): Don't create the
local/non-local labels for large code model if we are using
PC-relative addressing.
2026-08-07 Jakub Jelinek <jakub@redhat.com>
PR target/126667
* config/s390/s390.md (usubc<mode>5): If operands[4] is
an immediate operand other than const0_rtx, force it into reg
before using it in xor<mode>3 insn.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
PR target/120528
* config/rs6000/rs6000.md (zero_extend??ti2 peephole2): Add a
peephole2 to simplify zero extending a QI/HI/SI/DImode value in
memory to a TImode target in a vector register to use the
LXVR{B,H,W,D}X instructins.
2026-08-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126641
* value-range.h (class frange): Declare widen method.
* range-op-float.cc (float_widen_bound): Move to value-range.cc.
(float_widen_lhs_range): Remove.
(operator_plus::op1_range, operator_minus::op1_range,
operator_minus::op2_range, operator_mult::op1_range,
foperator_div::op1_range, foperator_div::op2_range,
operator_cast::op1_range, range_op_float_tests): Replace
X = float_widen_lhs_range (T, R) with X = R; X.widen (T).
* value-range.cc (float_widen_bound): New, moved from
range-op-float.cc.
(frange::widen): New method, partially based on
float_widen_lhs_range, but replace lhs with *this and
avoid using set/union_ to construct range, instead modify
m_pair and m_num_ranges directly.
* real.cc (set_significand_bit, clear_significand_bit,
test_significand_bit): Add
gcc_checking_assert (n < SIGNIFICAND_BITS).
(clear_significand_below): Add
gcc_checking_assert (n <= SIGNIFICAND_BITS).
2026-08-07 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (operator_cast::fold_range): Convert each
integer sub-range and union the results.
(range_op_float_tests): New test.
2026-08-07 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (((x >> 1) + (y >> 1)) + (x & y & 1)): New simplification
to (x & y) + ((x ^ y) >> 1).
2026-08-07 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((X % C1) % C2): New simplification.
2026-08-07 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (MIN (MAX (X, Y + CST), Y)): New simplification.
(MAX (MIN (X, Y + CST), Y)): Likewise.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.opt (-mblock-ops-vector-pair): Undo change to
make the -mblock-ops-vector-pair option a documented option.
* doc/invoke.texi (RS/6000 and PowerPC Options): Likewise.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
PR target/99293
* config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
PR target/117487
* config/rs6000/vsx.md (SFmode logical peephoole): Update comments in
the original code that supports power8.
(SFBOOL2_*): New constants.
(power9/power10 define_peephol2): Add a new define_peephole2 to optimize
float and logical operations on power9/power10/power11 similar to the
optimiztion that is done on power8.
2026-08-07 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Enable using load
vector pair and store vector pair instructions for memory and string
built-in functions.
(POWERPC_MASKS): Make -mblock-ops-vector-pair an option that is set by
the -mcpu=<xxx> command line option.
* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
-mblock-ops-vector-pair from influencing .machine selection.
* config/rs6000/rs6000.opt (-mblock-ops-vector-pair): Document the
option.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document the
-mblock-ops-vector-pair option.
2026-08-07 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/64992
* match.pd: Fix two typos and format.
2026-08-06 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/126669
* tree-ssa-strlen.cc (use_in_zero_equality): Remove dead code.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (operator_abs::fold_range): Take the absolute
value of each sub-range and union the results.
(range_op_float_tests): New test.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (operator_negate::fold_range): Negate each
sub-range and union the results.
(range_op_float_tests): New test.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (frange_add_zeros): Detect a contained zero with
the contains_zero_p method instead of inspecting the hull endpoints.
(range_op_float_tests): Test that op1_range for == admits +0.0 for a
multi-pair operand holding an inner -0.0.
2026-08-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (X + (X | -X)): New simplification.
(X + ((-X) & (C - 1))): Likewise.
2026-08-06 Uros Bizjak <ubizjak@gmail.com>
PR target/126685
* config/i386/i386.md (bswaphisi2_lowpart): Use %w operand
modifier to emit HImode register name for ROLW alternative.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
PR tree-optimization/126637
* range-op-float.cc (operator_equal::fold_range): Use the
contains_zero_p method to detect a contained zero instead of
inspecting the hull endpoints.
(operator_not_equal::fold_range): Likewise.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (contains_zero_p): Remove the free-standing irange
overload.
* range-op.cc (operator_equal::op1_op2_relation): Use the
irange::contains_zero_p method.
(operator_not_equal::op1_op2_relation): Likewise.
(operator_lt::op1_op2_relation): Likewise.
(operator_le::op1_op2_relation): Likewise.
(operator_gt::op1_op2_relation): Likewise.
(operator_ge::op1_op2_relation): Likewise.
(operator_lshift::op1_range): Likewise.
(operator_rshift::op1_range): Likewise.
(operator_cast::op1_range): Likewise.
(operator_logical_and::fold_range): Likewise.
(operator_bitwise_and::wi_fold): Likewise.
(operator_bitwise_xor::op1_range): Likewise.
(operator_addr_expr::fold_range): Likewise.
(operator_addr_expr::op1_range): Likewise.
* range-op-float.cc (operator_equal::op1_op2_relation): Likewise.
(operator_not_equal::op1_op2_relation): Likewise.
(operator_lt::op1_op2_relation): Likewise.
(operator_le::op1_op2_relation): Likewise.
(operator_gt::op1_op2_relation): Likewise.
(operator_ge::op1_op2_relation): Likewise.
2026-08-06 Karl Meakin <karl.meakin@arm.com>
PR target/126652
* config/aarch64/arm_neon.h (vaddd_s64, vaddd_u64): Delete
function definitions.
2026-08-06 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_call): Get scalar argument
type from the representative call stmt.
2026-08-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-vect-patterns.cc (vect_recog_mulhs_pattern): Do not give up
when LHS_TYPE has no vector type.
2026-08-06 Richard Biener <rguenther@suse.de>
PR middle-end/123175
* fold-const.cc (test_vnx4si_v4si): Fixup vec_perm_indices
construction.
(test_v4si_vnx4si): Likewise.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (vrange::nonzero_p): Remove.
(unsupported_range::nonzero_p): Remove.
(irange::nonzero_p): Remove.
(prange::nonzero_p): Remove.
(frange::nonzero_p): Remove.
(Value_Range::nonzero_p): Remove.
* value-range.cc (unsupported_range::nonzero_p): Remove.
(frange::nonzero_p): Remove.
(range_tests_misc): Test contains_zero_p instead of nonzero_p.
(range_tests_sub_ranges_zero): Likewise.
* range-op.cc (range_op_bitwise_and_tests): Likewise.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (get_legacy_range): Compare against a set_nonzero
prange instead of calling nonzero_p.
* value-range-storage.cc (nonzero_range_p): New.
(prange_storage::prange_format): Use it instead of nonzero_p.
(prange_storage::equal_p): Likewise.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* gimple-range-path.cc (path_range_query::adjust_for_non_null_uses):
Use !contains_zero_p instead of nonzero_p.
* tree-ssa-structalias.cc (find_what_p_points_to): Likewise.
* tree-ssanames.cc (set_range_info): Likewise.
* tree-vrp.cc (execute_ranger_vrp): Likewise.
2026-08-06 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (vrange::contains_zero_p): New pure virtual.
(unsupported_range::contains_zero_p): Declare.
(irange::contains_zero_p): Declare and define.
(prange::contains_zero_p): Declare and define.
(frange::contains_zero_p): Declare.
(Value_Range::contains_zero_p): New.
* value-range.cc (unsupported_range::contains_zero_p): Define.
(frange::contains_zero_p): Define.
2026-08-06 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* match.pd: Combine several patterns into fors.
2026-08-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-sve.md (<su>mul<mode>3_highpart): Extend
from SVE_I to SVE_I_SIMD_DI.
(@aarch64_pred_<optab><mode>): Likewise for the MUL_HIGHPART form,
and print the data operands with %Z.
* config/aarch64/aarch64-sve2.md (@aarch64_sve2_<optab><mode>):
Likewise.
2026-08-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((X / Y) ==/!= 0): Preserve a possible zero-divisor
exception.
((X % Y) ==/!= X): New simplification. Preserve a possible
zero-divisor exception.
2026-08-06 Josef Melcr <josef.melcr@suse.com>
* attr-callback.cc (callback_build_attr): Use "callback_only"
instead of the macro.
(callback_edge_callee_has_attr): Likewise.
(callback_fetch_attr_by_edge): Likewise.
(get_nth_list_elem): Move to c-family/c-attribs.cc.
(handle_callback_attribute): Rename to
handle_callback_only_attribute, move to c-family/c-attribs.cc.
* attr-callback.h (CALLBACK_ATTR_IDENT): Remove the macro.
(handle_callback_attribute): Remove the declaration.
* builtin-attrs.def (ATTR_CALLBACK): Rename to
ATTR_CALLBACK_ONLY.
(ATTR_CALLBACK_ONLY): Identifier for the attribute for builtins.
(DEF_CALLBACK_ATTRIBUTE): Rename to DEF_CALLBACK_ONLY_ATTRIBUTE.
(DEF_CALLBACK_ONLY_ATTRIBUTE): Renamed definition macro for builtins.
(GOMP): Use the renamed macro.
(ATTR_CALLBACK_GOMP_LIST): Renamed to
ATTR_CALLBACK_ONLY_GOMP_LIST.
(ATTR_CALLBACK_ONLY_GOMP_LIST): ATTR_NOTHROW_LIST with the
callback_only attribute for libgomp functions.
* cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): Use
"callback_only" instead of the macro.
(cgraph_node::verify_node): Likewise.
* doc/extend.texi: Add callback_only attribute docs.
* ipa-cp.cc (purge_useless_callback_edges): Use "callback_only"
instead of the macro.
* ipa-param-manipulation.cc
(drop_decl_attribute_if_params_changed_p): Likewise.
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Likewise.
* omp-builtins.def (BUILT_IN_GOMP_PARALLEL_LOOP_STATIC): Use the
renamed attribute list.
(BUILT_IN_GOMP_PARALLEL_LOOP_GUIDED): Likewise.
(BUILT_IN_GOMP_PARALLEL_LOOP_NONMONOTONIC_DYNAMIC): Likewise.
(BUILT_IN_GOMP_PARALLEL_LOOP_NONMONOTONIC_RUNTIME): Likewise.
(BUILT_IN_GOMP_PARALLEL): Likewise.
(BUILT_IN_GOMP_PARALLEL_SECTIONS): Likewise.
(BUILT_IN_GOMP_TEAMS_REG): Likewise.
* tree-core.h: Update the ECF_CB flag comment.
2026-08-06 Kito Cheng <kito.cheng@sifive.com>
PR target/126454
* config/riscv/riscv-opt-popretz.cc (pass_combine_popretz::execute):
Stop the backward scan at any use or definition of a0, including
those hidden in CALL_INSN_FUNCTION_USAGE or in a PARALLEL.
2026-08-06 Jakub Jelinek <jakub@redhat.com>
* common/config/i386/cpuinfo.h (get_available_features): Make
last change valid C89. Formatting fix.
2026-08-06 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/riscv-v.cc (expand_const_vector): Force VLS
constants to mem.
2026-08-06 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc
(riscv_ext_info_t::implied_exts): Return const reference
instead of by-value copy.
2026-08-06 Ewan <ewanhai-oc@zhaoxin.com>
* config/i386/cpuid.h (__get_cpuid_max): Update comment to
document 0x40000000 and 0xC0000000 as valid ext values.
(__get_cpuid): Replace "__leaf & 0x80000000" with explicit
range checks for Basic, Hypervisor, Extended, and
Centaur/Zhaoxin CPUID ranges.
(__get_cpuid_count): Likewise.
2026-08-06 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126580
* tree-ssa-phiopt.cc (cond_store_replacement_limited): Allow
a load before the store; not removing the store.
2026-08-06 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd ((X | C) ==/!= (Y | C)): New simplification.
2026-08-06 Matt Turner <mattst88@gmail.com>
PR target/124495
* config/alpha/alpha.md (UNSPECV_LDGP2): New unspec_volatile.
(*ldgp_er_2_v): New insn.
(*builtin_setjmp_receiver_1): Split the second half of the gpdisp
pair to it instead of *ldgp_er_2.
(*exception_receiver_1): Ditto.
2026-08-06 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_tune_param): Add reassociation
widths.
(generic_ooo_tune_info): Set reassociation widths.
(xt_c9501_tune_info): Likewise.
(riscv_reassociation_width): New function.
(TARGET_SCHED_REASSOCIATION_WIDTH): Define.
2026-08-06 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-05 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-fixed.md: Use alldiv as code iterator for the
16-bit fixed-point insns and expanders of [U]HAmode, [U]HQmode.
Support saturated divisions in [U]HAmode, [U]HQmode.
2026-08-05 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (code_stdname): Add code attributes
for: ss_div, us_div, div, udiv.
* config/avr/avr-fixed.md (alldiv): New code iterator.
Use it in all [U]SAmode division expanders and insns.
Use <code_stdname> instead of <code> as needed.
2026-08-05 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_conversion): Elide op0/op1.
(vect_is_simple_use): New overload.
(supportable_indirect_convert_operation): Drop optional and
unused scalar op argument.
* tree-vectorizer.h (supportable_indirect_convert_operation):
Adjust prototype.
(vect_is_simple_use): New overload.
2026-08-05 Sivan Shani <sivan.shani@arm.com>
* config/aarch64/aarch64.h (TARGET_SVE_AES2): Define.
* config/aarch64/aarch64.md (UNSPEC_SSVE_LANE_SELECT): New unspec.
* config/aarch64/aarch64-acle-builtins.cc
(function_resolver::finish_opt_n_resolution): Add overload taking an
sve_type argument. Make the existing overload delegate to it.
* config/aarch64/aarch64-acle-builtins.h
(function_resolver::finish_opt_n_resolution): Declare the new overload.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_SVE_AES2 and __ARM_FEATURE_SSVE_AES.
* config/aarch64/aarch64-sve-builtins-functions.h
(unspec_based_aes_lane_function): New typedef.
(unspec_based_aes_lane_mc_function): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(binary_to_pair_opt_n_def): New shape.
(ternary_to_pair_opt_n_def): Likewise.
(binary_aes_lane_def): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h: Declare new shapes.
* config/aarch64/aarch64-sve-builtins-sve2.cc: Add new function
entries.
* config/aarch64/aarch64-sve-builtins-sve2.def: Add new ACLE
builtin definitions.
* config/aarch64/aarch64-sve-builtins-sve2.h: Declare new functions.
* config/aarch64/aarch64-sve2.md: Add PMULL/PMLAL pair and AES
indexed multi-vector patterns.
* config/aarch64/iterators.md: Add iterators and attrs for new
patterns.
* config/aarch64/predicates.md (const_0_to_3_operand): New predicate.
2026-08-05 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_get_vec_defs): Adjust to take
bool instead of tree arguments.
* tree-vect-stmts.cc (vect_get_vec_defs): Likewise.
(vectorizable_bswap): Simplify.
(vectorizable_conversion): Likewise.
(vectorizable_assignment): Likewise.
(vectorizable_shift): Likewise.
(vectorizable_operation): Likewise.
(vectorizable_condition): Likewise.
(vectorizable_comparison_1): Likewise.
* tree-vect-loop.cc (vect_transform_lc_phi): Likewise.
2026-08-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/126650
* tree-affine.cc (get_inner_reference_aff): Fixup rounding
of size.
2026-08-05 Jakub Jelinek <jakub@redhat.com>
* fold-const.cc (split_address_to_core_and_offset): Use STRIP_NOPS.
* match.pd ((&a + b) !=/== (&a[1] + c) -> (&a[0] - &a[1]) + b !=/== c):
Don't require captures to be ADDR_EXPR.
((&a+b) - (&a[1] + c) -> sizeof(a[0]) + (b - c)): Likewise.
((p + b) - &p->d -> offsetof (*p, d) + b): Likewise.
(Try folding difference of addresses): Likewise. Remove
redundant simplifications because of that.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h (_mm_cvts_bf8_bf6): New intrin.
(_mm256_cvts_bf8_bf6): Ditto.
(_mm512_cvts_bf8_bf6): Ditto.
(_mm_cvts_hf8_hf6): Ditto.
(_mm256_cvts_hf8_hf6): Ditto.
(_mm512_cvts_hf8_hf6): Ditto.
(_mm_cvtbf6_hf8): Ditto.
(_mm_mask_cvtbf6_hf8): Ditto.
(_mm_maskz_cvtbf6_hf8): Ditto.
(_mm256_cvtbf6_hf8): Ditto.
(_mm256_mask_cvtbf6_hf8): Ditto.
(_mm256_maskz_cvtbf6_hf8): Ditto.
(_mm512_cvtbf6_hf8): Ditto.
(_mm512_mask_cvtbf6_hf8): Ditto.
(_mm512_maskz_cvtbf6_hf8): Ditto.
(_mm_cvthf6_hf8): Ditto.
(_mm_mask_cvthf6_hf8): Ditto.
(_mm_maskz_cvthf6_hf8): Ditto.
(_mm256_cvthf6_hf8): Ditto.
(_mm256_mask_cvthf6_hf8): Ditto.
(_mm256_maskz_cvthf6_hf8): Ditto.
(_mm512_cvthf6_hf8): Ditto.
(_mm512_mask_cvthf6_hf8): Ditto.
(_mm512_maskz_cvthf6_hf8): Ditto.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/sse.md (vcvt<convertfp82fp6s><mode>): New.
(vcvt<convertfp62hf8><mode><mask_name>): Ditto.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h (_mm_cvts_bf8_bf4): New intrin.
(_mm256_cvts_bf8_bf4): Ditto.
(_mm512_cvts_bf8_bf4): Ditto.
(_mm_cvts_hf8_bf4): Ditto.
(_mm256_cvts_hf8_bf4): Ditto.
(_mm512_cvts_hf8_bf4): Ditto.
(_mm_cvtbf4_hf8): Ditto.
(_mm_mask_cvtbf4_hf8): Ditto.
(_mm_maskz_cvtbf4_hf8): Ditto.
(_mm256_cvtbf4_hf8): Ditto.
(_mm256_mask_cvtbf4_hf8): Ditto.
(_mm256_maskz_cvtbf4_hf8): Ditto.
(_mm512_cvtbf4_hf8): Ditto.
(_mm512_mask_cvtbf4_hf8): Ditto.
(_mm512_maskz_cvtbf4_hf8): Ditto.
* config/i386/i386-builtin-types.def : New function types.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new function types.
* config/i386/sse.md (vcvt<convertfp82bf4s>v16qi): New.
(*vcvt<convertfp82bf4s>v16qi): Ditto.
(vcvt<convertfp82bf4s><mode>): Ditto.
(vcvtbf42hf8<mode><mask_name>): Ditto.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h (_mm_cvtbf8_ps): New intrins.
(_mm_mask_cvtbf8_ps): Ditto.
(_mm_maskz_cvtbf8_ps): Ditto.
(_mm256_cvtbf8_ps): Ditto.
(_mm256_mask_cvtbf8_ps): Ditto.
(_mm256_maskz_cvtbf8_ps): Ditto.
(_mm512_cvtbf8_ps): Ditto.
(_mm512_mask_cvtbf8_ps): Ditto.
(_mm512_maskz_cvtbf8_ps): Ditto.
(_mm_cvthf8_ps): Ditto.
(_mm_mask_cvthf8_ps): Ditto.
(_mm_maskz_cvthf8_ps): Ditto.
(_mm256_cvthf8_ps): Ditto.
(_mm256_mask_cvthf8_ps): Ditto.
(_mm256_maskz_cvthf8_ps): Ditto.
(_mm512_cvthf8_ps): Ditto.
(_mm512_mask_cvthf8_ps): Ditto.
(_mm512_maskz_cvthf8_ps): Ditto.
* config/i386/i386-builtin-types.def: New function types.
* config/i386/i386-builtin.def (BDESC): New builtins for avx10v2aux.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new function types.
* config/i386/sse.md (vcvt<convertfp82ps><mode><mask_name>): New.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h (_mm_cvtbiasps_bf8): New intrin.
(_mm_mask_cvtbiasps_bf8): Ditto.
(_mm_maskz_cvtbiasps_bf8): Ditto.
(_mm256_cvtbiasps_bf8): Ditto.
(_mm256_mask_cvtbiasps_bf8): Ditto.
(_mm256_maskz_cvtbiasps_bf8): Ditto.
(_mm512_cvtbiasps_bf8): Ditto.
(_mm512_mask_cvtbiasps_bf8): Ditto.
(_mm512_maskz_cvtbiasps_bf8): Ditto.
(_mm_cvts_biasps_bf8): Ditto.
(_mm_mask_cvts_biasps_bf8): Ditto.
(_mm_maskz_cvts_biasps_bf8): Ditto.
(_mm256_cvts_biasps_bf8): Ditto.
(_mm256_mask_cvts_biasps_bf8): Ditto.
(_mm256_maskz_cvts_biasps_bf8): Ditto.
(_mm512_cvts_biasps_bf8): Ditto.
(_mm512_mask_cvts_biasps_bf8): Ditto.
(_mm512_maskz_cvts_biasps_bf8): Ditto.
(_mm_cvtbiasps_hf8): Ditto.
(_mm_mask_cvtbiasps_hf8): Ditto.
(_mm_maskz_cvtbiasps_hf8): Ditto.
(_mm256_cvtbiasps_hf8): Ditto.
(_mm256_mask_cvtbiasps_hf8): Ditto.
(_mm256_maskz_cvtbiasps_hf8): Ditto.
(_mm512_cvtbiasps_hf8): Ditto.
(_mm512_mask_cvtbiasps_hf8): Ditto.
(_mm512_maskz_cvtbiasps_hf8): Ditto.
(_mm_cvts_biasps_hf8): Ditto.
(_mm_mask_cvts_biasps_hf8): Ditto.
(_mm_maskz_cvts_biasps_hf8): Ditto.
(_mm256_cvts_biasps_hf8): Ditto.
(_mm256_mask_cvts_biasps_hf8): Ditto.
(_mm256_maskz_cvts_biasps_hf8): Ditto.
(_mm512_cvts_biasps_hf8): Ditto.
(_mm512_mask_cvts_biasps_hf8): Ditto.
(_mm512_maskz_cvts_biasps_hf8): Ditto.
* config/i386/i386-builtin-types.def (V16QI): New function types.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new function types.
* config/i386/sse.md (vcvt<biasps2fp8>v4sf): New.
(*vcvt<biasps2fp8>v4sf): Ditto.
(vcvt<biasps2fp8>v8sf): Ditto.
(*vcvt<biasps2fp8>v8sf): Ditto.
(vcvt<biasps2fp8>v4sf_mask): Ditto.
(*vcvt<biasps2fp8>v4sf_mask): Ditto.
(vcvt<biasps2fp8>v8sf_mask): Ditto.
(*vcvt<biasps2fp8>v8sf_mask): Ditto.
(vcvt<biasps2fp8>v16sf<mask_name>): Ditto.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10v2auxintrin.h:(_mm_cvtrops_hf8): New intrins.
(_mm_mask_cvtrops_hf8): Ditto.
(_mm_maskz_cvtrops_hf8): Ditto.
(_mm256_cvtrops_hf8): Ditto.
(_mm256_mask_cvtrops_hf8): Ditto.
(_mm256_maskz_cvtrops_hf8): Ditto.
(_mm512_cvtrops_hf8): Ditto.
(_mm512_mask_cvtrops_hf8): Ditto.
(_mm512_maskz_cvtrops_hf8): Ditto.
(_mm_cvts_rops_hf8): Ditto.
(_mm_mask_cvts_rops_hf8): Ditto.
(_mm_maskz_cvts_rops_hf8): Ditto.
(_mm256_cvts_rops_hf8): Ditto.
(_mm256_mask_cvts_rops_hf8): Ditto.
(_mm256_maskz_cvts_rops_hf8): Ditto.
(_mm512_cvts_rops_hf8): Ditto.
(_mm512_mask_cvts_rops_hf8): Ditto.
(_mm512_maskz_cvts_rops_hf8): Ditto.
* config/i386/i386-builtin.def (BDESC): New avx10v2aux builtins.
* config/i386/sse.md: Add RTO UNSPEC.
2026-08-05 Dipesh Sharma <Dipesh.Sharma@amd.com>
Venkataramanan Kumar <Venkataramanan.Kumar@amd.com>
Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h (get_available_features): Add AVX10V2AUX.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10V2AUX_SET): New.
(OPTION_MASK_ISA2_AVX10_1_UNSET): Disable AVX10_1.
(OPTION_MASK_ISA2_AVX10V2AUX_UNSET): New.
(ix86_handle_option): Handle AVX10V2AUX.
* common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10V2AUX.
* common/config/i386/i386-isas.h: Handle avx10v2aux.
* config.gcc: Include avx10v2auxintrin.h.
* config/i386/cpuid.h (bit_AVX10V2AUX): New.
* config/i386/i386-builtin-types.def: Add new function type.
* config/i386/i386-builtin.def (BDESC): New AVX10V2AUX builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Handle avx10v2aux.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle avx10v2aux function types.
* config/i386/i386-isa.def (AVX10V2AUX): New DEF_PTA
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): Handle avx10v2aux.
* config/i386/i386.opt: Add avx10v2aux.
* config/i386/i386.opt.urls: Regenerated.
* config/i386/immintrin.h: Include avx10v2auxintrin.h.
* config/i386/sse.md (vcvt<convertps2fp8>v4sf): New.
(*vcvt<convertps2fp8>v4sf): Ditto.
(vcvt<convertps2fp8>v8sf): Ditto.
(*vcvt<convertps2fp8>v8sf): Ditto.
(vcvt<convertps2fp8>v4sf_mask): Ditto.
(*vcvt<convertps2fp8>v4sf_mask): Ditto.
(vcvt<convertps2fp8>v8sf_mask): Ditto.
(*vcvt<convertps2fp8>v8sf_mask): Ditto.
(vcvt<convertps2fp8>v16sf<mask_name>): Ditto.
* doc/extend.texi: Add avx10v2aux documentation.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
* config/i386/avx10v2auxintrin.h: New file.
2026-08-05 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/56223
* match.pd (X >=/> 0 ? Y + X : Y - X): New simplification.
(X <=/< 0 ? Y - X : Y + X): Likewise.
2026-08-05 liuhongt <hongtao.liu@intel.com>
PR middle-end/125708
* expr.cc: Include gimple-range.h.
(near_pow2_divisor_range_p): New function.
(expand_expr_divmod): Split eligible TRUNC_DIV_EXPRs into two
constant divisions selected by a conditional move.
2026-08-05 Lewis Hyatt <lhyatt@gmail.com>
* mem-stats.h (mem_alloc_description::mem_alloc_description): Make
private.
(mem_alloc_description::~mem_alloc_description): Disallow
destruction entirely.
(mem_alloc_description::instance): New function.
* alloc-pool.cc (dump_alloc_pool_statistics): Adapt to
pool_allocator_usage being a function instead of a variable.
* alloc-pool.h (pool_allocator_usage): New function.
(TBlockAllocator>::initialize): Adapt to
pool_allocator_usage being a function instead of a variable.
(TBlockAllocator>::release): Likewise.
(TBlockAllocator>::allocate): Likewise.
(TBlockAllocator>::remove): Likewise.
* bitmap.cc (bitmap_mem_desc): Change from a static variable to an
inline function.
(bitmap_register): Adapt to bitmap_mem_desc being a function instead
of a variable.
(register_overhead): Likewise.
(release_overhead): Likewise.
(bitmap_list_find_element): Likewise.
(bitmap_tree_splay): Likewise.
(bitmap_tree_find_element): Likewise.
(dump_bitmap_statistics): Likewise.
* bitmap.h (bitmap_mem_desc): Remove unneeded extern declaration.
* ggc-common.cc (ggc_mem_desc): Change from a static variable to an
inline function.
(ggc_record_overhead): Adapt to ggc_mem_desc being a function
instead of a variable.
(ggc_free_overhead): Likewise
(ggc_prune_overhead_list): Likewise.
* vec.cc (vec_mem_desc): Change from a static variable to a
function.
(vec_prefix::register_overhead): Adapt to vec_mem_desc being a
function instead of a variable.
(vec_prefix::release_overhead): Likewise.
(dump_vec_loc_statistics): Likewise.
* hash-table.cc (hash_table_usage): Move to...
* hash-table.h (hash_table_usage): ...here, and use new singleton
interface.
2026-08-05 Lewis Hyatt <lhyatt@gmail.com>
PR middle-end/28734
* mem-stats.h (mem_alloc_description::release_object_overhead):
Handle the case that PTR was not found in the hash map, which can
happen after PCH restore.
2026-08-04 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/126550
* config/riscv/riscv-v.cc (expand_const_vector_single_step_npatterns):
User global builder's npatterns.
2026-08-04 Roger Sayle <roger@nextmovesoftware.com>
Richard Biener <rguenther@suse.de>
PR tree-optimization/126242
PR tree-optimization/126325
* match.pd ((FTYPE) N CMP CST): Always attempt to initialize
value range information. Check undefined_p before using range
bounds. Check that icst_val hasn't overflowed, i.e. that
(FTYPE)ICST == CST, before transforming to integer comparison.
2026-08-04 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/100173
* fold-const.h (safe_operand_equal_p): New function.
* tree-ssa-phiopt.cc (factor_out_conditional_load): Add simple
support for TARGET_MEM_REF.
2026-08-04 Philipp Tomsich <philipp.tomsich@vrull.eu>
Revert:
2026-08-04 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/107090
* match.pd: Add atom match recognizers for long-multiply
(mul_hi, mul_lo, mul_hilo, mul_lolo, mul_hihi, mul_cross_sum,
mul_low_sum, mul_low_accum, mul_carry_cross_sum,
mul_carry_low_sum, mul_carry_low, mul_ladder_sum1,
mul_ladder_sum2, mul_ladder_sum3, mul_ladder_part_sum), the
cond_carry_add and cond_carry_add_neg recognizers for the 2-arg
PHI carry form, one per gcond polarity, and long_mul_high_chain
for the emitted chain shape.
* tree-ssa-forwprop.cc (gimple_cond_carry_add): Declare.
(gimple_cond_carry_add_neg): Likewise.
(gimple_mul_hi): Likewise.
(gimple_mul_lo): Likewise.
(gimple_mul_hilo): Likewise.
(gimple_mul_lolo): Likewise.
(gimple_mul_hihi): Likewise.
(gimple_mul_cross_sum): Likewise.
(gimple_mul_low_sum): Likewise.
(gimple_mul_low_accum): Likewise.
(gimple_mul_carry_cross_sum): Likewise.
(gimple_mul_carry_low_sum): Likewise.
(gimple_mul_carry_low): Likewise.
(gimple_mul_ladder_sum1): Likewise.
(gimple_mul_ladder_sum2): Likewise.
(gimple_mul_ladder_sum3): Likewise.
(gimple_mul_ladder_part_sum): Likewise.
(build_mul_high_seq): New, emits (N)(((2N) op1 * (2N) op2) >> N)
into a caller-supplied destination.
(long_mul_apply_extras): New, combines the preserved addends back
on top of the folded multiply.
(create_mul_high_seq): New, replaces the statement with the
high-part multiply plus any extras.
(create_mul_low_seq): New, likewise for the low part.
(enum long_mul_kind): New.
(enum long_mul_extract): New.
(struct long_mul_summand): New.
(long_mul_linearize_chain): New, walks the outer add/ior chain
into a multiset of leaves.
(long_mul_is_lshift_def): New.
(long_mul_set_summand): New.
(long_mul_classify_carry): New, most-specific carry atom first.
(long_mul_classify_plus_kinds): New, likewise by specificity.
(long_mul_classify_hi_extract): New.
(long_mul_classify_lo_extract): New.
(long_mul_classify_shl_extract): New.
(long_mul_classify_bare): New.
(long_mul_classify_summand): New, classify a summand via the
match.pd atoms.
(long_mul_summand_compare): New.
(struct long_mul_row): New.
(long_mul_same_ops): New.
(long_mul_is_cross_half): New.
(long_mul_hilo_orientation): New, orientation of a mul_hilo
capture relative to (op0, op1).
(long_mul_canonical_ops): New.
(long_mul_find_summand): New.
(long_mul_check_consistency): New, cross-summand consistency
check (operand pairing, half-width shifts, hilo cross-half).
(long_mul_signature_matches): New.
(long_mul_check_two_carries): New extra check, validates the
two-carry row's carry operands against the canonical (op0, op1).
(long_mul_check_low_plus_defer): New extra check, defers the
low-plus row while a GT/LT/GE/LE use shares an operand with the
PLUS.
(long_mul_hint_shared_intermediate): New, dump-file hint pointing
at a shared inner addition.
(long_mul_classify_match): New, looks a summand multiset up in
long_mul_table, runs the per-row checks, and gates the high-part
emit on optimize_widening_mul_active_p.
(long_mul_classify_chain): New, linearize plus classify plus
table lookup; sets aside leaves that classify as no summand and
takes an optional pre-classified summand.
(match_long_mul): New, top-level entry: starts only at a chain
end and dispatches to create_mul_high_seq / create_mul_low_seq
with any preserved addends.
(match_long_mul_phi): New PHI-driven entry, recognizes a
cond_carry_add(_neg) PHI and folds the long-multiply shape when
the rest of the high-part chain matches.
(pass_forwprop::execute): Call match_long_mul on PLUS_EXPR and
BIT_IOR_EXPR statements, and match_long_mul_phi on each PHI in
the degenerate-PHI walk.
* tree-ssa-math-opts.cc (can_widen_to_narrow_p): New.
(build_long_mul_partials): New, emits the four partial products
using widening or plain multiplies.
(emit_long_mul_highpart): New, the high N bits of an N-bit
product, as a longhand over (N/2)-bit partials.
(combine_long_mul_halves): New, the high N bits of a product of
two 2N-bit values given as N-bit halves.
(long_mul_op_fits_p): New, true when an operand is provably
representable in narrow_prec unsigned bits.
(long_mul_split_operand): New, splits an operand into N-bit
halves using only N-bit operations.
(long_mul_only_low_half_used_p): New.
(narrow_long_mul_low_half): New, narrow a 2N low-half-only mult
the target cannot expand to an N-bit mult.
(narrow_long_mul_operands): New, recurse into chained wide
products after a narrowing/lowering.
(gimple_long_mul_high_chain): Declare.
(lower_long_mul_high_chain): New, lowers the high-part chain to a
longhand at narrow precision, splitting each operand into N-bit
halves and combining them, then narrowing or dropping the
residual 2N mult via the helpers.
(optimize_widening_mul_active_p): New, shared gate used by
pass_optimize_widening_mul::gate and by the forwprop long-multiply
recognizer. Return false when optimize_debug.
(math_opts_dom_walker::after_dom_children): Dispatch to
lower_long_mul_high_chain on the outer convert. Run
narrow_long_mul_low_half on MULT_EXPR before the widen/fma
conversion attempts.
* tree-ssa-math-opts.h (optimize_widening_mul_active_p): Declare.
2026-08-04 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/107090
* match.pd: Add atom match recognizers for long-multiply
(mul_hi, mul_lo, mul_hilo, mul_lolo, mul_hihi, mul_cross_sum,
mul_low_sum, mul_low_accum, mul_carry_cross_sum,
mul_carry_low_sum, mul_carry_low, mul_ladder_sum1,
mul_ladder_sum2, mul_ladder_sum3, mul_ladder_part_sum), the
cond_carry_add and cond_carry_add_neg recognizers for the 2-arg
PHI carry form, one per gcond polarity, and long_mul_high_chain
for the emitted chain shape.
* tree-ssa-forwprop.cc (gimple_cond_carry_add): Declare.
(gimple_cond_carry_add_neg): Likewise.
(gimple_mul_hi): Likewise.
(gimple_mul_lo): Likewise.
(gimple_mul_hilo): Likewise.
(gimple_mul_lolo): Likewise.
(gimple_mul_hihi): Likewise.
(gimple_mul_cross_sum): Likewise.
(gimple_mul_low_sum): Likewise.
(gimple_mul_low_accum): Likewise.
(gimple_mul_carry_cross_sum): Likewise.
(gimple_mul_carry_low_sum): Likewise.
(gimple_mul_carry_low): Likewise.
(gimple_mul_ladder_sum1): Likewise.
(gimple_mul_ladder_sum2): Likewise.
(gimple_mul_ladder_sum3): Likewise.
(gimple_mul_ladder_part_sum): Likewise.
(build_mul_high_seq): New, emits (N)(((2N) op1 * (2N) op2) >> N)
into a caller-supplied destination.
(long_mul_apply_extras): New, combines the preserved addends back
on top of the folded multiply.
(create_mul_high_seq): New, replaces the statement with the
high-part multiply plus any extras.
(create_mul_low_seq): New, likewise for the low part.
(enum long_mul_kind): New.
(enum long_mul_extract): New.
(struct long_mul_summand): New.
(long_mul_linearize_chain): New, walks the outer add/ior chain
into a multiset of leaves.
(long_mul_is_lshift_def): New.
(long_mul_set_summand): New.
(long_mul_classify_carry): New, most-specific carry atom first.
(long_mul_classify_plus_kinds): New, likewise by specificity.
(long_mul_classify_hi_extract): New.
(long_mul_classify_lo_extract): New.
(long_mul_classify_shl_extract): New.
(long_mul_classify_bare): New.
(long_mul_classify_summand): New, classify a summand via the
match.pd atoms.
(long_mul_summand_compare): New.
(struct long_mul_row): New.
(long_mul_same_ops): New.
(long_mul_is_cross_half): New.
(long_mul_hilo_orientation): New, orientation of a mul_hilo
capture relative to (op0, op1).
(long_mul_canonical_ops): New.
(long_mul_find_summand): New.
(long_mul_check_consistency): New, cross-summand consistency
check (operand pairing, half-width shifts, hilo cross-half).
(long_mul_signature_matches): New.
(long_mul_check_two_carries): New extra check, validates the
two-carry row's carry operands against the canonical (op0, op1).
(long_mul_check_low_plus_defer): New extra check, defers the
low-plus row while a GT/LT/GE/LE use shares an operand with the
PLUS.
(long_mul_hint_shared_intermediate): New, dump-file hint pointing
at a shared inner addition.
(long_mul_classify_match): New, looks a summand multiset up in
long_mul_table, runs the per-row checks, and gates the high-part
emit on optimize_widening_mul_active_p.
(long_mul_classify_chain): New, linearize plus classify plus
table lookup; sets aside leaves that classify as no summand and
takes an optional pre-classified summand.
(match_long_mul): New, top-level entry: starts only at a chain
end and dispatches to create_mul_high_seq / create_mul_low_seq
with any preserved addends.
(match_long_mul_phi): New PHI-driven entry, recognizes a
cond_carry_add(_neg) PHI and folds the long-multiply shape when
the rest of the high-part chain matches.
(pass_forwprop::execute): Call match_long_mul on PLUS_EXPR and
BIT_IOR_EXPR statements, and match_long_mul_phi on each PHI in
the degenerate-PHI walk.
* tree-ssa-math-opts.cc (can_widen_to_narrow_p): New.
(build_long_mul_partials): New, emits the four partial products
using widening or plain multiplies.
(emit_long_mul_highpart): New, the high N bits of an N-bit
product, as a longhand over (N/2)-bit partials.
(combine_long_mul_halves): New, the high N bits of a product of
two 2N-bit values given as N-bit halves.
(long_mul_op_fits_p): New, true when an operand is provably
representable in narrow_prec unsigned bits.
(long_mul_split_operand): New, splits an operand into N-bit
halves using only N-bit operations.
(long_mul_only_low_half_used_p): New.
(narrow_long_mul_low_half): New, narrow a 2N low-half-only mult
the target cannot expand to an N-bit mult.
(narrow_long_mul_operands): New, recurse into chained wide
products after a narrowing/lowering.
(gimple_long_mul_high_chain): Declare.
(lower_long_mul_high_chain): New, lowers the high-part chain to a
longhand at narrow precision, splitting each operand into N-bit
halves and combining them, then narrowing or dropping the
residual 2N mult via the helpers.
(optimize_widening_mul_active_p): New, shared gate used by
pass_optimize_widening_mul::gate and by the forwprop long-multiply
recognizer. Return false when optimize_debug.
(math_opts_dom_walker::after_dom_children): Dispatch to
lower_long_mul_high_chain on the outer convert. Run
narrow_long_mul_low_half on MULT_EXPR before the widen/fma
conversion attempts.
* tree-ssa-math-opts.h (optimize_widening_mul_active_p): Declare.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
* match.pd (((X + C1) & LOWMASK) ==/!= C2): New simplification.
((X & HIGHMASK) >/<= C): Likewise.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126593
* tree-vect-slp-patterns.cc (compatible_complex_nodes_p): Check def
stmts of real and imag pairs.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126301
* tree-vect-loop-manip.cc (vect_use_loop_latch_condition_p): New.
(vect_set_loop_condition_partial_vectors, vect_set_loop_condition): Use
it to rewrite latch and condition.
(vect_set_loop_controls_directly): Adjust IV for do-loop conversion.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126592
* tree-vect-slp-patterns.cc (is_linear_load_p): Rewrite using
vec_perm_indices.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR target/126589
* config/aarch64/aarch64-simd.md (cmul<conj_op><mode>3): Require not
honor signed zeros.
* config/aarch64/aarch64-sve.md (cmul<conj_op><mode>3): Require not
honor signed zeros.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR target/126589
* tree-vect-slp-patterns.cc (vect_validate_multiplication): Refactor.
(vect_validate_multiplication_commutative): New.
(complex_mul_pattern::matches, complex_fms_pattern::matches): Use it.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126602
* match.pd: Fix constraints.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-acle-builtins.h (map_to_rtx_codes): Make
arguments default to `UNSPEC_NONE`.
(map_to_unspecs): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h
(unspec_based_function_base): Make arguments default to
`UNSPEC_NONE`.
(sme_1mode_function): Likewise.
(integer_conversion): Likewise.
(reduction): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl):
Delete unnecessary `UNSPEC_NONE` arguments.
(svcmla_impl): Likewise.
(svnot_impl): Likewise.
(svsub_impl): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc (svadd_write_za): Likewise.
(svaddha_za): Likewise.
(svbmopa_za): Likewise.
(svbmops_za): Likewise.
(svsudot_lane_za): Likewise.
(svsuvdot_lane_za): Likewise.
(svsumopa_za): Likewise.
(svsumops_za): Likewise.
(svusdot_za): Likewise.
(svusdot_lane_za): Likewise.
(svusbdot_lane_za): Likewise.
(svusmopa_za): Likewise.
(svusmops_za): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc (svqcadd_impl): Likewise.
(svqrshl_impl): Likewise.
(svqshl_impl): Likewise.
(svrshl_impl): Likewise.
(svuqadd_impl): Likewise.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.cc (struct
aarch64_pragma_builtins_data): Change type to `unspec`.
(aarch64_get_low_unspec): Likewise.
(aarch64_expand_fpsr_fpcr_setter): Likewise.
(aarch64_expand_tbl_tbx): Add `default` case to `switch` statement to silence warning.
* config/aarch64/aarch64-sve-builtins-base.cc (unspec_cmla): Change type to `unspec`.
(unspec_fcmla): Likewise.
(unspec_cond_fcmla): Likewise.
(expand_mla_mls_lane): Likewise.
(svac_impl): Likewise.
(svbrk_binary_impl): Likewise.
(svbrk_unary_impl): Likewise.
(svclast_impl): Likewise.
(svcmla_impl): Likewise.
(svcmp_impl): Likewise.
(svcmp_wide_impl): Likewise.
(svcvt_impl): Likewise.
(svlast_impl): Likewise.
(svldxf1_impl): Likewise.
(svldxf1_extend_impl): Likewise.
(svnot_impl): Likewise.
(svpfirst_svpnext_impl): Likewise.
(svrint_impl): Likewise.
(svsel_impl): Likewise.
(svwhilelx_impl): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h(rtx_code_function_base): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc (expand_ld1_st1): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc (expand_ld1_st1): Likewise.
* config/aarch64/aarch64-acle-builtins.cc (function_expander::map_to_rtx_codes): Likewise.
(function_expander::map_to_unspecs): Likewise.
* config/aarch64/aarch64-acle-builtins.h: Likewise.
* config/aarch64/aarch64.cc (aarch64_replace_reg_mode): Likewise.
(aarch64_split_sve_subreg_move): Likewise.
(aarch_pac_insn_p): Likewise.
(aarch64_evpc_hvla): Likewise.
* config/aarch64/aarch64.md: Add `UNSPEC_NONE` enum member.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.h (enum aarch64_type_qualifiers): Use shifts.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-acle-builtins.cc (VECTOR_TYPE_none):
Delete preprocessor macro.
* config/aarch64/aarch64-acle-builtins.h (VECTOR_TYPE_none): Add
enum member.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.cc (DEF_SIMD_TYPE): Reformat.
* config/aarch64/aarch64-acle-builtins.cc (vector_types): Likewise.
(mode_suffixes): Likewise.
(group_suffixes): Likewise.
(function_groups): Likewise.
(neon_sve_function_groups): Likewise.
(sme_function_groups): Likewise.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.h (DEF_SIMD_TYPE): Use
variadic arguments.
* config/aarch64/aarch64-acle-builtins.h (DEF_SVE_TYPE): Likewise.
(DEF_SVE_MODE): Likewise.
(DEF_SVE_NEON_TYPE_SUFFIX): Likewise.
(DEF_SME_ZA_SUFFIX): Likewise.
(DEF_SVE_GROUP_SUFFIX): Likewise.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-sve-builtins.def (DEF_SVE_TYPE_SUFFIX): Define
in terms of `DEF_SVE_NEON_TYPE_SUFFIX`.
* config/aarch64/aarch64-acle-builtins.cc (DEF_SVE_TYPE_SUFFIX): Delete
since it is now defined in terms of `DEF_SVE_NEON_TYPE_SUFFIX`.
(DEF_SVE_NEON_TYPE_SUFFIX): Move to be next to `DEF_SVE_TYPE_SUFFIX`.
* config/aarch64/aarch64-acle-builtins.h (DEF_SVE_TYPE_SUFFIX): Rename to ...
(DEF_SVE_NEON_TYPE_SUFFIX): ... here.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-sve-bridge-builtins.def (DEF_NEON_SVE_FUNCTION): Document.
* config/aarch64/aarch64-simd-builtin-types.def (DEF_SIMD_TYPE): Likewise.
* config/aarch64/aarch64-sve-builtins-base.def (DEF_SVE_FUNCTION_GS_FPM): Likewise.
(DEF_SVE_FUNCTION_GS): Likewise.
(DEF_SVE_FUNCTION): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.def (DEF_SME_FUNCTION): Likewise.
(DEF_SME_FUNCTION_GS): Likewise.
(DEF_SME_ZA_FUNCTION_GS): Likewise.
(DEF_SME_ZA_FUNCTION): Likewise.
* config/aarch64/aarch64-sve-builtins.def (DEF_SVE_MODE): Likewise.
(DEF_SVE_TYPE): Likewise.
(DEF_SVE_TYPE_SUFFIX): Likewise.
(DEF_SME_ZA_SUFFIX): Likewise.
(DEF_SVE_GROUP_SUFFIX): Likewise.
(DEF_SVE_FUNCTION_GS_FPM): Likewise.
(DEF_SVE_FUNCTION_GS): Likewise.
(DEF_SVE_NEON_TYPE_SUFFIX): Likewise.
(DEF_SVE_FUNCTION): Likewise.
2026-08-04 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-builtins.cc (ENTRY): Rename to ...
(DEF_SIMD_TYPE): Here.
* config/aarch64/aarch64-builtins.h (ENTRY): Likewise.
(DEF_SIMD_TYPE): Likewise.
* config/aarch64/aarch64-simd-builtin-types.def (ENTRY): Likewise.
(DEF_SIMD_TYPE): Likewise.
* config/aarch64/aarch64-acle-builtins.h (ENTRY): Likewise.
(DEF_SIMD_TYPE): Likewise.
2026-08-04 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126369
* tree-vect-data-refs.cc (vect_enhance_data_refs_alignment): Move
DR_SCALAR_KNOWN_BOUNDS safe speculation check.
2026-08-04 Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
* config/riscv/riscv.cc (riscv_subword_address): Add emit_move_insn for big-endian.
2026-08-04 Shreya Munnangi <smunnang@qti.qualcomm.com>
PR target/108031
* config/riscv/predicates.md (riscv_atomic_memory_operand): New
predicate.
* config/riscv/sync.md (<atomic_optab><mode> pattern and expander):
Use riscv_atomic_memory_operand.
(amo_atomic_<atomic_optab><mode>): Likewise.
(lrsc_atomic_<atomic_optab><mode>): Likewise.
(atomic_fetch_<atomic_optab><mode): Likewise.
(amo_atomic_fetch_<atomic_optab><mode>): Likewise.
(lrsc_atomic_fetch_<atomic_optab><mode>): Likewise.
(subword_atomic_fetch_strong_<atomic_optab>): Likewise.
(atomic_fetch_nand<mode>): Likewise.
(subword_atomic_fetch_strong_nand): Likewise.
(zabha_atomic_fetch_<atomic_optab><mode>): Likewise.
(lrsc_atomic_fetch_<atomic_optab><mode>): Likewise.
(atomic_exchange<mode>): Likewise.
(amo_atomic_exchange<mode>): Likewise.
(amo_atomic_exchange<mode>_extended): Likewise.
(lrsc_atomic_exchange<mode>): Likewise.
(subword_atomic_exchange_strong): Likewise.
(zacas_atomic_cas_value_strong<mode>): Likewise.
(zalrsc_atomic_cas_value_strong<mode>): Likewise.
(subword_atomic_cas_strong): Likewise.
(atomic_test_and_set): Likewise.
2026-08-04 Richard Earnshaw <rearnsha@arm.com>
PR target/124043
* config/arm/vfp.md (thumb2_movsi_vfp): Don't hide the t->r
alternative from register preferencing.
2026-08-04 Richard Earnshaw <rearnsha@arm.com>
* config/arm/neon.md (neon_vdup_lane<VDQW:mode>_internal):
Handle core registers as the input vector operand by splitting.
(neon_vdup_lane<VHFBF:mode>_internal): Likewise.
(neon_vdupq_lane<VQ2BF:mode>_internal): New pattern.
2026-08-04 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (float_widen_lhs_range): Convert to
sub-ranges.
(range_op_float_tests): New test.
2026-08-04 Aldy Hernandez <aldy@quesejoda.com>
* range-op-float.cc (float_widen_bound): New, factored out of...
(float_widen_lhs_range): ...here.
2026-08-04 Egas Ribeiro <egas.g.ribeiro@gmail.com>
PR analyzer/119697
* langhooks.h (struct lang_hooks): Add exception_matches_type_p.
* langhooks-def.h (LANG_HOOKS_EH_MAY_CATCH_P): Define as
hook_bool_tree_tree_false.
(LANG_HOOKS_INITIALIZER): Add it.
2026-08-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126601
* tree-ssa-math-opts.cc (maybe_optimize_guarding_check): Use safe_push
on mul_stmts rather than quick_push.
2026-08-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126564
* tree-ssa-phiopt.cc (spaceship_replacement): Fix up condition
when to punt because of redundant cmp1 with cmp2, xor in
lhs1 == lhs2 with difference of cmp2 from cmp1 (ignoring
LT_EXPR vs. LE_EXPR and GT_EXPR vs. GE_EXPR differences) and
1 if cond2_phi_edge is EDGE_FALSE_VALUE.
2026-08-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126549
* range-op-float.cc (operator_cast::fold_range): Don't call
frange_drop_infs.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/116815
* config/aarch64/aarch64.md
(*aarch64_plus_within_<optab><mode>3_<ovf_commutate>): Add a
clobber of CC_REGNUM.
(*aarch64_minus_within_<optab><mode>3): Likewise.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
* sched-int.h (struct deps_desc): Add pending_barriers. Update the
reg_last_dirty description.
(deps_reg_last): Declare.
* sched-deps.cc: Include selftest-rtl.h.
(deps_reg_last): New.
(sched_analyze_insn): Materialize pending barriers when required.
Use the lazy barrier form before reload outside selective scheduling.
Reconcile reg_last_dirty entries at barriers.
(init_deps): Initialize pending_barriers.
(free_deps): Release pending_barriers.
(selftest::observed_barrier_deps): New.
(selftest::observe_barrier_dependence): New.
(selftest::assert_insn_list): New.
(selftest::test_full_lazy_barrier): New.
(selftest::test_sparse_lazy_barrier): New.
(selftest::test_lazy_barrier_join): New.
(selftest::test_lazy_barriers): New.
(selftest::sched_deps_cc_tests): Run the lazy-barrier tests.
* sched-rgn.cc (deps_join): Combine pending and materialized barrier
state.
* sel-sched-ir.cc (has_dependence_p): Assert that selective
scheduling has no pending barriers.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
* sched-deps.cc (reg_last_pool, reg_last_pool_max_reg): New.
(alloc_reg_last, release_reg_last): New.
(init_deps, init_deps_reg_last): Use alloc_reg_last.
(free_deps): Reset the list length fields and release reg_last to the
pool.
(sched_deps_finish): Release the pooled arrays.
(selftest::test_reg_last_pool): New.
(selftest::sched_deps_cc_tests): Run it.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
* sched-int.h (struct deps_desc): Add reg_last_dirty.
* sched-deps.cc: Include selftest.h.
(sched_analyze_insn): Record debug-insn uses and control uses in
reg_last_dirty.
(init_deps): Initialize reg_last_dirty.
(free_deps): Merge reg_last_dirty into reg_last_in_use for teardown,
then clear it.
(selftest::test_dirty_reg_last_release): New.
(selftest::sched_deps_cc_tests): New. Provide an empty definition
when INSN_SCHEDULING is not defined.
* selftest-run-tests.cc (selftest::run_tests): Call
sched_deps_cc_tests.
* selftest.h (selftest::sched_deps_cc_tests): Declare.
2026-08-04 Kyrylo Tkachov <ktkachov@nvidia.com>
* sched-deps.cc (sched_deps_finish): Reset cache_size after clearing
and freeing the dependency caches.
2026-08-04 H.J. Lu <hjl.tools@gmail.com>
PR target/126320
PR target/126450
PR target/126529
* config/i386/i386.cc (ix86_spill_register_argument_p): Removed.
(ix86_argument_passed_on_stack_p): Remove the second argument.
Return true if the argument's DECL_INCOMING_RTL is a memory
operand.
(ix86_update_stack_alignment): Updated.
2026-08-04 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-sr.cc (riscv_sr_match_epilogue): Accept
SP-only stack ties.
* config/riscv/riscv.cc (riscv_emit_stack_tie): Use parameterized
generators and emit SP-only ties.
(riscv_expand_epilogue): Use SP ties without a frame pointer.
* config/riscv/riscv.md (@stack_tie<mode>): Use a parameterized name.
(@stack_tie_sp<mode>): New pattern.
2026-08-04 Avinal Kumar <avinal.xlvii@gmail.com>
PR tree-optimization/101650
* match.pd: Simplify (A | C) == A to (A & C) != 0 when C is
power of 2.
2026-08-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/msp430/msp430.cc (msp430_insn_cost): Handle insns with
NOOP_MOVE_INSN_CODE.
2026-08-03 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/63387
* match.pd: Combine four simplify into one for.
2026-08-03 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* hwint.h (sext_hwi): Combine duplicated C++ code.
2026-08-03 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (frange::set_nonzero): Implement.
(frange::nonzero_p): Implement.
(range_tests_excluding): Test set_nonzero and nonzero_p.
2026-08-03 Reshma Roy <Reshma.Roy@amd.com>
PR tree-optimization/126466
* match.pd: Fix incorrect POPCOUNT identification in the third
32-bit Hacker's Delight matcher.
2026-08-03 Jakub Jelinek <jakub@redhat.com>
PR target/126484
* config/mips/mips-ftypes.def (MIPS_SI_FTYPE_VOID,
MIPS_USI_FTYPE_VOID): Use DEF_MIPS_FTYPE with 0 as
first argument rather than 1 and leave out ", VOID" from
second argument.
* config/mips/mips.cc (MIPS_FTYPE_NAME0): Define.
(MIPS_FTYPE_ATYPES0): Define.
2026-08-03 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (class frange): Declare set_excluding.
* value-range.cc (frange::set_excluding): New.
(frange::set): Assert KIND is VR_RANGE or VR_ANTI_RANGE and that the
endpoints are not NAN. Turn a VR_ANTI_RANGE into the two sub-ranges
that exclude the point.
(frange_float_excluding, range_tests_excluding): New.
(range_tests_floats): Call range_tests_excluding.
* value-range-storage.cc (frange_storage::get_frange): Return early
for VR_VARYING, like irange_storage::get_irange.
2026-08-03 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (class frange): Raise MAX_PAIRS to 2.
* value-range.cc: Include value-range-storage.h.
(real_from_str, range_tests_sub_ranges, range_tests_sub_ranges_nan)
(range_tests_sub_ranges_zero, range_tests_sub_ranges_storage): New.
(range_tests_floats): Call them, and adjust the disjoint-union test.
2026-08-03 Souradipto Das <souradiptodas6@gmail.com>
PR target/126411
* config/riscv/riscv-v.cc (shuffle_slide_patterns): Check that
the sequence endpoints correspond to OP0's and OP1's expected
positions and also reject a second pivot when need_slideup_p is set.
2026-08-02 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/19832
* match.pd: Combine two patterns into one for.
2026-08-02 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/117760
PR tree-optimization/125442
* match.pd: Combine four fors into one for.
2026-08-02 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* match.pd: Combine two patterns into for.
2026-08-02 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126569
* tree-ssa-phiopt.cc (cond_store_replacement_limited): A
clobber is not a store.
2026-08-02 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126571
* tree-ssa-phiopt.cc (factor_out_conditional_load): Reject
when the pointer types are not compatible when creating a phi.
2026-08-01 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-expand.cc (ix86_expand_vector_init_one_nonzero):
Improved implementations for V2DI, V2DF, V4SI, V4SF, V4DI and V4DF
modes. Return false for V2SI and V2SF modes if the one non-zero
element isn't the first/lowest. Improved implementations for V8HI,
V16QI, V2HI and V8QI modes.
(nonzero_int_const_count): New helper function to count the
number of non-zero integer constants in a given array.
(nonzero_float_const_count): Likewise for SFmode floats.
(nonzero_double_const_count): Likewise for DFmode doubles.
(ix86_expand_vector_init_insert): New function to initialize a
V4SI, V8HI or V16QI vector using a sequence of pinsr[bwd] insns.
(onevar_perm_p): New local helper function.
(twovar_perm_p): Likewise.
(ix86_expand_vector_init_v2di): New mode-specific function.
(ix86_expand_vector_init_v2df): Likewise.
(ix86_expand_vector_init_v4si): Likewise.
(ix86_expand_vector_init_v4sf): Likewise.
(ix86_expand_vector_init_v8hi): Likewise.
(ix86_expand_vector_init_v16qi): Likewise.
(ix86_expand_vector_init_v4di): Likewise.
(ix86_expand_vector_init_v4df): Likewise.
(ix86_expand_vector_init_v8si): Likewise.
(ix86_expand_vector_init_v8sf): Likewise.
(ix86_expand_vector_init_general): Call the above custom helper
functions for the relevant modes.
* config/i386/sse.md (*vec_interleave_lowv4si_sse): New pattern
for (V4SImode) unpcklps on TARGET_SSE but not TARGET_SSE2.
2026-08-01 Jakub Jelinek <jakub@redhat.com>
* ipa-polymorphic-call.cc (csftc_abort_walking_p): Remove useless
"? true : false".
* tree-ssa-loop-im.cc (ref_indep_loop_p): Likewise.
* match.pd (X ==/!= !X is false/true): Replace "? false : true"
with negation of the condition.
(((C << x) & D) != 0): Likewise.
(fold_sign_changed_comparison and fold_widened_comparison): Likewise.
Remove useless "? true : false".
(if the second operand is NaN, the result is constant): Replace
"? false : true" with negation of the condition.
(__builtin_ctz (x) >= C -> (x & ((1 << C) - 1)) == 0): Likewise.
Remove useless "? true : false".
(__builtin_ctz (x) == C -> (x & ((1 << (C + 1)) - 1)) == (1 << C)):
Replace "? false : true" with negation of the condition.
(__builtin_ffs (X) == 0 -> X == 0): Remove useless "? true : false".
(__builtin_ffs (X) > 6 -> X != 0 && (X & 63) == 0): Likewise.
Replace "? false : true" with negation of the condition.
* gimple-pretty-print.cc (dump_phi_nodes): Use !(flags & TDF_GIMPLE)
instead of (flags & TDF_GIMPLE) ? false : true.
2026-08-01 Pan Li <pan2.li@intel.com>
Claude Opus 5 (1M context) <noreply@anthropic.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-08-01 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126313
* gimple-fold.cc (follow_outer_ssa_edges): Swap around returning
for undefined overflow and saving off the global range.
2026-07-31 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126458
* match.pd (min/max detection): Fix precision of
the signed type min.
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126504
* match.pd ((CST1 << A) == CST2 -> A == ctz (CST2) - ctz (CST1)):
If cand isn't representable in TREE_TYPE (@1), simplify to
cmp == NE_EXPR.
(((1 << n) & M) != 0 -> n == log2 (M)): Don't simplify if
log2 doesn't fit into TREE_TYPE (@0).
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126503
* gimple-lower-bitint.cc (bitint_large_huge::handle_plus_minus): If
IFN_ADDC/IFN_SUBC can't be used and rhs1_type is not the limb type
and is signed, perform both additions or both subtractions in
unsigned type for the rhs1_type and cast to rhs1_type at the end.
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR middle-end/126497
* gimplify.cc (recalculate_side_effects): Return for
tcc_declaration.
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126490
* match.pd ((a & b) == (a ^ b) -> !(a | b)): If @0 has
integral one bit precision type, use (convert:type ...) around the
bit_not just in case the comparison has a different result type
from the type of its operands. Otherwise do that too but with
bit_not replaced with bit_xor with one of the appropriate type.
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126464
* range-op-float.cc (float_widen_lhs_range): Remove also_inf
argument, replace its uses as if it was always true.
(operator_cast::op1_range): Don't pass third argument to
float_widen_lhs_range.
2026-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126476
* match.pd (((C << A) & D) != 0 -> A == 0,
((C << A) & D) == 0 -> A != 0): Fold to false/true if
c1 - c2 resp. c2 - c1 doesn't fit into TREE_TYPE (@0).
2026-07-30 Aldy Hernandez <aldy@quesejoda.com>
* value-range-storage.h (class frange_storage): Replace the fixed
m_pairs[MAX_PAIRS] with a variable-length trailing array and an
m_max_ranges capacity; declare size and the constructor.
* value-range-storage.cc (frange_storage::size): New.
(frange_storage::alloc): Allocate size (r) bytes.
(frange_storage::frange_storage): New; record m_max_ranges.
(frange_storage::fits_p): Check m_max_ranges.
2026-07-30 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (frange::union_): Merge both operands' sub-ranges
via set_pairs instead of widening to the hull.
2026-07-30 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (frange_min, frange_max): New.
(frange::intersect_nans): Use set_nan.
(frange::intersect): Meet every sub-range against every other.
2026-07-30 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_vectorization_profitable_p):
Dump SLP graph entries.
2026-07-30 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vectorizable_live_operation): Insert
on entry when the vector def is a default def or a constant.
2026-07-30 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/122848
* match.pd (zero_extend & sign_extend -> zero_extend): New pattern.
(zero_extend | sign_extend -> sign_extend): Likewise.
2026-07-30 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/109843
* match.pd ((signbit (x) cmp 0) cmp (signbit (y) cmp 0) ? y : -y):
New simplification to copysign (y, +-x).
2026-07-30 Richard Biener <rguenther@suse.de>
* config/rs6000/rs6000.cc (rs6000_cost_data::density_test):
Start BB walk after labels.
2026-07-30 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/autovec-opt.md: Match the new vwmacc-like pattern.
* config/riscv/genrvv-type-indexer.cc: Support
DOUBLE_TRUNC_SIGNED type for v[u]int types.
* config/riscv/riscv-vector-builtins-bases.cc (class vabd): New
class.
(class vabs): Ditto.
(class vabda): Ditto.
(BASE): Define.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
Ditto.
(vabs): Ditto.
(vabd): Ditto.
(vabdu): Ditto.
(vwabda): Ditto.
(vwabdau): Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QU_HU_OPS):
Define.
(DEF_RVV_HU_SU_OPS): Ditto.
* config/riscv/riscv-vector-builtins.cc (qu_hu_ops): Ditto.
(hu_su_ops): Ditto.
(ss_args): Ditto.
(wwss_args): Ditto.
(qu_hu_vss_ops): Ditto
(qu_hu_vvv_ops): Ditto
(hu_su_wwss_ops): Ditto
(hu_su_wwvv_ops): Ditto
(u_s_ops): Ditto
(get_builtin_partition): Add Zvabd case.
* config/riscv/riscv-vector-builtins.h (enum required_ext):
Ditto.
(enum rvv_builtin_partition): Ditto.
(required_ext_to_isa_name): Ditto.
(required_extensions_specified): Ditto.
* config/riscv/riscv_vector.h (__riscv_intrinsic_zvabd): Define.
* config/riscv/vector.md: Rewrite pred_widen_abd_plus as
vwmacc-like form.
2026-07-30 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/autovec-opt.md (*vwabda<su><mode>): Limit mode to
VWEXTI_HS.
(*vwabda_right<su><mode>): Ditto.
* config/riscv/autovec.md (<su>abd<mode>3): Limit mode to VI_QH.
* config/riscv/vector-iterators.md: New iterators. VWEXTI
rewritten using VWEXTI_HS and VWEXTI_D.
* config/riscv/vector.md: Limit modes in Zvabd patterns except
vabs.
2026-07-30 Christopher Bazley <chris.bazley@arm.com>
* config/aarch64/aarch64.cc (aarch64_detect_scalar_stmt_subtype):
Call the new vect_is_truncating_store function and return 0 if
vect_is_truncating_store returns true.
(aarch64_sve_adjust_stmt_cost): Call vect_is_truncating_store
and assign 0 to stmt_cost if vect_is_truncating_store returns
true.
* tree-vectorizer.h (vect_is_truncating_store): New function
analogous to vect_is_extending_load.
2026-07-30 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Also
skip labels.
* tree-vect-slp.cc (_bb_vec_info::_bb_vec_info): Likewise.
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
Skip labels.
2026-07-30 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_add_slp_permutation): We no longer
need a copy when the extraction is readily available.
(vect_schedule_slp_node): Handle default defs or constants
in vector defs.
2026-07-30 Sebastian Galindo <sebastian.galindo143@gmail.com>
Thomas Schwinge <tschwinge@baylibre.com>
* builtin-types.def (BT_FN_VOID_INT_INT): New definition.
* omp-builtins.def (BUILT_IN_GOACC_INIT): New builtin for
init directive.
(BUILT_IN_GOACC_SHUTDOWN): New builtin for shutdown directive.
(BUILT_IN_GOACC_SET_DEVICE): New builtin for set directive.
2026-07-30 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/123311
* match.pd (min(clz(x), clz(y)) -> clz(x | y)): New pattern.
(min(ctz(x), ctz(y)) -> ctz(x | y)): Likewise.
2026-07-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126464
* range-op-float.cc (float_widen_lhs_range): Add also_inf argument
defaulted to false, if true, extend even lb of +inf and ub of -inf.
(operator_cast::op1_range): Adjust float_widen_lhs_range caller.
2026-07-30 Jakub Jelinek <jakub@redhat.com>
PR middle-end/126084
* asan.cc (maybe_instrument_call): Don't instrument
BUILT_IN_ASAN_REPORT_{LOAD,STORE}{1,2,4,8,16,_N} builtins.
(initialize_sanitizer_builtins): Use
(*lang_hooks.types.type_for_mode) (ptr_mode, 0) instead of
pointer_sized_int_mode for PTRMODE arguments.
(asan_expand_poison_ifn): Likewise.
2026-07-30 Jakub Jelinek <jakub@redhat.com>
* match.pd (parity(bswap(x)) is parity(x)): Use BSWAP BITREVERSE
instead of BUILT_IN_BSWAP16 BUILT_IN_BSWAP32 BUILT_IN_BSWAP64
BUILT_IN_BSWAP128.
2026-07-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126471
* match.pd (parity(~X) is parity(X)): Only optimize this way
if element_precision is even, otherwise optimize into parity(X) ^ 1.
2026-07-30 Jin Ma <jinma@linux.alibaba.com>
PR target/126449
* config/riscv/riscv.cc (riscv_legitimize_call_address): Use
STATIC_CHAIN_REGNUM when a sibcall address is materialized in
post-reload thunk code.
2026-07-30 Gerald Pfeifer <gerald@pfeifer.com>
* doc/invoke.texi (AArch64 Options): Spell CPU in uppercase
letters.
(RS/6000 and PowerPC Options): Ditto.
(S/390 and zSeries Options): Ditto.
(SPARC Options): Ditto.
2026-07-30 Avinash Jayakar <avinashd@linux.ibm.com>
PR target/126438
* config/rs6000/darwin.h (REGISTER_NAMES): Add dmf registers.
2026-07-30 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (class frange): Declare set_pairs. Document the
sub-range representation and that the no-argument bounds are the
convex hull.
* value-range.cc (frange_fusible_p): New.
(frange::set_pairs): New.
(frange::flush_denormals_to_zero): Reinstall the endpoints through
set_pairs.
(frange::normalize_kind): Note a range with a gap is never varying.
(frange::verify_range): Check the sub-range invariants.
2026-07-30 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126455
* match.pd: Fix up patterns dealing with bitwise AND/OR/XOR
and comparisons for floating point types.
2026-07-30 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126470
* match.pd (`(a != 0) ? (a / b) : 0`): Fix argument
to expr_no_side_effects_p.
2026-07-30 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126456
* match.pd (`a CMP b ? MIN/MAX<a, c> : MIN/MAX<a, d>`): Fix
order of minmax_from_comparison arguments.
2026-07-30 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-29 Jakub Jelinek <jakub@redhat.com>
PR target/126446
* gimple-isel.cc (gimple_expand_vec_set_extract_expr): Punt if
idx doesn't fit into poly_uint64 but is poly_int_tree_p. Use
known_ge rather than known_gt for out of bounds check. Formatting
fixes.
2026-07-29 Roger Sayle <roger@nextmovesoftware.com>
PR target/126276
* config/cris/cris.md (*btst<BWD><ZnNNZSET): Handle BWD modes,
not just SImode.
(*cbranch<mode>4_btstrq1_<CC>): Likewise.
(*cbranch<mode>4_btstqb0_<CC>): Likewise.
2026-07-29 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/126434
* avoid-store-forwarding.cc (process_store_forwarding): Unshare the
load destination when building the re-extension move.
2026-07-29 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/126465
* match.pd: Fix FMS patterns.
2026-07-29 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/126415
PR tree-optimization/124545
* match.pd ((T)A +- CST -> (T)(A +- CST')): Revert.
* tree-ssa-sccvn.cc (ssa_integral_conversion_op): New function.
(vn_nary_result_avail_or_insertable_p): New function, split out
from ...
(visit_nary_op): ... here. Handle ((T)p) +- X by looking up
(p +- X') and converting the result, for X an integer constant
that narrows and extends back unchanged or a conversion from
the same narrow type.
2026-07-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/126457
* tree-vect-loop.cc (vectorizable_reduction): Reject
operations where not all operands correspond to a SLP
child early.
2026-07-29 Thomas Schwinge <tschwinge@baylibre.com>
* gimplify.cc (gimplify_omp_workshare)
[OMP_TARGET && OMP_CLAUSE_DEVICE_TYPE_NOHOST]: Use
'build_string_literal'. Use 'build_int_cst'.
2026-07-29 mengqinggang <mengqinggang@loongson.cn>
* config/loongarch/loongarch.cc (loongarch_output_dwarf_dtprel):
Remove 0x8000.
2026-07-29 Jakub Jelinek <jakub@redhat.com>
PR target/126446
* config/i386/i386-expand.cc (ix86_expand_vector_set): If elt is
out of bounds, emit a no-op move.
2026-07-29 H.J. Lu <hjl.tools@gmail.com>
PR target/126450
* config/i386/i386.cc (ix86_spill_register_argument_p): Check
the argument-linked memory used to store local variable.
2026-07-29 Jakub Jelinek <jakub@redhat.com>
PR middle-end/126447
* gimple-lower-bitint.cc (gimple_lower_bitint): For
ifn calls with large/huge _BitInt (ab) SSA_NAME lhs if they
have such (ab) argument too, force it into temporary SSA_NAME
for IFN_BSWAP, IFN_BITREVERSE, IFN_UBSAN_CHECK_MUL and, if
bitint_big_endian, also for IFN_UBSAN_CHECK_{ADD,SUB}.
2026-07-29 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/gcc-auto-profile: Probe for arm_spe with
"perf list pmu" instead of "perf list".
* configure.ac: Likewise.
* configure: Regenerate.
2026-07-29 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (s390_canonicalize_comparison): Verify op0
for an UNSPEC_CC_TO_INT is a register.
2026-07-29 Hongyu Wang <hongyu.wang@intel.com>
* config/i386/i386.md (*addqi_1<nf_name>): Merge the two
preferred_for_speed attributes into one.
(*andqi_1<nf_name>): Likewise.
(*andqi_2_maybe_si): Likewise.
(*<code>qi_1<nf_name>): Likewise.
(*notxorqi_1): Likewise.
(*one_cmplqi2_1): Likewise.
(*ashlqi3_1<nf_name>): Likewise.
2026-07-28 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/126397
* tree-ssa-ifcombine.cc (ifcombine_ifandif): Remove
true condition.
2026-07-28 Reshma Roy <Reshma.Roy@amd.com>
* config/i386/i386-features.cc (ix86_emit_tls_call): Additional
check to see if DRAP register is live in basic block with DF_LR_IN.
2026-07-28 Aldy Hernandez <aldy@quesejoda.com>
* value-range-storage.cc (frange_storage::get_frange): Restore
every sub-range.
* value-range-pretty-print.cc (vrange_printer::visit): Print each
sub-range.
2026-07-28 John David Anglin <danglin@gcc.gnu.org>
* configure.ac: Set gcc_cv_as_cfi_directive to no on
hppa*-*-hpux*.
* configure: Regenerate.
2026-07-28 Arsen Arsenović <aarsenovic@baylibre.com>
* gcc.cc (execute): Make "signal terminated program" message
clearer.
2026-07-28 Aldy Hernandez <aldy@quesejoda.com>
* value-range.h (struct frange_pair): New.
(class frange): Replace m_min and m_max with m_pairs[MAX_PAIRS]
and m_num_ranges. Add MAX_PAIRS, num_pairs, and the indexed
lower_bound and upper_bound. Have canonicalize_zeros take an
frange_pair.
(frange::lower_bound, frange::upper_bound): Adjust.
(frange::set_varying, frange::set_undefined, frange::set_nan)
(frange::known_isfinite, frange::known_isnormal)
(frange::known_isdenormal_or_zero, frange::maybe_isinf)
(frange::known_isinf, frange::signbit_p): Adjust.
* value-range.cc (frange::flush_denormals_to_zero): Adjust.
(frange::canonicalize_zeros): Take an frange_pair.
(frange::set, frange::normalize_kind, frange::union_nans)
(frange::union_, frange::intersect, frange::operator=)
(frange::operator==, frange::contains_p)
(frange::internal_singleton_p, frange::singleton_p)
(frange::verify_range, frange::zero_p): Adjust.
* value-range-storage.h (class frange_storage): Replace m_min
and m_max with m_pairs and m_num_ranges.
* value-range-storage.cc (frange_storage::set_frange): Adjust.
(frange_storage::get_frange): Adjust.
2026-07-28 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* match.pd: Combine patterns into five for.
2026-07-28 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-acle-builtins.h
(TYPES_cvtzn): New function types.
(TYPES_cvttb): Likewise.
(cvtzn): Likewise.
(cvttb): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc
(class svcvtt_impl): New function impl.
(class svcvtb_impl): Likewise.
(FUNCTION): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def
(svcvtn): New function.
(svcvtt): Likewise.
(svcvtb): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h: Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve2_scvtfb<mode>): New pattern.
(@aarch64_sve2_scvtflt<mode>): Likewise.
(@aarch64_sve2_ucvtfb<mode>): Likewise.
(@aarch64_sve2_ucvtflt<mode>): Likewise.
(@aarch64_sve2_fcvtzsn<mode>): Likewise.
(@aarch64_sve2_fcvtzun<mode>): Likewise.
* config/aarch64/iterators.md
(b): Ventype changes.
(VNx16HF): Likewise.
(VNx16QI): Likewise.
2026-07-28 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-c.cc
(aarch64_update_cpp_builtins): New target flag.
* config/aarch64/aarch64-simd-builtins.def: New functions.
* config/aarch64/aarch64-simd.md
(sdot_prod<VDQSF:vsi2qi><vczle><vczbe>): New pattern.
(sdot_lane<VF:isquadop><VDQSF:vsi2qi><vczle><vczbe>): Likewise.
* config/aarch64/aarch64.h
(TARGET_F16F32DOT): New target flag.
* config/aarch64/arm_neon.h
(target): Add f16f32dot section.
(__attribute__): New builtin function calls.
(vdot_f32_f16): Likewise.
(vdotq_f32_f16): Likewise.
(vdot_lane_f32_f16): Likewise.
(vdot_laneq_f32_f16): Likewise.
(vdotq_lane_f32_f16): Likewise.
(vdotq_laneq_f32_f16): Likewise.
* config/aarch64/iterators.md
(q): New options for isquadop.
* doc/invoke.texi: Add f16f32dot.
2026-07-28 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-acle-builtins.h
(TYPES_s_narrow_su): New type array.
(s_narrow_su): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc
(class svdot_impl): Update impl.
(FUNCTION): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def
(REQUIRED_EXTENSIONS): New function.
(svdot): Likewise.
(svdot_lane): Likewise.
* config/aarch64/aarch64-sve2.md
(<sur>dot_prodvnx4sivnx8hi): Renamed.
(@<sur>dot_prod<VNx4SI_ONLY:mode><VNx8HI_ONLY:mode>): New Name.
(@<sur>dot_prod<VNx8HI_ONLY:mode><VNx16QI_ONLY:mode>): New pattern.
(@aarch64_<sur>dot_prod_lane<VNx8HI_ONLY:mode><VNx16QI_ONLY:mode>): Likewise.
* config/aarch64/aarch64.h
(TARGET_SVE2p3): New Target Flag.
(TARGET_SME2p3): Likewise.
(TARGET_STREAMING_SME2p3): Likewise.
(TARGET_SVE2p3_OR_SME2p3): Likewise.
* doc/invoke.texi: Add sve2p3/sme2p3.
2026-07-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/126404
* tree-vect-patterns.cc (vect_recog_popcount_clz_ctz_ffs_pattern):
Avoid recursing to vect_recog_ctz_ffs_pattern with a reduction.
2026-07-28 H.J. Lu <hjl.tools@gmail.com>
Richard Biener <rguenther@suse.de>
PR middle-end/126410
* tree-vect-stmts.cc (vectorizable_store): Only commit to
recorded base alignment when transforming.
(vectorizable_load): Likewise.
2026-07-28 Haochen Jiang <haochen.jiang@intel.com>
PR target/126429
* config/i386/sse.md (avx512fmaskhalfmode): Removed.
(avx512f_dpbf16ps_<mode>_maskz): Use avx512fmaskmode instead of
avx512fmaskhalfmode.
(avx512f_dpbf16ps_<mode>_mask): Ditto.
(avx512f_dpbf16ps_<mode><maskz_half_name>): Rename to ...
(avx512f_dpbf16ps_<mode><sd_maskz_name>): ... this. Use
corresponding sd_mask_op4.
* config/i386/subst.md (maskz_half): Remove not used pattern.
2026-07-28 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/126405
* cfgexpand.cc (verify_partition_mem_exprs): New function.
(pass_expand::execute): Call it.
2026-07-28 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/126405
* tree-outof-ssa.cc (split_overlapping_partition_decls): Also split
partitions of PARM_DECLs and RESULT_DECLs.
2026-07-28 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/126405
* cfgexpand.cc (leader_merge): Rename to...
(expand_leader_merge): ...this. Make external.
* cfgexpand.h (expand_leader_merge): Declare.
* tree-outof-ssa.cc: Include cfgexpand.h.
(split_overlapping_partition_decls): Determine the variable of a
partition from all of its names.
2026-07-28 Uros Bizjak <ubizjak@gmail.com>
PR target/126433
* config/i386/i386.md (*bswaphi2_movbe) Use enabled attribute.
Remove preferred_for_speed and preferred_for_size attributes.
(*bswaphi2): Ditto.
(*bswaphisi2_lowpart): Ditto.
2026-07-28 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree.cc (ssa_uniform_vector_p): Look through a
VEC_DUPLICATE_EXPR SSA definition.
2026-07-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/126417
* tree-vect-slp.cc (vectorizable_bb_reduc_epilogue): Check
the total number of lanes instead of the vector type against
the two-lane special case that doesn't need fold-left reduction
handling.
2026-07-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/126404
* tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Fixup
conversion detection.
2026-07-27 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* match.pd: Combine two for into one for.
2026-07-27 Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (gimplify_scan_omp_clauses): Handle also TREE_LIST
for num_teams, num_threads, thread_num clauses. Add message clause
to switch statement.
* omp-expand.cc (expand_parallel_call, expand_teams_call,
get_target_arguments): Handle, mostly with 'sorry, unimplemented',
the 'dims' and 'strict' modifiers and the 'message' clause.
* omp-low.cc (scan_sharing_clauses): Add message clause to switch.
(lower_omp_teams): Handle TREE_LIST for num_threads + thread_num.
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_MESSAGE.
* tree-pretty-print.cc (dump_omp_clause): Handle 'message' clause,
update num_teams, num_threads, thread_num clause printing.
* tree.cc (omp_clause_num_ops, omp_clause_code_name): Update for
message clause.
* tree.h (OMP_CLAUSE_NUM_THREADS_STRICT,
OMP_CLAUSE_THREAD_LIMIT_STRICT, OMP_CLAUSE_NUM_TEAMS_DIMS,
OMP_CLAUSE_NUM_THREADS_DIMS, OMP_CLAUSE_THREAD_LIMIT_DIMS,
OMP_CLAUSE_MESSAGE_EXPR, OMP_CLAUSE_MESSAGE_LEN,
OMP_CLAUSE_MESSAGE_SEVERITY_WARN): New.
2026-07-27 Jakub Jelinek <jakub@redhat.com>
* doc/sourcebuild.texi (arm_neon_fp16_hw, arm_fp16_alternative_hw):
Use @code{...} instead of @code(...).
2026-07-27 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
* doc/sourcebuild.texi (arm_fp16_alternative_hw): Document.
(arm_neon_fp16_hw): Add reference to arm_neon_fp16_ok.
2026-07-27 liuhongt <hongtao.liu@intel.com>
* config/i386/i386.cc (ix86_vector_costs): Add
better_fold_left_reduc_than_p and m_num_fold_left_reduc_lanes.
(ix86_vector_costs::ix86_vector_costs): Initialize it.
(ix86_vector_costs::finish_cost): Count and dump fold-left
reduction lanes.
(ix86_vector_costs::better_fold_left_reduc_than_p): New function.
(ix86_vector_costs::better_main_loop_than_p): Use it.
(ix86_vector_costs::better_epilogue_loop_than_p): Likewise.
2026-07-26 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Return
false when wide_mode and mode are same.
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126138
* tree-ssa-phiopt.cc (one_feeding_comparison_into_p): New function.
(comparison_combine): New function.
(pass_phiopt::execute): Call comparison_combine.
2026-07-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126138
* tree-ssa-ifcombine.cc (bb_no_side_effects_p): Don't reject GIMPLE_COND
that can trap.
(ifcombine_ifandif): Handle trapping inner conditional specially.
2026-07-25 Andrea Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/126138
* fold-const.cc (combine_comparisons): Allow eq to combine
with || and ne combine with && if the original rcode was trapping
and the new code is trapping.
2026-07-25 Jakub Jelinek <jakub@redhat.com>
* sym-exec/sym-exec-expression.cc (symbolic_bit::print): Use
HOST_SIZE_T_PRINT_UNSIGNED instead of "%zu" and add cast to
fmt_size_t.
* genoutput.cc (main): Likewise.
2026-07-25 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/126184
* ifcvt.cc (init_noce_multiple_sets_info): Record only the most
recent prior definition of each pseudo register.
2026-07-25 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/126184
* ifcvt.cc (init_noce_multiple_sets_info): Assert that destinations
are pseudos.
(bb_ok_for_noce_convert_multiple_sets): Reject hard-register
destinations.
2026-07-25 Ashley Chekhova <giraffe.commits@aol.com>
PR tree-optimization/92408
* tree-ssa-forwprop.cc (optimize_strlen_comp): Rewrite
strlen(s) == 0 as *s == 0 and strlen(s) != 0 as *s != 0.
(simplify_builtin_call): Added call to optimize_strlen_comp.
2026-07-25 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/126334
* config/riscv/riscv-v.cc (get_gather_scatter_code): Use ordered
indexed stores.
2026-07-25 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/125507
* cfgloop.h (class loop): Remove ENUM_BITFIELD.
* cgraph.h (struct toplevel_node): Ditto.
(struct symtab_node): Ditto.
(struct cgraph_node): Ditto.
* combine.cc (struct reg_stat_type): Ditto.
* config/i386/i386.h (struct machine_function): Ditto.
* cse.cc (struct qty_table_elem): Ditto.
(struct table_elt): Ditto.
(struct set): Ditto.
* df.h (struct df_mw_hardreg): Ditto.
(struct df_base_ref): Ditto.
* domwalk.h (class dom_walker): Ditto.
* dwarf2out.h (struct dw_val_node): Ditto.
* gimple.h (struct gimple): Ditto.
* ipa-predicate.h (struct expr_eval_op): Ditto.
(struct condition): Ditto.
* ipa-ref.h (struct ipa_ref): Ditto.
* ira-int.h (struct ira_dependent_filter): Ditto.
(struct ira_allocno): Ditto.
* lra-int.h (struct lra_operand_data): Ditto.
(struct lra_insn_reg): Ditto.
* optabs.h (class expand_operand): Ditto.
* recog.h (struct operand_alternative): Ditto.
(struct insn_operand_data): Ditto.
* ree.cc (struct ext_modified): Ditto.
* regrename.h (struct du_chain): Ditto.
* rtl.h (struct rtx_def): Ditto.
* sched-int.h (struct _dep): Ditto.
* tree-into-ssa.cc (struct common_info): Ditto.
* tree-ssa-loop-ivopts.cc (struct iv_cand): Ditto.
* tree-ssa-sccvn.h (struct vn_nary_op_s): Ditto.
(struct vn_reference_op_struct): Ditto.
* value-range-storage.h (class vrange_storage): Ditto.
* value-range.h (class vrange): Ditto.
* var-tracking.cc (struct variable): Ditto.
* vmsdbg.h (struct _DST_HEADER): Ditto.
2026-07-24 Jeff Law <jeffrey.law@oss.qualcomm.com>
* print-rtl.cc (print_exp): Avoid -Wempty-body warning.
2026-07-24 H.J. Lu <hjl.tools@gmail.com>
Uros Bizjak <ubizjak@gmail.com>
PR target/126320
* config/i386/i386.cc (ix86_spill_register_argument_p): New
function.
(ix86_argument_passed_on_stack_p): Add a pattern argument. Call
ix86_spill_register_argument_p to check spill of register argument
by callee.
(ix86_update_stack_alignment): Pass pat to
ix86_argument_passed_on_stack_p.
2026-07-24 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR middle-end/126363
* builtins.cc (fold_builtin_atomic_always_lock_free): Replace
INTEGER_CST + expand_normal with tree_to_uwhi.
2026-07-24 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/mkoffload.cc (main): Pass -L<dir> on to the
device compiler.
2026-07-24 Pengfei Li <Pengfei.Li2@arm.com>
* config/aarch64/tuning_models/neoversev2.h: Update the costs
of SVE structure loads and stores.
2026-07-24 Richard Biener <rguenther@suse.de>
PR target/126328
PR target/126383
* config/i386/i386.md (cost_special): New attribute.
* config/i386/sse.md (avx_h<insn>v4df3): Add cost_special
attribute with value haddsub.
(*sse3_haddv2df3): Likewise.
(sse3_hsubv2df3): Likewise.
(*sse3_haddv2df3_low): Likewise.
(*sse3_hsubv2df3_low): Likewise.
(avx_h<insn>v8sf3): Likewise.
(sse3_h<insn>v4sf3): Likewise.
* config/i386/i386.cc (ix86_insn_cost): Cost insns with
the cost_special attribute value of haddsub like an add.
2026-07-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree_1): Remove failure
on unvectorizable shifts.
2026-07-24 Richard Biener <rguenther@suse.de>
PR target/126328
* combine.cc (combine_validate_cost): New arguments for
the insn codes. Set INSN_CODE to recognized values
before calling insn_cost.
(try_combine): Adjust.
2026-07-24 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-expand.cc (ix86_expand_vec_set_builtin): Don't
force op1 to a register when it is CONST0_RTX (mode1).
(ix86_expand_vector_set_var): For now, force VAL to a register.
(ix86_expand_vector_set): If val is CONST0_RTX, expand using
the new sse4_1_insertps_v4s[if]_zero patterns on TARGET_SSE4_1.
Otherwise, force val to a register (restoring previous behaviour).
* config/i386/sse.md (sse4_1_insertps_<mode>_zero): New insn
using vec_merge to select which elements to clear/preserve.
(vec_set<mode>): Tweak operand 1 to allow both REGs and CONST0_RTX.
2026-07-24 Philipp Tomsich <philipp.tomsich@vrull.eu>
* ifcvt.cc (noce_emit_store_flag): Document that a NULL_RTX
return signals an unreversible condition.
(noce_try_store_flag): Drop redundant noce_reversed_cond_code
pre-check.
(noce_try_shifted_store_flag): Likewise.
(noce_try_store_flag_constants): Drop redundant can_reverse
guards on the reversed 2^n and -1 cases.
(noce_try_store_flag_mask): Set reversep unconditionally; the
store-flag emission now handles an unreversible condition.
2026-07-23 John David Anglin <danglin@gcc.gnu.org>
* crc-verification.cc (sb_match): Use HOST_SIZE_T_PRINT_UNSIGNED
instead of "%zu".
(lfsr_and_crc_bits_match): Likewise.
2026-07-23 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/mma.md (UNSPEC_DMF_DMXVF16GERX2): New UNSPEC entry.
(UNSPEC_DMF_DMXVF16GERX2PP): Likewise.
(UNSPEC_DMF_DMXVF16GERX2PN): Likewise.
(UNSPEC_DMF_DMXVF16GERX2NP): Likewise.
(UNSPEC_DMF_DMXVF16GERX2NN): Likewise.
(UNSPEC_DMF_PMDMXVF16GERX2): Likewise.
(UNSPEC_DMF_PMDMXVF16GERX2PP): Likewise.
(UNSPEC_DMF_PMDMXVF16GERX2PN): Likewise.
(UNSPEC_DMF_PMDMXVF16GERX2NP): Likewise.
(UNSPEC_DMF_PMDMXVF16GERX2NN): Likewise.
(DMF_PV): Add UNSPEC_DMF_DMXVF16GERX2.
(DMF_DPV): Add f16 variants.
(DMF_PVI8I4I2): Add UNSPEC_DMF_PMDMXVF16GERX2.
(DMF_DPVI8I4I2): Add f16 prefixed variants.
(pv): Add dmxvf16gerx2 attribute.
(dpv): Add f16 attributes.
(pvi8i4i2): Add pmdmxvf16gerx2 attribute.
(dpvi8i4i2): Add f16 prefixed attributes.
* config/rs6000/rs6000-builtins.def (__builtin_mma_dmxvf16gerx2): New
builtin.
(__builtin_mma_dmxvf16gerx2pp): Likewise.
(__builtin_mma_dmxvf16gerx2pn): Likewise.
(__builtin_mma_dmxvf16gerx2np): Likewise.
(__builtin_mma_dmxvf16gerx2nn): Likewise.
(__builtin_mma_pmdmxvf16gerx2): Likewise.
(__builtin_mma_pmdmxvf16gerx2pp): Likewise.
(__builtin_mma_pmdmxvf16gerx2pn): Likewise.
(__builtin_mma_pmdmxvf16gerx2np): Likewise.
(__builtin_mma_pmdmxvf16gerx2nn): Likewise.
(__builtin_mma_dmxvf16gerx2_internal): New internal builtin.
(__builtin_mma_dmxvf16gerx2pp_internal): Likewise.
(__builtin_mma_dmxvf16gerx2pn_internal): Likewise.
(__builtin_mma_dmxvf16gerx2np_internal): Likewise.
(__builtin_mma_dmxvf16gerx2nn_internal): Likewise.
(__builtin_mma_pmdmxvf16gerx2_internal): Likewise.
(__builtin_mma_pmdmxvf16gerx2pp_internal): Likewise.
(__builtin_mma_pmdmxvf16gerx2pn_internal): Likewise.
(__builtin_mma_pmdmxvf16gerx2np_internal): Likewise.
(__builtin_mma_pmdmxvf16gerx2nn_internal): Likewise.
* doc/extend.texi (PowerPC Matrix-Multiply Assist Built-in Functions):
Document new MMA+ builtins for f16 operations.
2026-07-23 Odysseas Georgoudis <odygrd@hotmail.com>
PR middle-end/122715
* match.pd: Fold IFN_AVG_FLOOR and IFN_AVG_CEIL with equal
operands.
2026-07-23 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR rtl-optimization/126347
* ifcvt.cc (noce_emit_store_flag): Return NULL_RTX when the
comparison code is UNKNOWN.
2026-07-23 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/mma.md (UNSPEC_DMF_DMXVI8GERX4SPP): New UNSPEC entry.
(UNSPEC_DMF_PMDMXVI8GERX4SPP): Likewise.
(UNSPEC_DMF_DMXVBF16GERX2): Likewise.
(UNSPEC_DMF_DMXVBF16GERX2PP): Likewise.
(UNSPEC_DMF_DMXVBF16GERX2PN): Likewise.
(UNSPEC_DMF_DMXVBF16GERX2NP): Likewise.
(UNSPEC_DMF_DMXVBF16GERX2NN): Likewise.
(UNSPEC_DMF_PMDMXVBF16GERX2): Likewise.
(UNSPEC_DMF_PMDMXVBF16GERX2PP): Likewise.
(UNSPEC_DMF_PMDMXVBF16GERX2PN): Likewise.
(UNSPEC_DMF_PMDMXVBF16GERX2NP): Likewise.
(UNSPEC_DMF_PMDMXVBF16GERX2NN): Likewise.
(DMF_PV): Add UNSPEC_DMF_DMXVBF16GERX2.
(DMF_DPV): Add bf16 and int8 signed accumulate variants.
(DMF_DPVI8I4I4): Add UNSPEC_DMF_PMDMXVI8GERX4SPP.
(DMF_PVI8I4I2): New int iterator.
(DMF_DPVI8I4I2): Likewise.
(pv): Add dmxvbf16gerx2 attribute.
(apv): Removed dmxvi8gerx4pp attribute.
(dpv): New attribute.
(dpvi8i4i4): Add pmdmxvi8gerx4spp attribute.
(pvi8i4i2): New attribute.
(dpvi8i4i2): Likewise.
(dmf_<dpv>): Rename from dmf_<apv> and update to use dpv attribute.
(dmf_<pvi8i4i2>): New insn pattern.
(dmf_<dpvi8i4i2>): Likewise.
* config/rs6000/rs6000-builtins.def (__builtin_mma_dmxvi8gerx4spp): New
builtin.
(__builtin_mma_pmdmxvi8gerx4spp): Likewise.
(__builtin_mma_dmxvbf16gerx2): Likewise.
(__builtin_mma_dmxvbf16gerx2pp): Likewise.
(__builtin_mma_dmxvbf16gerx2pn): Likewise.
(__builtin_mma_dmxvbf16gerx2np): Likewise.
(__builtin_mma_dmxvbf16gerx2nn): Likewise.
(__builtin_mma_pmdmxvbf16gerx2): Likewise.
(__builtin_mma_pmdmxvbf16gerx2pp): Likewise.
(__builtin_mma_pmdmxvbf16gerx2pn): Likewise.
(__builtin_mma_pmdmxvbf16gerx2np): Likewise.
(__builtin_mma_pmdmxvbf16gerx2nn): Likewise.
(__builtin_mma_dmxvi8gerx4spp_internal): New internal builtin.
(__builtin_mma_pmdmxvi8gerx4spp_internal): Likewise.
(__builtin_mma_dmxvbf16gerx2_internal): Likewise.
(__builtin_mma_dmxvbf16gerx2pp_internal): Likewise.
(__builtin_mma_dmxvbf16gerx2pn_internal): Likewise.
(__builtin_mma_dmxvbf16gerx2np_internal): Likewise.
(__builtin_mma_dmxvbf16gerx2nn_internal): Likewise.
(__builtin_mma_pmdmxvbf16gerx2_internal): Likewise.
(__builtin_mma_pmdmxvbf16gerx2pp_internal): Likewise.
(__builtin_mma_pmdmxvbf16gerx2pn_internal): Likewise.
(__builtin_mma_pmdmxvbf16gerx2np_internal): Likewise.
(__builtin_mma_pmdmxvbf16gerx2nn_internal): Likewise.
* doc/extend.texi (PowerPC Matrix-Multiply Assist Built-in Functions):
Document new MMA+ builtins for int8 and bf16 operations.
2026-07-23 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtins.def (__builtin_dmr_extract512): New
built-in.
(__builtin_disassemble_dmr): Likewise.
(__builtin_dmr_extract512_internal): New internal built-in.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin):
Exempt RS6000_BIF_DISASSEMBLE_DMR from the early-return guard.
Generate appropriate gimple code for the extract builtins.
2026-07-23 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/gcn-devices.def (gfx9-4-generic): Set sram-ecc
default to HSACO_ATTR_ANY.
2026-07-23 Jakub Jelinek <jakub@redhat.com>
* configure.ac: Fix a typo, respones -> response.
* configure: Regenerate.
2026-07-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (HAVE_GAS_SECTION_LINK_ORDER): Clarify comment.
* config.in: Regenerate.
* doc/sourcebuild.texi (Effective-Target Keywords)
(o_flag_in_section): Rename to shf_link_order. Update description.
2026-07-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/126028
* tree-vect-slp.cc (vect_slp_check_for_roots): Move
fold-left reduction check ...
(vectorizable_bb_reduc_epilogue): ... here and allow
two reduction lanes to be unaffected. Handle the two
vector lane without target support for the reduction.
(vectorize_slp_instance_root_stmt): Implement manual two-lane
reduction.
2026-07-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (HAVE_GAS_SHF_GNU_RETAIN): Clarify comment.
* config.in: Regenerate.
* doc/sourcebuild.texi (Effective-Target Keywords)
(R_flag_in_section): Remove.
(Effective-Target Keywords, gnu_retain): New keyword.
(Effective-Target Keywords, shf_gnu_retain): Likewise.
(Effective-Target Keywords, sht_init_array): Likewise.
2026-07-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* doc/sourcebuild.texi (Effective-Target Keywords, Other
attributes): Document solaris_ld.
2026-07-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* doc/sourcebuild.texi (Effective-Target Keywords, Other
attributes): Document solaris_as.
2026-07-23 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2satcvtintrin.h
(_mm_cvtts_sd_i32): Renamed from _mm_cvtts_sd_epi32.
(_mm_cvtts_sd_si32): New alias of _mm_cvtts_sd_i32.
(_mm_cvtts_sd_u32): Renamed from _mm_cvtts_sd_epu32.
(_mm_cvtts_ss_i32): Renamed from _mm_cvtts_ss_epi32.
(_mm_cvtts_ss_si32): New alias of _mm_cvtts_ss_i32.
(_mm_cvtts_ss_u32): Renamed from _mm_cvtts_ss_epu32.
(_mm_cvtts_roundsd_i32): Renamed from _mm_cvtts_roundsd_epi32.
(_mm_cvtts_roundsd_si32): New alias of _mm_cvtts_roundsd_i32.
(_mm_cvtts_roundsd_u32): Renamed from _mm_cvtts_roundsd_epu32.
(_mm_cvtts_roundss_i32): Renamed from _mm_cvtts_roundss_epi32.
(_mm_cvtts_roundss_si32): New alias of _mm_cvtts_roundss_i32.
(_mm_cvtts_roundss_u32): Renamed from _mm_cvtts_roundss_epu32.
(_mm_cvtts_sd_i64): Renamed from _mm_cvtts_sd_epi64.
(_mm_cvtts_sd_si64): New alias of _mm_cvtts_sd_i64.
(_mm_cvtts_sd_u64): Renamed from _mm_cvtts_sd_epu64.
(_mm_cvtts_ss_i64): Renamed from _mm_cvtts_ss_epi64.
(_mm_cvtts_ss_si64): New alias of _mm_cvtts_ss_i64.
(_mm_cvtts_ss_u64): Renamed from _mm_cvtts_ss_epu64.
(_mm_cvtts_roundsd_i64): Renamed from _mm_cvtts_roundsd_epi64.
(_mm_cvtts_roundsd_si64): New alias of _mm_cvtts_roundsd_i64.
(_mm_cvtts_roundsd_u64): Renamed from _mm_cvtts_roundsd_epu64.
(_mm_cvtts_roundss_i64): Renamed from _mm_cvtts_roundss_epi64.
(_mm_cvtts_roundss_si64): New alias of _mm_cvtts_roundss_i64.
(_mm_cvtts_roundss_u64): Renamed from _mm_cvtts_roundss_epu64.
2026-07-23 liuhongt <hongtao.liu@intel.com>
PR target/126160
* config/i386/sse.md (lrint<ssePSmode2lower><mode>2): New expander.
(lrintv2sfv2di2): Likewise.
(ssedfsimode): New mode attribute.
(ssedfsimodelower): Likewise.
(lrint<mode><ssedfsimodelower>2): New expander.
2026-07-23 Avinash Jayakar <avinashd@linux.ibm.com>
Vijay Shankar <vijay@linux.ibm.com>
* config/rs6000/mma.md (mma_xxsetaccz): Use wD constraint and
accumulator operand.
(mma_<vv>): Likewise.
(mma_<avv>): Likewise.
(mma_<pv>): Likewise.
(mma_<apv>): Likewise.
(mma_<vvi4i4i8>): Likewise.
(mma_<avvi4i4i8>): Likewise.
(mma_<vvi4i4i2>): Likewise.
(mma_<avvi4i4i2>): Likewise.
(mma_<vvi4i4>): Likewise.
(mma_<avvi4i4>): Likewise.
(mma_<pvi4i2>): Likewise.
(mma_<apvi4i2>): Likewise.
(mma_<vvi4i4i4>): Likewise.
(mma_<avvi4i4i4>): Likewise.
* config/rs6000/rs6000.cc (print_operand): Print DMR register
numbers if dense math option enabled.
2026-07-23 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (frange_cmp): New.
(frange::combine_zeros): Remove.
(frange::union_): Use frange_cmp to merge endpoints.
(frange::intersect): Likewise.
(frange::contains_p): Use frange_cmp.
(frange::verify_range): Use frange_cmp.
* value-range.h (class frange): Remove combine_zeros.
2026-07-23 Peter Bergner <bergner@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/mma.md (MAX_MMA_OPERANDS): Increase from 7 to 9.
(UNSPEC_DMF_DMXOR): New unspec.
(UNSPEC_DMF_DMXVI8GERX4): Likewise.
(UNSPEC_DMF_DMXVI8GERX4PP): Likewise.
(UNSPEC_DMF_PMDMXVI8GERX4): Likewise.
(UNSPEC_DMF_PMDMXVI8GERX4PP): Likewise.
(UNSPEC_DMF_DMSETDMRZ): Likewise.
(DMF_PV): New iterator.
(DMF_DPV): Likewise.
(DMF_PVI8I4I4): Likewise.
(DMF_DPVI8I4I4): Likewise.
(pv): Add DMF mappings.
(apv): Likewise.
(pvi8i4i4): New attribute.
(dpvi8i4i4): Likewise.
(dmf_build_dmr): New define_expand.
(dmf_dmsetdmrz): New insn.
(dmf_dmxor): Likewise.
(dmf_<pv>): New insn pattern.
(dmf_<apv>): Likewise.
(dmf_<pvi8i4i4>): Likewise.
(dmf_<dpvi8i4i4>): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Add
DMF builtin support. Handle DMR pass-by-reference semantics.
Support up to nine builtin operands.
(mma_expand_builtin): Likewise.
(rs6000_expand_builtin): Handle DMF builtins.
* config/rs6000/rs6000-builtins.def: Add DMF and MMA+ builtin
definitions.
* doc/extend.texi
(PowerPC Matrix-Multiply Assist Built-in Functions): Document
MMA+ builtins.
(PowerPC Dense Math Facility Built-in Functions): Document DMF builtins.
2026-07-23 Manjunath Matti <mmatti@linux.ibm.com>
* config/rs6000/rs6000.h (RS6000_BTI_dmr1024): New enumerator.
(RS6000_BTI_ptr_dmr1024): New enumerator.
(dmr1024_type_node): New macro.
(ptr_dmr1024_type_node): New macro.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Handle
dmr1024_type_node.
(rs6000_init_builtins): Register the __dmr1024 opaque type and
its pointer-to-const variant, with 512-bit alignment.
* config/rs6000/rs6000.cc (rs6000_mangle_type): Handle
dmr1024_type_node.
(rs6000_invalid_conversion): Reject conversions to/from TDOmode.
(rs6000_opaque_type_invalid_use_p): Gate __vector_quad and
__vector_pair on TARGET_MMA and __dmr1024 on TARGET_DMF
independently, and require -mdense-math for __dmr1024.
2026-07-23 Filip Kastl <fkastl@suse.cz>
* lto-streamer.h: Remove the field 'stream_linemap_order' from
the class 'lto_location_cache'.
2026-07-23 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (factor_out_all): Call
cond_store_replacement_limited too.
2026-07-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-eh.cc (lhs_could_trap_p): New function.
* tree-eh.h (lhs_could_trap_p): New decl.
* tree-ssa-phiopt.cc (copy_mem_with_alias_set_zero): New function.
(cond_store_replacement_limited): New function.
(pass_cselim::execute): Call cond_store_replacement_limited before
2026-07-22 Aldy Hernandez <aldy@quesejoda.com>
* value-range.cc (frange::flush_denormals_to_zero): Collapse a
denormal endpoint to the zero of the same sign and defer the sign
to canonicalize_zeros.
(frange::canonicalize_zeros): New.
(frange::set): Use it.
(range_tests_flush_denormals): New.
(range_tests_floats): Call it.
* value-range.h (class frange): Declare canonicalize_zeros.
2026-07-22 Vijay Shankar <vijay@linux.ibm.com>
* config/rs6000/mma.md (*movxo): renamed to movxo_nodmf
(*movxo_nodmf): updated contraint to use wD and add !TARGET_DMF
(*movxo_dmf): New pattern to handle dmf insert/extract from vsx
2026-07-22 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_schedule_slp_node): Simplify scheduling.
2026-07-22 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_schedule_slp_node): Correct in-region
stmt check.
2026-07-22 Surya Kumari Jangala <jskumari@linux.ibm.com>
Peter Bergner <bergner@linux.ibm.com>
* config/rs6000/mma.md (UNSPEC_DMR_RELOAD_FROM_MEMORY): New unspec.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(reload_tdo_load): New define_insn_and_split.
(reload_tdo_store): Likewise.
* config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Set
reload_load and reload_store for TDOmode when TARGET_DMF.
2026-07-22 Tobias Burnus <tburnus@baylibre.com>
* doc/invoke.texi (-fopenmp-ompt): Add 'scope' construct.
(-fopenmp-ompt-detailed): Fix typo.
2026-07-22 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
* config/rs6000/mma.md (UNSPEC_DMF_EXTRACT512): New unspec.
(dm_extract512): New insn.
(movtdo): New expander.
(*movtdo): New insn_and_split to support TDOmode moves between
memory, VSX registers, and Dense Math Registers.
* config/rs6000/rs6000.cc (rs6000_emit_move): Diagnose constant
assignments to TDOmode objects.
(rs6000_split_multireg_move): Handle TDOmode when splitting
multi-register moves.
2026-07-22 Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/mma.md (UNSPEC_DMF_INSERT512): New unspec.
(UNSPEC_DMF_INSERT1024): Likewise.
(movoo): Enable for TARGET_DMF.
(*movoo): Likewise.
(vsx_assemble_pair): Likewise.
(*vsx_assemble_pair): Likewise.
(vsx_disassemble_pair): Likewise.
(*vsx_disassemble_pair): Likewise.
(dm_insert512): New insn.
(dm_insert1024): Likewise.
(mma_assemble_acc): Use accumulator_operand.
Build accumulators via DMR insert operations when TARGET_DMF.
(*mma_assemble_acc): Use accumulator_operand.
(mma_<acc>): New define_expand treating xxmtacc/xxmfacc as no-ops
for TARGET_DMF.
(*mma_<acc>): Restrict to !TARGET_DMF and use accumulator_operand.
(mma_disassemble_acc): Use accumulator_operand.
* config/rs6000/predicates.md (dmr_register_operand): New predicate.
(gpc_reg_operand): Accept DMR registers.
* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do
not emit xxmfacc for DISASSEMBLE_ACC when TARGET_DMF.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Allow
OOmode in VSX register pairs for TARGET_DMF.
(rs6000_split_multireg_move): Avoid emitting xxmtacc/xxmfacc when
TARGET_DMF.
* config/rs6000/rs6000.md (type): Add dmf type.
(isa): Add mma and dmf ISA attributes.
(enabled): Add mma and dmf enable conditions.
2026-07-22 Juergen Christ <jchrist@linux.ibm.com>
* config/s390/s390-protos.h (s390_expand_vec_compare_gen_cc):
New function.
* config/s390/s390.cc (s390_expand_vec_compare_cc): Extract
part of this function into a ...
(s390_expand_vec_compare_gen_cc): ... new function.
* config/s390/vector.md (vec_cbranch_any<mode>): Implement.
(vec_cbranch_all<mode>): Implement.
2026-07-22 Avinash Jayakar <avinashd@linux.ibm.com>
* config/rs6000/constraints.md
(rs6000_constraints[RS6000_CONSTRAINT_wD]): New wD constraint.
* config/rs6000/predicates.md (accumulator_operand): New predicate.
* config/rs6000/rs6000.cc (rs6000_debug_reg_global): Support wD
register class.
(rs6000_init_hard_regno_mode_ok): Map wD to FLOAT_REGS.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wD constraint.
* doc/md.texi: Document the new constraint.
2026-07-22 Surya Kumari jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
(enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
(LAST_RELOAD_REG_CLASS): Update to RELOAD_REG_DMR.
(reload_reg_map): Add DMR entry.
(rs6000_reg_names): Add DMR register names.
(alt_reg_names): Add alternate DMR register names.
(rs6000_hard_regno_nregs_internal): Handle DMR registers.
(rs6000_hard_regno_mode_ok_uncached): Add TDOmode and XOmode support for
DMR registers.
(rs6000_debug_reg_global): Add TDOmode to debug modes and print DMR
register range.
(rs6000_setup_reg_addr_masks): Handle RELOAD_REG_DMR.
Allow offset loads for TDOmode values.
(rs6000_init_hard_regno_mode_ok): Add DMR_REGS to reg_class_to_reg_type
mapping.
Update precalculation of CLASS_MAX_NREGS.
(rs6000_secondary_reload_memory): Handle DMR_REGS class.
(rs6000_secondary_reload_simple_move): Add DMR to VSX moves.
(rs6000_preferred_reload_class): Handle DMR_REGS.
(rs6000_modes_tieable_p): Exclude TDOmode from register tying.
(reg_offset_addressing_ok_p): Allow XOmode with TARGET_DMF.
Add TDOmode support with TARGET_DMF.
(rs6000_secondary_reload_class): Handle DMR_REGS reload routing.
(rs6000_dmr_register_move_cost): New helper.
(rs6000_register_move_cost): Handle DMR_REGS as source or destination.
(rs6000_memory_move_cost): Add DMR_REGS case routing cost through VSX.
(rs6000_compute_pressure_classes): Add DMR_REGS when TARGET_DMF.
(rs6000_debugger_regno): Add DMR register numbering.
* config/rs6000/rs6000.h (UNITS_PER_DMR_WORD): Define as 128.
(FIRST_PSEUDO_REGISTER): Increase from 111 to 119.
(FIXED_REGISTERS): Add 8 DMR registers as non-fixed.
(CALL_USED_REGISTERS): Mark all DMR registers as call-used.
(REG_ALLOC_ORDER): Add DMR registers to allocation order.
(DMR_REGNO_P): New macro.
(VECTOR_ALIGNMENT_P): Add TDOmode.
(enum reg_class): Add DMR_REGS entry.
(REG_CLASS_CONTENTS): Add DMR_REGS bitmask.
(REGISTER_NAMES): Add dmr0-dmr7 register names.
(ADDITIONAL_REGISTER_NAMES): Add dmr0-dmr7 mappings.
* config/rs6000/rs6000.md (FIRST_DMR_REGNO): Define as 111.
(LAST_DMR_REGNO): Define as 118.
2026-07-21 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR tree-optimization/124663
* match.pd: Fold constant conditional selects.
2026-07-21 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.cc (aarch64_fold_while_ult_to_ptrue): New.
(aarch64_instruction_selection): Use it.
2026-07-21 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-acle-builtins.cc
(gimple_folder::fold_to_vl_pred): Refactor folding logic into
aarch64_fold_sve_ptrue_vl.
* config/aarch64/aarch64-protos.h (aarch64_fold_sve_ptrue_vl): New.
* config/aarch64/aarch64.cc (aarch64_instruction_selection): Move down.
(aarch64_fold_sve_ptrue_vl): New.
2026-07-21 Tamar Christina <tamar.christina@arm.com>
* gimple-isel.cc (pass_gimple_isel::execute): Enable and disable ranger
on fun.
2026-07-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_legitimize_address):
Completely rewrite it into an equivalent but more easily under-
standable description.
2026-07-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h (LOCAL_REGNO):
New macro definition.
2026-07-21 Tamar Christina <tamar.christina@arm.com>
* tree-vect-slp-patterns.cc (compatible_complex_nodes_p): Support
mismatched group sizes and use group size to iterate.
* tree-vect-slp.cc (vect_build_slp_instance,
vect_analyze_slp_reduc_chain, vect_analyze_slp_reduction,
vect_analyze_slp_reduction_group, vect_analyze_slp_instance,
vect_analyze_slp): Compare against lanes instead of .length ().
(vect_optimize_slp_pass::get_result_with_layout): replace .length ()
with .exist ().
(vect_transform_slp_perm_load_1): Use lanes instead of .length ().
(vect_remove_slp_scalar_calls): Replace iterators.
* tree-vect-stmts.cc (vectorizable_shift): Use group size over ops
length.
2026-07-21 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/rs6000.cc (print_operand): Add the `%W`
print modifier to print the VSX register number plus two.
2026-07-21 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-21 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/126341
* tree-outof-ssa.cc (split_overlapping_partition_decls): Preserve
DECL_IGNORED_P. Check that the replacement uses memory.
2026-07-21 Richard Biener <rguenther@suse.de>
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Simplify scalar vec_select of vec_concat.
2026-07-21 Robin Dapp <robin.dapp@oss.qualcomm.com>
* doc/md.texi: Document that scatters are left-to-right.
2026-07-21 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (define_split): Split *vec_extractv2di_0_sse
before reload on !TARGET_64BIT with TARGET_SSE2.
(define_split): Likewise split *vec_concatv2di_0 before reload
on !TARGET_64BIT with TARGET_SSE2.
2026-07-21 H.J. Lu <hjl.tools@gmail.com>
PR target/125297
* config/i386/i386.cc (init_cumulative_args): Don't set
cum->preserve_none_abi to true for MS ABI functions.
* doc/extend.texi: Update x86-64 preserve_none attribute
documentation.
2026-07-20 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/64992
* match.pd: Combine two patterns into for neeq (ne eq) and fix typo.
2026-07-20 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.cc (bpf_insn_cost): Return pattern_cost () by default.
2026-07-20 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.cc (bpf_rtx_costs): set CONST_INT 0 insns.
* config/bpf/bpf.h (BPF_IMM32_P): New helper macro.
* config/bpf/predicates.md (imm32_operand): Use new macro.
2026-07-20 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.cc (bpf_rtx_costs): Assign MPY/DIV/MOD cost 1.
2026-07-20 Jakub Jelinek <jakub@redhat.com>
* gen-pass-instances.awk: Use [ \t] instead of [[:blank:]]
for compatibility with mawk <= 1.3.3.
2026-07-20 Alex Coplan <alex.coplan@arm.com>
* config/aarch64/aarch64.cc (aarch64_handle_attr_isa_flags):
Warn if +tme is enabled by the target attribute/pragma, relying
on the feature flags from aarch64_parse_extension.
(aarch64_process_target_attr): Drop +tme warning based on custom
string parsing.
2026-07-20 Paul-Antoine Arras <parras@baylibre.com>
* builtin-types.def (BT_FN_VOID_ULONGLONG_ULONGLONG): New.
(BT_FN_VOID_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG):
Remove.
* omp-builtins.def (BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_DISPATCH,
BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_DISPATCH): Update
signature.
* omp-expand.cc (expand_omp_for_static_nochunk): Pass chunk start
and iteration count instead of loop bounds.
(expand_omp_for_static_chunk): Likewise.
2026-07-20 Paul-Antoine Arras <parras@baylibre.com>
* omp-builtins.def (BUILT_IN_GOMP_SCOPE_START_WITH_END): New
builtin.
(BUILT_IN_GOMP_SCOPE_END): Likewise.
* omp-low.cc (lower_omp_scope): Emit calls to
GOMP_scope_start_with_end and GOMP_scope_end when -fopenmp-ompt.
2026-07-20 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR testsuite/126261
* doc/sourcebuild.texi (can_deref_null): Document.
2026-07-20 Shreya Munnangi <smunnang@qti.qualcomm.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124741
* config/riscv/constraints.md (B1, B2, B3, B4): New constraints for
atomic loads with and without ZALASR & MEMMODEL_ACQUIRE.
* config/riscv/iterators.md (cond_extend): New iterator to for use
in extending atomic loads.
* config/riscv/sync-rvwmo.md (atomic_load_rvwmo<mode>): Adjust
contraints to enable folding small offsets into memory load.
(atomic_store_rvwmo): Likewise.
(extending atomic_load_rvwmo): New pattern.
* config/riscv/sync-ztso.md (atomic_load_ztso<mode>): Adjust
constraints to enable folding small offsets into memory load.
(atomic_store_ztso): Likewise.
(extending atomic_load_ztso): New pattern.
2026-07-20 Juergen Christ <jchrist@linux.ibm.com>
* config/s390/vector.md (VEC_SET_SINGLEFLOAT): Remove V1TF.
2026-07-20 Richard Biener <rguenther@suse.de>
PR target/126271
* config/i386/i386-expand.cc (ix86_expand_reduc): Honor
TARGET_V2DF_REDUCTION_PREFER_HADDPD and expand via
gen_sse3_haddv2df3.
2026-07-20 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-20 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/126291
* match.pd ((trunc)copysign ((extend)x, (extend)y) -> copysign
(x, y), (trunc)copysign ((extend)x, CST) -> copysign (x, CST)):
Use element_precision.
2026-07-19 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/126291
* match.pd ((trunc)abs (extend x) -> abs (x)): Use
element_precision. Require target ABS support for the
vector case.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (svrsw60t59b): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (ssqosid): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (ssctr): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (smctr): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (smcdeleg): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (ssccfg): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (ziccamoc): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/riscv-ext.def (ziccid): Add new extension.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
2026-07-19 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/125731
* ifcvt.cc (noce_cond_zero_binary_op_supported): Move earlier.
(noce_try_shifted_store_flag): New function.
(noce_process_if_block): Use it.
2026-07-19 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126222
* value-range-storage.cc (prange_storage::equal_p): Comment change.
* value-range.h (prange::pt_equal_p): Use vrp_operand_equal_p.
2026-07-19 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126212
* value-relation.cc (dom_oracle::set_one_relation): Start with
first dominator in the dominator search.
(dom_oracle::recomputed_relation): New.
(dom_oracle::find_relation_dom): query recomputed_relation.
* value-relation.h (dom_oracle::recomputed_relation): New prototype.
2026-07-19 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126212
* range-op.cc (operator_logical_and::op1_range): Add case for
[0, 0] = op1 & [1, 1]
(operator_logical_or::op1_range): Add case for [1, 1] = op1 | [0, 0]
2026-07-18 Luke Zhuang <luke.zhuang@linux.alibaba.com>
Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.md (@tlsdesc<mode>): Use individual
RVVM1QI clobbers instead of four RVVM8QI.
2026-07-18 wangjue <juewang@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_override_options_after_change): New
function.
(riscv_option_override): Call it.
(TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define.
2026-07-18 Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com>
PR target/123883
* match.pd ((1<<N) & (1<<N) with different types): New
pattern.
2026-07-18 Matt Turner <mattst88@gmail.com>
PR target/117184
* lra-eliminations.cc (setup_can_eliminate): Mark the hard frame
pointer live when setting frame_pointer_needed.
2026-07-18 Xi Ruoyao <xry111@xry111.site>
PR target/126200
* config/loongarch/predicates.md
(par_const_vector_shf_set_operand): Define as special predicate.
* config/loongarch/lsx.md (lsx_vshuf4i_<lsxfmt_f>): Pass VIMODE
to the predicate of selector.
2026-07-18 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-17 Iain Sandoe <iain@sandoe.co.uk>
* doc/sourcebuild.texi: Document aarch64_mbig_endian.
2026-07-17 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/126087
* match.pd: Move tree_expr_nonnegative_p (@1) to tree_expr_nonnegative_p@1.
2026-07-17 Tobias Burnus <tburnus@baylibre.com>
* doc/invoke.texi (-fopenmp-ompt, -fopenmp-ompt-detailed): Improve
wording.
2026-07-17 Richard Earnshaw <rearnsha@arm.com>
* config/aarch64/aarch64.cc (aarch64_override_options): Warn if
+tme is used as an architecture feature
(aarch64_process_target_attr): Similarly, but only if TME
was previously disabled.
* doc/invoke.texi (aarch64): Remove mentions of +tme.
2026-07-17 Matt Turner <mattst88@gmail.com>
* config/alpha/alpha.cc (alpha_cannot_copy_insn_p): Do not return
false before reload_completed. Update comment.
2026-07-17 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-cores.def (RISCV_CORE): Remove zama16b from
xt-c9501fdvt.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
PR middle-end/80922
PR middle-end/106823
PR lto/107936
* lto-streamer-in.cc (lto_create_loc_map): Process diagnostic
pragmas from the linemap sections.
* lto-streamer-out.cc (location_output::produce_linemap_section):
Stream diagnostic pragmas into the linemap section.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
PR lto/65536
* doc/lto.texi: Document the new LTO_section_linemap and the new
option -fltrans-linemap-file.
* lto-opts.cc (lto_write_options): Handle the new option.
* opts.cc (gen_command_line_string): Likewise.
* lto-section-in.cc (lto_section_name[]): Add new name for
LTO_section_linemap.
* lto-streamer-in.cc (get_location_from_idx): New function.
(lto_location_cache::cmp_loc): Remove.
(bp_unpack_delta): New function.
(create_loc_map): New function.
(get_loc_map): New function.
(lto_location_cache::override_loc_map): New function.
(lto_location_cache::apply_location_cache): Pervasive changes to
implement new location streaming format.
(lto_location_cache::input_location_and_block): Likewise.
(lto_location_cache::input_location): Rename argument LOC -> DEST
for clarity.
(lto_read_body_or_constructor): Handle LINEMAP_ID in the decl state.
(lto_data_in_create): Add NEED_LOCATION_CACHE argument. Rename local
variable DATA_IN to D to avoid clash with the type name.
* lto-streamer-out.cc (clear_line_info): Update for change to class
output_block.
(compute_map_hash): New function.
(class location_output): New class.
(location_output::record_location): New function.
(bp_pack_delta): New function.
(location_output::produce_linemap_section): New function.
(lto_output_location_1): Pervasive changes to implement new location
streaming format.
(copy_function_or_variable): Set the LINEMAP_ID in the decl state.
(copy_linemap_section): New function.
(copy_linemap_sections): New function.
(lto_copy_linemaps): New function.
(lto_register_linemap_for_output): New function.
(lto_output_decl_state_refs): Output the LINEMAP_ID for function
decls.
(lto_out_decl_state_written_size): Adapt for new LINEMAP_ID output.
(produce_asm_for_decls): Output the linemap section when needed.
* lto-streamer.cc (lto_get_section_name): Handle linemap sections,
which need an order suffix.
* lto-streamer.h (enum lto_section_type): Fix typo in the
comment. Add LTO_section_linemap.
(struct lto_loc_map): New struct.
(class lto_location_cache): Pervasive changes to implement new
location streaming format.
(struct lto_in_decl_state): Add LINEMAP_ID member.
(struct lto_out_decl_state): Likewise.
(struct lto_file_decl_data): Add LOC_MAP_DECL_DATA, LOC_MAPS,
and NUM_LINEMAP_SECTIONS members.
(lto_linemap_output_id): New function.
(struct output_block): Adjust members for new streaming format.
(data_in::data_in): New function.
(lto_data_in_create): Adjust prototype for new NEED_LOCATION_CACHE
argument.
(lto_register_linemap_for_output): Declare.
(lto_copy_linemaps): Declare.
* lto-wrapper.cc (run_gcc): Pass new argument -fltrans-linemap-file.
* timevar.def (TV_IPA_LTO_LINEMAP_IN): New timevar.
(TV_IPA_LTO_LINEMAP_OUT): New timevar.
(TV_IPA_LTO_LINEMAP_COPY): New timevar.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
* doc/sourcebuild.texi: Document ar-link and incr-link options to
dg-lto-do directive.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
* doc/sourcebuild.texi: Document dg-lto-additional-options
directive.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
* diagnostic.h (diagnostic_classify_diagnostic): Adapt for removal
of return value in option_classifier::classify_diagnostic.
* diagnostics/context.h: Likewise.
* diagnostics/kinds.h (enum kind): Add trailing element to indicate
the total number of kinds.
* diagnostics/option-classifier.cc
(option_classifier::classify_diagnostic): Remove the return value,
which was not correct and which was not used anyway.
* diagnostics/option-classifier.h (class option_classifier): Adjust
prototype for classify_diagnostic. Make the name of nested strruct
classification_change_t publicly accessible.
2026-07-17 Lewis Hyatt <lhyatt@gmail.com>
* input.cc (test_accessing_ordinary_linemaps): Test new
line_map_add_raw_map() functionality.
2026-07-17 Neal Patalay <nealpatalay0@gmail.com>
PR tree-optimization/126087
* match.pd: Simplify MIN and BIT_IOR compared to 0 when
one operand is non-negative.
2026-07-17 Uros Bizjak <ubizjak@gmail.com>
PR target/126283
* config/i386/i386.md (bswaphi2): Add flags reg clobber.
(*bswaphi2_movbe): Add flags reg clobber. Add ROLW alternative
and update instruction attributes. Add preferred_for_size and
preferred_for_speed attributes.
(*bswaphi2): Ditto.
(*bswaphisi2_lowpart): Ditto.
(XCHGB -> ROLW peephole2 patterns): Remove.
(ROLW reg,8 -> BSWAP splitter): Update for added flags reg clobber.
Always split.
* config/i386/i386-expand.cc (ix86_expand_gfni_bitreverse):
Update for bswaphi2 change.
2026-07-17 Paul-Antoine Arras <parras@baylibre.com>
* omp-builtins.def (BUILT_IN_GOMP_HAS_MASKED_THREAD_NUM_WITH_END):
New builtin.
* omp-low.cc (lower_omp_master): Use it when -fopenmp-ompt.
2026-07-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* et-gather.awk, gen-et-static.awk: New scripts.
* Makefile.in (testsuitedir): New.
(native): Depend on testsuite/et-static.exp.
(clean): Remove etlist.
(distclean): Remove et-static.exp.
(install-testsuite): New target.
(install): Depend on it.
(site.exp): Depend on testsuite/et-static.exp.
(testsuite/et-static.exp): New target.
* doc/sourcebuild.texi (Effective-Target Keywords): Document
et-static.def.
(Effective-Target Keywords, Other attributes): Document
ld_at_file.
2026-07-17 H.J. Lu <hjl.tools@gmail.com>
PR target/126275
* config/i386/i386-expand.cc (ix86_expand_set_or_cpymem): Don't
use misaligned prologue if count <= epilogue size.
2026-07-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/126028
* tree-vect-slp.cc (vect_slp_check_for_roots): Do not
force the BB reduction root to have an even number of lanes.
(vect_build_slp_instance): For failed discovery of a BB
reduction attempt to re-try discovery on the matching or
non-matching part.
2026-07-16 Paul-Antoine Arras <parras@baylibre.com>
* builtin-types.def (BT_FN_VOID_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG): New.
* omp-builtins.def (BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_DISPATCH): Use
BT_FN_VOID_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_DISPATCH): Likewise.
* omp-expand.cc (expand_omp_for_static_nochunk): Pass niter, start,
incr, chunk size, and istart to the dispatch call.
(expand_omp_for_static_chunk): Likewise.
2026-07-16 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125986
* value-relation.cc (path_oracle::query): Query root oracle for
relations.
2026-07-16 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-protos.h
(riscv_legitimize_call_address): Add a sibcall parameter.
* config/riscv/riscv.cc
(riscv_legitimize_call_address): Use a pseudo for sibcalls.
* config/riscv/riscv.md (sibcall): Pass true for sibcalls.
(sibcall_value): Likewise.
(call): Pass false for ordinary calls.
(call_value): Likewise.
2026-07-16 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_regno_to_class): Map t1 to
JALR_REGS.
* config/riscv/riscv.h (RISCV_PROLOGUE_TEMP_REGNUM): Document
the SIBCALL_REGS restriction.
(REG_CLASS_CONTENTS): Remove t1 from SIBCALL_REGS.
2026-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de>
* tree-profile.cc (emit_assign): Append to a gimple_seq instead
of inserting on an edge. Make the functions static.
(emit_bitwise_op): Likewise.
(instrument_decisions): Build up a local gimple_seq per edge and
insert it once instead of inserting each statement individually.
2026-07-16 Sebastian Huber <sebastian.huber@embedded-brains.de>
* tree-profile.cc (emit_bitwise_op): Build/fold the operation with
gimple_build() instead of gimple_build_assign(), and return the
folded result as-is instead of always materializing a new SSA
name.
(instrument_decisions): Do not emit bitwise-or operations with a
zero constant operand.
2026-07-16 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-16 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_noce_conversion_profitable_p): Ignore
reg->reg copies too.
2026-07-16 Richard Biener <rguenther@suse.de>
* tree-switch-conversion.cc (gen_log2): Use gimple_seq
overload of gimple_build.
(gen_pow2p): Likewise.
2026-07-16 Tobias Burnus <tburnus@baylibre.com>
* omp-offload.cc (omp_discover_declare_target_tgt_fn_r): Fix
the condition for anchestor + nohost handling.
2026-07-16 Eric Botcazou <ebotcazou@adacore.com>
* expmed.cc (invert_mod2n): Fix typo in comment and add references.
2026-07-16 Tobias Burnus <tburnus@baylibre.com>
PR fortran/126279
* omp-low.cc (lower_omp_target): Avoid creating a second static const
variable for the trait array used by uses_allocators.
2026-07-16 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Options): Fix a typo.
2026-07-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/netbsd-elf.h (NETBSD_LINK_LD_ELF_SO_SPEC): Remove.
(NETBSD_SUBTARGET_EXTRA_SPECS): Remove netbsd_link_ld_elf_so.
2026-07-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126262
* gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Treat
IFN_MUL_OVERFLOW and IFN_UBSAN_CHECK_MUL like IFN_BSWAP, regardless
of bitint_big_endian.
2026-07-16 Peter Bergner <bergner@linux.ibm.com>
Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add
ENB_DM diagnostic.
(rs6000_builtin_is_supported): Handle ENB_DM.
* config/rs6000/rs6000-gen-builtins.cc: Update comments for new
Dense Math builtin attributes.
(bif_stanza): Add BSTZ_DM.
(stanza_map): Add "dm" stanza.
(enable_string): Add ENB_DM.
(basetype): Add BT_DMR.
(attrinfo): Add isdm, isdmint and isdmr fields.
(type_map): Add dmr1024 and ptr_dmr1024 type mappings.
(match_type): Recognize dmr1024 type.
(parse_bif_attrs): Parse dm, dmint and dmr attributes.
(complete_vector_type): Handle BT_DMR.
(write_decls): Emit ENB_DM and Dense Math builtin attribute bits
and predicates.
(write_bif_static_init): Initialize Dense Math builtin attributes
and associate dmint builtins with their internal variants.
2026-07-15 H.J. Lu <hjl.tools@gmail.com>
PR target/126231
* config/i386/i386.md (*fix_trunc<mode>si_sse_2_zext): New.
2026-07-15 wangjue <juewang@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_legitimize_address): Use
riscv_add_offset for scaled indexed addresses.
2026-07-15 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/126110
* gimple-range-cache.cc (ranger_cache::mark_stale): Default defs
get a new timestamp to make them stale.
* gimple-range-infer.cc (infer_range_manager::add_range): When
an inferred range is added, mark the name as updated.
2026-07-15 Jim Lin <jim@andestech.com>
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch): Check m_loc instead of *m_loc
before emitting the diagnostic.
2026-07-15 Jim Lin <jim@andestech.com>
* config/riscv/zicond.md: Emit any_ge instead of any_gt in the
GE/GEU if-then-else splitter.
2026-07-15 Jeff Law <jeffrey.law@oss.qualcomm.com>
Revert:
2026-06-29 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/mips.h (ASM_SPEC): Add placeholders for -mmxu and
-mno-mxu.
* config/mips/mips.opt: New undocumented target option.
2026-07-15 Nathan Sidwell <nathan@acm.org>
* gen-pass-instances.awk: Require only white-space before
macro invocations.
2026-07-15 Tobias Burnus <tburnus@baylibre.com>
* omp-low.cc (lower_private_allocate): When called on 'target'
and the allocator is a variable, obtain the device variable.
(lower_omp_target): Move processing of OMP_CLAUSE_USES_ALLOCATORS
on the device/receiver side in before the loop over clauses to
ensure the VALUE_EXPR points to uses_allocators's inited var.
2026-07-15 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_transform_stmt): Return void.
* tree-vect-stmts.cc (vect_transform_stmt): Likewise.
2026-07-15 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Enhance
dumping in the failure case.
2026-07-15 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/123236
* simplify-rtx.cc (simplify_context::simplify_truncation): Handle
cases where a ZERO_EXTRACT or SIGN_EXTRACT has a different mode
to (but at least as wide as) its first operand.
2026-07-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/126171
* tree-scalar-evolution.cc (scev_dfs::add_to_evolution):
Remove code argument. Remove MINUS_EXPR handling here.
(scev_dfs::follow_ssa_edge_binary): Likewise.
(scev_dfs::follow_ssa_edge_expr): Handle MINUS_EXPR
separately here, promoting the whole operation to unsigned
instead of just the addend.
2026-07-15 Andrew Stubbs <ams@baylibre.com>
* regrename.cc (scan_rtx_address): Recurse for segment UNSPECs.
2026-07-15 Luke Zhuang <luke.zhuang@linux.alibaba.com>
* config/riscv/riscv.md (VXSAT_REGNUM): New constant.
(@tlsdesc<mode>): update clobbering.
2026-07-15 H.J. Lu <hjl.tools@gmail.com>
PR target/126231
* config/i386/i386.md (*fix_trunc<mode>si_sse_zext): New.
* config/i386/sse.md (*avx512fp16_vcvtsh2<sseintconvertsignprefix>si<round_zext_name>):
Likewise.
(*avx512fp16_vcvtsh2<sseintconvertsignprefix>si_2_zext): Likewise.
(*unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncsi2<round_saeonly_zext_name>): Likewise.
(*sse_cvtss2si<round_zext_name>): Likewise.
(*sse_cvtss2si_2_zext): Likewise.
(*unspec_sse_cvttss2si<round_saeonly_zext_name>): Likewise.
(*sse_cvttss2si<round_saeonly_zext_name>): Likewise.
(*avx512f_vcvtss2usi<round_zext_name>): Likewise.
(*unspec_avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise.
(*avx512f_vcvttss2usi<round_saeonly_zext_name>): Likewise.
(*avx512f_vcvtsd2usi<round_zext_name>): Likewise.
(*unspec_avx512f_vcvttsd2usi<round_saeonly_zext_name>):
Likewise.
(*avx512f_vcvttsd2usi<round_saeonly_zext_name>): Likewise.
(*sse2_cvtsd2si<round_zext_name>): Likewise.
(*sse2_cvtsd2si_2_zext): Likewise.
(*unspec_sse2_cvttsd2si<round_saeonly_zext_name>): Likewise.
(*sse2_cvttsd2si<round_saeonly_zext_name>): Likewise.
(*avx10_2_vcvttsd2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>):
Likewise.
(*avx10_2_vcvttss2<sat_cvt_sign_prefix>sissi<round_saeonly_zext_name>):
Likewise.
* config/i386/subst.md (round_zext_name): Likewise.
(round_zext_constraint): Likewise.
(round_zext_constraint2): Likewise.
(round_zext_nimm_predicate): Likewise.
(round_zext_nimm_scalar_predicate): Likewise.
(round_zext_op2): Likewise.
(round_zext): Likewise.
(round_saeonly_zext_name): Likewise.
(round_saeonly_zext_constraint): Likewise.
(round_saeonly_zext_constraint2): Likewise.
(round_saeonly_zext_nimm_scalar_predicate): Likewise.
(round_saeonly_zext_op2): Likewise.
(round_saeonly_zext): Likewise.
2026-07-15 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/126257
* match.pd (x+x -> x*2): Only optimize if 2 is representable in the
type.
2026-07-15 Jakub Jelinek <jakub@redhat.com>
PR c++/120635
* doc/extend.texi: Document variant spelling of
standard attributes and that alternate namespace
spelling for clang namespace is _Clang rather
than __clang__. For no_specializations use
_Clang:: rather than __clang__::.
2026-07-15 Tobias Burnus <tburnus@baylibre.com>
* omp-expand.cc (expand_omp_target): For 'device_type(host)',
invoke with device(omp_initial_device)'.
* omp-low.cc (create_omp_child_function): Take host_only
argument to prevent generating offload code.
(scan_omp_parallel, scan_omp_task, scan_omp_target, scan_omp_teams,
lower_omp_target): Update call.
* omp-offload.cc (omp_discover_declare_target_tgt_fn_r,
omp_discover_declare_target_fn_r): Do not add implicit 'declare
target' to target regions with 'device_type(host)'.
2026-07-15 Hu, Lin1 <lin1.hu@intel.com>
PR middle-end/126203
PR middle-end/126221
PR middle-end/126232
* optabs.cc (emit_cmp_and_jump_insns): Take the masked_op mode
from TREE_TYPE (masked_op).
2026-07-14 Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (gimplify_omp_workshare): Handle 'device_type(nohost)'
on 'target'.
* omp-low.cc (lower_omp_target): Remove sorry for this case.
2026-07-14 Karl Meakin <karl.meakin@arm.com>
PR target/126064
* config/aarch64/aarch64-neon-builtins-base.cc: Compare
`arg_type` and `TREE_TYPE (b)` using `types_compatible_p` rather
than comparing their pointer addresses.
2026-07-14 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
* doc/sourcebuild.texi (arm_v8_1m_mve_link): Document.
2026-07-14 Cem Akgok <cemakgok@gmail.com>
PR tree-optimization/126225
* tree-vect-loop.cc (vect_slp_induction_reuse_p): New function.
(vectorizable_induction): Validate SLP induction IV reuse. Reuse
generated IVs cyclically when filling the SLP group.
2026-07-14 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.cc (darwin_globalize_label): Handle Protocol
references.
(darwin_label_is_anonymous_local_objc_name): Likewise.
2026-07-14 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/102202
* gimple-fold.cc (gimple_fold_builtin_memset): Hoist
tree_to_uhwi (len) before the INTEGER_CST guard. Fold
length-one memset calls through arbitrary pointer destinations.
Build a ref-all MEM_REF at offset zero and preserve the call
result when it is used.
2026-07-14 Jakub Jelinek <jakub@redhat.com>
PR middle-end/126084
* gimple-lower-bitint.cc: Include "attribs.h" and "asan.h".
(gimple_lower_bitint): Use asan_expand_poison_ifn to lower
.ASAN_POISON calls with large/huge _BitInt lhs.
* asan.cc (report_error_func): Set *nargs and use _n builtin
even if size is not a power of two or larger than 16.
(asan_expand_poison_ifn): Handle nargs == 2.
2026-07-14 Jakub Jelinek <jakub@redhat.com>
H.J. Lu <hjl.tools@gmail.com>
PR tree-optimization/120201
* cfgexpand.cc (expand_used_vars): Set data.asan_alignb to
maximum of itself and crtl->stack_alignment_needed
/ BITS_PER_UNIT.
2026-07-14 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/123625
PR target/121957
* tree-outof-ssa.cc (split_overlapping_partition_decls): New function.
Use use_register_for_decl to identify memory partitions.
(remove_ssa_form): Call split_overlapping_partition_decls.
2026-07-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/126194
* gimple-ssa-pta-constraints.cc (find_func_aliases_for_call):
Only ignore calls to delete if DECL_IS_REPLACEABLE_OPERATOR.
2026-07-14 Jakub Jelinek <jakub@redhat.com>
* asan.h (asan_var_and_redzone_size): Fix comment typo,
occupis -> occupies.
2026-07-14 H.J. Lu <hjl.tools@gmail.com>
PR target/126202
* alias.cc (static_reg_base_value): Revert commit e754b70fe54.
(find_base_term): Likewise.
* alias.h (find_base_term): Likewise.
* function.cc (thread_prologue_and_epilogue_insns): Likewise.
* rtl.h (static_reg_base_value): Likewise.
* config/i386/i386.cc (stack_access_data): Likewise.
(ix86_find_all_reg_uses_1): Likewise.
(ix86_find_all_reg_uses): Likewise.
(ix86_access_stack_p): Likewise.
(ix86_need_alignment_p_2): Likewise.
(ix86_need_alignment_p_1): Likewise.
(ix86_need_alignment_p): Likewise.
(ix86_update_stack_alignment): Likewise.
(ix86_find_max_used_stack_alignment): Likewise.
(ix86_update_stack_alignment_2): Removed.
(ix86_update_stack_alignment_1): Likewise.
2026-07-14 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Leverage Wvr constraint.
2026-07-13 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR driver/124058
* gcc-diagnostic-spec.cc (nowarn_spec_t::nowarn_spec_t):
Remove leftover reference to OPT_Wuse_after_free.
2026-07-13 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR driver/124058
* common.opt (Wuse-after-free): Make an alias for
-Wuse-after-free=1.
* doc/invoke.texi: Document alias.
* gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer):
Use OPT_Wuse_after_free_.
2026-07-13 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/120165
* lra-constraints.cc (virtual_reg_p, contains_virtual_reg_p): New.
(reg_has_incdec_p): Ditto.
(lra_constraints): Use reg_has_incdec_p and contains_virtual_reg_p
to switch off the equiv.
2026-07-13 Nathan Sidwell <nathan@acm.org>
* print-rtl.cc (rtx_writer::print_rtx_operand_code_i): Don't
fallback to UNSPEC enums if there are any UNSPECV enums.
(print_exp): Print unspec/unspecv name, when available.
2026-07-13 Jakub Jelinek <jakub@redhat.com>
PR c++/120635
* doc/extend.texi (no_specializations): Document new
attribute.
* doc/invoke.texi (-Wno-invalid-specialization): Document new
warning.
2026-07-13 Odysseas Georgoudis <odygrd@hotmail.com>
PR tree-optimization/113894
* match.pd: Add simplifications for branchless conditional negate
and sign-test absolute value idioms.
2026-07-13 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
PR target/78799
* config/i386/i386.cc (function_value_ms_64): Do not treat
integral 16-byte values as SSE returns.
(ix86_return_in_memory): Likewise avoid treating integral 16-byte
values as XMM returns.
2026-07-13 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Handle
TDOmode and emit "Dense Math" diagnostics.
(rs6000_function_arg): Reject TDOmode function parameters and
emit "Dense Math" diagnostics.
* config/rs6000/rs6000-modes.def: Add TDOmode.
2026-07-13 Dylan Rees <dylan.rees@arm.com>
* cse.cc (struct cse_vec_duplicate_match): New struct.
(struct cse_basic_block_data): New member added.
(cse_prescan_cache_vec_dup): New function to cache any vector
duplications and check for potential matches.
(cse_prescan_path): Extended pre_scan loop to cache vector
duplication matches + New loop added to assign a list of
matches to a block of data inside new struct member.
(cse_main): New loop to emit wider vector duplication earlier
and update narrower vector duplicate to SUBREG insn.
2026-07-13 Dylan Rees <dylan.rees@arm.com>
* config/aarch64/aarch64-builtins.cc (aarch64_fold_lo_call_to_hi):
New branch to check for uniform vectors, extend and then add
them to the new highpart builtin call.
2026-07-13 Josef Melcr <josef.melcr@suse.com>
PR ipa/125121
* cgraph.cc (cgraph_edge::make_callback): Add missing call to
duplication hooks.
* ipa-prop.cc (init_callback_edge_summary): Remove function.
(ipa_compute_jump_functions_for_edge): Remove call to
init_callback_edge_summary, fix comment.
(ipa_edge_args_sum_t::duplicate): Fix the initialization of jump
functions vector for callback edges.
2026-07-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/t-sol2 (install-clearcap-map): Install as clearcap.map.
2026-07-13 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Common Attributes): Delete instances of
extra "the".
* doc/invoke.texi (Visium Options): Likewise.
* doc/tree-ssa.texi (SSA Operands): Likewise.
2026-07-13 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Options Summary) [C Language Options]:
Group --ansi with -ansi since they are documented together.
Correctly alphabetize -ffso-struct.
(C Dialect Options): Likeise correctly alphabetize -ffso-struct.
2026-07-13 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Option Summary): Add -fdeps-file, -fdeps-format,
and -fdeps-target.
(C Dialect Options): Properly alphabetize entries for the above
options, group them together, move the introductory paragraph
into the discussion of this group of items, and make the docs
more descriptive.
2026-07-12 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.md (*<any_extract:optab><GPR:mode>3):
Remove (clobber (match_scratch)) and use operand 0 as the
intermediate destination for the shift-left half of the split.
2026-07-12 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/104280
* match.pd: Remove redundant build_one_cst (type) [PR104280]
2026-07-12 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/114009
* match.pd: Remove redundant build_zero_cst (type) [PR114009]
2026-07-12 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
* match.pd: Remove one build_minus_one_cst (type) in r15-6257.
2026-07-12 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Add OPTION_MASK_DMF.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Enable
OPTION_MASK_DMF by default when TARGET_FUTURE is set and the
flag was not explicitly given; emit an error and clear the flag
when -mdense-math is requested on a non-future target.
(rs6000_opt_masks): Add "dense-math" entry for OPTION_MASK_DMF.
* config/rs6000/rs6000.opt (mdense-math): New option backed by Mask(DMF).
* config/rs6000/rs6000.opt.urls: Regenerated.
* doc/invoke.texi: Add -mdense-math.
2026-07-12 MITSUNARI Shigeo <herumi@nifty.com>
* config/i386/i386.md (*bmi2_umul<mode>3_highpart): New pattern.
2026-07-12 MITSUNARI Shigeo <herumi@nifty.com>
* expmed.cc (expand_wide_mulh_udiv): New function.
(expand_divmod): Use it for unsigned constant division needing a
wide multiplier on 64-bit targets, when no more expensive than the
sub/shift/add sequence.
2026-07-11 Surya Kumari Jangala <jskumari@linux.ibm.com>
Revert:
2026-07-11 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Add OPTION_MASK_DMF.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Enable
OPTION_MASK_DMF by default when TARGET_FUTURE is set and the
flag was not explicitly given; emit an error and clear the flag
when -mdense-math is requested on a non-future target.
(rs6000_opt_masks): Add "dense-math" entry for OPTION_MASK_DMF.
* config/rs6000/rs6000.opt (mdense-math): New option backed by Mask(DMF).
* doc/invoke.texi: Add -mdense-math.
2026-07-11 Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Add OPTION_MASK_DMF.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Enable
OPTION_MASK_DMF by default when TARGET_FUTURE is set and the
flag was not explicitly given; emit an error and clear the flag
when -mdense-math is requested on a non-future target.
(rs6000_opt_masks): Add "dense-math" entry for OPTION_MASK_DMF.
* config/rs6000/rs6000.opt (mdense-math): New option backed by Mask(DMF).
* doc/invoke.texi: Add -mdense-math.
2026-07-10 Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/57371
* fold-const.cc (fold_cmp_float_cst_p): New helper function.
* fold-const.h (fold_cmp_float_cst_p): Prototype here.
* match.pd ((FTYPE) N CMP CST): Use the new helper
fold_cmp_float_cst_p to check that transformation to an integer
comparison is safe.
2026-07-10 Roger Sayle <roger@nextmovesoftware.com>
PR target/48609
* expr.cc (emit_group_load_1): When passing a complex value in an
integer mode of the same size, explicitly construct (hi<<N)+lo to
avoid spilling to memory before reload.
2026-07-10 Roger Sayle <roger@nextmovesoftware.com>
Richard Biener <rguenther@suse.de>
PR target/99668
* expr.cc (try_expand_complex_as_vector): Try to use vec_init_optab
to convert a complex number to a two-component vector with the same
inner type.
(expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Check whether the
above function can be used to implement this VIEW_CONVERT_EXPR.
2026-07-10 Jim Lin <jim@andestech.com>
* common/config/riscv/riscv-common.cc
(riscv_multi_lib_info_t::parse): Remove early-out for multilibs
matching only the default march/mabi.
2026-07-10 Pengfei Li <Pengfei.Li2@arm.com>
* match.pd: Simplify vector permute and insert patterns.
2026-07-10 Kael Andrew Franco <kaelfandrew@gmail.com>
PR tree-optimization/125738
PR tree-optimization/64130
* match.pd: Use tree_expr_nonnegative_p for (X / Y) (==,!=) 0 -> X (<,>=) Y.
2026-07-10 Léo Hardt <leom.hardt@inf.ufrgs.br>
* sel-sched-ir.cc (struct succs_info): Removed
unused variable current_succs.
2026-07-10 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/124808
* match.pd(`(A >> CST1) CMP CST2`): New pattern.
2026-07-10 Thomas Schwinge <tschwinge@baylibre.com>
* system.h [INCLUDE_ITERATOR]: '#include <iterator>'.
2026-07-10 Mark Wielaard <mark@klomp.org>
* config/i386/i386.opt.urls: Regenerate.
2026-07-10 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/117922
* fold-mem-offsets.cc (INCLUDE_ALGORITHM): Added definition.
(INCLUDE_FUNCTIONAL): Likewise.
(class pass_fold_mem_offsets): Moved to bottom of file.
(class change_info): New.
(def_shadowed_by_cond_exec_p): New.
(get_single_def_in_bb): Converted to RTL-SSA.
(get_fold_mem_offset_root): Converted to RTL-SSA.
(get_uses): Removed.
(fold_offsets): Converted to RTL-SSA.
(fold_offsets_value): New.
(fold_offsets_1): Converted to RTL-SSA.
(has_foldable_uses_p): Converted to RTL-SSA.
(get_fold_mem_root): Removed.
(insn_uses_not_in_bitmap): New.
(drop_unsafe_candidates): New.
(do_commit_offset): Converted to RTL-SSA.
(do_analysis): Removed.
(do_commit_insn): Converted to RTL-SSA.
(do_fold_info_calculation): Removed.
(sort_changes): New.
(struct regno_changes): New.
(sort_pairs): New.
(do_check_validity): Removed.
(get_last_def): New.
(move_uses_to_prev_def): New.
(compute_validity_closure): Removed.
(change_in_vec_p): New.
(cancel_changes_for_group): New.
(find_keys_to_remove): New.
(free_changes_info): New.
(update_insns): New.
(fold_mem_offsets_1): New.
(pass_fold_mem_offsets::execute): Moved to bottom of file.
(fold_mem_offsets): New.
2026-07-10 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (flexible_array_member_type_p): Rename to
'nvptx_flexible_array_member_type_p'.
2026-07-10 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/m68k/m68k.h (ASM_PREFERRED_EH_DATA_FORMAT): Adjust parens
so they wrap the macro parameter.
2026-07-10 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-protos.h (is_frac_vlmul_p): Add new func
decl to predicate frac vlmul for a mode.
* config/riscv/riscv-v.cc (is_frac_vlmul_p): Add new func impl
for above.
(riscv_v_widen_constraint_ok): Add Source and Dest lmul less
and equal 1 handling.
* config/riscv/vector.md: Leverage widen constraint Wvr.
2026-07-10 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/116860
PR tree-optimization/114326
* match.pd (`((a ^ b) & c) cmp d || a != b`): Expand
to support bit_and and fix up the :c.
2026-07-09 Paul-Antoine Arras <parras@baylibre.com>
Thomas Schwinge <tschwinge@baylibre.com>
* builtin-types.def (BT_FN_COMPLEX_INT): Remove.
(BT_FN_COMPLEX_INT_ULONGLONG): New.
* omp-builtins.def (BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING): Use
BT_FN_COMPLEX_INT_ULONGLONG.
(BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_START): Likewise.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING): Likewise.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_START): Likewise.
* omp-expand.cc (expand_omp_for_static_nochunk): Move worksharing
builtin call after iteration count computation; pass n as niter.
(expand_omp_for_static_chunk): Likewise.
2026-07-09 Paul-Antoine Arras <parras@baylibre.com>
* common.opt (fopenmp-ompt): New option.
(fopenmp-ompt-detailed): New option.
* common.opt.urls: Regenerate.
* doc/invoke.texi (Option Summary): Add -fopenmp-ompt and
-fopenmp-ompt-detailed.
(OpenMP and OpenACC Options): Document -fopenmp-ompt and
-fopenmp-ompt-detailed.
* omp-builtins.def (BUILT_IN_GOMP_SINGLE_START_WITH_END): New builtin.
(BUILT_IN_GOMP_SINGLE_END): New builtin.
(BUILT_IN_GOMP_MASKED_END): New builtin.
(BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_START): New builtin.
(BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_END): New builtin.
(BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING_DISPATCH): New builtin.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_START): New builtin.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_END): New builtin.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING_DISPATCH): New builtin.
* omp-expand.cc (expand_omp_for_static_nochunk): With -fopenmp-ompt,
emit _start and _end variants instead of the plain worksharing call;
with -fopenmp-ompt-detailed, also emit _dispatch.
(expand_omp_for_static_chunk): Likewise.
* omp-low.cc (lower_omp_single_simple): With -fopenmp-ompt, use
GOMP_single_start_with_end instead of GOMP_single_start.
(lower_omp_single): With -fopenmp-ompt, emit GOMP_single_end.
(lower_omp_master): With -fopenmp-ompt, emit GOMP_masked_end.
* opts.cc (finish_options): Diagnose -fopenmp-ompt and
-fopenmp-ompt-detailed used without -fopenmp.
2026-07-09 Richard Sandiford <rdsandiford@googlemail.com>
PR debug/126169
* rtl.h (rtx_def::u2): Add value_uid to the union.
(CSELIB_VAL_UID): New macro.
* cselib.h (cselib_val::HASH_MASK): Delete.
(cselib_val::hash): Restore to a full int.
(cselib_val::uid): Delete.
(canonical_cselib_val): Use CSELIB_VAL_UID instead of cselib_val::uid.
* alias.cc (refs_newer_value_p): Likewise.
* dse.cc (canon_address): Likewise.
* print-rtl.cc (rtx_writer::print_rtx_operand_code_0): Likewise.
* var-tracking.cc (dv_uid, canon_value_cmp): Likewise.
(variable_post_merge_new_vals): Likewise.
* cselib.cc (new_elt_loc_list, new_cselib_val): Likewise.
(cselib_lookup): Likewise.
(cselib_find_slot): Remove use of cselib_val::HASH_MASK.
2026-07-09 Andreas Schwab <schwab@linux-m68k.org>
PR target/126121
* config/m68k/m68k.md (bsetmemqi, *bsetmemqi_ext, bclrmemqi)
(*bclrmemqi_ext): Add AND with 7 around bit number.
2026-07-09 Karl Meakin <karl.meakin@arm.com>
* bitmap.h: Replace uses of `CONSTEXPR` with `constexpr`.
* config/aarch64/aarch64-acle-builtins.cc: Likewise.
* config/aarch64/aarch64-builtins.cc: Likewise.
* config/aarch64/aarch64-protos.h: Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
* config/aarch64/aarch64.cc: Likewise.
* config/aarch64/driver-aarch64.cc: Likewise.
* config/arm/arm-mve-builtins-base.cc: Likewise.
* config/arm/arm-mve-builtins-functions.h: Likewise.
* config/arm/arm-mve-builtins-shapes.cc: Likewise.
* config/arm/arm-mve-builtins.cc: Likewise.
* config/riscv/andes-vector-builtins-bases.cc: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv-vector-builtins-bases.cc: Likewise.
* config/riscv/riscv-vector-builtins-shapes.cc: Likewise.
* config/riscv/riscv-vector-builtins.cc: Likewise.
* config/riscv/riscv-vector-builtins.h: Likewise.
* config/riscv/sifive-vector-builtins-bases.cc: Likewise.
* machmode.h: Likewise.
2026-07-09 Philipp Tomsich <philipp.tomsich@vrull.eu>
* doc/params.texi (widening-mul-defer-fma): Document.
* params.opt (-param=widening-mul-defer-fma=): New param.
* tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children):
Gate fma_deferring_state's enable predicate on
param_widening_mul_defer_fma on top of param_avoid_fma_max_bits.
* config/aarch64/aarch64-tuning-flags.def (AVOID_CROSS_LOOP_FMA):
Update the comment for the widening-mul-defer-fma effect.
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Inside the AARCH64_EXTRA_TUNE_AVOID_CROSS_LOOP_FMA block, set
param_widening_mul_defer_fma to 0.
2026-07-09 Nathan Sidwell <nathan@acm.org>
* Makefile.in (genprogrtl, genprogmd, genprogerr, genprog): Append,
rather than set.
* config/riscv/t-riscv: Delete genrvv-type-indexer workaround rule,
it is no longer needed.
2026-07-09 Martin Jambor <mjambor@suse.cz>
PR ipa/125207
* ipa-cp.cc (decide_about_value): Add detailed dumping about skipping
a value when there are no edges for it. Make dumping about skipping
because of growth limit violation consistent with other cases.
(decide_whether_version_node): Only create all-context nodes for local
nodes, remove the logic doing it in other cases, allow cloning for
single constant lattices for non-local nodes. Adjust dumping.
2026-07-09 Jim Lin <jim@andestech.com>
* config/riscv/riscv-string.cc (riscv_vector_expand_block_move):
Gate the memcpy path on riscv_memcpy_size_threshold instead of
riscv_memmove_size_threshold.
2026-07-09 Jovan Dmitrovic <jovan.dmitrovic@htecgroup.com>
* tree-ssa-loop-ivopts.cc (ivopts_estimate_reg_pressure):
Return zero if there are enough registers to store new
invariants and induction variables.
2026-07-09 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/112472
* match.pd ((trunc)copysign ((extend)x, CST) --> copysign (x, -1.0/1.0)):
New pattern.
2026-07-09 Zhou Xuhang <zhouxh2002@gmail.com>
* match.pd: Canonicalize shifted high-half unsigned multiply
overflow checks to widened comparisons. Simplify widened unsigned
multiply comparison against the narrow type maximum to IFN_MUL_OVERFLOW.
2026-07-09 Avinash Jayakar <avinashd@linux.ibm.com>
* config/rs6000/rs6000-builtins.def: Move AES builtins to future-vsx
stanza.
* doc/extend.texi: Add subheading for AES builtins.
2026-07-09 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config.gcc: Remove target s390-*. Don't accept
--with-mode=esa anymore.
* config.host: Remove target s390-*.
* config/host-linux.cc (TRY_EMPTY_VM_SPACE): Remove definition
for s390.
* config/s390/2827.md: Remove scheduling information for
mnemonics which are only used by -m31 but not by -m64.
* config/s390/2964.md: Ditto.
* config/s390/3906.md: Ditto.
* config/s390/3931.md: Ditto.
* config/s390/8561.md: Ditto.
* config/s390/9175.md: Ditto.
* config/s390/constraints.md (ZL): Remove TARGET_64BIT test.
* config/s390/driver-native.cc (s390_host_detect_local_cpu):
Remove handling for -mesa/-mzarch.
* config/s390/htmxlintrin.h (__TM_failure_address): Remove
-m31 part.
* config/s390/linux.h: Remove -m31 parts.
* config/s390/predicates.md: Ditto.
* config/s390/s390-builtins.def: Rename RTL expander name for
s390_vsce[fg].
* config/s390/s390-c.cc (s390_cpu_cpp_builtins): Remove
TARGET_{64BIT,ZARCH} tests.
* config/s390/s390-d.cc (s390_d_target_versions): Remove
TARGET_64BIT test.
* config/s390/s390.cc: Remove -m31 parts. In particular, there
is no need to distinguish between 64-bit registers in ABI
contexts anymore which is why UNITS_PER_WORD and UNITS_PER_LONG
always equal, now. Hence, replace UNITS_PER_LONG by
UNITS_PER_WORD.
* config/s390/s390.h: Ditto.
* config/s390/s390.md: Ditto. Mode iterator GPR is replaced by
DSI. Likewise, DGPR by new mode iterator TDSI. Remove mode
iterators P, DW, W because they are singletons, now.
* config/s390/s390.opt: Keep -m64 and -mzarch for backwards
compatibility. Mark -m31 and -mesa as undocumented.
* config/s390/s390.opt.urls: Regenerate.
* config/s390/t-linux64: Remove -m31 parts.
* config/s390/tpf.h (POINTERS_EXTEND_UNSIGNED): This is only
required for TPF which is why it is moved from s390.h here.
(TARGET_DEFAULT): Remove MASK_64BIT and MASK_ZARCH.
* config/s390/vector.md: Remove -m31 parts.
* config/s390/vx-builtins.md
(vec_scatter_element<V_HW_2:mode>_SI): There is no need for
multiplexing different address sizes for vec_scatter_element
anymore.
(vec_scatter_element<V_HW_32_64:mode>): Ditto.
* configure: Regenerate.
* configure.ac: Remove target s390-*.
* doc/install.texi: Remove mentions of s390 without also
referring to s390x.
* doc/invoke.texi: Remove options -m31 and -mesa. Document that
-m64 and -mzarch are the defaults, now, and that they don't have
any additional effect when explicitly specified.
* config/s390/s390x.h: Removed.
2026-07-08 Jim Lin <jim@andestech.com>
* config/riscv/riscv.h (TARGET_SFB_ALU): Add andes_45_series.
2026-07-08 Uros Bizjak <ubizjak@gmail.com>
PR target/126148
* config/i386/i386-expand.cc (ix86_gen_ccmp_first): Restrict
floating-point modes accepted for ccmp according to the
available floating-point instruction set.
2026-07-08 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/126136
* ifcvt.cc (noce_try_store_flag_logical): Fix for STORE_FLAG_VALUE
of -1.
2026-07-08 Jim Lin <jim@andestech.com>
* config/riscv/spacemit-x60.md (spacemit_x60_alu): Remove cpop
from the type list.
2026-07-08 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_tree_1): Remove group_size
argument and adjust.
(vect_build_slp_tree_2): Likewise.
(vect_build_slp_tree): Likewise.
(optimize_load_redistribution_1): Likewise.
(vect_build_slp_instance): Likewise.
(vect_analyze_slp_reduc_chain): Likewise.
(vect_analyze_slp_reduction): Likewise.
(vect_analyze_slp_reduction_group): Likewise.
(vect_analyze_slp_instance): Likewise.
(vect_lower_load_permutations): Likewise.
2026-07-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/126150
* tree-cfg.cc (replace_uses_by): Delay purging of EH edges
until after FOR_EACH_IMM_USE_STMT finished.
2026-07-08 Martin Uecker <uecker@tugraz.at>
* tree.h (flexible_array_member_type_p): New helper function.
* tree.cc (flexible_array_member_type_p): New helper function.
(flexible_array_type_p): Use new helper function.
2026-07-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/126159
* tree-data-ref.cc (dr_analyze_indices): Handle non-aggregate
union field accesses.
(access_fn_component_p): Adjust.
2026-07-08 Pengfei Li <Pengfei.Li2@arm.com>
* match.pd: Simplify SAD(x, x, acc) into acc.
2026-07-08 Evgeny Karpov <evgeny.karpov@arm.com>
* config/i386/cygming.h (TARGET_ASM_FUNCTION_END_PROLOGUE):
Rename.
(TARGET_ASM_EMIT_EXCEPT_PERSONALITY): Likewise.
(TARGET_ASM_INIT_SECTIONS): Likewise.
(SUBTARGET_ASM_UNWIND_INIT): Likewise.
(ASM_DECLARE_FUNCTION_SIZE): Likewise.
(ASM_DECLARE_COLD_FUNCTION_SIZE): Likewise.
* config/i386/i386-protos.h (i386_pe_end_function):
Remove declarations.
(i386_pe_end_cold_function): Likewise.
(i386_pe_seh_init): Likewise.
(i386_pe_seh_end_prologue): Likewise.
(i386_pe_seh_cold_init): Likewise.
(i386_pe_seh_emit_except_personality): Likewise.
(i386_pe_seh_init_sections): Likewise.
* config/mingw/winnt.cc (defined): Update.
(struct seh_frame_state): Move to mingw/winnt.h.
(i386_pe_seh_init): Rename into ...
(mingw_pe_seh_init): ... this.
(i386_pe_seh_end_prologue): Rename into ...
(mingw_pe_seh_end_prologue): ... this.
(i386_pe_seh_cold_init): Rename into ...
(mingw_pe_seh_cold_init): ... this.
(i386_pe_seh_fini): Rename into ...
(mingw_pe_seh_fini): ... this.
(seh_emit_stackalloc): Rename into ...
(mingw_pe_seh_emit_stackalloc): ... this.
(seh_cfa_adjust_cfa): Update.
(seh_frame_related_expr): Update.
(i386_pe_seh_emit_except_personality): Rename into ...
(mingw_pe_seh_emit_except_personality): ... this.
(i386_pe_seh_init_sections): Rename into ...
(mingw_pe_seh_init_sections): ... this.
(i386_pe_end_function): Rename into ...
(mingw_pe_end_function): ... this.
(i386_pe_end_cold_function): Rename into ...
(mingw_pe_end_cold_function): ... this.
* config/mingw/winnt.h (struct seh_frame_state):
Move from mingw/winnt.cc.
(mingw_pe_end_cold_function): Add declarations.
(mingw_pe_end_function): Likewise.
(mingw_pe_seh_init): Likewise.
(mingw_pe_seh_init_sections): Likewise.
(mingw_pe_seh_cold_init): Likewise.
(mingw_pe_seh_emit_except_personality): Likewise.
(mingw_pe_seh_end_prologue): Likewise.
2026-07-08 Tamar Christina <tamar.christina@arm.com>
* tree-vect-data-refs.cc (vect_create_addr_base_for_vector_ref):
Restructure computations to force separate base.
2026-07-08 Tamar Christina <tamar.christina@arm.com>
* tree-vect-data-refs.cc (vect_slp_analyze_store_dependences,
vect_slp_analyze_load_dependences,
vect_slp_analyze_instance_dependence): Use for-each over for with len.
* tree-vect-slp.cc (vect_mark_slp_stmts_relevant,
,vect_find_last_scalar_stmt_in_slp, vect_find_first_scalar_stmt_in_slp,
vect_build_slp_store_interleaving, vect_analyze_slp,
vect_slp_prune_covered_roots, vect_bb_partition_graph_r,
vect_remove_slp_scalar_calls): Likewise.
2026-07-08 Richard Biener <rguenther@suse.de>
* gimple-ssa-pta-constraints.cc (find_func_aliases_for_builtin_call):
Correctly use SCALAR rhs from the variadic argument part of
the function info or from NONLOCAL in case of intra-PTA.
(find_func_aliases_for_call): Handle .VA_ARG.
2026-07-08 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/aarch64/tuning_models/ampere1.h (ampere1_scalar_issue_info)
(ampere1_advsimd_issue_info, ampere1_vec_issue_info): New.
(ampere1_vector_cost): Use ampere1_vec_issue_info for issue_info.
* config/aarch64/tuning_models/ampere1b.h (ampere1b_scalar_issue_info)
(ampere1b_advsimd_issue_info, ampere1b_vec_issue_info): New.
(ampere1b_vector_cost): Use ampere1b_vec_issue_info for issue_info.
2026-07-08 H.J. Lu <hjl.tools@gmail.com>
Richard Sandiford <rdsandiford@googlemail.com>
PR target/124798
PR target/125436
* config/i386/i386-expand.cc: Include "function-abi.h".
(x86_64_ms_sysv_extra_clobbered_registers): Removed.
(ix86_expand_call): Don't add explicit call and ABI-switch
clobbers.
* config/i386/i386-features.cc (ix86_emit_tls_call): Call
ix86_tls_get_addr_abi to get GNU TLS ABI and use it, instead of
default_function_abi, for registers clobbered by GNU TLS call.
(ix86_place_single_tls_call): Set CALL_INSN_ABI_ID on TLS calls.
* config/i386/i386-options.cc (ix86_set_current_function): Don't
call reinit_regs.
* config/i386/i386-protos.h
(ix86_type_no_callee_saved_registers_p): Removed.
(ix86_tls_get_addr_abi): New.
* config/i386/i386.cc (ix86_alternate_abi): New prototype.
(ix86_conditional_register_usage): Changed to describe the
system ABI.
(ix86_type_no_callee_saved_registers_p): Make it static.
(ix86_function_value_regno_p): Replace ix86_cfun_abi () with
ix86_abi.
(ix86_save_reg): Only check TYPE_NO_CALLEE_SAVED_REGISTERS as
a special case.
(ix86_tls_get_addr_abi): New.
(legitimize_tls_address): Set CALL_INSN_ABI_ID on TLS calls.
Call ix86_alternate_abi to initialize the alternate function ABI.
(ix86_initialize_abi): New function.
(ix86_no_callee_saved_abi): Likewise.
(ix86_no_caller_saved_abi): Likewise.
(ix86_standard_abi): Likewise.
(ix86_alternate_abi): Likewise.
(ix86_function_abi_id): Likewise.
(ix86_fntype_abi): Likewise.
(ix86_hard_regno_call_part_clobbered): Handle newly added ABIs.
(TARGET_FNTYPE_ABI): New.
* config/i386/i386.md: Add ABI_ALTERNATE, ABI_NO_CALLEE_SAVED,
ABI_NO_CALLER_SAVED_RETURN_VOID, ABI_NO_CALLER_SAVED_RETURN_AX,
ABI_NO_CALLER_SAVED_RETURN_AX_DX,
ABI_NO_CALLER_SAVED_RETURN_AX_XMM0,
ABI_NO_CALLER_SAVED_RETURN_XMM0 and
ABI_NO_CALLER_SAVED_RETURN_XMM0_XMM1.
2026-07-08 Richard Sandiford <rdsandiford@googlemail.com>
* config/i386/i386.cc (ix86_function_arg): Remove always-true
condition.
2026-07-08 Richard Sandiford <rdsandiford@googlemail.com>
* config/i386/i386-features.cc: Include function-abi.h.
(ix86_emit_tls_call): Use default_function_abi instead of
call_used_regs.
* config/i386/i386.cc (x86_order_regs_for_local_alloc): Likewise.
(ix86_save_reg, x86_64_select_profile_regnum): Use crtl->abi
instead of call_used_regs.
2026-07-08 Richard Sandiford <rdsandiford@googlemail.com>
* config/i386/i386-protos.h (ix86_fntype_call_saved_registers):
Declare.
* config/i386/i386-options.cc (ix86_fntype_call_saved_registers): New
function, split out from...
(ix86_set_func_type): ...here. Avoid calling it if the result
would be ignored.
* config/i386/i386.cc (ix86_type_no_callee_saved_registers_p): Use
ix86_fntype_call_saved_registers instead of querying attributes
directly.
2026-07-08 Pan Li <pan2.li@intel.com>
* config/riscv/constraints.md (Wtt): Rename to Wvr to
indicate widen vector register constraint.
* config/riscv/riscv-protos.h (riscv_widen_overlap_ok): Rename
from...
(riscv_vector_mode_p): Add new decl for riscv-v.cc visibile.
(riscv_hard_regno_nregs): Ditto.
(riscv_v_widen_constraint_ok): Rename to...
* config/riscv/riscv-v.cc (riscv_v_widen_constraint_ok): Rename
to... and take care of Wvr constraint.
* config/riscv/riscv.cc (riscv_vector_mode_p): Remove static.
(riscv_hard_regno_nregs): Ditto.
(riscv_widen_overlap_ok): Remove.
* config/riscv/vector.md: Rename to Wvr.
2026-07-07 Richard Earnshaw <rearnsha@arm.com>
* config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION):
Remove +mpamv2.
* config/aarch64/aarch64-sys-regs.def: Remove sysregs associated
with MPAMv2_VID and adjust other related sysregs to use the
base permitted architecture.
* doc/invoke.texi (aarch64: +mpamv2): Remove option.
2026-07-07 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-cores.def (rigel): New entry.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AArch64 Options): Document the above.
2026-07-07 wangjue <juewang@linux.alibaba.com>
* common/config/riscv/riscv-common.cc (riscv_option_optimization_table):
Enable -funroll-loops and -munroll-only-small-loops at -O2 and above.
* config/riscv/riscv.cc (struct riscv_tune_param): Add fields
small_loop_unroll_ninsns and small_loop_unroll_factor.
(xt_c9501_tune_info): Set them.
(riscv_loop_unroll_adjust): New function.
(riscv_option_override): Turn off -munroll-only-small-loops when
-funroll-loops or -funroll-all-loops is explicitly given.
(TARGET_LOOP_UNROLL_ADJUST): Define.
* config/riscv/riscv.opt (munroll-only-small-loops): New option.
* config/riscv/riscv.opt.urls: Regenerate.
* doc/invoke.texi (RISC-V Options): Document -munroll-only-small-loops.
2026-07-07 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_abs_plus<mode>): New
define_insn_and_split.
2026-07-07 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/124146
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment):
Ignore user alignment left on a type's main variant; use the
mode's natural alignment instead.
2026-07-07 Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/altivec.md (UNSPEC_VUCMPRHN): New unspec entry.
(UNSPEC_VUCMPRLN): Likewise.
(UNSPEC_VUCMPRHB): Likewise.
(UNSPEC_VUCMPRLB): Likewise.
(UNSPEC_VUCMPRHH): Likewise.
(UNSPEC_VUCMPRLH): Likewise.
(UNSPEC_VUPKHSNTOB): Likewise.
(UNSPEC_VUPKLSNTOB): Likewise.
(UNSPEC_VUPKINT4TOBF16): Likewise.
(UNSPEC_VUPKINT8TOBF16): Likewise.
(UNSPEC_VUPKINT4TOFP32): Likewise.
(UNSPEC_VUPKINT8TOFP32): Likewise.
(vu_hl): New attribute.
(vu_lh): Likewise.
(VUPKNTOB): New int iterator.
(altivec_vupkhsntob): New define_insn.
(altivec_vupklsntob): Likewise.
(altivec_vupkint4tobf16): Likewise.
(altivec_vupkint8tobf16): Likewise.
(altivec_vupkint4tofp32): Likewise.
(altivec_vupkint8tofp32): Likewise.
(vucmpr_splat): New attribute.
(vucmpr_pcv): Likewise.
(vucmpr_uim): Likewise.
(VUCMPR_N): New int iterator.
(VUCMPR_B): Likewise.
(VUCMPR_H): Likewise.
(altivec_vucmpr<vu_hl>n): New define_expand.
(altivec_vucmpr<vu_hl>n_direct): New define_insn for vucmpr<vu_hl>n.
(altivec_vucmpr<vu_hl>b): New define_expand.
(altivec_vucmpr<vu_hl>b_direct): New define_insn for vucmpr<vu_hl>b.
(altivec_vucmpr<vu_hl>h): New define_expand.
(altivec_vucmpr<vu_hl>h_direct): New define_insn for vucmpr<vu_hl>h.
* config/rs6000/rs6000-builtins.def: Add vector uncompress and unpack
builtins under [future].
* config/rs6000/rs6000-overload.def: Add vec_uncompress* and vec_unpack*
interfaces.
2026-07-07 Stafford Horne <shorne@gmail.com>
PR target/126081
* config/or1k/or1k.cc (or1k_hard_regno_mode_ok): Stop allowing
SImode for FLAG_REGS.
(or1k_can_change_mode_class): Stop allowing SImode for
FLAG_REGS.
(or1k_noce_conversion_profitable_p): Always check
or1k_is_cmov_insn.
2026-07-07 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/102202
* tree-call-cdce.cc: Include "value-query.h" and "value-range.h".
(len_has_boolean_range_p): Remove.
(get_len_nonzero_value): New function. Return the nonzero member of
LEN's value range when it is a boolean range [0, 1] or an exact
two-value set {0, N}.
(can_shrink_wrap_len_p): Replace len_has_boolean_range_p call with
get_len_nonzero_value. Add NONZERO_LEN output parameter and set it
to the returned nonzero value on success.
(shrink_wrap_len_call): Use it to pin the length argument on the
guarded call path instead of build_one_cst.
(shrink_wrap_conditional_dead_built_in_calls): Declare local
nonzero_len and pass it to can_shrink_wrap_len_p and forward it to
shrink_wrap_len_call.
(pass_call_cdce::execute): Pass nullptr as NONZERO_LEN to
can_shrink_wrap_len_p.
2026-07-07 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125758
* gimple-range.cc (gimple_ranger::gimple_ranger): Create prefill stack.
(gimple_ranger::gimple_ranger): Dispose of prefill stack.
(gimple_ranger::prefill_name): Maybe push name on prefill stack.
(gimple_ranger::prefill_stmt_dependencies): Implement a DFS
stack for dependency satisfaction.
* gimple-range.h (struct prefill_frame): New.
(m_prefill_stack): New.
(prefill_name): Sadjust parameters.
(m_active_prefill): New.
2026-07-07 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125758
* gimple-range-cache.cc (struct time_stamp): New.
(set_timestamp): Deleted.
(set_timestamp_stored): New.
(set_timestamp_calc): New.
(set_always_current): Remove a parameter.
(temporal_value): Remove.
(temporal_value_stored): New.,
(temporal_value_calc): New.
(m_timestamp): Change to vector of struct time_stamp.
(temporal_cache::temporal_cache): Adjust.
(temporal_cache::current_p): Use both timestamps.
(temporal_cache::set_always_current): 0 means always current.
(temporal_cache::always_current_p): Check for 0.
(ranger_cache::get_global_range): adjust params.
(ranger_cache::update_consumers): Set stored timestamp.
(ranger_cache::set_global_range): Use new timestamps.
2026-07-06 Mark Zhuang <zhuangqiubin@linux.spacemit.com>
* config/riscv/riscv-cores.def (spacemit-x60): Use rva22u64
profile shorthand, add missing entries.
2026-07-06 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_build_slp_instance): For BB reductions
note the first root stmt.
2026-07-06 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-valu.md (*vec_set<mode>): Ad TImode instruction.
2026-07-06 Eric Botcazou <ebotcazou@adacore.com>
* config/vms/vms.h (ADA_LONG_TYPE_SIZE): Delete.
* doc/tm.texi.in (ADA_LONG_TYPE_SIZE): Likewise.
* doc/tm.texi: Regenerate.
* system.h (ADA_LONG_TYPE_SIZE): Poison.
2026-07-06 Eric Botcazou <ebotcazou@adacore.com>
* config/aarch64/aarch64.h (WIDEST_HARDWARE_FP_SIZE): Delete.
* config/alpha/alpha.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/i386/i386.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/ia64/vms.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/pa/pa.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/rs6000/rs6000.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/s390/s390.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/sparc/sparc.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* config/visium/visium.h (WIDEST_HARDWARE_FP_SIZE): Likewise.
* doc/tm.texi.in (WIDEST_HARDWARE_FP_SIZE): Likewise.
* doc/tm.texi: Regenerate.
* system.h (WIDEST_HARDWARE_FP_SIZE): Poison.
2026-07-06 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/120892
* gimple-ssa-split-paths.cc: Remove.
* passes.def (pass_split_paths): Remove.
* tree-pass.h (make_pass_split_paths): Remove.
* Makefile.in (OBJS): Remove gimple-ssa-split-paths.o.
* timevar.def (TV_SPLIT_PATHS): Remove.
* opts.cc (default_options_table): Remove the OPT_LEVELS_3_PLUS entry
for OPT_fsplit_paths.
* common.opt (fsplit-paths): Make it a deprecated no-op using Ignore.
* doc/invoke.texi (-fsplit-paths): Document as deprecated and remove it
from the option summary and the -O3 list.
2026-07-06 H.J. Lu <hjl.tools@gmail.com>
Richard Biener <rguenther@suse.de>
PR target/109780
PR target/109093
PR target/123210
PR target/124098
PR target/124165
PR target/124684
PR target/124759
PR target/124789
* alias.cc (static_reg_base_value): Moved to rtl.h.
(find_base_term): Remove static.
* alias.h (find_base_term): New prototype.
* function.cc (thread_prologue_and_epilogue_insns): Call
init_alias_analysis and end_alias_analysis.
* rtl.h (static_reg_base_value): Moved from alias.cc.
* config/i386/i386.cc (stack_access_data): Removed.
(ix86_find_all_reg_uses_1): Likewise.
(ix86_find_all_reg_uses): Likewise.
(ix86_access_stack_p): Likewise.
(ix86_need_alignment_p_2): Likewise.
(ix86_need_alignment_p_1): Likewise.
(ix86_need_alignment_p): Likewise.
(ix86_update_stack_alignment_2): New function.
(ix86_update_stack_alignment_1): Likewise.
(ix86_update_stack_alignment): Rewrite.
(ix86_find_max_used_stack_alignment): If check_stack_slot is
true, call ix86_update_stack_alignment on each INSN.
2026-07-06 liuhongt <hongtao.liu@intel.com>
PR target/126098
* config/i386/sse.md (VI1_AVX512VNNIBW): Remove.
(sdot_prod<ssedvecmodelower><mode>): Use VI1_AVX512 instead of
VI1_AVX512VNNIBW so V64QI is enabled only under AVX512BW.
(udot_prod<ssedvecmodelower><mode>): Likewise.
2026-07-05 Roger Sayle <roger@nextmovesoftware.com>
PR target/126094
* config/aarch64/aarch64-simd.md (aarch64_cmtst<mode><vczle><vczbe>):
Update pattern to match recent RTL simplification.
(*aarch64_cmtst<mode><vczle><vczbe>): Preserve the original.
(*aarch64_cmtst_same_<mode><vczle><vczbe>): Additional variant.
2026-07-05 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/125641
* match.pd: Fix #ifdef GIMPLE typo.
2026-07-05 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_cv_ld_clearcap): Remove.
Link clearcap.map to config/sol2-clearcap.map with Solaris ld.
* configure: Regenerate.
* config.in: Likewise.
* config/sol2-clearcap.map: Remove.
* config/sol2-clearcapv2.map: Rename to sol2-clearcap.map.
* config/t-sol2 (install-clearcap-map): Install source file
directly.
* config/sol2.h (LINK_CLEARCAP_SPEC): Guard with HAVE_SOLARIS_LD.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/67643
PR target/126117
* config/sh/sh.cc (fpscr_set_from_mem): Add missing argument to
get_free_reg invocation.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/67643
* config/sh/sh.cc (fpscr_set_from_mem): Specify a post-inc memory
operand for lds_fpscr after RA.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/55212
* config/sh/sh-protos.h (sh_lra_p): Remove.
(sh_legitimize_reload_address): Remove.
* config/sh/sh.h (LEGITIMIZE_RELOAD_ADDRESS): Remove.
* config/sh/sh.cc (sh_legitimize_reload_address): Remove.
(prepare_move_operands, broken_move): Remove sh_lra_p uses.
* config/sh/constraints.md (Rab, Rai, Ssd): Likewise.
* config/sh/sh.md: Likewise. Remove reload-only *addsi3 patterns.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.cc (emit_fpu_switch): Delete and merge into...
(fpscr_set_from_mem): ...this.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/116709
* config/sh/sh.md (movsf_ie): Mark constant-pool load FPUL
alternative with '*'.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/67459
PR target/122948
* config/sh/sh.md (addc): Fix T bit set expression.
(subc): Likewise.
2026-07-05 Oleg Endo <olegendo@gcc.gnu.org>
PR target/124778
* config/sh/sh.md (extend<mode>si2_short_mem_disp_z): Move after
'*extend<mode>si2_compact_mem_disp' patterns.
2026-07-04 Filip Kastl <fkastl@suse.cz>
* config/i386/i386.cc: Add override specifier for
better_epilogue_loop_than_p.
2026-07-03 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/122569
* match.pd (clz_msb_iso_table_index): New match pattern.
* tree-ssa-forwprop.cc (gimple_clz_msb_iso_table_index): Declare.
(simplify_count_zeroes): Recognize the new pattern; route its
table validation through the CTZ checkfn. Relax the element
type check to accept integer types up to 64 bits.
2026-07-03 Philipp Tomsich <philipp.tomsich@vrull.eu>
* match.pd (msb_or_cascade_32, msb_or_cascade_64): New match
helpers.
(clz_table_index): Rewrite the 32-bit and 64-bit forms to use
the cascade helpers.
2026-07-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/106164
PR tree-optimization/126042
PR tree-optimization/94589
* fold-const.cc (combine_comparisons): Split into
2 versions. Also handle BIT_AND_EXPR and BIT_IOR_EXPR.
* fold-const.h (combine_comparisons): New declaration.
* match.pd (`(a CMP1 b) BITOP (a CMP2 b)`): New pattern.
2026-07-03 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_out_plus_1): Handle +/-1 on the
lower regs without needing a scratch.
* config/avr/avr.md (add<mode>3_clobber, *add<mode>3_clobber)
(add<mode>3, *add<mode>3, addpsi3, *addpsi3): Add constraint
alternative "Y01 Ym1" for +/-1 without scratch.
2026-07-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (synthesize_add): Utilize shNadd.uw when
appropriate.
2026-07-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (and_synthesis): Use riscv_integer_cost rather
than riscv_const_insns. Use rotate+clear_bits+rotate when useful.
2026-07-03 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_vectorization_profitable_p): Make
profitabilty decision easier to debug.
2026-07-03 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/102202
* tree-call-cdce.cc: Include "tree-ssanames.h", "gimple-fold.h".
(len_has_boolean_range_p): New function.
(can_shrink_wrap_len_p): New function.
(gen_zero_len_conditions): New function.
(shrink_wrap_len_call): New function.
(shrink_wrap_conditional_dead_built_in_calls): Dispatch to
shrink_wrap_one_memset_call for memset calls eligible for the [0, 1]
length transform, ahead of the generic LHS and range-test paths.
(pass_call_cdce::execute): Collect memset calls satisfying
can_shrink_wrap_memset_p as shrink-wrap candidates.
2026-07-03 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/120027
* config/aarch64/aarch64-sve-builtins-base.cc (svext_bhw_impl::fold):
New member function. Fold the unsigned svextb/svexth/svextw
intrinsics to a bitwise AND when the merging form has an all-true
predicate.
2026-07-03 Tamar Christina <tamar.christina@arm.com>
Chris Bazley <Chris.Bazley@arm.com>
* expr.cc (store_constructor): Handle VLA vec_init support and generic
fall through piecewise copy.
* doc/md.texi: Document change
2026-07-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (synthesize_ior_xor): Use riscv_integer_cost
rather than riscv_const_insns.
2026-07-03 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.opt.urls: Renegerate.
* config/vax/vax.opt.urls: Renegerate.
2026-07-03 Oleg Endo <olegendo@gcc.gnu.org>
PR target/55212
* config/sh/sh.opt (mlra): Ignore option but keep it around
for compatibility.
* config/sh/sh.cc (TARGET_LRA_P): Remove.
(sh_lra_p): Move definition ...
* config/sh/sh-protos.h (sh_lra_p): ... here. Always return true.
* doc/invoke.texi: Remove mention of -mlra for SH.
2026-07-03 Oleg Endo <olegendo@gcc.gnu.org>
PR target/55212
* config/sh/sh.md (movv2sf, movv2sf_i, unnamed splits): New patterns.
* config/sh/sh.cc (sh_hard_regno_mode_ok): Allow V2SF only in fp-regs.
(sh_max_mov_insn_displacement): Return 0 for any float mode.
2026-07-03 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR target/55212
* config/sh/sh.md (extend<mode>si2_short_mem_disp_z): New
insn_and_split.
(extend<mode>si2): Use it for LRA.
(mov<mode>_store_mem_index, *mov<mode>_store_mem_index): New patterns.
(mov<mode>): Use it for LRA.
(movsf_ie_store_mem_index, movsf_ie_load_mem_index,
*movsf_ie_store_mem_inde, *movsf_ie_load_mem_index): New patterns.
(movsf): Use it for LRA.
2026-07-03 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR target/55212
* config/sh/predicates.md (pc_relative_load_operand): New predicate.
* config/sh/sh-protos.h (sh_movsf_ie_ra_split_p): Remove.
(sh_movsf_ie_y_split_p): New proto.
(sh_movsf_ie_subreg_multiword_p): New proto.
* config/sh/sh.cc: (sh_movsf_ie_ra_split_p): Remove.
(sh_movsf_ie_y_split_p): New function.
(sh_movsf_ie_subreg_multiword_p): New function.
(broken_move): Take movsf_ie_ra into account for fldi cases.
* config/sh/sh.md (movdf_i4_F_z): New insn.
(movdf): Use it when expanding.
(movsf_ie_ra): Use define_insn instead of define_insn_and_split.
Adjust alternatives.
(movsf_ie_rffr): New insn_and_split.
(movsf_ie_F_z, movsf_ie_Q_z, movsf_ie_y): New insns.
(movsf): Use new patterns when expanding.
2026-07-02 Pengfei Li <Pengfei.Li2@arm.com>
* config/aarch64/aarch64.cc
(aarch64_vector_costs::determine_suggested_unroll_factor): Add a
loop_vec_info parameter.
(determine_suggested_unroll_factor): Cap the suggested unroll for
small-niters loops.
(aarch64_vector_costs::finish_cost): Pass loop_vinfo to
determine_suggested_unroll_factor.
2026-07-02 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/bitmanip.md (xor_for_plus_minint): New pattern.
* config/riscv/riscv.cc (synthesize_add): Handle INT_MIN as
bit inversion. Add support for add.uw. Use riscv_integer_cost
rather than riscv_const_insns.
(synthesize_add_extended): Use riscv_integer_cost rather than
riscv_const_insns.
2026-07-02 Sivan Shani <sivan.shani@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Check for SVE2 and SVE_AES directly.
* config/aarch64/aarch64-sve-builtins-sve2.def (REQUIRED_EXTENSIONS):
Make AES builtins streaming-compatible with SSVE AES.
* config/aarch64/aarch64-sve2.md: Use TARGET_SVE_AES instead of
TARGET_SVE2_AES.
* config/aarch64/aarch64.h (TARGET_SVE2_AES): Rename to...
(TARGET_SVE_AES): Add support for SSVE AES.
* config/aarch64/iterators.md: Use TARGET_SVE2 for VNx2DI
PMULL pair mode.
2026-07-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/97344
* config.in: Re-generate.
* config/aarch64/aarch64.cc (aarch64_output_dwarf_dtprel): Define
function.
(TARGET_ASM_OUTPUT_DWARF_DTPREL): Define macro.
* configure: Re-generate.
* configure.ac: Add assemler check for dtprel relocation.
2026-07-02 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (SHAPE): Add a
trailing statement that lacks a semicolon. Add that to all
existing uses.
2026-07-02 Richard Earnshaw <rearnsha@arm.com>
* config/aarch64/aarch64-sve-builtins-shapes.cc (SHAPE): Add a
trailing statement that lacks a semicolon. Add that to all
existing uses.
2026-07-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_fn_gld_min_version): New function.
(gcc_fn_gld_elf_min_version): Likewise.
Use them.
* configure: Regenerate.
2026-07-02 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/124545
* match.pd: Add (T)A +- CST -> (T)(A +- CST') for widening
conversions from a signed inner type with undefined overflow.
2026-07-02 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR target/117182
PR target/55212
* target.def (cannot_substitute_const_equiv_p): New target hook.
* doc/tm.texi.in: Add it.
* lra-constraints.cc (get_equiv): Use it.
* config/sh/sh.cc (sh_cannot_substitute_const_equiv_p): Override it.
* doc/tm.texi: Re-generate.
2026-07-02 Kaz Kojima <kkojima@rr.iij4u.or.jp>
PR target/55212
* config/sh/predicates.md (hard_reg_r0..r7): New predicates.
* config/sh/sh.md (udivsi3_i4, udivsi3_i4_single,
udivsi3_i1): Rewrite with match_operand and match_dup.
(block_lump_real, block_lump_real_i4): Ditto.
(udivsi3): Adjust for it.
* config/sh/sh-mem.cc (expand_block_move): Ditto.
2026-07-01 Iain Sandoe <iain@sandoe.co.uk>
PR objc/124260
* config/darwin.cc (darwin_objc2_section): Also allow meta data
in const_data.
(darwin_label_is_anonymous_local_objc_name): Make ClassList linker-
visible.
(darwin_file_end): Update comments on the ImageInfo flags. Do not
claim we have signed pointers.
2026-07-01 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.md: Annotate mnemonic for
extzv_<mode>_{srl,sll}<clobbercc_or_nocc>.
2026-07-01 Icenowy Zheng <zhengxingda@iscas.ac.cn>
PR target/126049
* config/riscv/autovec.md: Change fmin/fmax reduction initial
value from inf/-inf to NaN for proper semantics of corresponding
C funtion.
2026-07-01 Robin Dapp <robin.dapp@oss.qualcomm.com>
* doc/md.texi: Document new behavior.
* lra-constraints.cc (get_dependent_filter): Call filter with
INVALID_REGNUM ref op instead of allowing everything.
2026-07-01 Thomas Schwinge <tschwinge@baylibre.com>
* config/gcn/gcn.h (ASM_V_SPEC): Define.
2026-07-01 Alfie Richards <alfie.richards@arm.com>
* tree-vect-loop-manip.cc (vect_set_loop_condition_normal):
Check if loop_vinfo is null before dereference.
2026-07-01 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-features.cc (compute_convert_gain) <ZERO_EXTEND>:
Provide costs for the new transformation.
(convert_insn): Implement *zero_extendsidi2 using the backend's
vec_setv2di_0_zero_extendsi_1 pattern (i.e. movq mem, %xmm).
(general_scalar_to_vector_candidate_p): Consider the pattern
(zero_extend:DI (mem:SI ...)) to be a candidate for DImode STV.
2026-07-01 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_context::simplify_ternary_operation)
<case VEC_MERGE>: Simplify a vec_merge of a vec_merge with a
repeated operand.
2026-07-01 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/126054
* config/s390/s390.md: Fix
extzv_<mode>_{srl,sll}<clobbercc_or_nocc> by adjusting the
bitmasks in the output templates.
2026-07-01 Jakub Jelinek <jakub@redhat.com>
* config/aarch64/tuning_models/neoversev2.h
(neoversev2_dispatch_constraint_callback): Remove spurious semicolon.
* config/aarch64/aarch64-elf-metadata.cc
(gnu_property_features_to_string): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc (SHAPE (write_zt),
SHAPE (write_lane_zt)): Likewise.
2026-07-01 Jakub Jelinek <jakub@redhat.com>
* config/aarch64/aarch64-neon-builtins-base.h: Use
namespace aarch64_acle { namespace functions { ... } } instead of
C++17 namespace aarch64_acle::functions { ... }.
* config/aarch64/aarch64-neon-builtins-shapes.h: Use
namespace aarch64_acle { namespace shapes { ... } } instead of
C++17 namespace aarch64_acle::shapes { ... }.
* config/aarch64/aarch64-neon-builtins-shapes.cc: Likewise.
2026-07-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/125040
* tree-ssa-pre.cc (clean): Iterate processing.
2026-07-01 Alfie Richards <alfie.richards@arm.com>
* tree-ssa-loop-manip.h: Add argument to create_iv.
* tree-ssa-loop-manip.cc (create_iv): Change step to not
necessarily be loop invariant.
* tree-vect-data-refs.cc (bump_vector_ptr): Remove logic for
updating use-def chain.
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
Change to use LOOP_VINFO_IV_INCREMENT instead of VF.
(vect_set_loop_condition_partial_vectors_avx512):
Change to use LOOP_VINFO_IV_INCREMENT instead of VF.
(vect_gen_vector_loop_niters): Update to handle
LOOP_VINFO_IV_INCREMENT.
(vect_get_loop_iv_increment): New function.
* tree-vect-loop.cc (vectorizable_induction): Update to use
LOOP_VINFO_IV_INCREMENT instead of VF, and remove SELECT_VL
logic.
(vect_update_ivs_after_vectorizer_for_early_breaks):
Update to use LOOP_VINFO_IV_INCREMENT over VF and move IV
update to vect_iv_increment_position.
(vect_transform_loop): Add initialization of
LOOP_VINFO_IV_INCREMENT.
* tree-vect-stmts.cc (vect_get_strided_load_store_ops):
Update to use dr_increment and dr_bump, remove SELECT_VL logic.
(vect_get_data_ptr_increment): Change to return the increment
needed to advance the pointer to the next iteration.
(vect_get_data_ptr_bump): New function.
(vectorizable_scan_store): Update to use vect_get_data_ptr_bump
and to remove SELECT_VL logic.
(vectorizable_store): Update to use vect_get_data_ptr_bump and
vect_get_data_ptr_increment.
(vectorizable_load): Update to use vect_get_data_ptr_bump and
vect_get_data_ptr_increment.
* tree-vectorizer.h (loop_vec_info): Add iv_increment field.
(LOOP_VINFO_IV_INCREMENT): New macro.
(LOOP_VINFO_IV_INCREMENT_INVARIANT_P): New macro.
(bump_vector_ptr): Remove incr_ptr argument.
(vect_get_loop_iv_increment): New function.
2026-07-01 Alfie Richards <alfie.richards@arm.com>
* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Check for null
pntr_incr.
2026-07-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/125040
* tree-ssa-pre.cc (sorted_array_from_bitmap_set): Compute
the set of entries to the value graph before building the
final sorted expression set.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac: Remove --with-gnu-ld, gnu_ld_flag.
* configure: Regenerate.
* config.gcc: Remove gnu_ld_flag.
* doc/install.texi (Configuration, --with-gnu-ld): Remove.
(Specific, all ELF targets): Remove GNU ld link.
* doc/invoke.texi (IA-64 Options, -mgnu-ld): Remove comment.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config.gcc: Remove gnu_ld.
<*-*-vms*>: Check ld_flavor instead of gnu_ld.
<ia64*-*-elf*> (target_cpu_default): Always add MASK_GNU_LD.
<mips*-*-*> (target_cpu_default2): Always add
MASK_SPLIT_ADDRESSES.
<hppa*64*-*-hpux11*> (target_cpu_default): Check ld_flavor instead
of gnu_ld. Move ...
* configure.ac: ... here.
Remove gnu_ld.
Check ld_flavor instead of gnu_ld.
(gcc_cv_ld_static_dynamic) <*-*-hpux*>: Don't check gnu_ld.
(gcc_cv_ld_version_script): Check ld --help for --version-script.
(gcc_cv_ld_soname): Check ld --help for -soname.
<*-*-darwin*>: Always use Darwin version.
<*-*-solaris2*>: Always use Solaris version with Solaris ld.
(gcc_cv_ld_demangle): Don't check gnu_ld.
* configure: Regenerate.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (HAVE_GNU_LD): Remove.
(gcc_cv_ld_at_file): New test.
* configure: Regenerate.
* config.in: Regenerate.
* collect2.cc: Check HAVE_LD_AT_FILE instead of HAVE_GNU_LD.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac: Remove --with-gnu-as, gas_flag.
* configure: Regenerate.
* config.gcc: Remove gas_flag.
* doc/install.texi (Configuration, --with-gnu-as): Remove.
(Specific, hppa64-hp-hpux11*): Remove --with-gnu-as reference.
(Specific, ia64-*-hpux*): Likewise. Recomment --with-as instead.
* doc/invoke.texi (IA-64 Options, -mgnu-as): Remove comment.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* acinclude.m4 (gcc_GAS_FLAGS): Check as_flavor instead of gas.
* config.gcc: Remove gas.
<ia64*-*-elf*> (target_cpu_defaults): Always add MASK_GNU_AS.
<ia64-hp-*vms*>: Likewise.
<hppa*-*-*> (target_cpu_default2): Always add MASK_GAS.
* configure.ac: Remove gas.
* configure: Regenerate.
2026-07-01 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa-structalias.cc (set_uids_in_ptset): If ANYTHING is
present in the ESCAPED_RETURN solution, record that the global
solution has an escaped heap if FROM contains a heap variable.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* gcc.cc (asm_options) [HAVE_GNU_AS]: Move to ...
(ASM_V_SPEC) ... this.
* config/nvptx/nvptx.h (ASM_SPEC): Rename to ASM_V_SPEC.
Adjust comment.
* config/rs6000/aix.h [HAVE_AIX_AS] (ASM_V_SPEC): Define.
* config/sol2.h (ASM_SPEC_BASE): Move -v handling to ...
[HAVE_SOLARIS_AS] (ASM_V_SPEC): ... this. Also handle -w.
* doc/tm.texi.in (Driver, ASM_V_SPEC): Document.
* doc/tm.texi: Regenerate.
* config/darwin.h (ASM_OPTIONS): Remove.
* config/i386/darwin.h (ASM_SPEC): Remove ASM_OPTIONS.
* config/ia64/hpux.h (AS_NEEDS_DASH_FOR_PIPED_INPUT): Remove.
* configure.ac (HAVE_GNU_AS): Remove.
* configure: Regenerate.
* config.in: Regenerate.
2026-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* acinclude.m4: Check as_flavor, ld_flavor instead of solaris_as,
solaris_ld.
* configure.ac: Likewise.
(as_flavor, ld_flavor): New variables.
Adapt messages.
Set based on as, ld version output.
(HAVE_AIX_AS): Define.
* configure: Regenerate.
* config.in: Regenerate.
2026-07-01 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h
(get_available_features): Remove AMX-TF32.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AMX_TF32_SET): Removed.
(OPTION_MASK_ISA2_AMX_TF32_UNSET): Ditto.
(OPTION_MASK_ISA2_AMX_TILE_UNSET): Remove AMX_TF32.
(ix86_handle_option): Ditto.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Remove FEATURE_AMX_TF32.
* common/config/i386/i386-isas.h: Remove AMX-TF32.
* config.gcc: Do not include amxtf32intrin.h.
* config/i386/amxtf32intrin.h: Remove AMX-TF32 intrins.
* config/i386/cpuid.h (bit_AMX_TF32): Removed.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Remove AMX_TF32.
* config/i386/i386-isa.def (AMX_TF32): Removed.
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Remove AMX-TF32.
* config/i386/i386.opt: Ditto.
* config/i386/i386.opt.urls: Ditto.
* config/i386/immintrin.h: Do not include amxtf32intrin.h.
* doc/extend.texi: Remove amx-tf32.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
2026-07-01 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_DIAMONDRAPIDS): Remove PTA_AMX_TF32.
* doc/invoke.texi: Correct documentation.
2026-06-30 Oleg Endo <olegendo@gcc.gnu.org>
PR target/55212
* config/sh/predicates.md (simple_mem_operand):
Use 'satisfies_constraint_Sra'.
(post_inc_mem, pre_dec_mem): Use 'satisfies_constraint_Rab'.
* config/sh/constraints.md (Rab, Rai, Sgb): New constraints.
(Sua, Sdd, Snd, Ssd, Sbv, Sra, Ara, Add): Use Rab and Rai constraints.
* config/sh/sync.md (atomic_mem_operand_0, atomic_mem_operand_1): Reject
GBR addresses when hard-llcs atomic mode is enabled.
2026-06-30 Abhishek Kaushik <abhishek.kaushik@arm.com>
* config/aarch64/aarch64.cc: Include gimple-fold.h.
(aarch64_try_widen_mult_by_pow2): New function.
(aarch64_instruction_selection): Call it for conversion assignments.
2026-06-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125961
* tree-ssa-phiopt.cc (factor_out_conditional_operation): Use
remove_phi_node instead of gsi_remove for the phi node.
(factor_out_conditional_load): Likewise.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-acle-builtins.h
(TYPES_neon_reinterpret1, TYPES_neon_reinterpret,
TYPES_neon_reinterpretq1, TYPES_neon_reinterpretq,
neon_reinterpret, neon_reinterpretq): New type lists.
* config/aarch64/aarch64-builtins.cc (VREINTERPRET_BUILTIN2,
VREINTERPRET_BUILTINS1, VREINTERPRET_BUILTINS,
VREINTERPRETQ_BUILTIN2, VREINTERPRETQ_BUILTINS1,
VREINTERPRETQ_BUILTINS, VREINTERPRET_BUILTIN): Delete macros.
(AARCH64_SIMD_VREINTERPRET_BUILTINS): Delete enum member.
(aarch64_init_simd_intrinsics): Delete function.
(init_arm_neon_builtins): Delete call to
`aarch64_init_simd_intrinsics`.
(aarch64_general_fold_builtin): Delete case for
`AARCH64_SIMD_VREINTERPRET_BUILTINS`.
* config/aarch64/aarch64-neon-builtins-base.cc (struct
gimple_reinterpret): New struct.
(vreinterpret, vreinterpretq): New function bases.
* config/aarch64/aarch64-neon-builtins-base.def (vreinterpret,
vreinterpretq): New function groups.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-simd-pragma-builtins.def (vext_mf8,
vextq_mf8, vrev64_mf8, vrev64q_mf8, vrev32_mf8, vrev32q_mf8,
vrev16_mf8, vrev16q_mf8, vtrn1_mf8, vtrn1q_mf8, vtrn2_mf8,
vtrn2q_mf8, vtrn_mf8, vtrnq_mf8, vuzp1_mf8, vuzp1q_mf8,
vuzp2_mf8, vuzp2q_mf8, vuzp_mf8, vuzpq_mf8, vzip1_mf8,
vzip1q_mf8, vzip2_mf8, vzip2q_mf8, vzip_mf8, vzipq_mf8):
Delete functions.
* config/aarch64/aarch64-sve-builtins-shapes.cc (parse_type):
Handle `D` or `Q` followed by `x1,x2,x3,x4` to mean tuple
types.
* config/aarch64/aarch64-acle-builtins.h (TYPES_bh_poly,
TYPES_bhs_neon, TYPES_neon_rev16, TYPES_neon_rev32,
TYPES_neon_rev64): New type lists.
(bh_poly, bhs_neon, neon_rev16, neon_rev32, neon_rev64):
Likewise.
* config/aarch64/aarch64-builtins.cc (aarch64_simd_tuple_types):
Remove `static` qualifier.
* config/aarch64/aarch64-builtins.h (aarch64_simd_tuple_types):
New declaration.
* config/aarch64/aarch64-neon-builtins-base.cc (build_tuple_get,
build_tuple_set): New functions.
(class gimple_permute, class gimple_permute_pair): New classes.
(ext_mask, rev_mask, trn_mask, uzp_mask, zip_mask): New
functions.
(vext, vextq, vrev16, vrev16q, vrev32, vrev32q, vtrn1, vtrn1q,
btrn2, vtrn2q, vtrn, vtrnq, vuzp1, vuzp1q, vuzp2, vuzp2q, vuzp,
vuzpq, vzip1, vzip1q, vzip2, vzip2q, vzip, vzipq): New function
bases.
* config/aarch64/aarch64-neon-builtins-base.def (vext, vextq,
vrev16, vrev16q, vrev32, vrev32q, vrev64, vrev64q, vtrn,
vtrn1, vtrn1q, vtrn2, vtrn2q, vtrnq, vuzp, vuzp1, vuzp1q,
vuzp2, vuzp2q, vuzpq, vzip, vzip1, vzip1q, vzip2, vzip2q,
vzipq): New function groups.
* config/aarch64/aarch64-simd-builtins.def (zip1, zip2, uzp1,
uzp2, trn1, trn2): Delete builtin functions.
* config/aarch64/arm_neon.h (vext_f16, vext_f32, vext_f64,
vext_p8, vext_p16, vext_p64, vext_s8, vext_s16, vext_s32,
vext_s64, vext_u8, vext_u16, vext_u32, vext_u64, vextq_f16,
vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_p64,
vextq_s8, vextq_s16, vextq_s32, vextq_s64, vextq_u8,
vextq_u16, vextq_u32, vextq_u64, vrev16_p8, vrev16_s8,
vrev16_u8, vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8,
vrev32_p16, vrev32_s8, vrev32_s16, vrev32_u8, vrev32_u16,
vrev32q_p8, vrev32q_p16, vrev32q_s8, vrev32q_s16, vrev32q_u8,
vrev32q_u16, vrev64_f16, vrev64_f32, vrev64_p8, vrev64_p16,
vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f16, vrev64q_f32, vrev64q_p8, vrev64q_p16,
vrev64q_s8, vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16,
vrev64q_u32, vtrn1_f16, vtrn1_f32, vtrn1_p8, vtrn1_p16,
vtrn1_s8, vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16,
vtrn1_u32, vtrn1q_f16, vtrn1q_f32, vtrn1q_f64, vtrn1q_p8,
vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32, vtrn1q_s64,
vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_p64, vtrn1q_u64,
vtrn2_f16, vtrn2_f32, vtrn2_p8, vtrn2_p16, vtrn2_s8,
vtrn2_s16, vtrn2_s32, vtrn2_u8, vtrn2_u16, vtrn2_u32,
vtrn2q_f16, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8,
vtrn2q_u16, vtrn2q_u32, vtrn2q_u64, vtrn2q_p64, vtrn_f16,
vtrn_f32, vtrn_p8, vtrn_p16, vtrn_s8, vtrn_s16, vtrn_s32,
vtrn_u8, vtrn_u16, vtrn_u32, vtrnq_f16, vtrnq_f32, vtrnq_p8,
vtrnq_p16, vtrnq_s8, vtrnq_s16, vtrnq_s32, vtrnq_u8,
vtrnq_u16, vtrnq_u32, vuzp1_f16, vuzp1_f32, vuzp1_p8,
vuzp1_p16, vuzp1_s8, vuzp1_s16, vuzp1_s32, vuzp1_u8,
vuzp1_u16, vuzp1_u32, vuzp1q_f16, vuzp1q_f32, vuzp1q_f64,
vuzp1q_p8, vuzp1q_p16, vuzp1q_s8, vuzp1q_s16, vuzp1q_s32,
vuzp1q_s64, vuzp1q_u8, vuzp1q_u16, vuzp1q_u32, vuzp1q_u64,
vuzp1q_p64, vuzp2_f16, vuzp2_f32, vuzp2_p8, vuzp2_p16,
vuzp2_s8, vuzp2_s16, vuzp2_s32, vuzp2_u8, vuzp2_u16,
vuzp2_u32, vuzp2q_f16, vuzp2q_f32, vuzp2q_f64, vuzp2q_p8,
vuzp2q_p16, vuzp2q_s8, vuzp2q_s16, vuzp2q_s32, vuzp2q_s64,
vuzp2q_u8, vuzp2q_u16, vuzp2q_u32, vuzp2q_u64, vuzp2q_p64,
vzip1_f16, vzip1_f32, vzip1_p8, vzip1_p16, vzip1_s8,
vzip1_s16, vzip1_s32, vzip1_u8, vzip1_u16, vzip1_u32,
vzip1q_f16, vzip1q_f32, vzip1q_f64, vzip1q_p8, vzip1q_p16,
vzip1q_s8, vzip1q_s16, vzip1q_s32, vzip1q_s64, vzip1q_u8,
vzip1q_u16, vzip1q_u32, vzip1q_u64, vzip1q_p64, vzip2_f16,
vzip2_f32, vzip2_p8, vzip2_p16, vzip2_s8, vzip2_s16,
vzip2_s32, vzip2_u8, vzip2_u16, vzip2_u32, vzip2q_f16,
vzip2q_f32, vzip2q_f64, vzip2q_p8, vzip2q_p16, vzip2q_s8,
vzip2q_s16, vzip2q_s32, vzip2q_s64, vzip2q_u8, vzip2q_u16,
vzip2q_u32, vzip2q_u64, vzip2q_p64): Delete functions.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64.md (UNSPEC_BSL): Delete unspec.
* config/aarch64/aarch64-simd-pragma-builtins.def (vbsl_mf8,
vbslq_mf8): Delete functions.
* config/aarch64/aarch64-neon-builtins-base.cc (build_cast): New
function.
(class gimple_not_rhs, class gimple_bsl, class gimple_rbit,
class gimple_eor3, class gimple_bcax, class gimple_rax1, class
gimple_xar, class gimple_ifn): New classes.
(vand, vandq, vbic, vbicq, vbsl, vbslq, veor, veorq, vmvn,
vmvnq, vorn, vornq, vorr, vorrq, vrbit, vrbitq, vbcaxq, veor3q,
vrax1q, vxarq, vcls, vclsq, vclz, vclzq, vcnt, vcntq): New
function bases.
* config/aarch64/aarch64-neon-builtins-shapes.cc (shift): New function.
* config/aarch64/aarch64-builtins.cc
(aarch64_types_bsl_p_qualifiers,
aarch64_types_bsl_s_qualifiers,
aarch64_types_bsl_u_qualifiers): Delete unused qualifiers.
* config/aarch64/aarch64-simd.md
(@aarch64_rbit<mode><vczle><vczbe>): Add `@` modifier so that
it is callable from `aarch64-neon-builtins-base.cc`.
* config/aarch64/aarch64-acle-builtins.h (TYPES_b_neon,
TYPES_b_poly): New type lists.
* config/aarch64/aarch64-neon-builtins-base.def (vand, vandq,
vbic, vbicq, vbsl, vbslq, veor, veorq, vmvn, vmvnq, vorn,
vornq, vorr, vorrq, vrbit, vrbitq, vbcaxq, veor3q, vrax1q,
vxarq, vcls, vclsq, vclz, vclzq, vcnt, vcntq): New function
groups.
* config/aarch64/aarch64-simd-builtins.def (clrsb, clz, ctz,
popcount, rbit, simd_bsl): Delete builtin functions.
* config/aarch64/arm_neon.h (vbsl_f16, vbsl_f32, vbsl_f64,
vbsl_p8, vbsl_p16, vbsl_p64, vbsl_s8, vbsl_s16, vbsl_s32,
vbsl_s64, vbsl_u8, vbsl_u16, vbsl_u32, vbsl_u64, vbslq_f16,
vbslq_f32, vbslq_f64, vbslq_p8, vbslq_p16, vbslq_s8,
vbslq_s16, vbslq_p64, vbslq_s32, vbslq_s64, vbslq_u8,
vbslq_u16, vbslq_u32, vbslq_u64, vcls_s8, vcls_s16, vcls_s32,
vclsq_s8, vclsq_s16, vclsq_s32, vcls_u8, vcls_u16, vcls_u32,
vclsq_u8, vclsq_u16, vclsq_u32, vclz_s8, vclz_s16, vclz_s32,
vclz_u8, vclz_u16, vclz_u32, vclzq_s8, vclzq_s16, vclzq_s32,
vclzq_u8, vclzq_u16, vclzq_u32, vcnt_p8, vcnt_s8, vcnt_u8,
vcntq_p8, vcntq_s8, vcntq_u8, vrbit_p8, vrbit_s8, vrbit_u8,
vrbitq_p8, vrbitq_s8, vrbitq_u8, veor3q_u8, veor3q_u16,
veor3q_u32, veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32,
veor3q_s64, vrax1q_u64, vxarq_u64, vbcaxq_u8, vbcaxq_u16,
vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
vbcaxq_s64): Delete functions.
2026-06-30 Karl Meakin <karlwfmeakin@gmail.com>
* config/aarch64/aarch64-simd-pragma-builtins.def (
vcopy_lane_mf8, vcopyq_lane_mf8, vcopy_laneq_mf8,
vcopyq_laneq_mf8, vdup_lane_mf8, vdupq_lane_mf8,
vdup_laneq_mf8, vdupq_laneq_mf8, vset_lane_mf8,
vsetq_lane_mf8): Delete entries.
* config/aarch64/aarch64-builtins.cc
(AARCH64_SIMD_VGET_LOW_BUILTINS,
AARCH64_SIMD_VGET_HIGH_BUILTINS, VGET_LOW_BUILTIN,
VGET_HIGH_BUILTIN): Delete macros.
(enum aarch64_builtins): Delete
`AARCH64_SIMD_BUILTIN_LANE_CHECK`.
(aarch64_init_simd_builtin_functions): Delete code that
registers `__builtin_aarch64_im_lane_boundsi`.
(aarch64_pragma_builtins_checker::check): Delete cases for
`UNSPEC_DUP_LANE`, `UNSPEC_GET_LANE` and `UNSPEC_VEC_COPY`.
(aarch64_simd_expand_builtin): Delete case for
`AARCH64_SIMD_BUILTIN_LANE_CHECK`.
(aarch64_expand_pragma_builtin): Delete cases for
`UNSPEC_DUP_LANE` and `UNSPEC_VEC_COPY`.
(aarch64_general_fold_builtin): Delete cases for
`AARCH64_SIMD_VGET_LOW_BUILTINS`,
`AARCH64_SIMD_VGET_HIGH_BUILTINS` and
`AARCH64_SIMD_BUILTIN_LANE_CHECK`.
(aarch64_gimple_fold_pragma_builtin): Delete cases for
`UNSPEC_DUP_LANE` and `UNSPEC_VEC_COPY`.
(aarch64_general_gimple_fold_builtin): Delete cases for
`AARCH64_SIMD_BUILTIN_LANE_CHECK`.
* config/aarch64/aarch64.md (UNSPEC_DUP_LANE): Delete unspec.
* config/aarch64/aarch64-neon-builtins-shapes.cc (range, lane):
New functions.
(struct neon_shape): Add new fields for additional checks, and
call them in `check()`.
* config/aarch64/aarch64-acle-builtins.cc
(gimple_folder::force_val, gimple_folder::assign): New
functions.
* config/aarch64/aarch64-acle-builtins.h (TYPES_all_neon,
TYPES_bhsd_neon, TYPES_neon_copy_lane): New type lists.
* config/aarch64/iterators.md (VALL_F16_NO_V2Q): Add `V4BF` and `V8BF`.
* config/aarch64/aarch64-neon-builtins-base.def (vget_lane,
vgetq_lane, vget_high, vget_low, vset_lane, vsetq_lane,
vdup_lane, vdupq_lane, vdup_laneq, vdupq_laneq, vcopy_lane,
vcopy_laneq, vcopyq_lane, vcopyq_laneq): New function groups.
* config/aarch64/aarch64-neon-builtins-base.cc (build_lane_get,
build_lane_set, build_vec_dup): New functions.
(struct gimple_get_lane, struct gimple_get_half, struct
gimple_set_lane, struct gimple_copy_lane, struct gimple_dup,
struct gimple_dup_lane): New structs.
(vget_lane, vgetq_lane, vset_lane, vsetq_lane, vcopy_lane,
vcopyq_lane, vcopy_laneq, vcopyq_laneq, vdup_lane, vdupq_lane,
vdupq_lane, vdupq_laneq): New function bases.
* config/aarch64/arm_neon.h (__aarch64_vdup_lane_p8,
__aarch64_vdup_lane_p16, __aarch64_vdup_lane_p64,
__aarch64_vdup_lane_s8, __aarch64_vdup_lane_s16,
__aarch64_vdup_lane_s32, __aarch64_vdup_lane_s64,
__aarch64_vdup_lane_u8, __aarch64_vdup_lane_u16,
__aarch64_vdup_lane_u32, __aarch64_vdup_lane_u64,
__aarch64_vdup_laneq_p8, __aarch64_vdup_laneq_p16,
__aarch64_vdup_laneq_p64, __aarch64_vdup_laneq_s8,
__aarch64_vdup_laneq_s16, __aarch64_vdup_laneq_s32,
__aarch64_vdup_laneq_s64, __aarch64_vdup_laneq_u8,
__aarch64_vdup_laneq_u16, __aarch64_vdup_laneq_u32,
__aarch64_vdup_laneq_u64, __aarch64_vdupq_lane_p8,
__aarch64_vdupq_lane_p16, __aarch64_vdupq_lane_p64,
__aarch64_vdupq_lane_s8, __aarch64_vdupq_lane_s16,
__aarch64_vdupq_lane_s32, __aarch64_vdupq_lane_s64,
__aarch64_vdupq_lane_u8, __aarch64_vdupq_lane_u16,
__aarch64_vdupq_lane_u32, __aarch64_vdupq_lane_u64,
__aarch64_vdupq_laneq_p8, __aarch64_vdupq_laneq_p16,
__aarch64_vdupq_laneq_p64, __aarch64_vdupq_laneq_s8,
__aarch64_vdupq_laneq_s16, __aarch64_vdupq_laneq_s32,
__aarch64_vdupq_laneq_s64, __aarch64_vdupq_laneq_u8,
__aarch64_vdupq_laneq_u16, __aarch64_vdupq_laneq_u32,
__aarch64_vdupq_laneq_u64, __AARCH64_LANE_CHECK,
__aarch64_vget_lane_any, __aarch64_vset_lane_any): Delete
macros.
(vget_lane_f16, vget_lane_f32, vget_lane_f64, vget_lane_p8,
vget_lane_p16, vget_lane_p64, vget_lane_s8, vget_lane_s16,
vget_lane_s32, vget_lane_s64, vget_lane_u8, vget_lane_u16,
vget_lane_u32, vget_lane_u64, vgetq_lane_f16, vgetq_lane_f32,
vgetq_lane_f64, vgetq_lane_p8, vgetq_lane_p16, vgetq_lane_p64,
vgetq_lane_s8, vgetq_lane_s16, vgetq_lane_s32, vgetq_lane_s64,
vgetq_lane_u8, vgetq_lane_u16, vgetq_lane_u32, vgetq_lane_u64,
vset_lane_f16, vset_lane_f32, vset_lane_f64, vset_lane_p8,
vset_lane_p16, vset_lane_p64, vset_lane_s8, vset_lane_s16,
vset_lane_s32, vset_lane_s64, vset_lane_u8, vset_lane_u16,
vset_lane_u32, vset_lane_u64, vsetq_lane_f16, vsetq_lane_f32,
vsetq_lane_f64, vsetq_lane_p8, vsetq_lane_p16, vsetq_lane_p64,
vsetq_lane_s8, vsetq_lane_s16, vsetq_lane_s32, vsetq_lane_s64,
vsetq_lane_u8, vsetq_lane_u16, vsetq_lane_u32, vsetq_lane_u64,
vcopy_lane_f32, vcopy_lane_f64, vcopy_lane_p8, vcopy_lane_p16,
vcopy_lane_p64, vcopy_lane_s8, vcopy_lane_s16, vcopy_lane_s32,
vcopy_lane_s64, vcopy_lane_u8, vcopy_lane_u16, vcopy_lane_u32,
vcopy_lane_u64, vcopy_laneq_f32, vcopy_laneq_f64,
vcopy_laneq_p8, vcopy_laneq_p16, vcopy_laneq_p64,
vcopy_laneq_s8, vcopy_laneq_s16, vcopy_laneq_s32,
vcopy_laneq_s64, vcopy_laneq_u8, vcopy_laneq_u16,
vcopy_laneq_u32, vcopy_laneq_u64, vcopyq_lane_f32,
vcopyq_lane_f64, vcopyq_lane_p8, vcopyq_lane_p16,
vcopyq_lane_p64, vcopyq_lane_s8, vcopyq_lane_s16,
vcopyq_lane_s32, vcopyq_lane_s64, vcopyq_lane_u8,
vcopyq_lane_u16, vcopyq_lane_u32, vcopyq_lane_u64,
vcopyq_laneq_f32, vcopyq_laneq_f64, vcopyq_laneq_p8,
vcopyq_laneq_p16, vcopyq_laneq_p64, vcopyq_laneq_s8,
vcopyq_laneq_s16, vcopyq_laneq_s32, vcopyq_laneq_s64,
vcopyq_laneq_u8, vcopyq_laneq_u16, vcopyq_laneq_u32,
vcopyq_laneq_u64, vdup_lane_f16, vdup_lane_f32, vdup_lane_f64,
vdup_lane_p8, vdup_lane_p16, vdup_lane_p64, vdup_lane_s8,
vdup_lane_s16, vdup_lane_s32, vdup_lane_s64, vdup_lane_u8,
vdup_lane_u16, vdup_lane_u32, vdup_lane_u64, vdup_laneq_f16,
vdup_laneq_f32, vdup_laneq_f64, vdup_laneq_p8, vdup_laneq_p16,
vdup_laneq_p64, vdup_laneq_s8, vdup_laneq_s16, vdup_laneq_s32,
vdup_laneq_s64, vdup_laneq_u8, vdup_laneq_u16, vdup_laneq_u32,
vdup_laneq_u64, vdupq_lane_f16, vdupq_lane_f32,
vdupq_lane_f64, vdupq_lane_p8, vdupq_lane_p16, vdupq_lane_p64,
vdupq_lane_s8, vdupq_lane_s16, vdupq_lane_s32, vdupq_lane_s64,
vdupq_lane_u8, vdupq_lane_u16, vdupq_lane_u32, vdupq_lane_u64,
vdupq_laneq_f16, vdupq_laneq_f32, vdupq_laneq_f64,
vdupq_laneq_p8, vdupq_laneq_p16, vdupq_laneq_p64,
vdupq_laneq_s8, vdupq_laneq_s16, vdupq_laneq_s32,
vdupq_laneq_s64, vdupq_laneq_u8, vdupq_laneq_u16,
vdupq_laneq_u32, vdupq_laneq_u64, vmulq_lane_f64,
vset_lane_bf16, vsetq_lane_bf16, vget_lane_bf16,
vgetq_lane_bf16, vdup_lane_bf16, vdup_laneq_bf16,
vdupq_lane_bf16, vdupq_laneq_bf16, vcopy_lane_bf16,
vcopyq_lane_bf16, vcopy_laneq_bf16, vcopyq_laneq_bf16): Delete
functions.
2026-06-30 Karl Meakin <karlwfmeakin@gmail.com>
* config/aarch64/aarch64-simd-builtins.def (combine): Delete
function declarations.
* config/aarch64/aarch64-simd-pragma-builtins.def (vcombine_mf8,
vcreate_mf8, vdup_n_mf8, vdupq_n_mf8, vmov_n_mf8,
vmovq_n_mf8,): Delete entries.
(aarch64_expand_pragma_builtin): Delete cases for
`UNSPEC_COMBINE` and `UNSPEC_VCREATE`.
(aarch64_fold_combine): Delete function.
(aarch64_gimple_fold_pragma_builtin): Delete cases for
`UNSPEC_COMBINE` and `UNSPEC_VCREATE`.
(aarch64_general_gimple_fold_builtin): Delete cases for
`vcombine`.
* config/aarch64/aarch64.md (UNSPEC_COMBINE): Delete unspec.
* config/aarch64/aarch64-builtins.cc
(aarch64_expand_pragma_builtin): Delete cases for
`UNSPEC_COMBINE` and `UNSPEC_VCREATE`.
(aarch64_fold_combine): Delete function.
(aarch64_gimple_fold_pragma_builtin): Delete cases for
`UNSPEC_COMBINE` and `UNSPEC_VCREATE`.
(aarch64_general_gimple_fold_builtin): Delete cases for
`combine`.
* config/aarch64/aarch64-acle-builtins.cc
(gimple_folder::force_val, gimple_folder::assign): New
functions.
* config/aarch64/aarch64-acle-builtins.h (TYPES_all_neon,
TYPES_bhsd_neon): New type lists.
* config/aarch64/aarch64-neon-builtins-base.def (vcreate,
vcombine, vdup_n, vdupq_n, vmov_n, vmovq_n): New function groups.
* config/aarch64/aarch64-neon-builtins-base.cc (build_vec_dup): New function.
(struct gimple_create, struct gimple_combine, struct struct
gimple_dup): New structs.
(vcreate, vcombine, vdup_n, vdupq_n, vmov_n, vmovq_n): New
function bases.
* config/aarch64/arm_neon.h (vcreate_s8, vcreate_s16,
vcreate_s32, vcreate_s64, vcreate_f16, vcreate_f32,
vcreate_u8, vcreate_u16, vcreate_u32, vcreate_u64,
vcreate_f64, vcreate_p8, vcreate_p16, vcreate_p64,
vcombine_s8, vcombine_s16, vcombine_s32, vcombine_s64,
vcombine_f16, vcombine_f32, vcombine_u8, vcombine_u16,
vcombine_u32, vcombine_u64, vcombine_f64, vcombine_p8,
vcombine_p16, vcombine_p64, vdup_n_f16, vdup_n_f32,
vdup_n_f64, vdup_n_p8, vdup_n_p16, vdup_n_p64, vdup_n_s8,
vdup_n_s16, vdup_n_s32, vdup_n_s64, vdup_n_u8, vdup_n_u16,
vdup_n_u32, vdup_n_u64, vdupq_n_f16, vdupq_n_f32, vdupq_n_f64,
vdupq_n_p8, vdupq_n_p16, vdupq_n_p64, vdupq_n_s8, vdupq_n_s16,
vdupq_n_s32, vdupq_n_s64, vdupq_n_u8, vdupq_n_u16,
vdupq_n_u32, vdupq_n_u64, vmov_n_f16, vmov_n_f32, vmov_n_f64,
vmov_n_p8, vmov_n_p16, vmov_n_p64, vmov_n_s8, vmov_n_s16,
vmov_n_s32, vmov_n_s64, vmov_n_u8, vmov_n_u16, vmov_n_u32,
vmov_n_u64, vmovq_n_f16, vmovq_n_f32, vmovq_n_f64, vmovq_n_p8,
vmovq_n_p16, vmovq_n_p64, vmovq_n_s8, vmovq_n_s16,
vmovq_n_s32, vmovq_n_s64, vmovq_n_u8, vmovq_n_u16,
vmovq_n_u32, vmovq_n_u64, vcreate_bf16, vcombine_bf16,
vdup_n_bf16, vdupq_n_bf16): Delete functions.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config/aarch64/aarch64-neon-builtins-base.cc: New file.
* config/aarch64/aarch64-neon-builtins-base.def: New file.
* config/aarch64/aarch64-neon-builtins-base.h: New file.
* config/aarch64/aarch64-neon-builtins-functions.h: New file.
* config/aarch64/aarch64-neon-builtins-shapes.cc: New file.
* config/aarch64/aarch64-neon-builtins-shapes.h: New file.
* config/aarch64/aarch64-neon-builtins.def: New file.
* config.gcc (extra_headers, extra_objs): Add new files and
reformat for readability.
* config/aarch64/t-aarch64: Add recipes for new files.
* config/aarch64/aarch64-protos.h (handle_arm_neon_h): Rename to
`init_arm_neon_builtins`.
* config/aarch64/aarch64-builtins.cc (handle_arm_neon_h): Likewise.
* config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64): Call
`aarch64_acle::handle_arm_neon_h`.
* config/aarch64/aarch64-acle-builtins.cc (TYPES_*): Move to
aarch64-acle-builtins.h
(NONSTREAMING_SVE, SVE_AND_SME, SSVE): Likewise.
(neon_function_groups): New variable.
(arm_neon_h_handled): Likewise.
(handle_arm_neon_h): New function.
* config/aarch64/aarch64-sve-builtins-shapes.cc:
(gimple_folder::fold): Allow folding if `TARGET_SVE` is
false but `TARGET_SIMD` is true.
* config/aarch64/aarch64-sve-builtins.def (p8, p16, p64, 128):
New type suffixes.
* config/aarch64/aarch64-acle-builtins.h (enum
handle_pragma_index): New enum member `arm_neon_handle`.
(enum type_class_index): New enum member `TYPE_poly`.
(TYPES_*): Moved from `aarch64-acle-builtins.cc`.
(NONSTREAMING_SVE, SVE_AND_SME, SSVE): Likewise.
* config/aarch64/arm_neon.h (vadd_s8, vadd_s16, vadd_s32,
vadd_f32, vadd_f64, vadd_u8, vadd_u16, vadd_u32, vadd_s64,
vadd_u64, vaddq_s8, vaddq_s16, vaddq_s32, vaddq_s64,
vaddq_f32, vaddq_f64, vaddq_u8, vaddq_u16, vaddq_u32,
vaddq_u64, vadd_f16, vaddq_f16, vadd_p8, vadd_p16, vadd_p64,
vaddq_p8, vaddq_p16, vaddq_p64, vaddq_p128, vaddd_u64,
vaddd_s64): Delete function definitions.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config.gcc (target_gtfiles): Rename
`aarch64-sve-builtins.{h,cc}` to
`aarch64-acle-builtins.{h,cc}`.
* config/aarch64/t-aarch64: Likewise.
* config/aarch64/aarch64-sve-builtins.h: Move to...
* config/aarch64/aarch64-acle-builtins.h: ...here.
* config/aarch64/aarch64-sve-builtins.cc: Move to...
* config/aarch64/aarch64-acle-builtins.cc: ...here.
* config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64): Rename
namespace `aarch64_sve` to `aarch64_acle`.
(aarch64_resolve_overloaded_builtin): Likewise.
(aarch64_check_builtin_call): Likewise.
* config/aarch64/aarch64-protos.h: Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-base.h: Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h: Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-sme.h: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h: Likewise.
* config/aarch64/aarch64.cc: Likewise.
2026-06-30 Karl Meakin <karl.meakin@arm.com>
* config.gcc: Reformat lists over several lines.
2026-06-30 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (synthesize_ior_xor): If we must synthesize a
constant and Zbb is enabled, try both C and ~C to see which is cheaper.
(synthesize_and): Likewise.
2026-06-30 Jim Lin <jim@andestech.com>
PR target/125853
* common/config/riscv/riscv-common.cc (riscv_multi_lib_info_t::parse):
Remove the path parameter and compare multi_lib_info->path against
"." instead.
(riscv_compute_multilib): Update caller.
2026-06-30 Jim Tsung-Chun Lin <jim@andestech.com>
Backported from master:
2026-06-15 Jim Tsung-Chun Lin <jim@andestech.com>
* common/config/riscv/riscv-common.cc (riscv_select_multilib):
Don't set riscv_no_matched_multi_lib here; let the caller own
the flag.
(riscv_compute_multilib): Drop the early return that accepted
the generic-matched multilib_dir; always run the smart matcher
and set riscv_no_matched_multi_lib when it finds no candidate.
2026-06-30 Mark Zhuang <zhuangqiubin@linux.spacemit.com>
* config/riscv/riscv-ext-spacemit.def (xsmtvdotii): New extension.
* config/riscv/riscv-ext.opt: Regenerate.
* config/riscv/riscv-cores.def (RISCV_TUNE): Add spacemit-a100.
(RISCV_CORE): Add spacemit-a100.
* doc/riscv-ext.texi: Regenerate.
* doc/riscv-mcpu.texi: Regenerate.
* doc/riscv-mtune.texi: Regenerate.
2026-06-30 Richard Biener <rguenther@suse.de>
* tree-ssa-alias.h (pt_solution::vars_contains_auto): New.
(ptr_deref_may_alias_auto_p): Declare.
(pt_solution_includes_auto): Likewise.
* tree-ssa-structalias.cc (set_uids_in_ptset): Record auto
variables.
(pt_solution_includes_auto): New function.
(ipa_escaped_pt): Adjust.
* tree-ssa-alias.cc (ptr_deref_may_alias_auto_p): New function.
2026-06-30 Christopher Bazley <chris.bazley@arm.com>
Richard Sandiford <rdsandiford@googlemail.com>
* tree.cc (build_vector_from_ctor): Rename variables and
refactor assignments.
2026-06-30 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-ivopts.cc (rewrite_use_address): Always
avoid TARGET_MEM_REF with a base of zero.
* tree-ssa-sccvn.cc (vn_reference_maybe_forwprop_address): Do
not forward TARGET_MEM_REF addresses.
2026-06-30 Alfie Richards <alfie.richards@arm.com>
PR target/125838
* config/aarch64/aarch64.cc (aarch64_fntype_abi): Fall back to
AAPCS for preserve_none variadic calls.
2026-06-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/126032
* gimple-ssa-warn-access.cc (maybe_warn_for_bound): Fixup
diagnostic string.
2026-06-30 Chung-Lin Tang <cltang@baylibre.com>
* gimplify.cc (enum gimplify_omp_var_data):
Add GOVD_USES_ALLOCATORS_ALLOCATOR.
(gimplify_bind_expr): Diagnose missing uses_allocators clause.
(omp_get_attachment): Add GOMP_MAP_USES_ALLOCATORS cases.
(omp_group_base): Likewise.
(gimplify_scan_omp_clauses): Handle uses_allocators.
(gimplify_adjust_omp_clauses_1): Handle GOVD_USES_ALLOCATORS_ALLOCATOR.
* omp-low.cc (scan_sharing_clauses): Check if ALLOCATE clause in target
region has containing USES_ALLOCATORS clause.
Add OMP_CLAUSE_USES_ALLOCATORS cases.
(lower_omp_target): Add OMP_CLAUSE_USES_ALLOCATORS cases.
* tree-pretty-print.cc (dump_omp_clause): Handle GOMP_MAP_USES_ALLOCATORS.
2026-06-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/126008
* tree-ssa-loop-ivopts.cc (alloc_iv): Revert last change.
* tree-ssa-address.cc (add_to_parts): Use unsigned arithmetic
to accumulate to base.
2026-06-30 Christopher Bazley <chris.bazley@arm.com>
Richard Sandiford <rdsandiford@googlemail.com>
* poly-int.h (can_div_away_from_zero_p):
Exit early if |a| <= |b| instead of calling
can_div_trunc_p and returning false if it
returned false.
2026-06-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/126034
* tree-vect-stmts.cc (vectorizable_load): Elide dead else if.
2026-06-30 Jakub Jelinek <jakub@redhat.com>
PR target/126030
* config/i386/sse.md (avx512vl_<code><mode>v4hi2_mask_store_1):
Use a single output pattern instead of conditionally returning
the same string based on a condition.
2026-06-30 Jakub Jelinek <jakub@redhat.com>
PR c++/125837
* doc/invoke.texi (Wc++29-extensions): Document.
2026-06-30 Avinash Jayakar <avinashd@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add logic to
handle __builtin_ppc_atomic_cas_local.
* config/rs6000/rs6000-builtins.def: New builtins for
__builtin_ppc_atomic_cas_local with types.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Handle
builtins with up to 6 arguments.
* config/rs6000/rs6000-overload.def: Overload builtin for signed/unsiged
char, short, int, long, __int128.
* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap): Add
additional parameter 'local' to the prototype.
* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass new
parameter to generate load-locked instruction.
(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
emit_load_locked() with additional parameter value of EH bit.
(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL template.
Specify EH bit in the larx instruction.
(load_locked<QHI:mode>_si): Likewise.
(load_lockedpti): Likewise.
(load_lockedti): Add new operand in RTL template. Pass EH bit to
gen_load_lockedpti().
(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
rs6000_expand_atomic_compare_and_swap.
(atomic_compare_and_swap_local<mode>): New define_expand.
* doc/extend.texi: Add documentation for new builtin.
2026-06-30 Avinash Jayakar <avinashd@linux.ibm.com>
Revert:
2026-06-30 Avinash Jayakar <avinashd@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add logic to
handle __builtin_ppc_atomic_cas_local.
* config/rs6000/rs6000-builtins.def: New builtins for
__builtin_ppc_atomic_cas_local with types.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Handle
builtins with up to 6 arguments.
* config/rs6000/rs6000-overload.def: Overload builtin for signed/unsiged
char, short, int, long, __int128.
* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap): Add
additional parameter 'local' to the prototype.
* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass new
parameter to generate load-locked instruction.
(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
emit_load_locked() with additional parameter value of EH bit.
(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL template.
Specify EH bit in the larx instruction.
(load_locked<QHI:mode>_si): Likewise.
(load_lockedpti): Likewise.
(load_lockedti): Add new operand in RTL template. Pass EH bit to
gen_load_lockedpti().
(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
rs6000_expand_atomic_compare_and_swap.
(atomic_compare_and_swap_local<mode>): New define_expand.
* doc/extend.texi: Add documentation for new builtin.
2026-06-30 Avinash Jayakar <avinashd@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add logic to
handle __builtin_ppc_atomic_cas_local.
* config/rs6000/rs6000-builtins.def: New builtins for
__builtin_ppc_atomic_cas_local with types.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Handle
builtins with up to 6 arguments.
* config/rs6000/rs6000-overload.def: Overload builtin for signed/unsiged
char, short, int, long, __int128.
* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap): Add
additional parameter 'local' to the prototype.
* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass new
parameter to generate load-locked instruction.
(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
emit_load_locked() with additional parameter value of EH bit.
(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL template.
Specify EH bit in the larx instruction.
(load_locked<QHI:mode>_si): Likewise.
(load_lockedpti): Likewise.
(load_lockedti): Add new operand in RTL template. Pass EH bit to
gen_load_lockedpti().
(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
rs6000_expand_atomic_compare_and_swap.
(atomic_compare_and_swap_local<mode>): New define_expand.
* doc/extend.texi: Add documentation for new builtin.
2026-06-30 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md
(@stack_protect_combined_set_normal_<mode>): Replace `st.d'
with `st.<d>', reject stptr.d on LA32 with enabled attribute.
(@stack_protect_combined_test_internal_<mode>): Replace `ld.d'
with `ld.<d>', reject ldptr.d on LA32 with enabled attribute.
(@stack_protect_combined_set_extreme_<mode>): Rename to ...
(stack_protect_combined_set_extreme): ... here. Force DImode.
Add TARGET_ABI_LP64 as the condition.
(stack_protect_combined_set): Adapt for the change of
stack_protect_combined_set_extreme.
2026-06-30 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/125994
* config/riscv/riscv.cc (riscv_support_vector_misalignment):
Handle scalar modes.
2026-06-29 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (synthesize_and): Use srliw to handle
clearing both upper and lower bits in some cases.
* config/riscv/bitmanip.md (ZBA splitter using sext.w): Do not
use in cases where we can use srliw to clear those upper bits.
2026-06-29 Mark Zhuang <zhuangqiubin@linux.spacemit.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Add spacemit-x100.
(RISCV_CORE): Add spacemit-x100.
* config/riscv/riscv.cc (spacemit_x100_tune_info): New.
* doc/riscv-mcpu.texi: Regenerate.
* doc/riscv-mtune.texi: Regenerate.
2026-06-29 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/mips.h (ASM_SPEC): Add placeholders for -mmxu and
-mno-mxu.
* config/mips/mips.opt: New undocumented target option.
2026-06-29 Matthew Fortune <matthew.fortune@imgtec.com>
* config/mips/mips.cc (mips_frame_barrier): Upgrade to a full
blockage.
2026-06-29 Roger Sayle <roger@nextmovesoftware.com>
PR target/94871
* simplify-rtx.cc (simplify_unary_operation_1) <case NOT>:
Update (not (eq X Y)) -> (ne X Y) to support vector comparions
using VECTOR_STORE_FLAG_VALUE, and check SCALAR_INT_MODE_P
when checking STORE_FLAG_VALUE. Add equivalent optimization
(not (neg (eq X Y))) -> (neg (ne X Y)) for targets with
STORE_FLAG_VALUE == 1 or VECTOR_STORE_FLAG_VALUE is const1_rtx.
* config/i386/sse.md (*<sse>_imaskcmp<mode>3_comm): Clone
of *<sse>_maskcmp<mode>3_comm pattern with integer vector
result.
2026-06-29 Abhishek Kaushik <abhishek.kaushik@arm.com>
* config/aarch64/aarch64-sve2.md: Add unpredicated high-part
multiplication section.
(@aarch64_sve2_<optab><mode>): New insn.
* config/aarch64/aarch64-sve.md (@aarch64_pred_<optab><mode>):
Change to define_insn_and_split and split SVE2 highpart
multiplication into unpredicated MUL_HIGHPART.
2026-06-29 Jakub Jelinek <jakub@redhat.com>
PR target/125469
* config/i386/i386.md (*add<mode>_1<nf_name>): Revert 2026-05-28
changes.
(define_split from *add<mode>_1_nf to *lea<mode>): Set INSN_CODE
to -1 if <LEAMODE> and <MODE> are the same.
2026-06-29 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/105116
* lra-constraints.cc (simplify_operand_subreg): Reload a
non-representable narrowing subreg of a hard register through
memory instead of resolving it lossily.
2026-06-29 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/125737
* match.pd: Optimize X % Y < Y -> Y >= 0 and X % Y >= Y -> Y < 0
2026-06-29 H.J. Lu <hjl.tools@gmail.com>
PR target/125968
* config/i386/i386-expand.cc (ix86_expand_movmem): Don't call
ix86_expand_n_overlapping_move_movmem when max size == 1.
2026-06-29 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR tree-optimization/112390
* match.pd: Add simplifications for combined sign-bit and
magnitude checks:
((signed)A >= 0) &/&& ((A & INT_MAX) != 0) -> (signed)A > 0
((signed)A < 0) |/|| ((A & INT_MAX) == 0) -> (signed)A <= 0
2026-06-29 liuhongt <hongtao.liu@intel.com>
PR target/125907
* config/i386/i386.md (*cmov_bt<SWI248:mode>): New
define_insn_and_split handling a const_int false arm, forced into
a register by the splitter. Leave the existing define_split for
the nonimmediate case unchanged.
2026-06-29 Xi Ruoyao <xry111@xry111.site>
PR target/125474
* config/loongarch/simd.md (usdot_prod<wvec_half><mode>): New
define_expand.
(usdot_prod<wvec_quarter><mode>): New define_expand.
2026-06-29 Pan Li <pan2.li@intel.com>
* match-sat-alu.pd: Add pattern for unsigned scalar
SAT_MUL form 14.
2026-06-29 Pietro Monteiro <pietro@sociotechnical.xyz>
PR bootstrap/103459
* acinclude.m4: Replace AC_FOREACH with m4_foreach_w. Replace
AC_TRY_LINK with AC_LINK_IFELSE.
* configure: Regenerate.
* configure.ac: Replace AC_HELP_STRING with AS_HELP_STRING. Replace
AC_PROG_LIBTOOL with LT_INIT.
2026-06-28 Kevin Stefanov <kevinstefanov15@gmail.com>
PR middle-end/125274
* ctfc.h (ctf_dtdef): Likewise.
* dwarf2out.cc (die_struct): Likewise.
* dwarf2out.h (dw_cfa_location): Likewise.
* gengtype-lex.l (IWORD): Remove BOOL_BITFIELD.
* gimple-walk.h (walk_stmt_info): Replace BOOL_BITFIELD with bool.
* opts.h (cl_option): Likewise.
* config/i386/i386.h (machine_frame_state): Likewise.
(machine_function): Likewise.
* sched-int.h (deps_desc): Likewise.
* sel-sched-ir.h (_expr): Likewise.
(_fence): Likewise.
(transformed_insns): Likewise.
(_sel_insn_data): Likewise.
* sel-sched.cc (cmpd_local_params): Likewise.
* system.h: Remove #define for BOOL_BITFIELD.
2026-06-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/115571
* match.pd (`(float)(a CMP b)`): New pattern.
2026-06-28 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/125749
PR tree-optimization/125749
* match.pd: Use tree_expr_nonnegative_p for MAX (A, B) (==,!=) 0 ->
(A|B) (==,!=) 0.
2026-06-27 Jakub Jelinek <jakub@redhat.com>
PR target/125992
* config/s390/s390.md (*brx_stage1_<GPR:mode>): Add CC_REGNUM clobber.
2026-06-27 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/125385
* match.pd ((FTYPE) N CMP (FTYPE) M): Use range information
to decide whether integer operands are exactly representable.
((FTYPE) N CMP CST): Likewise.
* real.cc: Include backend.h and vr-values.h.
(format_helper::can_represent_range_value_p): New function.
* real.h (format_helper::can_represent_range_value_p): Declare.
* tree-core.h (class irange): Forward declare.
2026-06-26 H.J. Lu <hjl.tools@gmail.com>
PR middle-end/125977
* expr.cc (emit_block_move_via_pattern): Replace ops[6].value
in assert with GEN_INT (min_size).
2026-06-26 H.J. Lu <hjl.tools@gmail.com>
Hongtao Liu <hongtao.liu@intel.com>
PR target/125856
PR target/125865
* config/i386/i386-expand.cc (ix86_expand_set_or_cpymem):
Call ix86_expand_set_or_movmem for
TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES.
(ix86_expand_memset_val): New.
(ix86_expand_n_move_movmem): Renamed to ...
(ix86_expand_n_move_set_or_movmem): This. Add a pointer to rtx
argument for memset. Also expand memset.
(ix86_expand_n_overlapping_move_movmem): Renamed to ...
(ix86_expand_n_overlapping_move_set_or_movmem): This. Add a
pointer to rtx argument for memset. Also expand memset.
(ix86_expand_less_move_movmem): Renamed to ...
(ix86_expand_less_move_set_or_movmem): This. Add a pointer to
rtx argument for memset. Also expand memset.
(ix86_expand_movmem): Renamed to ...
(ix86_expand_set_or_movmem): This. Add bool arguments for memcpy
and memset. Also expand memcpy and memset.
* config/i386/i386-protos.h (ix86_expand_movmem): Renamed to ...
(ix86_expand_set_or_movmem): This. Add bool arguments for memcpy
and memset.
* config/i386/i386.md (movmem<mode>): Replace ix86_expand_movmem
with ix86_expand_set_or_movmem.
2026-06-26 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
PR target/123238
* config/i386/i386-expand.cc: Delay calling force_reg on
op_true and op_false. Generate an AND then XOR sequence
if op_true and op_false are both CONST_VECTOR_P.
* config/i386/mmx.md (vcond_mask_<mode>v4hi): Allow operands
1 and 2 to be vector_or_const_vector_operand.
(vcond_mask_<mode>v2hi): Likewise.
(vcond_mask_<mode><mmxintvecmodelower>): Likewise.
(vcond_mask_<mode><mode>): Likewise.
* config/i386/sse.md (vcond_mask_<mode><sseintvecmodelower>):
Likewise.
(vcond_mask_<mode><sseintvecmodelower>): Likewise.
(vcond_mask_v1tiv1ti): Likewise.
(vcond_mask_<mode><sseintvecmodelower>): Likewise.
(vcond_mask_<mode><sseintvecmodelower>): Likewise.
* config/i386/predicates.md (vector_or_0_or_1s_operand): Delete
predicate with no remaining uses.
2026-06-26 vekumar <Venkataramanan.Kumar@amd.com>
PR target/125949
* config/i386/i386.md ("isa"): Add avxvnniint8.
("enabled"): Adjust for avxvnniint8.
* config/i386/sse.md (vpdp<vpdotprodtype>_<mode>): Adjust for
AVXVNNIINT8.
2026-06-26 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/125972
* config/s390/s390.cc (s390_rtx_costs): Deal with non-compare
conditions during costing. Also fix some indentation.
2026-06-26 Richard Biener <rguenther@suse.de>
PR middle-end/125875
* match.pd: When checking for !can_vec_perm_const_p also
allow variable permutes and use the vec_perm_indices CTOR
with the original tree operands.
2026-06-26 Richard Biener <rguenther@suse.de>
* vec-perm-indices.h (vec_perm_indices::new_vector): New overload.
(vec_perm_indices::input_bitwise_zero_p): New method.
(vec_perm_indices::m_input0_bitwise_zero_p,
vec_perm_indices::m_input1_bitwise_zero_p): New members.
(vec_perm_indices::vec_perm_indices): Adjust.
(tree_to_vec_perm_indices): Declare.
* vec-perm-indices.cc (vec_perm_indices::new_vector): New overload.
(vec_perm_indices::new_expanded_vector): Adjust.
(tree_to_vec_perm_indices): New function.
* optabs-query.cc (can_vec_perm_const_p): Handle permute
patterns mapping to vec_shl/vec_shr.
* tree-vect-generic.cc (lower_vec_perm): Move vec_shl/vec_shr
detection to can_vec_perm_const_p and simplify.
2026-06-26 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125979
* dbgcnt.def: Add ranger_cnt.
* gimple-range.cc (gimple_ranger::range_of_expr): Add debug_cnt.
(gimple_ranger::range_on_entry): Likewise.
(gimple_ranger::range_on_exit): Likewise.
(gimple_ranger::range_on_edge); Likewise.
(gimple_ranger::range_of_stmt): Likewise
(dom_ranger::range_of_expr): Likewise.
(dom_ranger::range_on_edge): Likewise.
(dom_ranger::range_of_stmt): Likewise.
2026-06-26 H.J. Lu <hjl.tools@gmail.com>
PR middle-end/125977
* builtins.cc (determine_block_size): Change len_rtx to reference
and set it to min size if min size == max size.
* expr.cc (emit_block_move_via_pattern): Assert count == min_size
if min_size == max_size.
(set_storage_via_setmem): Likewise.
2026-06-26 Pengfei Li <Pengfei.Li2@arm.com>
* config/aarch64/aarch64.cc
(aarch64_sched_first_cycle_multipass_dfa_lookahead): Return 0
when dispatch scheduling is enabled.
2026-06-26 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_cv_as_ix86_quad): Remove.
* configure: Regenerate.
* config.in: Likewise.
* config/i386/sol2.h [!HAVE_AS_IX86_QUAD] (ASM_QUAD): Don't undefine.
2026-06-26 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_cv_as_ix86_diff_sect_delta): Remove.
* configure: Regenerate.
* config.in: Likewise.
* config/i386/sol2.h [!HAVE_AS_IX86_DIFF_SECT_DELTA]
(ASM_PREFERRED_EH_DATA_FORMAT): Remove.
(JUMP_TABLES_IN_TEXT_SECTION): Likewise.
(ASM_OUTPUT_DWARF_PCREL): Likewise.
2026-06-26 Jiahao Xu <xujiahao@loongson.cn>
* config/loongarch/loongarch.cc (loongarch_sched_reassociation_width):
Get a tree_code instead of unsigned int.
2026-06-25 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.md (seq_sne_qi): Mark name for debugging purposes
only.
2026-06-25 Peter Bergner <bergner@tenstorrent.com>
PR target/87466
* config/riscv/riscv.cc (TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P):
Define.
2026-06-25 Manjunath Matti <mmatti@linux.ibm.com>
* config/rs6000/predicates.md (const_0_to_6_operand): New predicate.
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmulmul): Add new
builtin definitions under [future] stanza.
(__builtin_vsx_xxmulmulhiadd): Likewise.
(__builtin_vsx_xxmulmulloadd): Likewise.
(__builtin_vsx_xxssumudm): Likewise.
(__builtin_vsx_xxssumudmc): Likewise.
(__builtin_vsx_xxssumudmcext): Likewise.
(__builtin_vsx_xsaddadduqm): Likewise.
(__builtin_vsx_xsaddaddsuqm): Likewise.
(__builtin_vsx_xsaddsubuqm): Likewise.
(__builtin_vsx_xsaddsubsuqm): Likewise.
(__builtin_vsx_xsmerge2t1uqm): Likewise.
(__builtin_vsx_xsmerge2t2uqm): Likewise.
(__builtin_vsx_xsmerge2t3uqm): Likewise.
(__builtin_vsx_xsmerge3t1uqm): Likewise.
(__builtin_vsx_xsrebase2t1uqm): Likewise.
(__builtin_vsx_xsrebase2t2uqm): Likewise.
(__builtin_vsx_xsrebase2t3uqm): Likewise.
(__builtin_vsx_xsrebase2t4uqm): Likewise.
(__builtin_vsx_xsrebase3t1uqm): Likewise.
(__builtin_vsx_xsrebase3t2uqm): Likewise.
(__builtin_vsx_xsrebase3t3uqm): Likewise.
* config/rs6000/vsx.md (UNSPEC_XXMULMUL): Add UNSPEC entry.
(UNSPEC_XXMULMULHIADD): Likewise.
(UNSPEC_XXMULMULLOADD): Likewise.
(UNSPEC_XXSSUMUDM): Likewise.
(UNSPEC_XXSSUMUDMC): Likewise.
(UNSPEC_XXSSUMUDMCEXT): Likewise.
(UNSPEC_XSADDADDUQM): Likewise.
(UNSPEC_XSADDADDSUQM): Likewise.
(UNSPEC_XSADDSUBUQM): Likewise.
(UNSPEC_XSADDSUBSUQM): Likewise.
(UNSPEC_XSMERGE2T1UQM): Likewise.
(UNSPEC_XSMERGE2T2UQM): Likewise.
(UNSPEC_XSMERGE2T3UQM): Likewise.
(UNSPEC_XSMERGE3T1UQM): Likewise.
(UNSPEC_XSREBASE2T1UQM): Likewise.
(UNSPEC_XSREBASE2T2UQM): Likewise.
(UNSPEC_XSREBASE2T3UQM): Likewise.
(UNSPEC_XSREBASE2T4UQM): Likewise.
(UNSPEC_XSREBASE3T1UQM): Likewise.
(UNSPEC_XSREBASE3T2UQM): Likewise.
(UNSPEC_XSREBASE3T3UQM): Likewise.
(vsx_xxmulmul): New define_insn.
(vsx_xxmulmulhiadd): Likewise.
(vsx_xxmulmulloadd): Likewise.
(vsx_xxssumudm): Likewise.
(vsx_xxssumudmc): Likewise.
(vsx_xxssumudmcext): Likewise.
(vsx_xsaddadduqm): Likewise.
(vsx_xsaddaddsuqm): Likewise.
(vsx_xsaddsubuqm): Likewise.
(vsx_xsaddsubsuqm): Likewise.
(vsx_xsmerge2t1uqm): Likewise.
(vsx_xsmerge2t2uqm): Likewise.
(vsx_xsmerge2t3uqm): Likewise.
(vsx_xsmerge3t1uqm): Likewise.
(vsx_xsrebase2t1uqm): Likewise.
(vsx_xsrebase2t2uqm): Likewise.
(vsx_xsrebase2t3uqm): Likewise.
(vsx_xsrebase2t4uqm): Likewise.
(vsx_xsrebase3t1uqm): Likewise.
(vsx_xsrebase3t2uqm): Likewise.
(vsx_xsrebase3t3uqm): Likewise.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add
documentation for ECC cryptography builtins available on
future ISA.
2026-06-25 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123884
PR target/106585
* config/riscv/bitmanip.md: Add new splits for single bit manipulation
cases followed by a sign extension.
2026-06-25 Jeff Law <jeffrey.law@oss.qualcomm.com>
Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR target/124019
* config/riscv/riscv.md (seq_sne_qi): New define_insn_and_split.
2026-06-25 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR tree-optimization/102793
* tree-ssa-ifcombine.cc (bb_guards_loop_p): New function.
(ifcombine_ifandif): Use it to avoid combining the conditions
guarding a loop.
* tree-ssa-tail-merge.cc: Include tree-ssa-ifcombine.h and
tree-ssa.h.
(ifcombine_candidate_bbs): New static bitmap.
(apply_clusters): Collect the merged block's predecessors as
ifcombine candidates.
(tail_merge_optimize): Run tree_ssa_ifcombine_bb on the candidates;
return TODO_cleanup_cfg when it changed the CFG.
2026-06-25 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* gimple-predicate-analysis.cc (get_pred_info_from_cond_edge):
New function.
(predicate::init_from_control_deps): Use it.
(predicate::drop_conjuncts_implied_by): New method.
(uninit_analysis::is_use_guarded): Retry the superset test
after relaxing the definition predicate by the maybe-undef
edge conditions.
* gimple-predicate-analysis.h (class predicate): Declare
drop_conjuncts_implied_by.
2026-06-25 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* tree-ssa-ifcombine.cc: Include tree-ssa-ifcombine.h.
(recognize_if_then_else): Removed 'static'.
(tree_ssa_ifcombine_bb): Removed 'static'.
* tree-ssa-ifcombine.h: New file.
2026-06-25 Richard Biener <rguenther@suse.de>
PR middle-end/125977
* cfgexpand.cc (pass_expand::execute): Guard ranger use
on optimize.
2026-06-25 Artemiy Volkov <artemiy.volkov@arm.com>
PR target/125716
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Add
(?w,r) alternative for VSUB64 types.
2026-06-25 Xi Ruoyao <xry111@xry111.site>
Revert:
2026-06-25 Xi Ruoyao <xry111@xry111.site>
PR target/125077
* config/mips/predicates.md (ssp_gp_operand): New
define_predicate.
(ssp_operand): New define_predicate.
(ssp_normal_operand): New define_predicate.
* config/mips/constraints.md (ZA): New define_constraint.
(ZB): New define_constraint.
* config/mips/mips.md (UNSPEC_SSP): New unspec.
(UNSPEC_SSP_GP): New unspec.
(cbranch<mode>4): Add '@' to generate the helper function taking
mode as a parameter.
(@stack_protect_combined_set_normal_<mode>): New define_insn.
(stack_protect_combined_set_abs64): New define_insn.
(@stack_protect_combined_test_internal_<mode>): New define_insn.
(stack_protect_combined_set): New define_expand.
(stack_protect_combined_test): New define_expand.
* config/mips/mips-protos.h (mips_canary_expose_gp_use):
Declare.
(mips_output_asm_load_canary): Declare.
* config/mips/mips.cc (mips_small_data_pattern_1): Don't rewrite
GP-relative symbol wrapped in UNSPEC_SSP_GP.
(mips_canary_expose_gp_use): Implement.
(mips_output_asm_load_canary): Implement.
(mips_print_operand): Allow 'w' to print d/w for DImode/SImode.
2026-06-25 Xi Ruoyao <xry111@xry111.site>
PR target/125628
* config/mips/sync.md (sync_old_<optab><mode>): Fix
uninitialized operand use.
(sync_new_<optab><mode>): Fix uninitialized operand use, use the
same expression for the set source of operand 0 and 1.
2026-06-25 Xi Ruoyao <xry111@xry111.site>
PR target/125077
* config/mips/predicates.md (ssp_gp_operand): New
define_predicate.
(ssp_operand): New define_predicate.
(ssp_normal_operand): New define_predicate.
* config/mips/constraints.md (ZA): New define_constraint.
(ZB): New define_constraint.
* config/mips/mips.md (UNSPEC_SSP): New unspec.
(UNSPEC_SSP_GP): New unspec.
(cbranch<mode>4): Add '@' to generate the helper function taking
mode as a parameter.
(@stack_protect_combined_set_normal_<mode>): New define_insn.
(stack_protect_combined_set_abs64): New define_insn.
(@stack_protect_combined_test_internal_<mode>): New define_insn.
(stack_protect_combined_set): New define_expand.
(stack_protect_combined_test): New define_expand.
* config/mips/mips-protos.h (mips_canary_expose_gp_use):
Declare.
(mips_output_asm_load_canary): Declare.
* config/mips/mips.cc (mips_small_data_pattern_1): Don't rewrite
GP-relative symbol wrapped in UNSPEC_SSP_GP.
(mips_canary_expose_gp_use): Implement.
(mips_output_asm_load_canary): Implement.
(mips_print_operand): Allow 'w' to print d/w for DImode/SImode.
2026-06-25 Richard Biener <rguenther@suse.de>
* target.def (reassociation_width): Use default_reassociation_width.
* targhooks.h (default_reassociation_width): Declare.
* targhooks.cc (default_reassociation_width): Define.
2026-06-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/125953
* gimple-range.cc (gimple_ranger::range_of_expr): Document.
Fall back to global ranges if 'stmt' is not in the IL.
2026-06-25 Richard Biener <rguenther@suse.de>
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Pass
the division stmt as context for the range query on op0.
Use the active ranger.
2026-06-25 Richard Biener <rguenther@suse.de>
* coretypes.h (enum tree_code): Declare.
* tree-core.h (enum tree_code): Adjust.
* target.def (reassociation_width): Get a tree_code instead
of unsigned int.
* doc/tm.texi: Regenerate.
* genmatch.cc (enum tree_code): Adjust.
* gimple-loop-versioning.cc (address_info_hasher::hash): Likewise.
* config/aarch64/aarch64.cc (aarch64_reassociation_width):
Likewise.
* config/loongarch/loongarch.cc
(loongarch_cpu_sched_reassociation_width): Likewise.
* config/mips/mips.cc (mips_sched_reassociation_width): Likewise.
* config/rs6000/rs6000.cc (rs6000_reassociation_width): Likewise.
* config/i386/i386.cc (ix86_reassociation_width): Likewise
and fix bogus compares.
2026-06-25 Martin Uecker <uecker@tugraz.at>
* doc/extend.texi (Constructing Calls): Document
__builtin_call_static_chain and __builtin_call_code_address
and update __builtin_call_with_static_chain.
(Nested Functions): Update.
2026-06-25 Martin Uecker <uecker@tugraz.at>
* builtins.def (BUILT_IN_CALL_CODE_ADDRESS,
BUILT_IN_CALL_STATIC_CHAIN): New.
* builtins.cc (expand_builtin): Emit errors for invalid uses.
(is_simple_builtin): Add new built-in functions.
* gimple-fold.cc (gimple_fold_builtin_call_info): New function.
(gimple_fold_builtin): Expand new built-ins for non-nested functions.
* tree-nested.cc (convert_tramp_reference_stmt): Ingore new built-ins.
(convert_gimple_call): Expand built-ins for nested functions.
* tree-inline.cc (initialize_inlined_parameters): Set a missing
static chain to NULL.
2026-06-25 Jan Beulich <jbeulich@suse.com>
* config/riscv/arch-canonicalize: Avoid f"..." strings.
2026-06-24 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
* config/i386/prfchwintrin.h (_m_prefetchw): Take
volatile const void * instead of void *.
2026-06-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125910
* value-range.cc (prange::set_pt): Do not set PT when zero.
(prange::intersect): If the result is zero_p, clear PT.
(prange::verify_range): Verify points-to range is valid.
* value-range.h (zero_p): Do not assert, move to verify range.
(prange::set_pt): Only set PT when the range valid.
2026-06-24 Vineet Gupta <vineet.gupta@linux.dev>
PR debug/125421
* dwarf2out.cc (modified_type_die): Handle qualified_type being
a variant of dtype as if they were identical to avoid peeling a
typdef.
For named types, use dentry unconditionally as that is valid for
both cases of qualified_type == and != dentry.
2026-06-24 Paul-Antoine Arras <parras@baylibre.com>
* omp-builtins.def (BUILT_IN_GOMP_REDUCTION_START): New builtin.
(BUILT_IN_GOMP_REDUCTION_END): New builtin.
* omp-low.cc (lower_reduction_clauses): Replace
BUILT_IN_GOMP_ATOMIC_START / BUILT_IN_GOMP_ATOMIC_END with
BUILT_IN_GOMP_REDUCTION_START / BUILT_IN_GOMP_REDUCTION_END.
(lower_omp_sections): Likewise.
(lower_omp_scope): Likewise.
(lower_omp_for): Likewise.
* tree-ssa-alias.cc (check_fnspec): Handle
BUILT_IN_GOMP_REDUCTION_START and BUILT_IN_GOMP_REDUCTION_END as
memory barriers.
2026-06-24 Paul-Antoine Arras <parras@baylibre.com>
* omp-builtins.def (BUILT_IN_GOMP_BARRIER): Change function to
GOMP_barrier_ext and type to BT_FN_VOID_INT.
(BUILT_IN_GOMP_BARRIER_CANCEL): Change function to
GOMP_barrier_cancel_ext and type to BT_FN_VOID_INT.
* omp-expand.cc (expand_omp_for_static_nochunk): Pass
GOMP_BARRIER_IMPLICIT_WORKSHARE to omp_build_barrier.
(expand_omp_for_static_chunk): Likewise.
(expand_omp_single): Likewise.
* omp-general.cc (omp_build_barrier): Add kind parameter; pass it
to GOMP_barrier_ext or GOMP_barrier_cancel_ext.
* omp-general.h (omp_build_barrier): Update declaration to add
kind parameter.
* omp-low.cc (lower_rec_input_clauses): Determine barrier kind from
the enclosing gimple statement code and pass it to omp_build_barrier.
(lower_omp_for_scan): Pass GOMP_BARRIER_IMPLICIT_WORKSHARE to
omp_build_barrier.
2026-06-24 Paul-Antoine Arras <parras@baylibre.com>
* builtin-types.def (BT_COMPLEX_INT, BT_FN_COMPLEX_INT): New types.
* omp-builtins.def (BUILT_IN_GOMP_LOOP_STATIC_WORKSHARING): New
builtin.
(BUILT_IN_GOMP_DISTRIBUTE_STATIC_WORKSHARING): Likewise.
* omp-expand.cc (expand_omp_for_static_nochunk): Replace separate calls
to public API functions with a single call to
GOMP_loop_static_worksharing or GOMP_distribute_static_worksharing, then
unpack id and count.
(expand_omp_for_static_chunk): Likewise.
2026-06-24 Paul-Antoine Arras <parras@baylibre.com>
* omp-builtins.def (BUILT_IN_GOMP_HAS_MASKED_THREAD_NUM): New builtin.
* omp-low.cc (lower_omp_master): Call it.
2026-06-24 Filip Kastl <fkastl@suse.cz>
* gimple-ssa-pta-constraints.cc (handle_call_arg): Mention in
comment that the function can get called in IPA mode.
2026-06-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/110743
* tree-ssa-uninit.cc (maybe_warn_operand): Also cover
VIEW_CONVERT_EXPR uses for RMW bit clear/set pattern
detection.
2026-06-24 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
* config/rs6000/altivec.md (V16QI_V2DI): New mode iterator.
(add<mode>3): Split into two patterns to support future ISA
alternatives.
(sub<mode>3): Likewise.
* config/rs6000/vsx.md (VIArith): New mode iterator.
(vsx_mul<mode>3): New insn pattern.
(smul<mode>3_highpart): Split into mode-specific patterns.
(umul<mode>3_highpart): Likewise.
(smulv8hi3_highpart): New insn pattern.
(smulv4si3_highpart): Likewise.
(smulv2di3_highpart): Likewise.
(umulv8hi3_highpart): Likewise.
(umulv4si3_highpart): Likewise.
(umulv2di3_highpart): Likewise.
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvmulhuh): New
builtin.
(__builtin_vsx_xvmulhsh): Likewise.
* config/rs6000/rs6000-overload.def (__builtin_vec_mulh): Add
overloads for vector multiply-high signed/unsigned halfword.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add entry for
BSTZ_FUTURE_VSX.
(stanza_map): Add future-vsx stanza mapping.
(enable_string): Add ENB_FUTURE_VSX.
(write_decls): Add ENB_FUTURE_VSX to the bif_enable enum in the
generated header file.
* config/rs6000/rs6000.md (define_attr "isa"): Add future to the list
of ISA values.
(define_attr "enabled"): Add check for future ISA.
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Handle
ENB_FUTURE_VSX and issue a diagnostic requiring -mcpu=future and -mvsx.
(rs6000_builtin_is_supported): Return TARGET_FUTURE && TARGET_VSX
for ENB_FUTURE_VSX built-ins.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions Available
on Future ISA): Document new functions.
2026-06-24 Christopher Bazley <chris.bazley@arm.com>
* config/aarch64/aarch64-sve.md: Update
vec_init<mode><Vel> and vec_shl_insert_<mode> to
accept all SVE vector modes.
2026-06-24 H.J. Lu <hjl.tools@gmail.com>
PR target/125958
* config/i386/i386-expand.cc (ix86_expand_lcp_stall_peephole):
Replace !REG_P (dest) with !GENERAL_REG_P (dest).
2026-06-24 Lili Cui <lili.cui@intel.com>
* config/i386/x86-tune-costs.h (generic_cost): Increase branch
mispredict scale from COSTS_N_INSNS (2) to COSTS_N_INSNS (2) + 3.
2026-06-24 Jan Beulich <jbeulich@suse.com>
* doc/ifn.texi: Drop blanks after @code.
2026-06-23 Kwok Cheung Yeung <kcyeung@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
* gimplify.cc (gimplify_omp_affinity): Use macros for accessing
iterator elements.
(compute_omp_iterator_count): Likewise.
(build_omp_iterator_loop): Likewise.
(copy_omp_iterator): Use a boolean to force creation of an
expanded iterator vector, instead of specifying the length explicitly.
(remove_unused_omp_iterator_vars): Use accessor macros.
(build_omp_iterators_loops): Likewise.
(enter_omp_iterator_loop_context_1): Likewise.
(extract_base_bit_offset): Likewise.
* omp-low.cc (lower_omp_map_iterator_expr): Likewise.
(lower_omp_map_iterator_size): Likewise.
* tree-inline.cc (copy_tree_body_r): Likewise.
* tree-pretty-print.cc (dump_omp_iterators): Likewise.
* tree.h (OMP_ITERATOR_VAR, OMP_ITERATOR_BEGIN, OMP_ITERATOR_END,
OMP_ITERATOR_STEP, OMP_ITERATOR_ORIG_STEP, OMP_ITERATOR_BLOCK,
OMP_ITERATOR_LABEL, OMP_ITERATOR_INDEX, OMP_ITERATOR_ELEMS,
OMP_ITERATOR_COUNT, OMP_ITERATOR_EXPANDED_P): New macros.
(make_omp_iterator, make_expanded_omp_iterator): New constructor
functions.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* ira-build.cc (ira_create_allocno): Initialize dependent
filters.
(copy_dependent_filters): New function to copy filters.
(create_cap_allocno): Use new function.
(propagate_allocno_info): Ditto.
(propagate_some_info_from_allocno): Ditto.
* ira-color.cc (ira_dependent_filter): New function that
calls lra_get_dependent_filter.
(assign_hard_reg): Use new function.
(improve_allocation): Ditto.
(fast_allocation): Ditto.
* ira-conflicts.cc (dependent_filter_same_reg_ok_p): New
function to check if a dependent filter allows the same reg.
(can_use_same_reg_p): Use new function.
* ira-int.h (struct ira_dependent_filter): New struct holding
allocno-specific dependent-filter properties.
(ALLOCNO_DEPENDENT_FILTERS): New accessor.
(ira_add_dependent_filter): Declare.
* ira-lives.cc (ira_add_dependent_filter): New function.
(process_dependent_filters): New function.
(process_bb_node_lives): Call new function.
* ira.cc (ira): Reset filters.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS):
Add widen overlap dependent constraint.
* config/riscv/riscv-protos.h (riscv_widen_overlap_ok): Declare.
* config/riscv/riscv.cc (riscv_widen_operand_ok): New function.
* config/riscv/vector.md: Use new constraint.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* lra-assigns.cc (find_hard_regno_for_1): Query dependent
filter of current pseudo.
* lra-constraints.cc (struct dependent_filter_cache_hasher): New
hasher.
(lra_init_dependent_filter_cache): New function.
(lra_finish_dependent_filter_cache): Ditto.
(lra_reset_dependent_filters): Ditto.
(lra_get_dependent_filter): New function to query (and add)
a dependent filter from/to the cache.
(lra_add_dependent_filter): New function to add a dependent
filter to an lra_reg.
(get_dependent_filter): New function to get a dependent filter
from a constraint.
(process_dependent_filters): New function to get all dependent
filters from the current insn's constraints.
(process_alt_operands): Initialize dependent-filter regset.
(curr_insn_transform): Fill lra_reg dependent filters.
* lra-int.h (struct dependent_filter): Declare.
(struct dependent_filter_entry): Ditto.
(lra_init_dependent_filter_cache): Ditto.
(lra_finish_dependent_filter_cache): Ditto.
* lra.cc (initialize_lra_reg_info_element): New function.
(finish_reg_info): Release dependent-filter vector.
(lra_init_once): Init hash table.
(lra_finish_once): Clear hash table.
* lra.h (lra_reset_dependent_filters): Declare.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* recog.cc (preprocess_constraints): Initialize dependent
filter.
(test_dependent_filter): New function wrapping
eval_dependent_filter.
(constrain_operands): Test dependent filter in strict mode.
* recog.h (struct operand_alternative): Declare
dependent_filters.
(alternative_dependent_filters): New function.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* doc/md.texi: Document dependent filters.
* doc/tm.texi: Ditto.
* doc/tm.texi.in: Ditto.
* genconfig.cc (main): Add number of dependent filters.
* genpreds.cc (add_constraint): Add dependent-filter reference
operand.
(process_define_register_constraint): Handle dependent filter.
(write_get_register_filter): Ditto.
(write_get_register_filter_id): Ditto.
(write_dependent_filter_helpers_h): Ditto.
(write_dependent_filter_functions_c): Ditto.
(write_tm_preds_h): Ditto.
(write_insn_preds_c): Ditto.
(main): Ditto.
* gensupport.cc (process_define_register_constraint): Ditto.
* gensupport.h (get_register_filter_id): Declare.
* rtl.def (DEFINE_REGISTER_CONSTRAINT): Adjust for dependent
filter.
2026-06-23 Robin Dapp <robin.dapp@oss.qualcomm.com>
* tree-vect-stmts.cc (vect_use_grouped_gather): Only use when
there are at least two pieces.
2026-06-23 Xi Ruoyao <xry111@xry111.site>
Revert:
2026-06-08 Xi Ruoyao <xry111@xry111.site>
* config/mips/sync.md (sync_old_<optab><mode>): Fix
uninitialized operand use.
(sync_new_<optab><mode>): Fix uninitialized operand use, use the
same expression for the set source of operand 0 and 1.
2026-06-23 Zhongyao Chen <chen.zhongyao@zte.com.cn>
Yuke Tang <tang.yuke@zte.com.cn>
* config/riscv/autovec.md: Add auto-vectorization patterns for
Zvabd instructions.
* config/riscv/autovec-opt.md: Add widening absolute-difference
accumulate combine patterns.
* config/riscv/riscv-ext.def: Add Zvabd extension entry.
* config/riscv/riscv-ext.opt: Add Zvabd option.
* config/riscv/vector-iterators.md: Update for Zvabd.
* config/riscv/vector.md: Add Zvabd patterns.
* doc/riscv-ext.texi: Document zvabd extension.
2026-06-23 Alex Coplan <alex.coplan@arm.com>
PR target/125818
* config/aarch64/aarch64-sve-builtins-base.cc (svset_impl::fold): Fix
unsharing to ensure the returned stmt has the exact same lhs as the
original.
2026-06-23 Sarvesh Chandra <Sarvesh.Chandra@amd.com>
Ashwin Godbole <Ashwin.Godbole@amd.com>
PR target/107057
* config/i386/sse.md (avx512f_movddup512<mask_name>): Add a
register source alternative that emits vunpcklpd.
(avx_movddup256<mask_name>): Likewise.
2026-06-23 H.J. Lu <hjl.tools@gmail.com>
PR target/125893
* config/i386/i386-expand.cc (ix86_expand_lcp_stall_peephole): New.
* config/i386/i386-protos.h (ix86_expand_lcp_stall_peephole):
Likewise.
* config/i386/i386.md (TARGET_LCP_STALL peepholes): Call
ix86_expand_lcp_stall_peephole.
2026-06-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/110743
* tree-ssa-uninit.cc (maybe_warn_operand): Suppress diagnostics
on RMW cycles setting/clearing bits.
2026-06-23 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/sse.md (V_ANY_CBRANCH): New mode iterator.
(cond_vec_cbranch_any<mode>): New define_expand.
(cond_vec_cbranch_all<mode>): Ditto.
2026-06-23 Hu, Lin1 <lin1.hu@intel.com>
* dojump.cc (do_compare_rtx_and_jump): Use simplify_expand_binop
instead of expand_binop.
2026-06-23 Hu, Lin1 <lin1.hu@intel.com>
* doc/md.texi (vec_cbranch_all<mode>): Clarify how the
middle-end invoke the pattern.
(cond_vec_cbranch_all<mode>): Ditto.
(cond_len_vec_cbranch_all<mode>): Ditto.
2026-06-23 Kishan Parmar <kishan@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Handle
ENB_FUTURE_ALTIVEC and issue a diagnostic requiring -mcpu=future
and -maltivec.
(rs6000_builtin_is_supported): Check TARGET_FUTURE && TARGET_ALTIVEC
for ENB_FUTURE_ALTIVEC built-ins.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
BSTZ_FUTURE_ALTIVEC entry.
(stanza_map): Add future-altivec stanza mapping.
(enable_string): Add ENB_FUTURE_ALTIVEC.
(write_decls): Add ENB_FUTURE_ALTIVEC to the bif_enable enum in the
generated header file.
2026-06-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (pass_cselim::execute): Don't
return TODO_TODO_update_ssa_only_virtuals.
2026-06-23 Xin Liu <liulxx@hygon.cn>
* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect HYGON
Family 18h model 8 as c86-4g-m8.
* common/config/i386/i386-common.cc (processor_names): Add
c86-4g-m8.
(processor_alias_table): Likewise.
* common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add
HYGONFAM18H_C86_4G_M8.
* config.gcc: Add c86-4g-m8 to supported x86 CPUs and handle
c86_4g_m8 target triples.
* config/i386/c86-4g-m7.md: Rename to ...
* config/i386/c86-4g-m7m8.md: ... this and extend shared c86-4g-m7
scheduling reservations to c86-4g-m8.
(c86_4g_m8_imovx_cwde): New reservation.
(c86_4g_m7_imov_xchg): Add c86_4g_m8 to CPU attribute.
(c86_4g_m7_imov_xchg_load): Ditto.
(c86_4g_m7_imov): Ditto.
(c86_4g_m7_imov_load): Ditto.
(c86_4g_m7_imov_store): Ditto.
(c86_4g_m7_push): Ditto.
(c86_4g_m7_push_mem): Ditto.
(c86_4g_m7_pop): Ditto.
(c86_4g_m7_pop_mem): Ditto.
(c86_4g_m7_imul): Ditto.
(c86_4g_m7_imul_load): Ditto.
(c86_4g_m7_idiv): Ditto.
(c86_4g_m7_idiv_QI): Ditto.
(c86_4g_m7_idiv_load): Ditto.
(c86_4g_m7_idiv_QI_load): Ditto.
(c86_4g_m7_insn): Ditto.
(c86_4g_m7_insn_load): Ditto.
(c86_4g_m7_insn_store): Ditto.
(c86_4g_m7_insn2_store): Ditto.
(c86_4g_m7_insn_both): Ditto.
(c86_4g_m7_setcc): Ditto.
(c86_4g_m7_setcc_load): Ditto.
(c86_4g_m7_setcc_store): Ditto.
(c86_4g_m7_alu1_double): Ditto.
(c86_4g_m7_alu1_double_load): Ditto.
(c86_4g_m7_alu1_vector): Ditto.
(c86_4g_m7_alu1_vector_load): Ditto.
(c86_4g_m7_alu1_direct): Ditto.
(c86_4g_m7_alu1_direct_load): Ditto.
(c86_4g_m7_call): Ditto.
(c86_4g_m7_branch): Ditto.
(c86_4g_m7_branch_load): Ditto.
(c86_4g_m7_lea): Ditto.
(c86_4g_m7_leave): Ditto.
(c86_4g_m7_str): Ditto.
(c86_4g_m7_str_load): Ditto.
(c86_4g_m7_ieu_vector): Ditto.
(c86_4g_m7_ieu_vector_load): Ditto.
(c86_4g_m7_sse_insertimm): Ditto.
(c86_4g_m7_sse_insert): Ditto.
(c86_4g_m7_fp_cmov): Ditto.
(c86_4g_m7_fp_mov_direct_load): Ditto.
(c86_4g_m7_fp_mov_direct_store): Ditto.
(c86_4g_m7_fp_mov_double_load): Ditto.
(c86_4g_m7_fp_mov_double_store): Ditto.
(c86_4g_m7_fp_mov_direct): Ditto.
(c86_4g_m7_fp_sqrt): Ditto.
(c86_4g_m7_fp_spc_direct): Ditto.
(c86_4g_m7_fp_spc): Ditto.
(c86_4g_m7_fp_op_mul): Ditto.
(c86_4g_m7_fp_op_mul_load): Ditto.
(c86_4g_m7_fp_op_imul_load): Ditto.
(c86_4g_m7_fp_div): Ditto.
(c86_4g_m7_fp_div_load): Ditto.
(c86_4g_m7_fp_idiv_load): Ditto.
(c86_4g_m7_fp_fsgn): Ditto.
(c86_4g_m7_fp_fcmp): Ditto.
(c86_4g_m7_fp_fcmp_load): Ditto.
(c86_4g_m7_fp_mmx): Ditto.
(c86_4g_m7_mmx_add_cmp): Ditto.
(c86_4g_m7_mmx_add_cmp_load): Ditto.
(c86_4g_m7_mmx_cvt): Ditto.
(c86_4g_m7_mmx_cvt_load): Ditto.
(c86_4g_m7_mmx_shift): Ditto.
(c86_4g_m7_mmx_shift_load): Ditto.
(c86_4g_m7_mmx_shift_avg): Ditto.
(c86_4g_m7_mmx_shift_avg_load): Ditto.
(c86_4g_m7_mmx_shift_sadbw): Ditto.
(c86_4g_m7_mmx_shift_sadbw_load): Ditto.
(c86_4g_m7_mmx_mov): Ditto.
(c86_4g_m7_mmx_mov_store): Ditto.
(c86_4g_m7_mmx_mov_load): Ditto.
(c86_4g_m7_mmx_mul): Ditto.
(c86_4g_m7_mmx_mul_load): Ditto.
(c86_4g_m7_sse_pinsr_reg): Ditto.
(c86_4g_m7_sse_pinsr_reg_load): Ditto.
(c86_4g_m7_avx_vpinsr_reg): Ditto.
(c86_4g_m7_avx_vpinsr_reg_load): Ditto.
(c86_4g_m7_avx512_perm_xmm): Ditto.
(c86_4g_m7_avx512_perm_xmm_opload): Ditto.
(c86_4g_m7_avx512_permi2_ymm): Ditto.
(c86_4g_m7_avx512_permi2_zmm): Ditto.
(c86_4g_m7_avx512_permi2_ymm_load): Ditto.
(c86_4g_m7_avx512_permi2_zmm_load): Ditto.
(c86_4g_m7_avx512_perm_zmm_imm): Ditto.
(c86_4g_m7_avx512_perm_zmm_imm_load): Ditto.
(c86_4g_m7_avx512_perm_zmm_noimm): Ditto.
(c86_4g_m7_sse_perm_zmm_noimm_load): Ditto.
(c86_4g_m7_avx512_insertx_ymm): Ditto.
(c86_4g_m7_avx512_insertx_ymem): Ditto.
(c86_4g_m7_avx512_insertx_zxmm): Ditto.
(c86_4g_m7_avx512_insertx_zxmem): Ditto.
(c86_4g_m7_avx512_insertx_zymm): Ditto.
(c86_4g_m7_avx512_insertx_zymem): Ditto.
(c86_4g_m7_avx_insertx_ymm): Ditto.
(c86_4g_m7_avx_insertx_ymem): Ditto.
(c86_4g_m7_avx512_shuf_xymm): Ditto.
(c86_4g_m7_avx512_shuf_zmm): Ditto.
(c86_4g_m7_avx512_shuf_xymem): Ditto.
(c86_4g_m7_avx512_shuf_zmem): Ditto.
(c86_4g_m7_sselogic_xymm): Ditto.
(c86_4g_m7_sselogic_xymm_load): Ditto.
(c86_4g_m7_avx512_cmpestr): Ditto.
(c86_4g_m7_avx512_cmpestr_load): Ditto.
(c86_4g_m7_avx512_log): Ditto.
(c86_4g_m7_avx512_log_load): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_xymm): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_xymem): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto.
(c86_4g_m7_avx512_abs): Ditto.
(c86_4g_m7_avx512_abs_load): Ditto.
(c86_4g_m7_avx_sign): Ditto.
(c86_4g_m7_avx_sign_load): Ditto.
(c86_4g_m7_avx_blend): Ditto.
(c86_4g_m7_avx_blend_load): Ditto.
(c86_4g_m7_avx512_aes): Ditto.
(c86_4g_m7_avx512_aes_load): Ditto.
(c86_4g_m7_avx_aes): Ditto.
(c86_4g_m7_avx_aes_load): Ditto.
(c86_4g_m7_extr): Ditto.
(c86_4g_m7_extr_store): Ditto.
(c86_4g_m7_avx_ssecomi_comi): Ditto.
(c86_4g_m7_avx_ssecomi_comi_load): Ditto.
(c86_4g_m7_avx_ssecomi_test): Ditto.
(c86_4g_m7_avx_ssecomi_test_load): Ditto.
(c86_4g_m7_avx512_imul): Ditto.
(c86_4g_m7_avx512_imul_mem): Ditto.
(c86_4g_m7_avx_imul): Ditto.
(c86_4g_m7_avx_imul_mem): Ditto.
(c86_4g_m7_avx512_mov_vmov): Ditto.
(c86_4g_m7_avx512_mov_vmov_store): Ditto.
(c86_4g_m7_avx512_mov_vmov_load): Ditto.
(c86_4g_m7_avx512_vpmovx_y): Ditto.
(c86_4g_m7_avx512_vpmovx_y_load): Ditto.
(c86_4g_m7_avx512_vpmovx_z): Ditto.
(c86_4g_m7_avx512_vpmovx_z_load): Ditto.
(c86_4g_m7_avx512_vpmovx_x): Ditto.
(c86_4g_m7_avx512_vpmovx_x_load): Ditto.
(c86_4g_m7_avx_vpmovx_xx): Ditto.
(c86_4g_m7_avx_vpmovx_xx_load): Ditto.
(c86_4g_m7_avx512_expand): Ditto.
(c86_4g_m7_avx512_expand_load): Ditto.
(c86_4g_m7_avx512_expand_z): Ditto.
(c86_4g_m7_avx512_expand_z_load): Ditto.
(c86_4g_m7_avx512_movnt_load): Ditto.
(c86_4g_m7_avx512_movnt_store): Ditto.
(c86_4g_m7_sse_movnt_store): Ditto.
(c86_4g_m7_sse_movnt): Ditto.
(c86_4g_m7_avx512_blendv): Ditto.
(c86_4g_m7_avx512_blendv_load): Ditto.
(c86_4g_m7_sse_mov2): Ditto.
(c86_4g_m7_sse_mov2_load): Ditto.
(c86_4g_m7_avx512_sseishft_aligr): Ditto.
(c86_4g_m7_avx512_sseishft_aligr_load): Ditto.
(c86_4g_m7_avx512_sseishft_vshift): Ditto.
(c86_4g_m7_avx512_sseishft_vshift_load): Ditto.
(c86_4g_m7_avx512_sseadd_maxmin): Ditto.
(c86_4g_m7_avx512_sseadd_maxmin_load): Ditto.
(c86_4g_m7_avx_sseadd_maxmin): Ditto.
(c86_4g_m7_avx_sseadd_maxmin_load): Ditto.
(c86_4g_m7_sse_sseadd_maxmin): Ditto.
(c86_4g_m7_sse_sseadd_maxmin_load): Ditto.
(c86_4g_m7_avx512_sseadd): Ditto.
(c86_4g_m7_avx512_sseadd_load): Ditto.
(c86_4g_m7_avx_sseadd_hplus): Ditto.
(c86_4g_m7_avx_sseadd_hplus_load): Ditto.
(c86_4g_m7_avx512_sseiadd_madd): Ditto.
(c86_4g_m7_avx512_sseiadd_madd_mem): Ditto.
(c86_4g_m7_avx_sseiadd_sadbw): Ditto.
(c86_4g_m7_avx_sseiadd_sadbw_mem): Ditto.
(c86_4g_m7_sse_sseiadd_sadbw): Ditto.
(c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto.
(c86_4g_m7_sse_sseiadd_madd): Ditto.
(c86_4g_m7_sse_sseiadd_madd_mem): Ditto.
(c86_4g_m7_avx512_sseiadd_avg): Ditto.
(c86_4g_m7_avx512_sseiadd_avg_load): Ditto.
(c86_4g_m7_avx_sseiadd_hplus): Ditto.
(c86_4g_m7_avx_sseiadd_hplus_load): Ditto.
(c86_4g_m7_sse_sseiadd_hplus): Ditto.
(c86_4g_m7_sse_sseiadd_hplus_load): Ditto.
(c86_4g_m8_avx512_ssemul): New reservation.
(c86_4g_m8_avx512_ssemul_load): Ditto.
(c86_4g_m7_avx512_ssediv_x): Add c86_4g_m8 to CPU attribute.
(c86_4g_m7_avx512_ssediv_xmem): Ditto.
(c86_4g_m7_avx512_ssediv_y): Ditto.
(c86_4g_m7_avx512_ssediv_ymem): Ditto.
(c86_4g_m7_avx512_ssediv_z): Ditto.
(c86_4g_m7_avx512_ssediv_zmem): Ditto.
(c86_4g_m7_avx512_ssecmp): Ditto.
(c86_4g_m7_avx512_ssecmp_load): Ditto.
(c86_4g_m7_avx512_ssecmp_z): Ditto.
(c86_4g_m7_avx512_ssecmp_z_load): Ditto.
(c86_4g_m7_avx512_ssecmp_vp): Ditto.
(c86_4g_m7_avx512_ssecmp_vp_load): Ditto.
(c86_4g_m7_avx512_ssecmp_vp_z): Ditto.
(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
(c86_4g_m7_avx_ssecmp_vp): Ditto.
(c86_4g_m7_avx_ssecmp_vp_load): Ditto.
(c86_4g_m7_avx512_ssecmp_test): Ditto.
(c86_4g_m7_avx512_ssecmp_test_load): Ditto.
(c86_4g_m7_avx512_ssecvt_xy): Ditto.
(c86_4g_m7_avx512_ssecvt_xy_load): Ditto.
(c86_4g_m7_avx512_ssecvt_y_z): Ditto.
(c86_4g_m7_avx512_ssecvt_y_z_load): Ditto.
(c86_4g_m7_avx512_ssecvt_z): Ditto.
(c86_4g_m7_avx512_ssecvt_z_load): Ditto.
(c86_4g_m7_avx_ssecvt): Ditto.
(c86_4g_m7_avx_ssecvt_load): Ditto.
(c86_4g_m7_sse_ssecvt_pspi): Ditto.
(c86_4g_m7_sse_ssecvt_pspi_load): Ditto.
(c86_4g_m7_sse_ssecvt_pi): Ditto.
(c86_4g_m7_sse_ssecvt_pi_load): Ditto.
(c86_4g_m8_avx512_muladd): New reservation.
(c86_4g_m8_avx512_muladd_load): Ditto.
(c86_4g_m7_avx512_muladd_madd): Add c86_4g_m8 to CPU attribute.
(c86_4g_m7_avx512_muladd_madd_load): Ditto.
(c86_4g_m7_avx512_sse_range): Ditto.
(c86_4g_m7_avx512_sse_range_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_x): Ditto.
(c86_4g_m7_avx512_sse_conflict_x_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_y): Ditto.
(c86_4g_m7_avx512_sse_conflict_y_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_z): Ditto.
(c86_4g_m7_avx512_sse_conflict_z_load): Ditto.
(c86_4g_m7_avx512_sse_class): Ditto.
(c86_4g_m7_avx512_sse_class_load): Ditto.
(c86_4g_m7_avx512_sse_class_z): Ditto.
(c86_4g_m7_avx512_sse_class_z_load): Ditto.
(c86_4g_m7_avx_sse): Ditto.
(c86_4g_m7_avx_sse_load): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_x): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_xload): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_y): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_yload): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_z): Ditto.
(c86_4g_m7_avx512_sse_sqrt_sf_zload): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_x): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_xload): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_y): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_yload): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_z): Ditto.
(c86_4g_m7_avx512_sse_sqrt_df_zload): Ditto.
(c86_4g_m7_avx512_msklog): Ditto.
(c86_4g_m7_avx512_msklog_vector): Ditto.
(c86_4g_m7_avx512_mskmov_reg_k): Ditto.
(c86_4g_m7_avx512_mskmov_xy_k): Ditto.
(c86_4g_m7_avx512_mskmov_z_k): Ditto.
(c86_4g_m7_avx512_mskmov_k_k): Ditto.
(c86_4g_m7_avx512_mskmov_k_reg): Ditto.
(c86_4g_m7_avx512_mskmov_k_m): Ditto.
* config/i386/driver-i386.cc (host_detect_local_cpu): Detect
c86-4g-m8.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
c86-4g-m8 arch and tune macros.
* config/i386/i386-options.cc (m_C86_4G_M8): New macro.
(m_C86_4G): Include m_C86_4G_M8.
(processor_cost_table): Add c86_4g_m8_cost.
* config/i386/i386.cc (ix86_reassociation_width): Handle
PROCESSOR_C86_4G_M8.
* config/i386/i386.h (enum processor_type): Add
PROCESSOR_C86_4G_M8.
(PTA_C86_4G_M8): New.
* config/i386/i386.md: Add c86_4g_m8 to cpu attribute.
* config/i386/x86-tune-costs.h (c86_4g_m8_cost): New.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle
PROCESSOR_C86_4G_M8.
(ix86_adjust_cost): Likewise.
* config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Include
m_C86_4G_M8.
(X86_TUNE_USE_SCATTER_4PARTS): Likewise.
(X86_TUNE_USE_SCATTER_8PARTS): Likewise.
(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Likewise.
(X86_TUNE_AVX512_SPLIT_REGS): Likewise.
(X86_TUNE_AVX512_AVOID_VEC_PERM): Likewise.
(X86_TUNE_AVX512_MOVE_BY_PIECES): Likewise.
(X86_TUNE_AVX512_MASKED_EPILOGUES): Likewise.
* doc/extend.texi: Document c86-4g-m8 for __builtin_cpu_is.
* doc/invoke.texi: Document c86-4g-m8.
2026-06-22 Marek Polacek <polacek@redhat.com>
PR c++/125697
* doc/invoke.texi: Clarify -Wrange-loop-construct description.
2026-06-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125923
* tree-ssa-phiopt.cc (factor_out_conditional_load): Change
assert of the vuse being the same to rejecting if they are
different without a virtual phi.
2026-06-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (cond_store_replacement): Fix comment
on no load for nontrapping.
2026-06-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (cond_store_replacement): Update
the vuse on the new load and the vuse/vdef on the new
store.
2026-06-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125917
* tree-ssa-phiopt.cc (cond_store_replacement): Just call
gsi_insert_before instead of checking gsi_end_p.
(cond_if_else_store_replacement_1): Likewise.
2026-06-22 Georg-Johann Lay <avr@gjlay.de>
* splay-tree-utils.cc: Remove -*- C++ -*- tags for Emacs.
* rtl-ssa/accesses.cc: Same.
* rtl-ssa/blocks.cc: Same.
* rtl-ssa/changes.cc: Same.
* rtl-ssa/functions.cc: Same.
* rtl-ssa/insns.cc: Same.
2026-06-22 Tobias Burnus <tburnus@baylibre.com>
* omp-general.cc (omp_runtime_api_procname): Update for added
functions and older additions.
* omp-low.cc (scan_omp_1_stmt): Update for added _dim function.
2026-06-22 Zhongjie Guo <guozhongjie@hygon.cn>
Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Cost
comparisons using the comparison operand mode.
2026-06-22 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-protos.h (avr_log_t) <insert_attributes>: New field.
* config/avr/avr-log.cc (avr_log_node): New static function.
(avr_log_vadump) [%N]: Call it.
(avr_log_set_avr_log) <insert_attributes>: New SET_DUMP_DETAIL.
* config/avr/avr.cc (avr_pgm_check_var_decl): Don't call avr_edump.
(avr_insert_attributes) [avr_log.insert_attributes]: Call avr_edump.
2026-06-22 H.J. Lu <hjl.tools@gmail.com>
PR target/125895
* config/i386/i386-features.cc (pass_x86_cse::x86_cse): Use
integer CONST_VECTOR to load FP CONST_VECTOR converted from
const_int.
2026-06-22 Pan Li <pan2.li@intel.com>
* match-sat-alu.pd: Add fits check before call to
tree_to_uhwi.
2026-06-22 Pan Li <pan2.li@intel.com>
* match-sat-alu.pd: Add pattern for unsigned scalar
SAT_MUL form 13.
2026-06-21 Iain Sandoe <iain@sandoe.co.uk>
* doc/sourcebuild.texi: Document object file checks.
2026-06-21 Iain Sandoe <iain@sandoe.co.uk>
* config/aarch64/aarch64-builtins.cc
(aarch64_expand_prefetch_range_builtin): Use LLONG_MAX instead
of LONG_LONG_MAX.
2026-06-21 H.J. Lu <hjl.tools@gmail.com>
PR target/125883
* config/i386/i386-features.cc (ix86_broadcast_inner): Skip JUMP
from asm goto.
2026-06-20 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (Integer Overflow Builtins): Spell compile time
without dash when a noun.
* doc/invoke.texi (Warning Options): Ditto.
* doc/passes.texi (Tree SSA passes): Ditto.
* doc/rtl.texi (Conversions): Ditto.
2026-06-20 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_progmem_p): Use strip_array_types to
peel off ARRAY_TYPEs.
(avr_nonconst_pointer_addrspace): Same.
(avr_insert_attributes): Same.
(avr_decl_maybe_lds_p): Same.
2026-06-20 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-features.cc (scalar_chain::convert_op): Check
if the (DImode) SUBREG being converted by STV has an original mode
that's tieable to the vector mode (V2DImode), if not (e.g. DDmode)
emit this "conversion" as a separate move for reload to handle.
2026-06-20 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_init_builtins): Use XALLOCAVEC
instead of alloca to locally alloc char[].
* config/avr/avr-c.cc (avr_cpu_cpp_builtins): Same.
* config/avr/avr-log.cc (avr_log_set_avr_log): Same.
2026-06-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125857
* ipa-prop.cc (ipa_record_return_value_range_1): Don't record
pranges which have non ipa-invariants in it.
2026-06-19 Iain Sandoe <iain@sandoe.co.uk>
* config/aarch64/aarch64.cc
(aarch64_vector_costs::count_ops): Treat vec_deconstruct in the
same way as vec_construct.
2026-06-19 Peter Bergner <bergner@tenstorrent.com>
* config/riscv/riscv-cores.def (RISCV_TUNE)<tt-ascalon-d8>: Rename from
this...
(RISCV_TUNE)<tt-ascalon-x>: ...to this.
(RISCV_CORE)<tt-ascalon-d8>: Likewise.
(RISCV_CORE)<tt-ascalon-x>: Likewise.
(RISCV_CORE_ALIAS): Add tt-ascalon-d8 alias for tt-ascalon-x.
* doc/riscv-mcpu.texi: Document the name change.
* doc/riscv-mtune.texi: Likewise.
2026-06-19 Peter Bergner <bergner@tenstorrent.com>
* common/config/riscv/riscv-common.cc (struct riscv_cpu_alias_info):
New struct.
(riscv_cpu_alias_table): New.
(riscv_find_cpu): Add support for cpu alias names.
(riscv_get_valid_option_values): Likewise.
Add an early loop exit if we found a duplicate name.
* config/riscv/riscv-cores.def (RISCV_CORE_ALIAS): New macro.
2026-06-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/122193
* tree-ssa-phiopt.cc (factor_out_conditional_load): Support non-zero
offsets.
2026-06-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (is_factor_profitable): Change arg_op
to operands and opcount.
(factor_out_conditional_operation): Update call to
is_factor_profitable.
(factor_out_conditional_load): Support when merge has
a virtual phi. The load's vuse needs to be the arguments
to the virtual phi. Call is_factor_profitable on the new phi
arguments. Update the vuse on the new load to the virtual phi.
2026-06-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/125557
* tree-ssa-phiopt.cc (factor_out_conditional_load): New function.
(factor_out_all): Call factor_out_conditional_load.
2026-06-19 Xin Wang <yw987194828@gmail.com>
* tree-ssa-loop-im.cc (mem_ref_hasher::equal): Refactor
for clarity.
2026-06-19 Arsen Arsenović <aarsenovic@baylibre.com>
* doc/extend.texi: Move @anchor-s referring to tops of nodes
after their corresponding @node lines.
* doc/invoke.texi: Ditto.
2026-06-19 Eric Botcazou <ebotcazou@adacore.com>
* acinclude.m4 (gcc_GAS_FLAGS): Set to --32 for abi32 targets.
* configure.ac (TLS support): Use 32-bit sequence for abi32 targets.
* configure: Regenerate.
2026-06-19 Eric Botcazou <ebotcazou@adacore.com>
* tree-nested.cc (lookup_field_for_decl): In the non-pointer case,
clear DECL_NONADDRESSABLE_P if the DECL is of an aggregate type.
2026-06-19 Kael Andrew Franco <kaelfandrew@gmail.com>
PR tree-optimization/125641
PR tree-optimization/125641
* match.pd: Add bit_ior/bit_and {bit_not} rshift to min/max.
2026-06-19 Léo Hardt <leom.hardt@inf.ufrgs.br>
* ddg.h (GCC_DDG_H): Removed orphaned comment from 60393bbc
* sel-sched-ir.h (GCC_SEL_SCHED_IR_H): Removed orphaned comment from c7131fb
2026-06-18 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
PR target/125405
* match.pd: New pattern added.
2026-06-18 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.md (splitter for equality test): New splitter.
2026-06-18 Paul Iannetta <piannetta@kalrayinc.com>
Thomas Schwinge <tschwinge@baylibre.com>
* tree.h (ENCODE_QUAL_ADDR_SPACE): Add missing parentheses.
2026-06-18 Andrew MacLeod <amacleod@redhat.com>
* value-range.cc (prange::intersect): Points-to and away results
in undefined.
2026-06-18 Andrew MacLeod <amacleod@redhat.com>
* value-range.h (prange::pt_invariant_p): Return true or false.
(prange::pt_invariant_away_p): Likewise.
2026-06-18 Andrew MacLeod <amacleod@redhat.com>
* value-range.h (prange::zero_p): Assert that is zero_p is true,
points_to is unknown.
2026-06-18 Richard Sandiford <rdsandiford@googlemail.com>
PR tree-optimization/125872
* gimple-ssa-backprop.cc (backprop::execute): Don't try to delete
default definitions.
2026-06-18 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-fold.cc (fold_using_range::range_of_phi): Remove
extranous logical not from expression.
2026-06-18 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125854
* gimple-range-fold.cc (fold_using_range::fold_stmt): Check if the
range_query matches the current one before invoking fold.
2026-06-18 Martin Jambor <mjambor@suse.cz>
PR ipa/124128
* ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Move the check if
the final type conversion needs to happen before the conversion.
2026-06-18 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Use vector construction scaling also for mult-lane
VMAT_STRIDED_SLP but use vector composition type recorded
to avoid excessive over-costing.
2026-06-18 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Expect vec_deconstruct where formerly handling vec_to_scalar
for emulated gather/scatter, elementwise and strided accesses.
2026-06-18 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_cd_cost): New function,
enhanced and split out from ...
(ix86_default_vector_cost): ... here.
2026-06-18 Richard Biener <rguenther@suse.de>
* target.h (vect_cost_for_stmt::vec_deconstruct): New kind.
* tree-vect-loop.cc (vect_model_reduction_cost): Use it.
* tree-vect-stmts.cc (vectorizable_store): Likewise.
(vectorizable_load): Likewise.
* tree-vectorizer.cc (dump_stmt_cost): Handle vec_deconstruct.
* config/aarch64/aarch64.cc (aarch64_builtin_vectorization_cost):
Handle vec_deconstruct like vec_construct.
* config/i386/i386.cc (ix86_default_vector_cost): Likewise.
* config/arm/arm.cc (arm_builtin_vectorization_cost): Likewise.
* config/loongarch/loongarch.cc (loongarch_builtin_vectorization_cost):
Likewise.
* config/riscv/riscv.cc (riscv_builtin_vectorization_cost):
Likewise.
* config/rs6000/rs6000.cc (rs6000_builtin_vectorization_cost):
Likewise.
* config/s390/s390.cc (s390_builtin_vectorization_cost): Likewise.
* targhooks.cc (default_builtin_vectorization_cost): Likewise.
2026-06-18 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_load_store_data::ls_eltype): New field.
* tree-vect-stmts.cc (vectorizable_load): Record ltype
as ls_eltype for VMAT_STRIDED_SLP.
(vectorizable_store): Likewise.
2026-06-17 James K. Lowden <jklowden@cobolworx.com>
* doc/install.texi: COBOL requires Bison 3.8.2.
2026-06-17 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125804
* tree-vect-loop-manip.cc (vect_do_peeling): Have
LOOP_VINFO_EARLY_BREAKS_VECT_PEELED require epilog.
2026-06-17 Dhruv Chawla <dhruvc@nvidia.com>
PR fortran/125717
* lto-streamer-in.cc (input_cfg): Stream loop->can_be_parallel in.
* lto-streamer-out.cc (output_cfg): Stream loop->can_be_parallel out.
2026-06-17 Zhongjie Guo <guozhongjie@hygon.cn>
* config/i386/x86-tune-costs.h (c86_4g_m7_cost): Increase
512-bit load/store and unaligned load/store costs.
2026-06-17 Xin Liu <liulxx@hygon.cn>
* config/i386/c86-4g-m7.md (c86_4g_m7_imov_xchg): Adjust
reservation units.
(c86_4g_m7_imov_xchg_load): Ditto.
(c86_4g_m7_call): Ditto.
(c86_4g_m7_branch): Ditto.
(c86_4g_m7_branch_load): Ditto.
(c86_4g_m7_fp_spc_direct): Add missing store unit.
(c86_4g_m7_sse_pinsr_reg): Adjust reservation units.
(c86_4g_m7_avx512_insertx_ymm): Ditto.
(c86_4g_m7_avx512_insertx_ymem): Ditto.
(c86_4g_m7_avx512_insertx_zxmm): Ditto.
(c86_4g_m7_avx512_insertx_zxmem): Ditto.
(c86_4g_m7_avx512_abs_load): Add missing store unit.
(c86_4g_m7_avx_sign): Use combined FPU reservation.
(c86_4g_m7_avx_sign_load): Ditto.
(c86_4g_m7_avx_aes): Ditto.
(c86_4g_m7_avx_aes_load): Ditto.
(c86_4g_m7_extr_load): Rename to ...
(c86_4g_m7_extr_store): ... this and restrict to store memory.
(c86_4g_m7_avx_imul): Use combined FPU reservation.
(c86_4g_m7_avx_imul_mem): Ditto.
(c86_4g_m7_avx512_vpmovx_y_load): Add missing store unit.
(c86_4g_m7_avx_vpmovx_xx_load): Ditto.
(c86_4g_m7_avx512_sseadd_maxmin_xy): Rename to ...
(c86_4g_m7_avx512_sseadd_maxmin): ... this and simplify
memory attribute check.
(c86_4g_m7_avx512_sseadd_maxmin_xy_load): Rename to ...
(c86_4g_m7_avx512_sseadd_maxmin_load): ... this and simplify
memory attribute check.
(c86_4g_m7_avx512_sseadd_xy): Rename to ...
(c86_4g_m7_avx512_sseadd): ... this.
(c86_4g_m7_avx512_sseadd_xy_load): Rename to ...
(c86_4g_m7_avx512_sseadd_load): ... this.
(c86_4g_m7_sse_sseiadd_sadbw): Use combined FPU reservation.
(c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto.
(c86_4g_m7_avx512_ssecmp_vp_z): Adjust reservation units.
(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
(c86_4g_m7_avx512_ssecmp_test_load): Ditto.
(c86_4g_m7_avx512_mskmov_k_m): Adjust latency.
2026-06-17 Robin Dapp <rdapp.gcc@gmail.com>
PR target/125478
* config/riscv/vector.md: Set widen-alu mode_idx to 3.
2026-06-17 Jeff Law <jeffrey.law@oss.qualcomm.com>
Revert:
2026-06-15 Jim Tsung-Chun Lin <jim@andestech.com>
* common/config/riscv/riscv-common.cc (riscv_select_multilib):
Don't set riscv_no_matched_multi_lib here; let the caller own
the flag.
(riscv_compute_multilib): Drop the early return that accepted
the generic-matched multilib_dir; always run the smart matcher
and set riscv_no_matched_multi_lib when it finds no candidate.
2026-06-17 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ranger_cache::set_global_range): Nonzero
pointer ranges are no longer invariant.
2026-06-17 Andrew MacLeod <amacleod@redhat.com>
* Makefile.in (OBJS): Remove value-pointer-equiv.o.
* tree-vrp.cc (rvrp_folder::m_pta): Delete member.
(rvrp_folder::rvrp_folder): Remove m_pta allocation.
(rvrp_folder::~rvrp_folder): Delete.
(rvrp_folder::pre_fold_bb): Remove m_pta reference.
(rvrp_folder::post_fold_bb): Delete.
(rvrp_folder::pre_fold_stmt): Remove m_pta reference.
* value-pointer-equiv.cc: Delete.
* value-pointer-equiv.h: Delete.
2026-06-17 Andrew MacLeod <amacleod@redhat.com>
* tree-vrp.cc (rvrp_folder::value_of_expr): Use prange PTA info.
(value_on_edge): Likewise.
2026-06-17 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-fold.cc (x_fold_context): New.
(pta_valueize): New.
(fold_using_range::fold_stmt): Set PTA fields.
(fold_using_range::range_of_phi): Ditto.
* ipa-prop.cc (ipa_vr::ipa_vr): Allocate unshared range.
* range-op-ptr.cc (pointer_plus_operator::fold_range): Handle PTA.
(pointer_plus_operator::op2_range): Ditto.
(operator_pointer_diff::fold_range): Ditto.
(operator_cast::fold_range): Ditto.
(operator_cast::lhs_op1_relation): Ditto.
(operator_equal::fold_range): Ditto.
(operator_not_equal::fold_range): Ditto.
* value-query.cc (range_query::get_tree_range): Ditto.
* value-range-pretty-print.cc (vrange_printer::print_pt): New.
(vrange_printer::visit): Add print support.
* value-range-pretty-print.h (vrange_printer::print_pt): New prototype.
* value-range-storage.cc (vrange_allocator::clone): Allow unshared
expression allocation.
(vrange_storage::alloc): Likewise.
(prange_storage::alloc): Likewise.
(prange_storage::prange_format): Copy PTA.
(prange_storage::set_prange): Ditto.
(prange_storage::get_prange): Ditto.
(prange_storage::equal_p): Compare points-to data.
(ggc_alloc_vrange_storage): Allow unshared expression.
* value-range-storage.h (clone): Adjust param list.
(prange_storage::m_pt, m_points_to_p): New.
* value-range.cc (inchash::add_vrange): Add points-to to hash value.
(prange::set_pt): New.
(prange::pt_base): New.
(prange::pt_offset): New.
(prange::pt_size): New.
(prange::set): Initialize PTA field.
(prange::union_): Handle PTA cases.
(prange::intersect): Ditto.
(prange::operator=): Ditto.
(prange::operator==): Ditto.
(prange::invert): Handle PTA cases.
(prange::verify_range): Ditto.
* value-range.h (set_pt, set_pt_unknown, pt_unknown_p,
pt_invariant, pt_invariant_away, pt_invariant_p, pt_invariant_away_p,
pt_invert, pt_inverted_p, pt_base, pt_offset, pt_size,
pt_equal_p): New prange prototypes.
(prange::m_pt, prange::m_points_to_p): New members.
(prange::set_undefined): Clear PTA fields.
(prange::set_varying): Ditto.
(prange::set_nonzero): Ditto.
(prange::set_zero): Ditto.
(prange::zero_p): Check PTA fields.
(varying_compatible_p): Ditto.
(prange::set_pt): New.
(prange::set_pt_unknown): New.
(prange::pt_unknown_p): New.
(prange::pt_equal_p): New prange prototypes.
(prange::pt_inverted_p): New.
(prange::pt_invert): New.
(prange::pt_invariant): New.
(prange::pt_invariant_away): New.
(prange::pt_invariant_p): New.
(prange::pt_invariant_away_p): New.
2026-06-16 H.J. Lu <hjl.tools@gmail.com>
PR c/125226
* targhooks.cc (default_stack_protect_guard): If UINTPTR_TYPE
isn't NULL, call unsigned_integer_tree_node_for_type with
UINTPTR_TYPE to get unsigned integer type for uintptr_t.
* tree.cc (unsigned_integer_tree_node_for_type): New function.
(build_common_tree_nodes): Call unsigned_integer_tree_node with
SIZE_TYPE to get unsigned integer type for size_t.
* tree.h (unsigned_integer_tree_node_for_type): New prototype.
2026-06-16 Jakub Jelinek <jakub@redhat.com>
* doc/invoke.texi (-std=c++2d, -std=c++29, -std=gnu++2d,
-std=gnu++29): Document.
(-std=c++2c, -std=c++26, -std=gnu++2c, -std=gnu++26): Tweak so that
26 comes first and is meant as the supported option.
* doc/cpp.texi: Adjust expected __cplusplus value for -std=c++26,
document value for -std=c++29.
* dwarf2out.cc (highest_c_language): Handle C++29.
(gen_compile_unit_die): Likewise. Adjust lversion for C++26.
2026-06-16 Robin Dapp <rdapp.gcc@gmail.com>
PR tree-optimization/125516
* tree-vect-data-refs.cc (vect_gather_scatter_fn_p): Set
supported_offset_vectype.
* tree-vect-stmts.cc (vectorizable_store): Skip nop conversions
when costing scatters.
(vectorizable_load): Ditto for gathers.
2026-06-16 Abhishek Kaushik <abhishek.kaushik@arm.com>
* tree-ssa-loop-niter.cc (determine_value_range): Query ranger
for integral expressions, not only SSA_NAMEs. Query ranges on the
loop preheader edge.
2026-06-16 Kyrylo Tkachov <ktkachov@nvidia.com>
* tree-vect-data-refs.cc (vect_slp_analyze_data_ref_dependence):
Return a three-way tree result (chrec_known when independent,
chrec_dont_know when the affine test cannot analyze the pair, the
dependence otherwise) instead of a bool.
(vect_slp_analyze_store_dependences): Resort to the alias oracle on
an unknown dependence as well as on a missing data reference; a
store is being moved so do not use TBAA.
(vect_slp_analyze_load_dependences): Likewise on the load-hoist
paths, using TBAA as a load is being hoisted; also record that the
ao_ref has been initialized in check_hoist.
2026-06-16 Robin Dapp <rdapp.gcc@gmail.com>
PR target/125670
* config/riscv/autovec-opt.md: Use avl_type operand number.
2026-06-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/125730
* tree-ssa-loop-ivopts.cc (alloc_iv): Do not convert pointer
IVs to unsigned before canonicalizing.
2026-06-16 Richard Biener <rguenther@suse.de>
* fold-const.cc (fold_plusminus_mult_expr): Use
wide_int for the case of two INTEGER_CST multiplicands.
2026-06-16 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/125794
* config/aarch64/aarch64.cc (aarch64_simd_valid_imm): Do not fall
through to the replicating SVE immediate forms for a 128-bit
Advanced SIMD constant whose high 64 bits are zero (output_width
!= 0).
2026-06-16 Avinash Jayakar <avinashd@linux.ibm.com>
PR tree-optimization/59429
* match.pd: New match patterns to recognize spaceship variants.
* tree-ssa-math-opts.cc (gimple_spaceship): Match function declaration.
(match_spaceship): New function to recognize spaceship given phi node.
(math_opts_dom_walker::after_dom_children): Add match_spaceship check.
2026-06-16 H.J. Lu <hjl.tools@gmail.com>
PR target/125614
* config/i386/i386-features.cc (replace_vector_const): Replace
gen_rtx_SUBREG with gen_lowpart.
2026-06-15 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386.cc (ix86_insn_cost): Add a suitable penalty
for USE of a MEM in a PARALLEL (for *<absneg>[sd]f2_1 splitter).
2026-06-15 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/125795
* config/aarch64/aarch64-early-ra.cc (early_ra::allocate_colors):
Compute the allocated-FPR mask as
((1ULL << color->group->size) - 1) << best.
2026-06-15 Kael Andrew Franco <kaelfandrew@gmail.com>
PR tree-optimization/125737
PR tree-optimization/125737
* match.pd: Use tree_expr_nonnegative_p for X % Y < Y to true.
2026-06-15 Kael Andrew Franco <kaelfandrew@gmail.com>
PR tree-optimization/125756
* match.pd: Use tree_expr_nonnegative_p for X < (typeof X)(X != 0) to false.
2026-06-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (factor_out_all): New function.
(pass_phiopt::execute): Call factor_out_all isntead
of factor_out_conditional_operation and
cond_if_else_store_replacement_limited.
2026-06-15 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/123754
* expmed.cc (store_integral_bit_field): When the SUBREG
narrowing fails, defer to store_split_bit_field instead of
asserting.
2026-06-15 Jim Tsung-Chun Lin <jim@andestech.com>
* common/config/riscv/riscv-common.cc (riscv_select_multilib):
Don't set riscv_no_matched_multi_lib here; let the caller own
the flag.
(riscv_compute_multilib): Drop the early return that accepted
the generic-matched multilib_dir; always run the smart matcher
and set riscv_no_matched_multi_lib when it finds no candidate.
2026-06-15 Filip Kastl <fkastl@suse.cz>
PR sanitizer/124206
* gcc.cc (driver::global_initializations): Ask for 128MB stack
instead of just 64MB when __SANITIZE_ADDRESS__ is defined.
* toplev.cc (toplev::main): Ditto.
2026-06-15 Richard Biener <rguenther@suse.de>
* tree-ssa-reassoc.cc (ovce_extract_ops): Fixup
false value matching for the inverted comparison case.
2026-06-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/125786
* tree-ssa-reassoc.cc (optimize_vec_cond_expr): Create a new
stmt instead of rewriting an existing possibly multi-use one.
2026-06-15 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-protos.h (avr_out_delay_loop): New proto.
* config/avr/avr.cc (avr_out_delay_loop): New function.
(avr_adjust_insn_length) [ADJUST_LEN_DELAY_LOOP]: Handle case.
(avr_expand_delay_cycles): Overhaul. Allow loop counts of
zero; they represent a power of 2.
* config/avr/avr.md (adjust_len) [delay_loop]: Add.
(*delay_cycles_1): Use avr_out_delay_loop for asm out.
(*delay_cycles_4): Same.
(*delay_cycles_3): Same.
(*delay_cycles_2): Same. Relax constraints to "d".
Use two QImode scratch regs instead of one HImode one.
2026-06-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125790
* match.pd (`(~x)>>x`): Reject truncation of shifter.
2026-06-15 Monk Chiang <62004175+monkchiang@users.noreply.github.com>
* config/riscv/riscv-zicfilp.cc (rest_of_insert_landing_pad):
Remove gen_lpad_align before non-local goto labels; LABEL_ALIGN
now handles their alignment. Simplify gpr_save handling: the
pattern now outputs the full CFI sequence itself.
* config/riscv/riscv.cc (riscv_output_mi_thunk): Add
gen_lpad_align before entry lpad.
* config/riscv/riscv.h (LABEL_ALIGN): New macro; ensures 4-byte
alignment for Zicfilp non-local goto target labels.
* config/riscv/riscv.md (gpr_save): When is_zicfilp_p, output
.p2align 2, .option push/norelax/norvc, call, .option pop, lpad 0.
2026-06-15 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv-protos.h (riscv_call_needs_lpad_p): Declare.
* config/riscv/riscv.cc (riscv_gnu_attributes): Register new
indirect_return attribute for function declarations.
(riscv_call_needs_lpad_p): New function.
* config/riscv/riscv.md (call_internal_cfi): New insn pattern with
length attribute.
(call_value_internal_cfi): Likewise for call-with-return-value,
with comment and length attribute.
(define_expand "call"): Emit call_internal_cfi when
riscv_call_needs_lpad_p returns true.
(define_expand "call_value"): Likewise.
2026-06-14 Stafford Horne <shorne@gmail.com>
* config/or1k/or1k.md (cbranchsi4): Add clobber clause.
2026-06-14 Stafford Horne <shorne@gmail.com>
* config/or1k/or1k.h (SHIFT_COUNT_TRUNCATED): Define.
* config/or1k/or1k.md (rotrsi3): Rename reg_or_u6_operand to
reg_or_u5_operand.
(<shift_op>si3): Ditto.
* config/or1k/predicates.md (reg_or_u6_operand): Remove.
(reg_or_u5_operand): New predicate.
2026-06-14 François-Xavier Coudert <fxcoudert@gcc.gnu.org>
PR target/120645
* config/darwin-driver.cc: Account for latest macOS numbering
scheme.
2026-06-14 Souradipto Das <souradiptodas6@gmail.com>
* match.pd: Add simplification rules for
(a == 0) | ((a | b) == 0) -> (a == 0) and
(a != 0) & ((a | b) != 0) -> (a != 0).
2026-06-14 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125774
* gimple-range-fold.cc (fold_using_range::relation_fold_and_or): Use
relation_swap rather than relation_negate when the operands are exchanged.
2026-06-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125776
* tree-ssa-phiopt.cc (is_factor_profitable): An
usage in a debug stmt should be ignored.
2026-06-13 Jeff Law <jeffrey.law@oss.qualcomm.com>
* gcc.cc (find_a_program): Implement the new behavior described
above.
(driver::set_up_specs): Initilize variable. It would be nice to
have less spooky-action-at-a-distince using C++ features, but I
just matched how the corresponding suffix variable worked for
now for uniformity.
2026-06-13 John Ericson <git@JohnEricson.me>
* gcc.cc (for_each_path): Pass an additional boolean argument to
the callback specifying whether the current directly being
searched is machine-specific, as described above.
(build_search_list): Add unused parameter to lambda match new
callback type.
(find_a_file): Add unused parameter to lambda match new callback
type.
(find_a_program): Add unused parameter to lambda match new
callback type.
(spec_path::operator()): Add unused parameter to match new
callback type.
2026-06-13 panciyan@eswincomputing.com <panciyan@eswincomputing.com>
* config/riscv/crypto.md (riscv_pack): Change HISI iterator to
HX as we must match half a target word for pack.
2026-06-13 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Configuration): Use AE spelling for "behavior".
2026-06-13 Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/125750
* match.pd (mult of a 0/1 value by a negated 0/1 value): New
simplification.
2026-06-13 Kael Andrew Alonzo Franco <kaelfandrew@gmail.com>
PR tree-optimization/125707
PR tree-optimization/125707
* match.pd: Add (~a) >> a to -1 for signed a.
2026-06-13 Sunil Dora <sunilkumar.dora@windriver.com>
PR driver/111527
* defaults.h (COLLECT2_OPTIONS_MAX_LENGTH): New macro.
* collect-utils.cc (read_collect_gcc_options): New function.
* collect-utils.h (read_collect_gcc_options): Declare.
* collect2.cc (main): Use read_collect_gcc_options instead
of getenv.
* doc/hostconfig.texi (Host Misc): Document
COLLECT2_OPTIONS_MAX_LENGTH.
* doc/invoke.texi (Environment Variables): Document the
@file form of COLLECT_GCC_OPTIONS.
* gcc.cc (xsetenv_collect_gcc_options): New function.
(set_collect_gcc_options): Use xsetenv_collect_gcc_options.
* lto-wrapper.cc (run_gcc): Use read_collect_gcc_options
instead of getenv.
2026-06-12 Claudio Bantaloukas <claudio.bantaloukas@arm.com>
* config/aarch64/aarch64-cores.def (cortex-a320): Update core.
* config/aarch64/aarch64.cc: Add cortexa320.h.
* config/aarch64/tuning_models/cortexa320.h: New file.
2026-06-12 Ramin Moussavi <lordrasmus@gmail.com>
* config/microblaze/microblaze.h (DWARF_ALT_FRAME_RETURN_COLUMN):
Define.
2026-06-12 Thomas Schwinge <tschwinge@baylibre.com>
PR target/101484
* config/gcn/gcn.cc (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Implement.
2026-06-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* lra-constraints.cc (reload_section_anchor_p): New function.
(curr_insn_transform): For offsetable MEMs, try reloading the
section anchor only.
2026-06-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125597
* tree-vect-loop-manip.cc (vect_do_peeling): Create IFN_VARYING for
early break scalar IV.
* tree-vect-loop.cc (vect_update_ivs_after_vectorizer_for_early_breaks):
Replace the IFN_VARYING with actual value.
2026-06-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125597
(vect_do_peeling): Create IFN_VARYING for masks.
* tree-vect-loop-manip.cc (vect_set_loop_condition): Replace the
IFN_VARYING.
2026-06-12 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125597
* internal-fn.def (VARYING): New.
* doc/ifn.texi: Document it.
* internal-fn.cc (expand_VARYING): New.
* internal-fn.h (expand_VARYING): New.
* tree-cfg.cc (verify_gimple_call): Check for leaked IFN_VARYING.
2026-06-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR rtl-optimization/125173
* ira.cc (combine_and_move_insns): Allow multiple uses within
an insn.
2026-06-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Kyrylo Tkachov <ktkachov@nvidia.com>
PR tree-optimization/125557
PR tree-optimization/64700
PR tree-optimization/29144
PR tree-optimization/94274
* tree-if-conv.cc (find_different_opnum): Move to ...
* gimple-match-exports.cc (find_different_opnum): Here.
* gimple-match.h (find_different_opnum): New decl.
* tree-ssa-phiopt.cc (is_factor_profitable): Take
gimple_match_op instead of one operand.
Rearrange the code to check the lifetime of the operands last.
(factor_out_conditional_operation): Handle operands > 1,
including operands communitive operands. Add early_p argument
for costing. Update call of is_factor_profitable.
(pass_phiopt::execute): Pass early_p to
factor_out_conditional_operation.
* tree.h (int_divide_or_mod_p): New function.
2026-06-12 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* ira-costs.cc (find_costs_and_classes): Do not honour equivs if
they get rejected by LRA anyway.
* ira-int.h (CONST_POOL_OK_P): Move CONST_POOL_OK_P here ...
* lra-constraints.cc (CONST_POOL_OK_P): from there.
2026-06-11 Iain Sandoe <iain@sandoe.co.uk>
* common/config/aarch64/aarch64-common.cc: Make the asm
crc bug workaround configurable.
2026-06-11 Georg-Johann Lay <avr@gjlay.de>
PR target/125751
* config/avr/avr.cc (avr_out_fract): Fix too small sequence
lengths in avr_asm_len calls.
2026-06-11 Roman Beliaev <r.beliaev@ispras.ru>
* gcov.cc (solve_flow_graph): Fix condition.
2026-06-11 Karl Meakin <karl.meakin@arm.com>
* doc/rtl.texi: Replace "fixed-point" with "integral" where
appropriate.
2026-06-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125706
* range-op.cc (operator_trunc_mod::wi_fold): Apply fixed
quotient refinement.
2026-06-11 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn.h (REG_CLASS_NAMES): Add missing comma.
2026-06-11 Naveen <naveen.siddegowda@oss.qualcomm.com>
PR target/113926
* config/aarch64/aarch64.cc (struct simd_immediate_info): Add width
field to record AdvSIMD output vector width.
(simd_immediate_info::simd_immediate_info): Initialize width to zero
in all constructors.
(aarch64_simd_valid_imm): Allow 128-bit AdvSIMD MOV immediates with
zero high 64 bits to be materialized using 64-bit MOVI.
(aarch64_output_simd_imm): Use recorded immediate width when outputting
AdvSIMD immediates.
2026-06-11 Zhongyao Chen <chenzhongyao.hit@gmail.com>
PR tree-optimization/123343
* tree-vect-slp.cc (vect_analyze_slp_reduction_group): Return
false for group_size <= 1 at entry.
(vect_analyze_slp_reductions): Add loop exit check for
group_size <= 1.
2026-06-11 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR testsuite/113276
* doc/sourcebuild.texi (arm_mixed_fp): Document.
2026-06-11 Hongyu Wang <hongyu.wang@intel.com>
* common/config/i386/i386-cpuinfo.h (enum feature_priority):
Add P_AVX10_2, P_APX_F, P_PROC_AVX10_2.
* common/config/i386/i386-isas.h: Set P_AVX10_2 for avx10.2
and P_APX_F for apxf.
* common/config/i386/i386-common.cc (processor_alias_table):
Use P_PROC_AVX10_2 for diamondrapids and novalake.
2026-06-11 Zhongyao Chen <chen.zhongyao@zte.com.cn>
PR tree-optimization/125567
* tree-vect-slp.cc (least_upthread_swappable_op_distance): New.
(vect_build_slp_tree_2): Compute swap checks before building operand
zero. Skip external fallback while swap retry is possible. Reuse the
swap checks in the retry path.
2026-06-10 Andrew MacLeod <amacleod@redhat.com>
* value-range-storage.cc (irange_storage::irange_storage):
Explicitly initialize vrange_storage.
(prange_storage::prange_storage): Likewise.
* value-range-storage.h (vrange_storage): Add GTY marker and
discriminator field.
(irange_storage): Add GTY marker.
(prange_storage): Add GTY marker and friend GTY functions.
(frange_storage): Add GTY marker and explcitly initialize
vrange_storage.
2026-06-10 Andrew MacLeod <amacleod@redhat.com>
* value-range-storage.cc (prange_storage::equal_p): Compare just
the required fields.
2026-06-10 Andrew MacLeod <amacleod@redhat.com>
* value-range-storage.cc (prange_storage::alloc): Use new
prange_format function.
(prange_storage::prange_storage): Likewise.
(prange_storage::prange_format): Rename from prange_format
constructor and rework.
(prange_storage::set_prange): Use prange_format function.
(prange_storage::fits_p): Likewise.
* value-range-storage.h (enum prange_kind): Move out of
prange_storage class.
(PRANGE_STORAGE_NINTS): Likewise.
(class prange_format): remove.
(m_trailing_ints): Use PRANGE_STORAGE_NINTS.
2026-06-10 tobby.li <tobby.li@armchina.com>
* config/arm/arm-cpus.in (cortex-m52): Remove quirk_vlldm.
* doc/invoke.texi: Remove cortex-m52 from the list of CPUs that
enable -mfix-cmse-cve-2021-35465 by default. Fix typo in CVE
number (CVE-2021-365465 -> CVE-2021-35465).
2026-06-10 Chung-Lin Tang <cltang@baylibre.com>
PR fortran/122910
* langhooks-def.h (LANG_HOOKS_OMP_ARRAY_DATA_PRIVATIZE): Define.
* langhooks.h (struct lang_hooks_for_decls): Define
omp_array_data_privatize hook.
* omp-low.cc (scan_sharing_clauses): Add new calls to
lang_hooks.decls.omp_array_data_privatize,
(lower_omp_target): Likewise.
2026-06-10 tobby.li <tobby.li@armchina.com>
* config/arm/arm-cpus.in (star-mc3): New CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Update docs.
2026-06-10 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR ipa/125699
* ipa-param-manipulation.cc (ipa_param_body_adjustments::prepare_debug_expressions): Fix
lifetime issue with m_dead_ssa_debug_equiv usage.
2026-06-10 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/zicond.md (combined sCC splitters): Avoid using
PUT_MODE to change existing RTL. Instead just generate a new node.
2026-06-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/125686
* tree-vect-patterns.cc (synth_lshift_by_additions): Specify
pattern vector type.
(apply_binop_and_append_stmt): Likewise.
(vect_synth_mult_by_constant): Adjust.
2026-06-09 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc: Fix typos in comments.
* config/avr/avr-c.cc: Same.
* config/avr/avr-passes.cc: Same.
* config/avr/avr-passes-fuse-move.h: Same.
2026-06-09 Uros Bizjak <ubizjak@gmail.com>
PR target/125636
* config/i386/i386.md (extendqihi2): Use movsbl instead of movsbw.
Adjust the destination operand to use %k0 and update the mode
attribute accordingly.
2026-06-09 Ciprian Arbone <Ciprian.Arbone@microchip.com>
Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
PR target/124077
* config/arm/arm.cc (thumb1_final_prescan_insn): Also skip
condition code update for thumb1_cbz instructions.
* config/arm/thumb1.md (thumb1_cbz): Use const0_rtx as the
recorded cc_op1 instead of operands[2].
2026-06-09 Lino Hsing-Yu Peng <linopeng@andestech.com>
* config/riscv/riscv-protos.h (enum altfmt_type): New.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): Pass
ALTFMT_NONE to gen_vsetvl.
(gen_no_side_effects_vsetvl_rtx): Pass ALTFMT_NONE to
gen_vsetvl_no_side_effects.
* config/riscv/riscv-vector-builtins-bases.cc: Include insn-attr.h.
(vsetvl::expand): Pass ALTFMT_NONE to gen_vsetvl_no_side_effects.
* config/riscv/riscv-vsetvl.cc (altfmt_to_str): New function.
(get_altfmt): New function.
(demand_flags): Add DEMAND_ALTFMT_P.
(altfmt_demand_type): New enum.
(vsetvl_info): Track altfmt.
(demand_system): Add altfmt compatibility, availability, and merge handling.
* config/riscv/riscv-vsetvl.def: Add altfmt rules.
* config/riscv/vector.md (altfmt): New attribute, numeric with
INVALID_ATTRIBUTE default.
(@vsetvl<mode>, vsetvl_vtype_change_only,
@vsetvl_discard_result<mode>, @vsetvl<mode>_no_side_effects,
*vsetvldi_no_side_effects_si_extend): Add altfmt operand.
2026-06-09 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md: Fix typos in comments.
* config/avr/avr-fixed.md: Same.
* config/avr/avr-passes.cc: Same
* config/avr/avr-passes-fuse-move.h: Same.
2026-06-09 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64-sve.md: Remove zeroing movprfx of merging MOV
2026-06-09 Artemiy Volkov <artemiy.volkov@arm.com>
PR target/125550
* config/aarch64/aarch64-simd.md
(*aarch64_combine_internal<mode>): Use zip1 instead of uzp1
to concatenate values residing in SIMD registers.
(*aarch64_combine_internal_be<mode>): Likewise.
2026-06-09 JRobinNTA <johnrobin044@gmail.com>
PR target/125395
* config/riscv/thead.cc (th_asm_output_opcode): Add VFCVT
and VFWCVT blocks. Add offset logic for static rounding suffixes.
2026-06-09 Alex Coplan <alex.coplan@arm.com>
PR middle-end/125621
* expmed.cc (make_tree): Fix CONST_POLY_INT case to pass type
instead of t, move it to its own switch case.
2026-06-09 Monk Chiang <monk.chiang@sifive.com>
"Jim Wilson <jimw@sifive.com>
* config/riscv/riscv-protos.h (riscv_zero_offset_address_bypass_p):
New function.
* config/riscv/riscv.cc (riscv_zero_offset_address_bypass_p): New
function.
* config/riscv/sifive-7.md: Add bypass definition.
2026-06-09 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.cc (riscv_trampoline_init): Remove redundant
LUI instruction.
2026-06-09 Martin Jambor <mjambor@suse.cz>
* config/pdp11/pdp11.cc (pdp11_conditional_register_usage): Change i
from int to unsigned int.
2026-06-09 Xi Ruoyao <xry111@xry111.site>
PR rtl-optimization/125609
PR middle-end/122992
* hard-reg-set.h
(build_error_on_rvalue): New function.
(EXECUTE_IF_SET_IN_HARD_REG_SET): Call the function above.
2026-06-09 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
* config/rs6000/amo.h (_AMO_LD): Add _AMO_LD_CS_EQ enumerator, gated on
_ARCH_FUTURE.
(amo_lwat_cas_eq, amo_lwat_scas_eq, amo_ldat_cas_eq,
amo_ldat_scas_eq): New compare-and-swap equal helper functions.
(_AMO_ERR_CMPSWP): New macro for error-attribute stubs on non-Future
targets.
* doc/extend.texi (PowerPC Atomic Memory Operation Functions): Document
new functions.
2026-06-08 Sam James <sam@gentoo.org>
* doc/tm.texi: Regenerate.
2026-06-08 Gerald Pfeifer <gerald@pfeifer.com>
* doc/cpp.texi: Spell "command-line option" with a dash.
(Binary Resource Inclusion): Ditto.
* doc/fragments.texi (Target Fragment): Ditto.
* doc/gcc.texi: Ditto.
(Indices): Ditto.
* doc/gccint.texi: Ditto.
(Top): Ditto.
(Option Index): Ditto.
* doc/gcov.texi (Invoking Gcov): Ditto. And fix grammar.
* doc/gm2.texi (Compiler options): Ditto.
(Extensions): Ditto.
(The PIM system module): Ditto.
(The ISO system module): Ditto.
* doc/invoke.texi (Debugging Options): Ditto.
(AVR Options): Ditto.
* doc/lto.texi (LTO object file layout): Ditto.
(WHOPR): Ditto.
* doc/md.texi (Machine Constraints): Ditto.
* doc/objc.texi (Constant string objects): Ditto. And fix grammar.
(Exceptions): Ditto.
(Synchronization): Ditto.
* doc/tm.texi.in: Ditto. And standardize on "option" over
"flag".
(strategy): Ditto. And standardize on "option" over "switch"
and fix grammar.
* target.def: Ditto.
* doc/tm.texi: Regenerate.
2026-06-08 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-builtins.cc (enum aarch64_builtins):
Add AARCH64_PREFETCH_PLD_RANGE and AARCH64_PREFETCH_PLDX_RANGE.
(aarch64_init_prefetch_builtins): Add initialization of
__pld_range and __pldx_range.
(require_const_argument): Update to return the minval if value
is out of range.
(aarch64_expand_prefetch_range_builtin): New function.
(aarch64_general_expand_builtin): Add support for
AARCH64_PREFETCH_PLD_RANGE and AARCH64_PREFETCH_PLDX_RANGE.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add
__ARM_PREFETCH_RANGE macro.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_PLDX_RANGE and
UNSPEC_PLD_RANGE
(aarch64_rprfm): New instruction.
2026-06-08 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.h (TARGET_FPRCVT): New macro definition.
* config/aarch64/aarch64.md (arches): Add fprcvt.
(arch_enabled): Add fprcvt.
(l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2): Add
FEAT_FPRCVT variant.
(<optab>_trunchf<GPI:mode>2): Likewise.
(<optab>_trunc<fcvt_change_mode><GPI:mode>2): Likewise.
(fix_to_zero_extend<mode>di2): Likewise.
(<optab><fcvt_iesize><GPF:mode>2): Likewise.
(define_insn "aarch64_fp16_<optab><mode>hf2): Likewise.
* config/aarch64/iterators.md (fpw): Add SF and DF variants.
2026-06-08 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-simd-builtins.def: (lround): Add new
forms for new conversions.
(lroundu): Likewise.
(lceil): Likewise.
(lceilu): Likewise.
(lfloor): Likewise.
(lflooru): Likewise.
(lfrintn): Likewise.
(lfrintnu): Likewise.
* config/aarch64/arm_neon.h (vcvtd_s32_f64): New intrinsic.
(vcvtd_s32_f64): Likewise.
(vcvtd_u32_f64): Likewise.
(vcvts_s64_f32): Likewise.
(vcvts_u64_f32): Likewise.
(vcvtad_s32_f64): Likewise.
(vcvtad_u32_f64): Likewise.
(vcvtas_s64_f32): Likewise.
(vcvtas_u64_f32): Likewise.
(vcvtmd_s32_f64): Likewise.
(vcvtmd_u32_f64): Likewise.
(vcvtms_s64_f32): Likewise.
(vcvtms_u64_f32): Likewise.
(vcvtnd_s32_f64): Likewise.
(vcvtnd_u32_f64): Likewise.
(vcvtns_s64_f32): Likewise.
(vcvtns_u64_f32): Likewise.
(vcvtpd_s32_f64): Likewise.
(vcvtpd_u32_f64): Likewise.
(vcvtps_s64_f32): Likewise.
(vcvtps_u64_f32): Likewise.
2026-06-08 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add
__ARM_FEATURE_SSVE_FEXPA.
* config/aarch64/aarch64-sve-builtins-base.def (svexpa): Change
gating to streaming compatible if AARCH64_FL_SSVE_FEXPA is
supported.
* config/aarch64/aarch64-sve.md: Update gating to be enabled if
TARGET_SSVE_FEXPA.
* config/aarch64/aarch64.h (TARGET_SVE_FEXPA): New macro.
* config/aarch64/iterators.md (SVE_FP_UNARY_INT): Update FEXPA
gating.
2026-06-08 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Add
__ARM_FEATURE_SSVE_BITPERM.
* config/aarch64/aarch64-sve-builtins-sve2.def:
Make sve-bitperm intrinsics streaming compatible.
* config/aarch64/aarch64-sve2.md: Change gating of sve-bitperm
instructions.
* config/aarch64/aarch64.h (TARGET_SVE_BITPERM): New macro.
(TARGET_SVE2_BITPERM): Removed.
2026-06-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/125668
* tree-ssa-forwprop.cc (forward_propagate_addr_expr_1):
Preserve alignment of the original access also for propagating
into the LHS.
2026-06-08 Richard Sandiford <rdsandiford@googlemail.com>
PR tree-optimization/125653
* gimple-ssa-backprop.cc (backprop::process_var): Avoid early
return for SSA names that occur in abnormal phis.
2026-06-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/125652
* tree-chrec.cc (chrec_fold_plus_poly_poly): Avoid UB
integer overflow in accumulating CHREC_RIGHT.
2026-06-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/125646
* tree-vect-patterns.cc (vect_synth_mult_by_constant): Assign
vector type to the pattern def sequence stmts.
2026-06-08 Andreas Schwab <schwab@suse.de>
PR rtl-optimization/122992
* config/m68k/m68k.cc (m68k_conditional_register_usage): Fix
signedness of register number var.
(m68k_zero_call_used_regs): Fix missing declaration.
2026-06-08 Richard Sandiford <rdsandiford@googlemail.com>
* config/aarch64/aarch64-sve.md
(*aarch64_vec_duplicate_subvector<vconsv><vconq><mode>): Remove
<vconq> from name.
2026-06-08 Richard Sandiford <rdsandiford@googlemail.com>
* simplify-rtx.cc (simplify_context::simplify_unary_operation_1):
Simplify vec_duplicates of vec_duplicates.
* config/aarch64/aarch64-sve.md
(*aarch64_vec_duplicate_subvector<vconsv><vconq><mode>): Remove
nested vec_duplicate.
2026-06-08 Richard Sandiford <rdsandiford@googlemail.com>
* config/sh/sh.md (bswapsi): Remove can_create_pseudo_p () check.
2026-06-08 Xi Ruoyao <xry111@xry111.site>
* config/mips/sync.md (sync_old_<optab><mode>): Fix
uninitialized operand use.
(sync_new_<optab><mode>): Fix uninitialized operand use, use the
same expression for the set source of operand 0 and 1.
2026-06-08 Naveen <naveen.siddegowda@oss.qualcomm.com>
* match.pd: ((type) minmax (wide) a, wide (b)): New pattern.
2026-06-07 Richard Sandiford <rdsandiford@googlemail.com>
* doc/sourcebuild.texi: Document that check-function-bodies
automatically adds the check_function_bodies options.
2026-06-07 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125612
* tree-ssa-phiopt.cc (cond_store_replacement): For the case where
lhs is "known" to be nontrapping make sure there are no loads in
the middle bb.
2026-06-07 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/sh/sh.md (bswapsi2): Move check for can_create_pseudos_p
into condition rather than FAILing.
2026-06-07 John Ericson <git@JohnEricson.me>
* gcc.cc (find_a_file): Remove mode parameter, because always
R_OK. Skip suffix logic, because suffix is always empty in that
case.
(read_specs): Remove mode from find_a_file call.
(find_a_program): Suffix is unconditional, inline mode constant.
(end_going_arg): Remove mode from find_a_file call.
(find_file): Remove mode from find_a_file call.
(driver::set_up_specs): Remove mode from find_a_file call.
(include_spec_function): Remove mode from find_a_file call.
2026-06-07 John Ericson <git@JohnEricson.me>
* gcc.cc (find_a_program): Inline find_a_file, instead of
calling.
2026-06-07 Kwok Cheung Yeung <kcyeung@baylibre.com>
Andrew Stubbs <ams@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
* gimplify.cc (compute_omp_iterator_count): Account for difference
in loop boundaries in Fortran.
(build_omp_iterator_loop): Change upper boundary condition for
Fortran. Insert block statements into innermost loop.
(remove_unused_omp_iterator_vars): Copy block subblocks of old
iterator to new iterator and remove original.
(extract_base_bit_offset): Add iterator argument. Remove iterator
variables from base.
(omp_accumulate_sibling_list): Add iterator argument to
extract_base_bit_offset.
* tree-pretty-print.cc (dump_block_node): Ignore BLOCK_SUBBLOCKS
containing iterator block statements.
2026-06-06 Richard Sandiford <rdsandiford@googlemail.com>
* optabs-query.cc (can_open_code_p): Use can_open_code_p rather
than can_implement_p when testing for AND and XOR.
2026-06-06 Richard Sandiford <rdsandiford@googlemail.com>
* optabs-query.cc (can_open_code_p): Handle more bswap cases,
incorporating logic from...
* gimple-ssa-store-merging.cc (maybe_optimize_vector_constructor)
(pass_optimize_bswap::execute)
(imm_store_chain_info::try_coalesce_bswap): ...here. Use
can_open_code_p instead of direct optab_handler checks.
2026-06-06 Jakub Jelinek <jakub@redhat.com>
PR target/125611
* config/i386/sse.md (<ssse3_avx2>_pmulhrsw<mode>3, smulhrs<mode>3):
Use vector_operand instead of nonimmediate_operand.
2026-06-06 Ramin Moussavi <lordrasmus@gmail.com>
* config/csky/csky.h (DWARF_ALT_FRAME_RETURN_COLUMN): Define.
2026-06-05 Sandra Loosemore <sloosemore@baylibre.com>
* gimplify.cc (remove_unused_omp_iterator_vars): Don't warn about
possibly-unused iterator variables. Simplify control flow of
remaining code.
2026-06-05 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/125501
* tree-ssa-dom.cc (set_global_ranges_from_unreachable_edges): Abort
if there are 2 SSA_NAMES on the branch condition.
2026-06-05 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
PR rtl-optimization/124713
* avoid-store-forwarding.cc (process_store_forwarding): Re-apply
SIGN_EXTEND/ZERO_EXTEND after bit insert sequence when the load is
not eliminated.
2026-06-05 Jakub Jelinek <jakub@redhat.com>
* gimple-ssa-store-merging.cc (maybe_optimize_vector_constructor):
Also support bswap32 if bswapdi2 expander is present. Add comment
about bswap64 support on 32-bit targets with bswapsi2 expander.
(pass_optimize_bswap::execute): Likewise.
* config/riscv/bitmanip.md (bswapsi2): Change condition to disable
the expander on TARGET_64BIT without TARGET_XTHEADBB, never FAIL.
2026-06-05 Roger Sayle <roger@nextmovesoftware.com>
Richard Earnshaw <richard.earnshaw@arm.com>
PR target/56102
PR middle-end/122871
* config/arm/arm.cc (thumb1_rtx_costs): Provide reasonable costs
for PLUS, MINUS, COMPARE, AND, XOR, IOR, NEG, NOT, ASHIFT,
ASHIFTRT and ROTATERT for SImode, DImode, HImode and QImode.
(thumb1_size_rtx_costs): Likewise.
(comp_not_to_clear_mask_str_un): Silence host compiler warning.
2026-06-05 Artemiy Volkov <artemiy.volkov@arm.com>
PR target/125538
* config/aarch64/aarch64-simd.md
(*aarch64_simd_dup_subvector<vcons><mode>): New insn pattern.
(*aarch64_simd_dup_subvectorv2qiqi): Likewise.
* config/aarch64/iterators.md (VSDUP): New mode iterator.
(VCONS): New mode attribute.
(vcons): Likewise.
2026-06-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/125602
* tree-ssa-loop-niter.cc (number_of_iterations_until_wrap):
Avoid double negation for assumption condition. Compute
negated step in niter_type.
2026-06-05 Jakub Jelinek <jakub@redhat.com>
* gimple-lower-bitint.cc (bitint_large_huge::lower_bswap_bitreverse):
Add OBJ argument, use it instead of m_vars[part] if non-NULL. Don't
gsi_remove stmt.
(bitint_large_huge::lower_call): Adjust caller.
(bitint_large_huge::lower_stmt): Handle store of
IFN_BSWAP/IFN_BITREVERSE result.
(stmt_needs_operand_addr): Return true also for
IFN_BSWAP/IFN_BITREVERSE.
(build_bitint_stmt_ssa_conflicts): Formatting fix.
(gimple_lower_bitint): Allow merging IFN_BSWAP/IFN_BITREVERSE with
subsequent non-bitfield store. Allow merging load of
IFN_{CLZ,CTZ,CLRSB,FFS,PARITY,POPCOUNT,BSWAP,BITREVERSE} argument
with the call.
2026-06-05 Jakub Jelinek <jakub@redhat.com>
PR c/122731
* doc/extend.texi (__builtin_bswapg, __builtin_bitreverseg): Document.
* internal-fn.def (DEF_INTERNAL_INTSZ_FN): Define.
(DEF_INTERNAL_INTSZ_EXT_FN): Define.
(BSWAP): New internal fn.
(BITREVERSE): Likewise.
* internal-fn.h (expand_BSWAP, expand_BITREVERSE): Declare.
* internal-fn.cc (DEF_INTERNAL_INTSZ_EXT_FN): Define.
(expand_BSWAP, expand_BITREVERSE): New functions.
* builtins.h (fold_build_builtin_bswapg_bitreverseg): Declare.
* builtins.cc (fold_build_builtin_bswapg_bitreverseg): New function.
* wide-int.h (wi::bswap): Fix up docs that only multiple of 8 bits
is required.
* gimple-match-exports.cc (build_call_internal): Handle IFN_BSWAP
and IFN_BITREVERSE.
* gencfn-macros.cc (internal_fn_intsz_names): New variable.
(intsz_suffixes): Likewise.
(suffix_lists): Add intsz_suffixes.
(main): Handle internal_fn_intsz_names.
* match.pd (BSWAP, BITREVERSE): Remove.
(popcount(bswap(x)) is popcount(x)): Use BSWAP BITREVERSE
op lists.
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p): Use
CASE_CFN_BSWAP and CASE_CFN_BITREVERSE.
(cond_removal_in_builtin_zero_pattern): Likewise.
* fold-const-call.cc (fold_const_call_ss): Likewise.
* fold-const.cc (tree_call_nonnegative_p): Likewise.
* gimple-lower-bitint.cc (struct bitint_large_huge): Declare
lower_bswap_bitreverse method.
(bitint_large_huge::lower_bswap_bitreverse): New method.
(bitint_large_huge::lower_call): Call it.
(build_bitint_stmt_ssa_conflicts): Set muldiv_p for IFN_BSWAP
and IFN_BITREVERSE.
2026-06-05 Richard Sandiford <rdsandiford@googlemail.com>
PR tree-optimization/125599
* gimple-ssa-backprop.cc (backprop::execute): Calculate the
transitive closure of replacement values.
2026-06-05 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/125609
PR middle-end/122992
* rtl-ssa/insns.cc (function_info::record_call_clobbers): Use a
variable to store out the result of abi.full_reg_clobbers().
2026-06-05 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Specify default
cmodel.
2026-06-04 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.cc (bitmap_elt_clear_from): Make static. Require a
list view.
(bitmap_tree_listify_from): Delete.
(bitmap_list_view): Rewrite to avoid separate vectors.
(bitmap_clear): Switch to a list view before calling
bitmap_elt_clear_from and restore the original view afterwards.
2026-06-04 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.cc (bitmap_tree_unlink_element): Optimize the handling
of the maximal node.
2026-06-04 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.cc: Include pretty-print.h and splay-tree-utils.h.
(bitmap_splay_tree_accessors): New class.
(bitmap_splay_tree): New type.
(bitmap_first_set_bit_worker): Use bitmap_splay_tree::min_node
for tree views.
(bitmap_last_set_bit_worker): Use bitmap_splay_tree::max_node
for tree views.
2026-06-04 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.cc (bitmap_tree_link_element): Require callers to have
done a splay operation. Avoid doing another one here.
2026-06-04 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/multilib-generator: Support extra options in the
multilib config string.
* doc/install.texi (--with-multilib-generator): Document the extra
options syntax.
2026-06-04 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc (riscv_supported_std_ext):
Move 'v' before 'p' and drop 'n' to match the spec.
* config/riscv/arch-canonicalize (CANONICAL_ORDER): Ditto.
2026-06-04 Raphael Zinsly <raphael.zinsly@oss.qualcomm.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/125387
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize and properly cost
mulh instructions.
2026-06-04 vekumar <Venkataramanan.Kumar@amd.com>
* config/i386/x86-tune.def (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM): Enable
for m_ZNVER6.
(X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM): Likewise.
(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Likewise.
2026-06-04 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/106895
* config/rs6000/rs6000.h (enum rs6000_builtin_type_index): Add
RS6000_BTI_INTPTI and RS6000_BTI_UINTPTI.
(intPTI_type_internal_node, uintPTI_type_internal_node): New
PTImode type macros.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Register
signed and unsigned PTImode internal builtin types.
* config/rs6000/sync.md (trunctipti2): New splitter.
(extendptiti2): Likewise.
(zero_extendptiti2): Likewise.
2026-06-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/125588
* match.pd (`if (cond) (A | CST1) : (A & ~CST1)`): Enable
for GIMPLE only.
2026-06-04 Kevin Stefanov <kevinstefanov15@gmail.com>
* config/m68k/m68k.cc (m68k_conditional_register_usage): Replace TEST_HARD_REG_BIT
with EXECUTE_IF_SET_IN_HARD_REG_SET in applicable loops.
(m68k_zero_call_used_regs): Likewise.
* config/pdp11/pdp11.cc (pdp11_conditional_register_usage): Likewise.
* ira-color.cc (create_new_allocno_hard_regs_node): Replace call to hard_reg_set_size
with hard_reg_set_popcount.
* ira-int.h (hard_reg_set_size): Remove.
* ira-lives.cc (process_bb_node_lives): Replace TEST_HARD_REG_BIT
with EXECUTE_IF_SET_IN_HARD_REG_SET in applicable loops.
* ira.cc (setup_class_hard_regs): Likewise.
(update_equiv_regs_prescan): Likewise.
(build_insn_chain): Likewise.
(setup_stack_reg_pressure_class): Replace call to hard_reg_set_size
with hard_reg_set_popcount.
* lra-eliminations.cc (spill_pseudos): Replace TEST_HARD_REG_BIT
with EXECUTE_IF_SET_IN_HARD_REG_SET in applicable loops.
* optabs.cc (expand_asm_reg_clobber_mem_blockage): Replace
TEST_HARD_REG_BIT with EXECUTE_IF_SET_IN_HARD_REG_SET in one instance
and with hard_reg_set_popcount in another.
* postreload.cc (reload_combine): Replace TEST_HARD_REG_BIT
with EXECUTE_IF_SET_IN_HARD_REG_SET in applicable loops.
* reginfo.cc (init_reg_sets_1): Likewise.
* regrename.cc (init_rename_info): Likewise.
* reload1.cc (maybe_fix_stack_asms): Likewise.
(update_eliminables_and_spill): Likewise.
* rtl-ssa/insns.cc (function_info::record_call_clobbers): Likewise.
* sched-deps.cc (sched_analyze_insn): Likewise.
* sel-sched-dump.cc (print_hard_reg_set): Likewise.
2026-06-04 Xiaomei Xue <xuexiaomei@hygon.cn>
* config/i386/sse.md (define_mode_attr sse2): Add V4SI/V8SI/V16SI/
V8HI/V16HI/V32HI.
(<sse2>_movnt<mode>): Change mode iterator from VI8 to VI_AVX_AVX512F.
(define_mode_iterator STORENT_MODE): Add V4SI/V8SI/V16SI/V8HI/V16HI/
V32HI/V16QI/V32QI/V64QI.
2026-06-03 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/124405
* tree-ssa-phiopt.cc (cond_store_replacement): Make ASSIGN (the
candidate store for cselim) an argument of the function instead. Update
legality check due to relaxing the restriction that middle_bb can have
only a single statement.
(cselim_candidate): New.
(pass_cselim::execute): Call cselim_candidate and pass the result to
cond_store_replacement.
2026-06-03 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Changed xt-c908
PIPELINE_MODEL and TUNE_INFO
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add entry
for xt-c908 design
* config/riscv/riscv.cc: New tune structure
for the xt-c908 design.
* config/riscv/riscv.md: Add xt-c908 .
Include xt-c908.md.
* config/riscv/xt-c908.md: New file.
2026-06-03 Abhishek Kaushik <abhishek.kaushik@arm.com>
* tree-scalar-evolution.cc
(compute_final_value_from_loop_phi_latch): New function.
(final_value_replacement_loop): Use it.
2026-06-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/103221
* passes.def (early_optimizations): Move sccopy
to after evrp.
2026-06-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* gimple-ssa-sccopy.cc (stmt_may_generate_copy): Remove restriction
on the ssa info being different for the "copy".
(scc_copy_prop::replace_scc_by_value): Call maybe_duplicate_ssa_info_at_copy
when copyproping a ssa name.
2026-06-03 Pan Li <pan2.li@intel.com>
* match-sat-alu.pd: Add pattern for unsigned scalar
SAT_MUL form 11.
2026-06-03 Richard Sandiford <rdsandiford@googlemail.com>
* rtl.def (CALL_INSN): Add a new integer field.
* rtl.h (CALL_INSN_ABI_ID): New macro.
* target.def (insn_callee_abi): Delete.
* doc/rtl.texi: Document CALL_INSN_ABI_ID.
* doc/tm.texi.in (TARGET_INSN_CALLEE_ABI): Remove.
* doc/tm.texi: Regenerate.
* calls.cc: Include regs.h and function-abi.h.
(emit_call_1): Initialize CALL_INSN_ABI_ID.
* cfgcleanup.cc (old_insns_match_p): Compare CALL_INSN_ABI_IDs.
* emit-rtl.cc (try_split): Copy the original insn's CALL_INSN_ABI_ID
to the new call.
(emit_copy_of_insn_after): Likewise.
(make_call_insn_raw): Initialise CALL_INSN_ABI_ID.
* function-abi.cc (insn_callee_abi): Remove use of the insn_callee_abi
hook and instead use CALL_INSN_ABI_ID.
* recog.cc (peep2_attempt): Copy the original insn's CALL_INSN_ABI_ID
to the new call.
* config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Remove
arm_pcs parameter.
* config/aarch64/aarch64.cc (aarch64_gen_callee_cookie): Likewise.
(aarch64_callee_abi): Delete.
(aarch64_insn_callee_abi): Likewise.
(aarch64_function_arg): Update call to aarch64_callee_abi.
(aarch64_output_mi_thunk): Likewise. Set CALL_INSN_ABI_ID instead.
(TARGET_INSN_CALLEE_ABI): Delete.
* config/aarch64/aarch64.md (tlsdesc_small_<mode>): Update call
to aarch64_callee_abi and set CALL_INSN_ABI_ID instead.
* config/i386/i386.cc (ix86_insn_callee_abi): Delete.
(ix86_expand_avx_vzeroupper): Set CALL_INSN_ABI_ID.
(TARGET_INSN_CALLEE_ABI): Delete.
* config/riscv/riscv-sr.cc (riscv_remove_unneeded_save_restore_calls):
Remove coding convention from calls to gen_sibcall_internal and
gen_sibcall_value_internal. Store the ABI identifier in
CALL_INSN_ABI_ID instead.
* config/riscv/riscv.cc (riscv_output_mi_thunk): Likewise.
(riscv_call_tls_get_addr): Likewise, but calling gen_call_value.
(riscv_function_arg): Return null for the end marker.
(get_riscv_cc, riscv_insn_callee_abi): Delete.
(TARGET_INSN_CALLEE_ABI): Delete.
* config/riscv/riscv.md (UNSPEC_CALLEE_CC): Delete.
(sibcall): Revert to treating operand 2 as a placeholder.
Do not pass it to gen_sibcall_internal.
(sibcall_value): Likewise operand 3 and gen_sibcall_value_internal.
(call): Likewise operand 2 and gen_call_internal.
(call_value): Likewise operand 3 and gen_call_value_internal.
(sibcall_internal, call_internal): Remove operand 2.
(sibcall_value_internal, call_value_internal): Remove operand 3.
(untyped_call): Update call to gen_call.
2026-06-03 Alex Coplan <alex.coplan@arm.com>
* config/aarch64/constraints.md (Uci): Drop @internal, slightly tweak
doc string.
(Ucj): Likewise.
* doc/md.texi (Machine Constraints): Document Uci and Ucj under AArch64
family.
2026-06-03 Alex Coplan <alex.coplan@arm.com>
* doc/ifn.texi (Direct Internal Functions): Flesh out
documentation for IFN_MASK_LOAD.
* doc/md.texi (Standard Names): Add anchor for maskloadmn so it
can be cross-referenced.
2026-06-03 Richard Sandiford <rdsandiford@googlemail.com>
PR tree-optimization/125579
* gimple-ssa-backprop.cc (backprop::execute): Avoid double deletions.
2026-06-03 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125431
* tree-vect-slp-patterns.cc (complex_mul_pattern::matches,
complex_fms_pattern::matches): Gate on FP contraction.
2026-06-03 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/125509
* tree-vect-loop-manip.cc (vect_do_peeling): Re-enable dominators
update for prolog peeling.
2026-06-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/125477
* tree-vect-loop-manip.cc (vect_loop_versioning): Verify we
can duplicate an outer loop before considering to version it.
2026-06-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/125507
* gengtype.cc (main): Add tree_code.
* tree-core.h (struct tree_base): Remove ENUM_BITFIELD.
(struct tree_type_common): Likewise.
(struct tree_decl_common): Likewise.
(struct tree_decl_with_vis): Likewise.
(struct tree_function_decl): Likewise.
2026-06-03 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_sched_reorder): Remove dead
return after the early-return guard.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.h (bitmap_element): Fix left/right distinction in comments.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* gimple-ssa-backprop.cc: Update the comment at head of the file.
(var_info::new_value, var_info::seq): New member variables.
(var_info::var_info): Initialize them.
(remove_unused_var): Replace with...
(remove_dead_stmt): ...this new function.
(note_replacement): Delete.
(backprop::prepare_change): Likewise.
(backprop::complete_change): Likewise.
(backprop::set_new_value): New function.
(backprop::subst_operand): Likewise.
(backprop::finish_stmt): Likewise.
(backprop::optimize_builtin_call): Replace the lhs and info parameters
with a var_info parameter. Create a new statement rather than
changing the existing one.
(backprop::optimize_assign): Likewise.
(backprop::optimize_phi): Likewise.
(backprop::replace_assign_rhs): Likewise, but replace gassign and lhs
parameters.
(backprop::propagate_change): New function.
(backprop::commit_replacement): Likewise.
(backprop::execute): Update phase 3 for the above changes. Do not
alter the original statements during phase 3. If one SSA name
is scheduled to be replaced, also require all its users in m_vars
to be replaced. Add a new phase that performs the scheduled
replacements.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* gimple-ssa-backprop.cc: Remove the claim at the head of the file
that we only need to revisit a statement once.
(backprop::m_worklist, backprop::m_worklist_names): Delete.
(backprop::m_worklist1): New member variable.
(backprop::m_worklist2, backprop::m_this_worklist): Likewise.
(backprop::m_next_worklist, backprop::m_worklist_threshold): Likewise.
(backprop::backprop): Update accordingly.
(backprop::~backprop): Likewise.
(backprop::push_to_worklist): Switch to using bitmap worklists that
use m_vars indices instead of SSA_NAME_VERSIONs. Decide which
worklist should be used based on m_worklist_threshold.
(backprop::pop_from_worklist): Pop the first bit from m_this_worklist.
Set m_worklist_threshold.
(backprop::execute): Use a double-worklist update in which each
iteration makes a post order walk.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* gimple-ssa-backprop.cc (var_info): New structure.
(var_info_hasher): Likewise.
(backprop::m_info_pool): Replace with...
(backprop::m_var_pool): ...this new member variable.
(backprop::m_info_map): Replace with...
(backprop::m_var_table): ...this new member variable.
(backprop::m_worklist): Store var_info pointers instead of SSA names.
(backprop::backprop): Update accordingly.
(backprop::~backprop): Likewise.
(backprop::lookup_operand): Return a var_info pointer instead of
a usage_info pointer.
(backprop::push_to_worklist): Take a var_info pointer instead
of an SSA name.
(backprop::pop_from_worklist): Return a var_info pointer instead
of an SSA name.
(backprop::process_builtin_call_use): Update calls accordingly.
(backprop::process_assign_use): Likewise.
(backprop::process_phi_use): Likewise.
(backprop::reprocess_inputs): Likewise.
(backprop::process_var): Take a pointer to the var_info entry
as a second parameter. Update for the above data structure changes.
(backprop::process_block): Update calls to process_var.
(backprop::execute): Likewise. Update for the above data structure
changes.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* gimple-ssa-backprop.cc (backprop::process_var): Don't try to
optimize SSA names that occur as a phi input for an abnormal edge,
moving the restriction from...
(backprop::optimize_phi): ...here.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* gimple-iterator.cc (completely_unused): New function.
(gsi_replace): Allow changes in lhs if the caller has updated
all uses of the old name, including all debug uses.
* gimple-fold.cc (gsi_replace_with_seq_vops): Likewise.
2026-06-02 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.h: Document the complexity of pop_largest aka
bitmap_clear_last_set_bit.
(bitmap_clear_last_set_bit): Declare.
* bitmap.cc (bitmap_last_set_bit_worker): New function,
split out from...
(bitmap_last_set_bit): ...here.
(bitmap_clear_last_set_bit): New function.
2026-06-02 Jonathan Yong <10walls@gmail.com>
Revert:
2026-05-27 oltolm <oleg.tolmatcev@gmail.com>
PR target/54412
* target.def (overaligned_stack_slot_required): New calls hook.
* calls.cc (allocate_call_dynamic_stack_space): New helper.
(initialize_argument_information): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
by-reference argument copies.
(expand_call): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
hidden return slots.
* function.cc (assign_stack_local_aligned): New helper.
(assign_parm_setup_block): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
stack parm slots.
(assign_parm_setup_reg): Likewise.
* config/i386/i386.cc (ix86_overaligned_stack_slot_required): New.
(TARGET_OVERALIGNED_STACK_SLOT_REQUIRED): Define for i386.
* doc/tm.texi.in: Add hook placement.
* doc/tm.texi: Regenerate.
2026-06-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/125545
* tree-ssa-reassoc.cc (insert_stmt_after): Allow asm goto
with a single successor.
2026-06-02 Lino Hsing-Yu Peng <linopeng@andestech.com>
* common/config/riscv/riscv-common.cc: Add zvfofp8min support.
* config/riscv/riscv-ext.def: Add zvfofp8min entry.
* config/riscv/riscv-ext.opt: Add zvfofp8min option.
* config/riscv/riscv-vector-builtins.cc: Require zvfofp8min.
* config/riscv/riscv-vector-builtins.h: Add zvfofp8min handling.
* doc/riscv-ext.texi: Document the new extension.
2026-06-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/125553
* tree-ssa-sccvn.cc (visit_nary_op): Valueize the BIT_FIELD_REF
operand before looking at its definition.
2026-06-02 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-cores.def: Switch xt-c9501fdvt tune to
xt_c9501_tune_info.
* config/riscv/riscv.cc (xt_c9501_vls_vector_cost): New.
(xt_c9501_vla_vector_cost): New.
(xt_c9501_vector_cost): New.
(xt_c9501_tune_info): New.
2026-06-02 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-v.cc (expand_vec_perm): Add missing return
after emit_vlmax_gather_insn.
2026-06-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/125502
* tree-ssa-forwprop.cc (optimize_vector_load): Do not
move defs of abnormals.
2026-06-02 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (crotate): Rename to inv_rotate.
Update all uses accordingly.
2026-06-02 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sol2.h (TARGET_OS_CPP_BUILTINS): Don't define
_XOPEN_SOURCE=600 for C++.
2026-06-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/120702
* gimple-fold.cc (maybe_fold_reference): Only fold
register type reads.
2026-06-02 Jakub Jelinek <jakub@redhat.com>
PR middle-end/125517
* wide-int.cc (wi::bitreverse_large): Rename LEN argument to XLEN and
use it as safe_uhwi argument. Add LEN automatic variable set to
BLOCKS_NEEDED (precision). Replace loop clearing val with memset.
Remove I automatic variable.
2026-06-02 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc: Fix typos in comments.
* config/riscv/andes-25-series.md: Likewise.
* config/riscv/autovec-opt.md: Likewise.
* config/riscv/autovec.md: Likewise.
* config/riscv/bitmanip.md: Likewise.
* config/riscv/constraints.md: Likewise.
* config/riscv/gen-riscv-ext-opt.cc: Likewise.
* config/riscv/gen-riscv-mcpu-texi.cc: Likewise.
* config/riscv/generic-vector-ooo.md: Likewise.
* config/riscv/multilib-generator: Likewise.
* config/riscv/riscv-avlprop.cc: Likewise.
* config/riscv/riscv-ext.def: Likewise.
* config/riscv/riscv-ext.opt: Likewise.
* config/riscv/riscv-modes.def: Likewise.
* config/riscv/riscv-opt-popretz.cc: Likewise.
* config/riscv/riscv-profiles.def: Likewise.
* config/riscv/riscv-protos.h: Likewise.
* config/riscv/riscv-selftests.cc: Likewise.
* config/riscv/riscv-sr.cc: Likewise.
* config/riscv/riscv-string.cc: Likewise.
* config/riscv/riscv-subset.h: Likewise.
* config/riscv/riscv-target-attr.cc: Likewise.
* config/riscv/riscv-v.cc: Likewise.
* config/riscv/riscv-vect-permconst.cc: Likewise.
* config/riscv/riscv-vector-builtins-bases.cc: Likewise.
* config/riscv/riscv-vector-builtins-functions.def: Likewise.
* config/riscv/riscv-vector-builtins-shapes.cc: Likewise.
* config/riscv/riscv-vector-builtins-types.def: Likewise.
* config/riscv/riscv-vector-builtins.cc: Likewise.
* config/riscv/riscv-vector-builtins.def: Likewise.
* config/riscv/riscv-vector-builtins.h: Likewise.
* config/riscv/riscv-vector-costs.cc: Likewise.
* config/riscv/riscv-vector-costs.h: Likewise.
* config/riscv/riscv-vsetvl.cc: Likewise.
* config/riscv/riscv-vsetvl.def: Likewise.
* config/riscv/riscv-zicfilp.cc: Likewise.
* config/riscv/riscv.cc: Likewise.
(riscv_zcmp_valid_stack_adj_bytes_p): Rename misspelled
variable additioanl_bytes to additional_bytes.
* config/riscv/riscv.h: Likewise.
* config/riscv/riscv.md: Likewise.
* config/riscv/sifive-vector-builtins-functions.def: Likewise.
* config/riscv/sifive_vector.h: Likewise.
* config/riscv/spacemit-x60.md: Likewise.
* config/riscv/thead.cc: Likewise.
* config/riscv/tt-ascalon-d8.md: Likewise.
* config/riscv/vector-crypto.md: Likewise.
* config/riscv/vector-iterators.md: Likewise.
* config/riscv/vector.md: Likewise.
* config/riscv/zicond.md: Likewise.
* doc/riscv-mcpu.texi: Regenerate.
2026-06-02 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc: Fix formatting.
* config/riscv/gen-riscv-mcpu-texi.cc: Likewise.
* config/riscv/gen-riscv-mtune-texi.cc: Likewise.
* config/riscv/genrvv-type-indexer.cc: Remove unused <assert.h>
include.
* config/riscv/riscv-string.cc: Fix formatting.
* config/riscv/riscv-target-attr.cc: Likewise.
* config/riscv/riscv-v.cc: Remove duplicate "targhooks.h" include.
Fix formatting.
* config/riscv/riscv-v.h: Fix formatting.
* config/riscv/riscv-vsetvl.cc: Likewise.
* config/riscv/riscv.cc (riscv_pass_by_reference): Remove stray
double semicolon. Fix formatting elsewhere.
(riscv_output_move): Use gcc_unreachable () instead of abort ().
(riscv_save_libcall_count): Use gcc_unreachable () instead of
abort ().
* config/riscv/riscv.h: Fix formatting.
* config/riscv/thead.cc: Likewise.
2026-06-02 Tianle Shi <shitianle@hygon.cn>
* config/i386/i386.cc (ix86_vector_costs): Add
m_num_avx512_vec_perm.
(ix86_vector_costs::ix86_vector_costs): Initialize it.
(ix86_count_cross_lane_perm_p): New helper to classify
cross-lane vec_perm for AVX256 and AVX512 handling.
(ix86_vector_costs::add_stmt_cost): Use the helper for
vec_perm accounting, record 256-bit and 512-bit counts,
and print detected width as avx%u.
(ix86_vector_costs::finish_cost): Reject AVX512 costs
when TARGET_AVX512_AVOID_VEC_PERM is set and 512-bit
cross-lane vec_perm is present.
* config/i386/i386.h (TARGET_AVX512_AVOID_VEC_PERM):
New macro.
* config/i386/x86-tune.def (X86_TUNE_AVX512_AVOID_VEC_PERM):
New tune for c86-4g-m7.
2026-06-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/125558
* common.opt (Wstrict-overflow): Mark as Ignore.
(Wstrict-overflow=): Fix up and mark as igore.
* gcc-diagnostic-spec.cc (nowarn_spec_t::nowarn_spec_t):
Remove OPT_Wstrict_overflow.
* opts.cc (common_handle_option): Likewise.
2026-06-01 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/122827
* config/aarch64/aarch64.cc (aarch64_hard_regno_call_part_clobbered):
For SVE modes use BYTES_PER_SVE_VECTOR for the per-register size
rather than GET_MODE_SIZE.
* config/aarch64/aarch64-early-ra.cc (early_ra::get_allocno_subgroup):
Classify any SVE mode as FPR_Z.
2026-06-01 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/tuning_models/olympus.h (olympus_scalar_issue_info,
olympus_advsimd_issue_info, olympus_sve_issue_info): Set
loads_stores_per_cycle to 6.
2026-06-01 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/tuning_models/olympus.h (olympus_tunings):
Adjust loop_align, function_align, jump_align.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/arm/arm-mve-builtins-shapes.cc (struct viddup_def):
Re-flow comment.
(struct vidwdup_def): Likewise.
* config/arm/arm.cc (arm_mve_check_reg_origin_is_num_elems): Likewise.
* config/loongarch/sync.md: Likewise.
* config/microblaze/microblaze.cc (compute_frame_size): Likewise.
* config/rs6000/rs6000-call.cc (rs6000_gimplify_va_arg): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/darwin-c.cc (find_subframework_header): Fix typos.
* config/darwin-driver.cc (darwin_find_version_from_kernel): Likewise.
* config/darwin.cc (darwin_label_is_anonymous_local_objc_name): Likewise.
(fprintf): Likewise.
* config/sol2-stubs.cc: Likewise.
* config/sol2.cc (solaris_elf_asm_comdat_section): Likewise.
* config/sol2.h: Likewise.
* config/vx-common.h: Likewise.
* config/vxworks.h (vxworks_asm_out_destructor): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/xtensa/xtensa.cc (xtensa_legitimize_address): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/vms/vms-c.cc (enum extern_model_kind): Fix typos.
(vms_pragma_message): Likewise.
(vms_c_register_includes): Likewise.
* config/vms/vms.cc (vms_function_section): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/visium/visium.h (CASE_VECTOR_PC_RELATIVE): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/vax/vax.cc (vax_expand_addsub_di_operands): Fix typos.
* config/vax/vax.h (PRINT_OPERAND_ADDRESS): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/sparc/freebsd.h: Fix typos.
* config/sparc/sparc.cc (emit_scc_insn): Likewise.
(sparc_emit_membar_for_model): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/sh/sh-mem.cc (sh_expand_cmpstr): Fix typos.
* config/sh/sh.cc (sh_option_override): Likewise.
(sh_rtx_costs): Likewise.
(fixup_addr_diff_vecs): Likewise.
(sh_expand_epilogue): Likewise.
(sh_legitimize_address_displacement): Likewise.
(sh_can_use_simple_return_p): Likewise.
(sh_find_equiv_gbr_addr): Likewise.
(sh_check_add_incdec_notes): Likewise.
* config/sh/sh.md: Likewise.
* config/sh/sh4-300.md: Likewise.
* config/sh/sh_treg_combine.cc (sh_treg_combine::try_combine_comparisons): Likewise.
(sh_treg_combine::try_eliminate_cstores): Likewise.
* config/sh/sync.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/rx/rx.cc (rx_print_operand): Fix typos.
(rx_expand_epilogue): Likewise.
* config/rx/rx.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/s390/2817.md: Fix typos.
* config/s390/s390.cc (s390_contiguous_bitmask_nowrap_p): Likewise.
(s390_contiguous_bitmask_p): Likewise.
(s390_short_displacement): Likewise.
(s390_expand_cmpmem): Likewise.
(s390_expand_vec_movstr): Likewise.
(s390_expand_cstoreti4): Likewise.
(s390_expand_int_spaceship): Likewise.
(s390_z10_optimize_cmp): Likewise.
(s390_support_vector_misalignment): Likewise.
* config/s390/s390.h (NO_FUNCTION_CSE): Likewise.
* config/s390/s390.md: Likewise.
* config/s390/subst.md: Likewise.
* config/s390/vx-builtins.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/rs6000/aix.h: Fix typos.
* config/rs6000/cell.md: Likewise.
* config/rs6000/darwin.h: Likewise.
* config/rs6000/mmintrin.h: Likewise.
* config/rs6000/rs6000-call.cc (rs6000_gimplify_va_arg): Likewise.
* config/rs6000/rs6000-internal.h: Likewise.
* config/rs6000/rs6000-logue.cc (is_altivec_return_reg): Likewise.
(rs6000_output_function_prologue): Likewise.
* config/rs6000/rs6000-p8swap.cc (quad_aligned_store_p): Likewise.
(const_load_sequence_p): Likewise.
(replace_swapped_aligned_store): Likewise.
* config/rs6000/rs6000-passes.def: Likewise.
* config/rs6000/rs6000-string.cc (expand_cmp_vec_sequence): Likewise.
(expand_compare_loop): Likewise.
* config/rs6000/rs6000.cc (rs6000_debug_addr_mask): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(darwin_rs6000_override_options): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_cost_data::determine_suggested_unroll_factor): Likewise.
(rs6000_cannot_force_const_mem): Likewise.
(rs6000_emit_le_vsx_move): Likewise.
(rs6000_secondary_reload_memory): Likewise.
(rs6000_reverse_condition): Likewise.
(rs6000_expand_float128_convert): Likewise.
(rs6000_adjust_atomic_subword): Likewise.
(rs6000_expand_atomic_op): Likewise.
(rs6000_xcoff_declare_object_name): Likewise.
(output_pcrel_opt_reloc): Likewise.
(rs6000_set_up_by_prologue): Likewise.
(rs6000_split_logical_inner): Likewise.
(rs6000_split_multireg_move): Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/rs6000/rs6000.md: Likewise.
* config/rs6000/sync.md: Likewise.
* config/rs6000/vector.md: Likewise.
* config/rs6000/vsx.md: Likewise.
* config/rs6000/vxworks.h: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/rl78/rl78.cc (rl78_alloc_physical_registers): Fix typos.
(set_origin): Likewise.
(rl78_remove_unused_sets): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/pdp11/pdp11.cc (pdp11_insn_cost): Fix typo.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* common/config/riscv/riscv-common.cc (riscv_subset_list::add): Fix
typos.
(riscv_subset_list::parse_single_multiletter_ext): Likewise.
(riscv_subset_list::set_loc): Likewise.
(riscv_arch_str): Likewise.
* config/riscv/riscv-avlprop.cc: Likewise.
* config/riscv/riscv-bclr-lowest-set-bit.cc (find_later_ctz): Likewise.
* config/riscv/riscv-ext-andes.def: Likewise.
* config/riscv/riscv-ext.def: Likewise.
* config/riscv/riscv-profiles.def: Likewise.
* config/riscv/riscv-selftests.cc (run_const_vector_selftests): Likewise.
(run_broadcast_selftests): Likewise.
(riscv_run_selftests): Likewise.
* config/riscv/riscv-string.cc (riscv_expand_strcmp): Likewise.
* config/riscv/riscv-v.cc (shuffle_decompress_patterns): Likewise.
(vls_mode_valid_p): Likewise.
* config/riscv/riscv-vect-permconst.cc (vector_permconst::process_bb): Likewise.
* config/riscv/riscv-vector-builtins.cc (riscv_pragma_intrinsic_flags_pollute): Likewise.
* config/riscv/riscv-vsetvl.cc: Likewise.
* config/riscv/riscv-zicfilp.cc: Likewise.
* config/riscv/riscv.cc (riscv_expand_mult_with_const_int): Likewise.
(riscv_rtx_costs): Likewise.
(riscv_address_cost): Likewise.
(riscv_vls_cc_function_abi): Likewise.
(riscv_frm_mode_needed): Likewise.
(dispatch_function_versions): Likewise.
* config/riscv/riscv.h (DWARF_REG_TO_UNWIND_COLUMN): Likewise.
* config/riscv/riscv.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/pa/pa.cc (pa_assemble_integer): Fix typos.
(pa_can_change_mode_class): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/or1k/or1k.cc (or1k_strict_argument_naming): Fix typos.
(or1k_print_operand_address): Likewise.
* config/or1k/or1k.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/nvptx/nvptx.cc (nvptx_option_override): Fix typos.
(nvptx_assemble_undefined_decl): Likewise.
(nvptx_mem_maybe_shared_p): Likewise.
(nvptx_discover_pars): Likewise.
(verify_neutering_labels): Likewise.
(nvptx_condjump_label): Likewise.
(nvptx_lockfull_update): Likewise.
* config/nvptx/nvptx.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* common/config/nds32/nds32-common.cc (nds32_except_unwind_info): Fix
typos.
* config/nds32/constants.md: Likewise.
* config/nds32/constraints.md: Likewise.
* config/nds32/nds32-cost.cc (nds32_rtx_costs_speed_prefer): Likewise.
* config/nds32/nds32-dspext.md: Likewise.
* config/nds32/nds32-e8.md: Likewise.
* config/nds32/nds32-fp-as-gp.cc (nds32_fp_as_gp_check_available): Likewise.
* config/nds32/nds32-intrinsic.cc (nds32_expand_priority_builtin): Likewise.
* config/nds32/nds32-isr.cc (nds32_emit_isr_vector_section): Likewise.
(nds32_asm_file_end_for_isr): Likewise.
* config/nds32/nds32-md-auxiliary.cc (output_cond_branch): Likewise.
(nds32_expand_cbranch): Likewise.
(nds32_expand_float_cstore): Likewise.
(nds32_expand_movcc): Likewise.
(nds32_output_stack_pop): Likewise.
(nds32_output_return): Likewise.
(nds32_split_sms): Likewise.
(nds32_legitimize_tls_address): Likewise.
* config/nds32/nds32-memory-manipulation.cc (nds32_expand_cpymemsi_unroll): Likewise.
(nds32_expand_load_multiple): Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-n7.md: Likewise.
* config/nds32/nds32-n8.md: Likewise.
* config/nds32/nds32-n9-2r1w.md: Likewise.
* config/nds32/nds32-pipelines-auxiliary.cc (extract_nth_access_reg): Likewise.
(pbsada_insn_ra_rb_dep_reg_p): Likewise.
* config/nds32/nds32-predicates.cc (nds32_can_use_bset_p): Likewise.
(nds32_can_use_btgl_p): Likewise.
(nds32_symbol_load_store_p): Likewise.
* config/nds32/nds32-protos.h (nds32_cond_move_p): Likewise.
(nds32_mem_format): Likewise.
* config/nds32/nds32-relax-opt.cc (nds32_plus_reg_load_store_p): Likewise.
* config/nds32/nds32-utils.cc (extract_offset_rtx): Likewise.
* config/nds32/nds32.cc (nds32_compute_stack_frame): Likewise.
(nds32_emit_stack_pop_multiple): Likewise.
(nds32_emit_stack_v3pop): Likewise.
(nds32_can_change_mode_class): Likewise.
(nds32_arg_partial_bytes): Likewise.
(nds32_function_ok_for_sibcall): Likewise.
(nds32_register_move_cost): Likewise.
(nds32_print_operand): Likewise.
(nds32_merge_decl_attributes): Likewise.
(nds32_insert_attributes): Likewise.
(nds32_init_libfuncs): Likewise.
(nds32_expand_epilogue_v3pop): Likewise.
(nds32_can_use_return_insn): Likewise.
(nds32_target_alignment): Likewise.
(nds32_split_double_word_load_store_p): Likewise.
* config/nds32/nds32.h (enum nds32_builtins): Likewise.
(CASE_VECTOR_MODE): Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/nds32_intrinsic.h (__attribute__): Likewise.
* config/nds32/nds32_isr.h: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/msp430/msp430-opts.h (enum msp430_cpu_types): Fix typos.
* config/msp430/msp430.cc (msp430_op_not_in_high_mem): Likewise.
* config/msp430/msp430.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/mingw/winnt-cxx.cc (i386_pe_adjust_class_at_definition): Fix
typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/microblaze/microblaze.cc (struct microblaze_frame_info): Fix
typos.
(compute_frame_size): Likewise.
* config/microblaze/microblaze.h: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/mcore/mcore.h: Fix typo.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/mips/driver-native.cc (host_detect_local_cpu): Fix typos.
* config/mips/mips-cpus.def (MIPS_CPU): Likewise.
* config/mips/mips.cc (mips_setup_incoming_varargs): Likewise.
(mips_function_ok_for_sibcall): Likewise.
(mips_expand_ext_as_unaligned_load): Likewise.
(mips_use_ins_ext_p): Likewise.
(mips_pop_asm_switch): Likewise.
(mips_cfun_has_inflexible_gp_ref_p): Likewise.
(mips_set_compression_mode): Likewise.
(mips_expand_vec_unpack): Likewise.
* config/mips/mips.h (while): Likewise.
* config/mips/mips.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/m68k/cf.md: Fix typos.
* config/m68k/m68k.cc (m68k_unwrap_symbol): Likewise.
(m68k_adjust_decorated_operand): Likewise.
(m68k_call_tls_get_addr): Likewise.
(m68k_call_m68k_read_tp): Likewise.
(m68k_sched_attr_size): Likewise.
(m68k_sched_dfa_post_advance_cycle): Likewise.
(sched_mem_operand_p): Likewise.
(m68k_sched_address_bypass_p): Likewise.
* config/m68k/m68kelf.h: Likewise.
* config/m68k/netbsd-elf.h (REGISTER_PREFIX): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/loongarch/lasx.md: Fix typos.
* config/loongarch/loongarch-builtins.cc: Likewise.
* config/loongarch/loongarch-c.cc (loongarch_pragma_target_parse): Likewise.
* config/loongarch/loongarch-opts.cc (loongarch_generate_mrecip_scheme): Likewise.
* config/loongarch/loongarch-opts.h (loongarch_config_target): Likewise.
* config/loongarch/loongarch.cc (loongarch_setup_incoming_varargs): Likewise.
(loongarch_build_integer): Likewise.
(loongarch_explicit_relocs_p): Likewise.
(loongarch_valid_lo_sum_p): Likewise.
(loongarch_addu16i_imm12_operand_p): Likewise.
(loongarch_rewrite_mem_for_simple_ldst): Likewise.
(loongarch_is_elem_duplicate): Likewise.
(loongarch_expand_vec_perm_const): Likewise.
(loongarch_sched_reassociation_width): Likewise.
(loongarch_expand_vec_unpack): Likewise.
(dispatch_function_versions): Likewise.
(loongarch_option_same_function_versions): Likewise.
* config/loongarch/loongarch.h: Likewise.
* config/loongarch/loongarch.md: Likewise.
* config/loongarch/lsx.md: Likewise.
* config/loongarch/predicates.md: Likewise.
* config/loongarch/simd.md: Likewise.
* config/loongarch/sync.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/lm32/lm32.cc (lm32_compute_frame_size): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/ia64/ia64.cc (ia64_add_bundle_selector_before): Fix typos.
* config/ia64/itanium2.md: Likewise.
* config/ia64/sync.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/i386/athlon.md: Fix typos.
* config/i386/avx512fintrin.h: Likewise.
* config/i386/btver2.md: Likewise.
* config/i386/c86-4g-m7.md: Likewise.
* config/i386/c86-4g.md: Likewise.
* config/i386/cygwin.h: Likewise.
* config/i386/i386-c.cc (ix86_target_macros_internal): Likewise.
* config/i386/i386-expand.cc (ix86_expand_branch): Likewise.
(ix86_expand_int_sse_cmp): Likewise.
(ix86_expand_vec_perm): Likewise.
(expand_small_cpymem_or_setmem): Likewise.
(ix86_copy_addr_to_reg): Likewise.
(ix86_expand_special_args_builtin): Likewise.
(ix86_expand_vector_init_interleave): Likewise.
(expand_vec_perm_shufps_shufps): Likewise.
(ix86_expand_sse2_mulvxdi3): Likewise.
(ix86_gen_ccmp_first): Likewise.
* config/i386/i386-features.cc (general_scalar_to_vector_candidate_p): Likewise.
(pass_x86_cse::x86_cse): Likewise.
(ix86_apx_nf_convert): Likewise.
(dispatch_function_versions): Likewise.
* config/i386/i386-features.h (class scalar_chain): Likewise.
* config/i386/i386-options.cc (ix86_function_specific_restore): Likewise.
(ix86_valid_target_attribute_tree): Likewise.
(ix86_override_options_after_change_1): Likewise.
(ix86_option_override_internal): Likewise.
* config/i386/i386.cc (ix86_can_inline_p): Likewise.
(ix86_function_regparm): Likewise.
(construct_container): Likewise.
(ix86_return_in_memory): Likewise.
(output_indirect_thunk): Likewise.
(ix86_compute_frame_layout): Likewise.
(choose_basereg): Likewise.
(ix86_emit_save_reg_using_mov): Likewise.
(pro_epilogue_adjust_stack): Likewise.
(ix86_expand_prologue): Likewise.
(ix86_emit_restore_sse_regs_using_mov): Likewise.
(ix86_memory_address_reg_class): Likewise.
(ix86_avx_u128_mode_after): Likewise.
(ix86_output_addr_diff_elt): Likewise.
(ix86_lea_outperforms): Likewise.
(ix86_avoid_lea_for_addr): Likewise.
(ix86_cc_modes_compatible): Likewise.
(add_parameter_dependencies): Likewise.
(ix86_data_alignment): Likewise.
(ix86_gimple_fold_builtin): Likewise.
(ix86_autovectorize_vector_modes): Likewise.
(ix86_max_noce_ifcvt_seq_cost): Likewise.
(ix86_vector_costs::add_stmt_cost): Likewise.
(ix86_vector_costs::finish_cost): Likewise.
(ix86_optab_supported_p): Likewise.
(ix86_push_rounding): Likewise.
* config/i386/i386.h (host_detect_local_cpu): Likewise.
(enum reg_class): Likewise.
* config/i386/i386.md: Likewise.
* config/i386/i386elf.h: Likewise.
* config/i386/predicates.md: Likewise.
* config/i386/sse.md: Likewise.
* config/i386/x86-tune-costs.h (struct processor_costs): Likewise.
* config/i386/x86-tune-sched-atom.cc (swap_top_of_ready_list): Likewise.
(ix86_atom_sched_reorder): Likewise.
* config/i386/x86-tune-sched-bd.cc (find_constant): Likewise.
* config/i386/x86-tune-sched.cc (exact_store_load_dependency): Likewise.
* config/i386/x86-tune.def (X86_TUNE_FUSE_MOV_AND_ALU): Likewise.
(X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Likewise.
(X86_TUNE_DOUBLE_WITH_ADD): Likewise.
(X86_TUNE_PROMOTE_QIMODE): Likewise.
* config/i386/zn4zn5.md: Likewise.
* config/i386/znver.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/gcn/constraints.md: Fix typos.
* config/gcn/gcn-opts.h (TARGET_ARCHITECTED_FLAT_SCRATCH): Likewise.
* config/gcn/gcn-valu.md: Likewise.
* config/gcn/gcn.cc (gcn_gen_undef): Likewise.
(gcn_addr_space_debug): Likewise.
(gcn_expand_prologue): Likewise.
(gcn_frame_pointer_rqd): Likewise.
* config/gcn/gcn.h (NUM_PARM_REGS): Likewise.
(enum gcn_builtin_codes): Likewise.
* config/gcn/gcn.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/ft32/ft32.cc (ft32_init_machine_status): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/frv/frv-opts.h: Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/fr30/fr30.cc (fr30_const_double_is_zero): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/epiphany/epiphany.cc (epiphany_expand_epilogue): Fix typos.
* config/epiphany/resolve-sw-modes.cc: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/csky/csky.cc (csky_output_inline_const): Fix typos.
(emit_csky_regs_pop): Likewise.
(csky_return_in_memory): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/c6x/c6x.cc (c6x_file_start): Fix typos.
(c6x_print_operand_address): Likewise.
(c6x_asm_emit_except_personality): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/bpf/bpf.cc (bpf_asm_named_section): Fix typos.
* config/bpf/core-builtins.cc (remove_parser_plugin): Likewise.
(make_core_relo): Likewise.
(bpf_handle_plugin_finish_type): Likewise.
(bpf_output_core_reloc): Likewise.
(core_make_builtins): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/bfin/bfin.cc (bfin_function_ok_for_sibcall): Fix typos.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* common/config/avr/avr-common.cc: Fix typos.
* config/avr/avr-passes.cc (size_to_mode): Likewise.
(struct absint_t): Likewise.
(plies_t::emit_sets): Likewise.
(avr_strict_unsigned_p): Likewise.
(avr_redundant_compare): Likewise.
(avr_optimize_casesi): Likewise.
(struct AVR_LdSt_Props): Likewise.
(avr_pass_split_nzb::split_nzb_insns): Likewise.
(make_avr_pass_fuse_move): Likewise.
* config/avr/avr.cc (avr_option_override): Likewise.
(avr_can_inline_p): Likewise.
(avr_expand_epilogue): Likewise.
(avr_init_cumulative_args): Likewise.
(reg_unused_after): Likewise.
(avr_out_lpm_no_lpmx): Likewise.
(avr_out_compare): Likewise.
(avr_out_plus_ext): Likewise.
(avr_out_fract): Likewise.
(avr_nonzero_bits_lsr_operands_p): Likewise.
* config/avr/avr.h (avr_no_devlib): Likewise.
(struct machine_function): Likewise.
* config/avr/avr.md: Likewise.
* config/avr/builtins.def (FLASH_SEGMENT): Likewise.
* config/avr/specs.h: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* common/config/arm/arm-common.cc (arm_config_default): Fix typos.
(arm_canon_arch_option_1): Likewise.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Likewise.
* config/arm/arm-builtins.cc (MAC_LANE_PAIR_QUALIFIERS): Likewise.
(USMAC_LANE_QUADTUP_QUALIFIERS): Likewise.
* config/arm/arm-modes.def (ADJUST_FLOAT_FORMAT): Likewise.
* config/arm/arm-mve-builtins-base.cc: Likewise.
* config/arm/arm-mve-builtins-shapes.cc (struct binary_lshift_unsigned_def): Likewise.
(struct binary_maxamina_def): Likewise.
(struct viddup_def): Likewise.
(struct vidwdup_def): Likewise.
* config/arm/arm-protos.h (struct tune_params): Likewise.
* config/arm/arm.cc (arm_option_override_internal): Likewise.
(arm_option_override): Likewise.
(optimal_immediate_sequence_1): Likewise.
(arm_pcs_from_attribute): Likewise.
(aapcs_vfp_advance): Likewise.
(aapcs_layout_arg): Likewise.
(arm_init_cumulative_args): Likewise.
(arm_rtx_costs_internal): Likewise.
(mve_bool_vec_to_const): Likewise.
(operands_ok_ldrd_strd): Likewise.
(emit_multi_reg_push): Likewise.
(arm_emit_vfp_multi_reg_pop): Likewise.
(thumb2_emit_ldrd_pop): Likewise.
(arm_print_condition): Likewise.
(get_arm_condition_code): Likewise.
(thumb_pop): Likewise.
(arm_print_asm_arch_directives): Likewise.
(arm_debugger_regno): Likewise.
(arm_target_bb_ok_for_lob): Likewise.
(arm_mve_load_store_insn_p): Likewise.
(arm_mve_check_reg_origin_is_num_elems): Likewise.
(arm_mve_dlstp_check_dec_counter): Likewise.
(arm_mve_loop_valid_for_dlstp): Likewise.
(arm_loop_unroll_adjust): Likewise.
* config/arm/arm.h (ROUND_UP_WORD): Likewise.
* config/arm/arm.md: Likewise.
* config/arm/constraints.md: Likewise.
* config/arm/cortex-a17-neon.md: Likewise.
* config/arm/cortex-r4f.md: Likewise.
* config/arm/crypto.md: Likewise.
* config/arm/elf.h: Likewise.
* config/arm/fa726te.md: Likewise.
* config/arm/iterators.md: Likewise.
* config/arm/neon.md: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/uclinuxfdpiceabi.h: Likewise.
* config/arm/unspecs.md: Likewise.
* config/arm/vec-common.md: Likewise.
* config/arm/vxworks.h (STACK_CHECK_PROTECT): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/arc/arc-arch.h (enum base_architecture): Fix typos.
* config/arc/arc-cpus.def: Likewise.
* config/arc/arc.cc (legitimate_small_data_address_p): Likewise.
(legitimate_scaled_address_p): Likewise.
(get_arc_condition_code): Likewise.
(arc_setup_incoming_varargs): Likewise.
(pop_reg): Likewise.
(arc_restore_callee_leave): Likewise.
(arc_asm_trampoline_template): Likewise.
(arc_add_jli_section): Likewise.
(arc_invalid_within_doloop): Likewise.
(arc_reorg): Likewise.
(conditionalize_nonjump): Likewise.
(arc_eh_uses): Likewise.
(arc_memory_move_cost): Likewise.
* config/arc/arc.h (TARGET_CPU_CPP_BUILTINS): Likewise.
(TARGET_PAD_RETURN): Likewise.
(arc_select_cc_mode): Likewise.
* config/arc/arc.md: Likewise.
* config/arc/arc.opt: Likewise.
* config/arc/arc700.md: Likewise.
* config/arc/elf.h (TARGET_ASM_FILE_END): Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* config/alpha/alpha.cc (alpha_pass_by_reference): Fix typos.
(alpha_reorg): Likewise.
* config/alpha/predicates.md: Likewise.
2026-06-01 Dhruv Chawla <dhruvc@nvidia.com>
* common/config/aarch64/aarch64-common.cc (aarch64_parse_cpu): Fix
typos.
* common/config/aarch64/cpuinfo.h: Likewise.
* config/aarch64/aarch64-builtins.cc: Likewise.
* config/aarch64/aarch64-c.cc (aarch64_pragma_target_parse): Likewise.
* config/aarch64/aarch64-modes.def (FLOAT_MODE): Likewise.
* config/aarch64/aarch64-simd.md: Likewise.
* config/aarch64/aarch64-speculation.cc: Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h: Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.cc (struct binary_za_m_def): Likewise.
* config/aarch64/aarch64-sve-builtins.cc (function_builder::add_function): Likewise.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/aarch64.cc (aarch64_init_sysregs): Likewise.
(aarch64_load_symref_appropriately): Likewise.
(aarch64_output_sve_cnt_immediate): Likewise.
(aarch64_replace_reg_mode): Likewise.
(aarch64_pass_by_reference_1): Likewise.
(aarch64_layout_arg): Likewise.
(aarch64_allocate_and_probe_stack_space): Likewise.
(aarch64_legitimize_address_displacement): Likewise.
(aarch64_output_casesi): Likewise.
(aarch64_stp_sequence_cost): Likewise.
(aarch64_vector_costs::add_stmt_cost): Likewise.
(aarch64_override_options): Likewise.
(aarch64_functions_b_resolvable_from_a): Likewise.
(dispatch_function_versions): Likewise.
(aarch64_can_inline_p): Likewise.
(aarch64_classify_symbol): Likewise.
(aarch64_build_builtin_va_list): Likewise.
(aarch64_sve_pred_valid_immediate): Likewise.
(aarch64_simd_lane_bounds): Likewise.
(aarch64_expand_vector_init_fallback): Likewise.
(aarch64_modes_compatible_p): Likewise.
(aarch64_ldrstr_offset_compare): Likewise.
(aarch64_speculation_safe_value): Likewise.
* config/aarch64/aarch64.h (DEFAULT_PCC_STRUCT_RETURN): Likewise.
(struct GTY): Likewise.
* config/aarch64/aarch64.md: Likewise.
* config/aarch64/aarch64.opt: Likewise.
* config/aarch64/arm_bf16.h: Likewise.
* config/aarch64/arm_neon.h (vbslq_u64): Likewise.
* config/aarch64/cortex-a57-fma-steering.cc: Likewise.
* config/aarch64/driver-aarch64.cc (get_cpu_from_id): Likewise.
(host_detect_local_cpu): Likewise.
* config/aarch64/iterators.md: Likewise.
* config/aarch64/thunderx.md: Likewise.
* config/aarch64/thunderx3t110.md: Likewise.
2026-06-01 Jakub Jelinek <jakub@redhat.com>
* configure: Regenerate.
2026-06-01 Hongyu Wang <hongyu.wang@intel.com>
* config/i386/i386.h (TARGET_ENABLE_NDD_MEM): New.
* config/i386/x86-tune.def (X86_TUNE_ENABLE_NDD_MEM): New.
* config/i386/i386.md (*add<dwi>3_doubleword): Split NDD rm
to r,m and add preferred_for_speed for NDD memory alternatives.
(*add<dwi>3_doubleword_zext): Likewise.
(*add<mode>_1<nf_name>): Likewise.
(addsi_1_zext): Likewise.
(*addhi_1<nf_name>): Likewise.
(*addqi_1<nf_name>): Likewise.
(*add<mode>_2): Likewise.
(*addsi_2_zext): Likewise.
(*add<mode>_3): Likewise.
(*addsi_3_zext): Likewise.
(*add<mode>_5): Likewise.
(*addv<mode>4): Likewise.
(addv<mode>4_1): Likewise.
(*addv<dwi>4_doubleword_1): Likewise.
(*addv<mode>4_overflow_1): Likewise.
(*addv<mode>4_overflow_2): Likewise.
(*sub<dwi>3_doubleword): Likewise.
(*sub<dwi>3_doubleword_zext): Likewise.
(*sub<mode>_1<nf_name>): Likewise.
(*subsi_1_zext): Likewise.
(*sub<mode>_2): Likewise.
(*subsi_2_zext): Likewise.
(*subv<mode>4): Likewise.
(subv<mode>4_1): Likewise.
(*subv<dwi>4_doubleword_1): Likewise.
(*subv<mode>4_overflow_1): Likewise.
(*subv<mode>4_overflow_2): Likewise.
(*sub<mode>_3): Likewise.
(*subsi_3_zext): Likewise.
(@add<mode>3_carry): Likewise.
(*add<mode>3_carry_2): Likewise.
(*addsi3_carry_zext): Likewise.
(*addsi3_carry_zext_0): Likewise.
(*addsi3_carry_zext_0r): Likewise.
(addcarry<mode>): Likewise.
(*addcarry<mode>_1): Likewise.
(@sub<mode>3_carry): Likewise.
(*sub<mode>3_carry_2): Likewise.
(*subsi3_carry_zext): Likewise.
(*subsi3_carry_zext_0): Likewise.
(*subsi3_carry_zext_0r): Likewise.
(subborrow<mode>): Likewise.
(*subborrow<mode>_1): Likewise.
(*add<mode>3_cconly_overflow_1): Likewise.
(@add<mode>3_cc_overflow_1): Likewise.
(*addsi3_zext_cc_overflow_1): Likewise.
(*add<mode>3_cconly_overflow_2): Likewise.
(*add<mode>3_cc_overflow_2): Likewise.
(*addsi3_zext_cc_overflow_2): Likewise.
(*mul<mode>3_1<nf_name>): Likewise.
(*mulsi3_1_zext<nf_name>): Likewise.
(*mulv<mode>4): Likewise.
(*mulvhi4): Likewise.
(*and<dwi>3_doubleword): Likewise.
(*anddi_1<nf_name>): Likewise.
(*andsi_1_zext): Likewise.
(*andqi_1<nf_name>): Likewise.
(*anddi_2): Likewise.
(*andsi_2_zext): Likewise.
(*andqi_2_maybe_si): Likewise.
(*and<mode>_2): Likewise.
(*<code><dwi>3_doubleword): Likewise.
(*<code><mode>_1<nf_name>): Likewise.
(*notxor<mode>_1): Likewise.
(*<code>si_1_zext): Likewise.
(*<code>si_1_zext_imm): Likewise.
(*<code>qi_1<nf_name>): Likewise.
(*notxorqi_1): Likewise.
(*<code><mode>_2): Likewise.
(*<code>si_2_zext): Likewise.
(*<code>si_2_zext_imm): Likewise.
(*neg<dwi>2_doubleword): Likewise.
(*neg<mode>_1<nf_name>): Likewise.
(*negsi_1_zext): Likewise.
(*neg<mode>_2): Likewise.
(*negsi_2_zext): Likewise.
(*neg<mode>_ccc_1): Likewise.
(*neg<mode>_ccc_2): Likewise.
(*one_cmpl<dwi>2_doubleword): Likewise.
(*one_cmpl<mode>2_1): Likewise.
(*one_cmplsi2_1_zext): Likewise.
(*one_cmplqi2_1): Likewise.
(*one_cmpl<mode>2_2): Likewise.
(*one_cmplsi2_2_zext): Likewise.
(*ashl<dwi>3_doubleword_highpart): Likewise.
(*ashl<mode>3_1<nf_name>): Likewise.
(*ashlsi3_1_zext): Likewise.
(*ashlhi3_1<nf_name>): Likewise.
(*ashlqi3_1<nf_name>): Likewise.
(*ashl<mode>3_cmp): Likewise.
(*ashlsi3_cmp_zext): Likewise.
(*ashl<mode>3_cconly): Likewise.
(ashr<mode>3_cvt<nf_name>): Likewise.
(*ashrsi3_cvt_zext): Likewise.
(*ashr<mode>3_1<nf_name>): Likewise.
(*highpartdisi2): Likewise.
(*lshr<mode>3_1<nf_name>): Likewise.
(*<insn>si3_1_zext): Likewise.
(*lshrqi3_1<nf_name>): Likewise.
(*lshrhi3_1<nf_name>): Likewise.
(*<insn><mode>3_cmp): Likewise.
(*<insn>si3_cmp_zext): Likewise.
(*<insn><mode>3_cconly): Likewise.
(*<insn><mode>3_1<nf_name>): Likewise.
(*<insn>si3_1_zext): Likewise.
(rcrsi2): Likewise.
(rcrdi2): Likewise.
(<insn><mode>3_carry): Likewise.
(*mov<mode>cc_noc): Likewise.
(*movsicc_noc_zext): Likewise.
(*movsicc_noc_zext_1): Likewise.
(*addqi3_carry_zext<mode>_0): Likewise.
(*addhi3_carry_zext<mode>_0): Likewise.
(*addqi3_carry_zext<mode>_0r): Likewise.
(*addhi3_carry_zext<mode>_0r): Likewise.
(*subqi3_carry_zext<mode>_0): Likewise.
(*subhi3_carry_zext<mode>_0): Likewise.
(*subqi3_carry_zext<mode>_0r): Likewise.
(*subhi3_carry_zext<mode>_0r): Likewise.
(*negqi_1_zext<mode><nf_name>): Likewise.
(*neghi_1_zext<mode><nf_name>): Likewise.
(*one_cmplqi2_1_zext<mode>): Likewise.
(*one_cmplhi2_1_zext<mode>): Likewise.
(x86_64_shld_ndd<nf_name>): Likewise.
(x86_64_shld_ndd_1<nf_name>): Likewise.
(x86_shld_ndd<nf_name>): Likewise.
(x86_shld_ndd_1<nf_name>): Likewise.
(*ashlqi3_1_zext<mode><nf_name>): Likewise.
(*ashlhi3_1_zext<mode><nf_name>): Likewise.
(x86_64_shrd_ndd<nf_name>): Likewise.
(x86_64_shrd_ndd_1<nf_name>): Likewise.
(x86_shrd_ndd<nf_name>): Likewise.
(x86_shrd_ndd_1<nf_name>): Likewise.
(*<insn>qi3_1_zext<mode><nf_name>): Likewise.
(*<insn>hi3_1_zext<mode><nf_name>): Likewise.
* config/i386/sse.md
(*kortest_cmp<mode>_mov<mode>cc): Add
preferred_for_speed for NDD memory alternatives.
2026-06-01 Hongyu Wang <hongyu.wang@intel.com>
* config/i386/x86-tune.def (X86_TUNE_DISABLE_SETZUCC): New.
Enable for m_DIAMONDRAPIDS | m_NOVALAKE.
* config/i386/i386.h (TARGET_DISABLE_SETZUCC): New define.
* config/i386/i386.md (*setcc_<mode>_zu): Guard with
TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC.
(*setcc_di_1, *setcc_<mode>_1_movzbl): Guard with
(!TARGET_APX_ZU || TARGET_DISABLE_SETZUCC).
(*setcc_qi, *setcc_qi_slp): Emit setzucc only when
TARGET_APX_ZU && !TARGET_DISABLE_SETZUCC.
2026-06-01 Martin Liska <martin.liska@hey.com>
* configure.ac: Declare Wild as capable of LTO bootstrap.
* configure: Regenerate.
2026-05-31 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/23471
PR tree-optimization/125513
* range-op-mixed.h (operator_mult): Add op1_op2_relation_effect
for 2xirange.
* range-op.cc (operator_mult::op1_op2_relation_effect): New function.
2026-05-31 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/123313
* ifcvt.cc (noce_try_store_flag_logical): New function.
(noce_process_if_block): Call it.
2026-05-31 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Options): Fix overly long URLs.
* doc/extend.texi (Specifying the size of an asm on AVR): Dito.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* common.opt: Updated Wstrict-overflow entries to indicate that
they do nothing now.
* coretypes.h (enum warn_strict_overflow_code): Enum removed.
* doc/invoke.texi: Updated Wstrict-overflow entries to indicate
that they do nothing now. Also removed the option from the
"Warning Options" list.
* opts.cc (common_handle_option): Removed OPT_Wstrict_overflow
logic.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* flags.h (issue_strict_overflow_warning): Removed.
* fold-const.cc (fold_defer_overflow_warnings): Removed.
(fold_undefer_overflow_warnings): Removed.
(fold_undefer_and_ignore_overflow_warnings): Removed.
(fold_deferring_overflow_warnings_p): Removed.
* fold-const.h (fold_defer_overflow_warnings): Removed.
(fold_undefer_overflow_warnings): Removed.
(fold_undefer_and_ignore_overflow_warnings): Removed.
(fold_deferring_overflow_warnings_p): Removed.
* gimple-fold.cc (fold_stmt_1): Removed
fold_*_overflow_warnings uses and all related logic.
* passes.cc (verify_interpass_invariants): Likewise.
(execute_one_ipa_transform_pass): Likewise.
(execute_one_pass): Likewise.
* tree-cfgcleanup.cc (cleanup_control_expr_graph): Likewise.
* tree-data-ref.cc (create_runtime_alias_checks): Likewise.
* tree-ssa-ccp.cc (evaluate_stmt): Likewise.
* tree-ssa-forwprop.cc (combine_cond_expr_cond): Likewise.
* tree-ssa-loop-niter.cc (expand_simple_operations): Likewise.
(number_of_iterations_exit_assumptions): Likewise.
(loop_niter_by_eval): Likewise.
(estimate_numbers_of_iterations): Likewise.
(loop_exits_before_overflow): Likewise.
* tree-ssa-threadedge.cc: Likewise.
* tree-vrp.cc (compare_values): Likewise.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Removed
warn_strict_overflow logic.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* expr.cc (maybe_optimize_sub_cmp_0): Removed warning_at () call
for Wstrict-overflow comparison.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* tree-vrp.cc (compare_values_warnv): Removed.
(compare_values): Changed to do the same thing as the former
compare_values_warn but without the strict_overflow_p logic.
* tree-vrp.h (compare_values_warnv): Removed.
* vr-values.cc (test_for_singularity): Removed the
supress_warning logic that was used by compare_values_warnv.
2026-05-31 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* tree-ssa-reassoc.cc (init_range_entry): Removed
strict_overflow_p use.
(force_into_ssa_name): Likewise.
(update_range_test): Removed strict_overflow_p from function
signature, along with the flag associated logic and the
warning_at call.
(optimize_range_tests_xor): Removed strict_overflow_p use.
(optimize_range_tests_diff): Likewise.
(optimize_range_tests_to_bit_test): Likewise.
(optimize_range_tests_cmp_bitwise): Likewise.
(optimize_range_tests_var_bound): Removed strict_overflow_p from
function signature, along with the flag associated logic and the
warning_at call.
(optimize_range_tests): Removed strict_overflow_p use.
* tree-ssa-reassoc.h (struct range_entry): Removed
strict_overflow_p flag.
2026-05-31 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_length_of_asm): Support "nl" as
the number of lines in the code template.
* doc/extend.texi (Size of an asm): Document [[len=nl]].
Simplify the description of the default length.
2026-05-31 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.cc (pa_trampoline_init): Rework to use
clear_cache pattern.
* config/pa/pa.md (dcacheflush): Use "<<" condition instead
of "<<=".
(icacheflush): Remove.
(icacheflush1, icacheflush2, icacheflush3): New flush patterns
for PA 1.x targets, PA 2.0 targets, and PA 1.x no space
register targets.
(clear_cache): Rework to flush data and instruction caches.
Skip flush if the start address is greater than or equal to
the end address. Don't align the end address to a cacheline
boundary. Handle instruction flushes for PA 1.x targets,
PA 2.0 targets, and PA 1.x no space register targets.
2026-05-30 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/m68k/m68k.h (ASM_PREFERRED_EH_DATA_FORMAT): Avoid
constant-logical diagnostic.
2026-05-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (insvsi_intermal):
Rename from 'insvsi'.
(insvsi): New expansion pattern that also addresses situations
where the DEPBITS machine instruction is unavailable.
2026-05-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*splice_bits):
Remove.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* builtins.def: Reflow long line.
* graphite-isl-ast-to-gimple.cc (graphite_copy_stmts_from_block): Likewise.
* lto-streamer.h: Likewise.
* prime-paths.cc (struct xpair): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Fix typos.
(vect_preserves_scalar_order_p): Likewise.
(vect_slp_analyze_instance_dependence): Likewise.
(vect_enhance_data_refs_alignment): Likewise.
(vect_check_gather_scatter): Likewise.
(vect_grouped_store_supported): Likewise.
* tree-vect-generic.cc (type_for_widest_vector_mode): Likewise.
* tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors_avx512): Likewise.
(get_live_virtual_operand_on_edge): Likewise.
(vect_can_peel_nonlinear_iv_p): Likewise.
(vect_do_peeling): Likewise.
* tree-vect-loop.cc (vec_init_loop_exit_info): Likewise.
(vect_verify_full_masking_avx512): Likewise.
(vect_verify_loop_lens): Likewise.
(vect_analyze_loop_costing): Likewise.
(vect_analyze_loop_2): Likewise.
(vect_analyze_loop): Likewise.
(vect_is_simple_reduction): Likewise.
(vect_create_epilog_for_reduction): Likewise.
(vectorizable_lane_reducing): Likewise.
(vectorizable_reduction): Likewise.
(vectorizable_live_operation): Likewise.
(vect_record_loop_len): Likewise.
(scale_profile_for_vect_loop): Likewise.
(vect_update_ivs_after_vectorizer_for_early_breaks): Likewise.
* tree-vect-patterns.cc (vect_recog_bit_insert_pattern): Likewise.
(vect_recog_build_binary_gimple_stmt): Likewise.
(vect_recog_sat_sub_pattern_transform): Likewise.
(vect_recog_sat_sub_pattern): Likewise.
(add_code_for_floorceilround_divmod): Likewise.
(vect_recog_bool_pattern): Likewise.
(struct vect_recog_func): Likewise.
* tree-vect-slp-patterns.cc (class complex_pattern): Likewise.
(compatible_complex_nodes_p): Likewise.
* tree-vect-slp.cc (vect_slp_tree_uniform_p): Likewise.
(vect_def_types_match): Likewise.
(vect_record_max_nunits): Likewise.
(vect_analyze_slp_instance): Likewise.
(vect_lower_load_permutations): Likewise.
(vect_optimize_slp_pass::is_compatible_layout): Likewise.
* tree-vect-stmts.cc (vect_get_strided_load_store_ops): Likewise.
(vectorizable_simd_clone_call): Likewise.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Likewise.
(vectorizable_early_exit): Likewise.
* tree-vectorizer.cc (vector_costs::compare_inside_loop_cost): Likewise.
* tree-vectorizer.h (enum vect_reduction_type): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* tree-ssa-alias-compare.h: Fix typos.
* tree-ssa-alias.cc (ptr_deref_may_alias_decl_p): Likewise.
(ao_ref_alignment): Likewise.
(component_ref_to_zero_sized_trailing_array_p): Likewise.
(access_path_may_continue_p): Likewise.
(nonoverlapping_component_refs_p_1): Likewise.
(nonoverlapping_array_refs_p): Likewise.
(refs_may_alias_p_2): Likewise.
(ref_maybe_used_by_call_p_1): Likewise.
(stmt_kills_ref_p): Likewise.
* tree-ssa-ccp.cc: Likewise.
* tree-ssa-dce.cc (mark_all_reaching_defs_necessary_1): Likewise.
(propagate_necessity): Likewise.
(propagate_counts): Likewise.
(eliminate_unnecessary_stmts): Likewise.
* tree-ssa-dom.cc (pass_dominator::execute): Likewise.
* tree-ssa-dse.cc: Likewise.
* tree-ssa-forwprop.cc (new_src_based_on_copy): Likewise.
(optimize_agr_copyprop_1): Likewise.
(pass_forwprop::execute): Likewise.
* tree-ssa-ifcombine.cc (tree_ssa_ifcombine_bb_1): Likewise.
(pass_tree_ifcombine::execute): Likewise.
* tree-ssa-live.cc (remove_unused_scope_block_p): Likewise.
* tree-ssa-loop-ch.cc (loop_combined_static_and_iv_p): Likewise.
(should_duplicate_loop_header_p): Likewise.
* tree-ssa-loop-im.cc (get_coldest_out_loop): Likewise.
(determine_max_movement): Likewise.
(execute_sm_exit): Likewise.
(hoist_memory_references): Likewise.
* tree-ssa-loop-ivcanon.cc (constant_after_peeling): Likewise.
(loop_edge_to_cancel): Likewise.
(unloop_loops): Likewise.
(try_unroll_loop_completely): Likewise.
(adjust_loop_info_after_peeling): Likewise.
(tree_unroll_loops_completely_1): Likewise.
* tree-ssa-loop-ivopts.cc (struct iv_inv_expr_ent): Likewise.
(dump_cand): Likewise.
(group_compare_offset): Likewise.
(split_address_groups): Likewise.
(get_computation_aff_1): Likewise.
(iv_ca_dump): Likewise.
* tree-ssa-loop-niter.cc (number_of_iterations_ne): Likewise.
(number_of_iterations_popcount): Likewise.
(idx_infer_loop_bounds): Likewise.
(infer_loop_bounds_from_signedness): Likewise.
(discover_iteration_bound_by_body_walk): Likewise.
(loop_exits_before_overflow): Likewise.
* tree-ssa-loop-niter.h: Likewise.
* tree-ssa-loop-prefetch.cc (should_issue_prefetch_p): Likewise.
(schedule_prefetches): Likewise.
* tree-ssa-loop-split.cc (split_loop): Likewise.
(find_vdef_in_loop): Likewise.
(get_cond_branch_to_split_loop): Likewise.
* tree-ssa-math-opts.cc (powi_as_mults): Likewise.
(expand_pow_as_sqrts): Likewise.
(gimple_expand_builtin_pow): Likewise.
(convert_mult_to_widen): Likewise.
(convert_plusminus_to_widen): Likewise.
* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Likewise.
(factor_out_conditional_operation): Likewise.
(cond_if_else_store_replacement_1): Likewise.
(execute_over_cond_phis): Likewise.
* tree-ssa-phiprop.cc (can_handle_load): Likewise.
(propagate_with_phi): Likewise.
* tree-ssa-pre.cc (get_or_alloc_expr_for_nary): Likewise.
(sorted_array_from_bitmap_set): Likewise.
(value_dies_in_block_x): Likewise.
(compute_antic_aux): Likewise.
* tree-ssa-propagate.cc (substitute_and_fold_engine::substitute_and_fold): Likewise.
* tree-ssa-reassoc.cc (get_rank): Likewise.
(remove_visited_stmt_chain): Likewise.
* tree-ssa-sccvn.cc (vn_reference_eq): Likewise.
(vn_reference_lookup_call): Likewise.
(vn_nary_op_eq): Likewise.
(vn_nary_op_insert_into): Likewise.
(visit_reference_op_call): Likewise.
(visit_phi): Likewise.
(eliminate_dom_walker::eliminate_stmt): Likewise.
(eliminate_dom_walker::eliminate_cleanup): Likewise.
(process_bb): Likewise.
* tree-ssa-scopedtables.cc (hashable_expr_equal_p): Likewise.
* tree-ssa-structalias.cc (determine_global_memory_access): Likewise.
(clear_dependence_clique): Likewise.
* tree-ssa-threadbackward.cc (back_threader_profitability::profitable_path_p): Likewise.
* tree-ssa-threadedge.cc (propagate_threaded_block_debug_into): Likewise.
* tree-ssa-uninit.cc (warn_uninit): Likewise.
(execute_late_warn_uninitialized): Likewise.
* tree-ssanames.cc (range_info_get_range): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* tree-assume.cc (assume_query::calculate_phi): Fix typos.
* tree-cfg.cc (assign_discriminators): Likewise.
(stmt_starts_bb_p): Likewise.
(move_stmt_op): Likewise.
(ifconvertable_edge): Likewise.
* tree-cfgcleanup.cc (maybe_remove_forwarder_block): Likewise.
(cleanup_tree_cfg_noloop): Likewise.
* tree-chrec.cc (scev_is_linear_expression): Likewise.
* tree-complex.cc (expand_complex_div_wide): Likewise.
* tree-core.h (enum built_in_class): Likewise.
* tree-data-ref.cc (dump_alias_pair): Likewise.
(create_ifn_alias_checks): Likewise.
* tree-data-ref.h (struct data_dependence_relation): Likewise.
* tree-eh.cc (lower_try_finally_fallthru_label): Likewise.
(lower_eh_dispatch): Likewise.
* tree-if-conv.cc (idx_within_array_bound): Likewise.
(base_object_writable): Likewise.
(ifcvt_memrefs_wont_trap): Likewise.
(get_loop_body_in_if_conv_order): Likewise.
(predicate_scalar_phi): Likewise.
* tree-inline.cc (remap_type_1): Likewise.
(declare_return_variable): Likewise.
(inline_forbidden_p): Likewise.
(estimate_num_insns): Likewise.
(copy_decl_for_dup_finish): Likewise.
* tree-into-ssa.cc (get_ssa_name_ann): Likewise.
(clear_ssa_name_info): Likewise.
(insert_updated_phi_nodes_compare_uids): Likewise.
(update_ssa): Likewise.
* tree-loop-distribution.cc (enum partition_kind): Likewise.
(struct partition): Likewise.
(class loop_distribution): Likewise.
(loop_distribution::classify_partition): Likewise.
(loop_distribution::pg_add_dependence_edges): Likewise.
(add_partition_graph_edge): Likewise.
(free_partition_graph_vdata): Likewise.
(pg_unmark_merged_alias_ddrs): Likewise.
(version_loop_by_alias_check): Likewise.
* tree-object-size.cc (gimplify_size_expressions): Likewise.
(object_sizes_execute): Likewise.
* tree-parloops.cc (parloops_is_simple_reduction): Likewise.
(transform_to_exit_first_loop_alt): Likewise.
* tree-predcom.cc (pcom_worker::suitable_component_p): Likewise.
(pcom_worker::determine_roots_comp): Likewise.
(prepare_initializers_chain_store_elim): Likewise.
(pcom_worker::tree_predictive_commoning_loop): Likewise.
* tree-profile.cc (condition_uid): Likewise.
(cov_length): Likewise.
(tree_profiling): Likewise.
* tree-scalar-evolution.cc (scev_dfs::add_to_evolution_1): Likewise.
(scev_reset): Likewise.
(expression_expensive_p): Likewise.
* tree-sra.cc (struct access): Likewise.
(build_access_from_call_arg): Likewise.
(path_comparable_for_same_access): Likewise.
(child_would_conflict_in_acc): Likewise.
(sra_modify_call_arg): Likewise.
* tree-switch-conversion.cc (can_log2): Likewise.
(switch_conversion::exp_index_transform): Likewise.
* tree-switch-conversion.h (enum cluster_type): Likewise.
* tree-vrp.cc (remove_unreachable::handle_early): Likewise.
* tree.cc (build5): Likewise.
(get_file_function_name): Likewise.
(build_opaque_vector_type): Likewise.
(array_ref_flexible_size_p): Likewise.
(verify_type_variant): Likewise.
(gimple_canonical_types_compatible_p): Likewise.
* tree.h (decl_debug_args_insert): Likewise.
(strip_pointer_types): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* rtl-ssa/access-utils.h (drop_memory_access): Fix typos.
* rtl-ssa/accesses.cc (clobber_info::recompute_group): Likewise.
* rtl-ssa/accesses.h: Likewise.
* rtl-ssa/blocks.cc (function_info::add_artificial_accesses): Likewise.
* rtl-ssa/functions.h: Likewise.
* rtl-ssa/insns.cc (function_info::record_use): Likewise.
* rtl-ssa/insns.h: Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* lto-cgraph.cc (get_alias_symbol): Fix typos.
(input_node): Likewise.
(input_varpool_node): Likewise.
* lto-ltrans-cache.cc: Likewise.
* lto-streamer-in.cc (lto_location_cache::revert_location_cache): Likewise.
(lto_location_cache::input_location_and_block): Likewise.
(lto_location_cache::input_location): Likewise.
(lto_input_location): Likewise.
* lto-streamer-out.cc (lto_variably_modified_type_p): Likewise.
(lto_is_streamable): Likewise.
(DFS::DFS): Likewise.
(cmp_symbol_files): Likewise.
(lto_output): Likewise.
* lto-streamer.h (enum LTO_tags): Likewise.
* lto-wrapper.cc (merge_flto_options): Likewise.
(run_gcc): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* ipa-comdats.cc: Fix typos.
* ipa-cp.cc (good_cloning_opportunity_p): Likewise.
(dump_profile_updates): Likewise.
(update_counts_for_self_gen_clones): Likewise.
(update_profiling_info): Likewise.
(adjust_refs_in_act_callers): Likewise.
(struct cloning_opportunity_ranking): Likewise.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Likewise.
(unmodified_parm_or_parm_agg_item): Likewise.
(guards_builtin_unreachable): Likewise.
(analyze_function_body): Likewise.
(estimate_edge_devirt_benefit): Likewise.
* ipa-fnsummary.h (cross_module_call_p): Likewise.
* ipa-free-lang-data.cc (fld_simplified_type_name): Likewise.
(free_lang_data_in_decl): Likewise.
* ipa-icf-gimple.cc (func_checker::compare_decl): Likewise.
(func_checker::compatible_types_p): Likewise.
(func_checker::compare_gimple_asm): Likewise.
* ipa-icf.cc (sem_function::hash_stmt): Likewise.
(sem_item_optimizer::subdivide_classes_by_equality): Likewise.
(sem_item_optimizer::traverse_congruence_split): Likewise.
(sem_item_optimizer::process_cong_reduction): Likewise.
* ipa-inline-transform.cc (mark_all_inlined_calls_cdtor): Likewise.
(preserve_function_body_p): Likewise.
* ipa-inline.cc (enum can_inline_edge_by_limits_flags): Likewise.
(can_early_inline_edge_p): Likewise.
(early_inliner): Likewise.
* ipa-locality-cloning.cc (edge_redirectable_p): Likewise.
(clone_node_as_needed): Likewise.
(partition_callchain): Likewise.
* ipa-modref.cc (modref_eaf_analysis::merge_with_ssa_name): Likewise.
* ipa-param-manipulation.cc (ipa_param_adjustments::get_surviving_params): Likewise.
(purge_all_uses): Likewise.
(ipa_param_body_adjustments::mark_dead_statements): Likewise.
(replace_with_mapped_expr): Likewise.
(ipa_param_body_adjustments::get_new_param_chain): Likewise.
(record_argument_state): Likewise.
(ipa_param_body_adjustments::perform_cfun_body_modifications): Likewise.
* ipa-param-manipulation.h (struct ipa_replace_map): Likewise.
* ipa-polymorphic-call.cc (ipa_polymorphic_call_context::combine_with): Likewise.
* ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Likewise.
(noted_fnptr_hasher::equal): Likewise.
(ipa_set_ancestor_jf): Likewise.
(check_stmt_for_type_change): Likewise.
(param_type_may_change_p): Likewise.
(find_dominating_aa_status): Likewise.
(parm_ref_data_pass_through_p): Likewise.
(build_agg_jump_func_from_list): Likewise.
(analyze_agg_content_value): Likewise.
(ipa_single_noted_fnptr_in_record): Likewise.
(ipa_make_edge_direct_to_target): Likewise.
(combine_controlled_uses_counters): Likewise.
(ipa_duplicate_jump_function): Likewise.
(ipa_write_jump_function): Likewise.
(useful_ipcp_transformation_info_p): Likewise.
* ipa-prop.h (struct GTY): Likewise.
* ipa-reference.cc (ipa_reference_var_uid): Likewise.
(ipa_reference_get_written_global): Likewise.
(union_static_var_sets): Likewise.
* ipa-split.cc (split_function): Likewise.
* ipa-sra.cc (isra_track_scalar_value_uses): Likewise.
(process_scan_results): Likewise.
(flip_all_hints_pessimistic): Likewise.
(flip_all_param_hints_pessimistic): Likewise.
* ipa-strub.cc (get_strub_mode_attr_parm): Likewise.
(compute_strub_mode): Likewise.
* ipa-utils.cc (ipa_merge_profiles): Likewise.
(recursive_call_p): Likewise.
(stmt_may_terminate_function_p): Likewise.
(find_always_executed_bbs): Likewise.
* ipa-utils.h (type_with_linkage_p): Likewise.
(lto_streaming_expected_p): Likewise.
* ipa-visibility.cc (varpool_node::externally_visible_p): Likewise.
* ipa.cc (update_inlined_to_pointer): Likewise.
(enqueue_node): Likewise.
(process_references): Likewise.
(set_readonly_bit): Likewise.
(clear_addressable_bit): Likewise.
(BOTTOM): Likewise.
(propagate_single_user): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* gimple-array-bounds.cc (trailing_array): Fix typos.
* gimple-crc-optimization.cc (crc_optimization::set_defs): Likewise.
* gimple-fold.cc (get_range_strlen): Likewise.
(can_refer_decl_in_current_unit_p): Likewise.
(gimple_fold_builtin_bcopy): Likewise.
(get_range_strlen_tree): Likewise.
(gimple_fold_builtin_stpcpy): Likewise.
(fold_stmt_1): Likewise.
(fold_truth_andor_for_ifcombine): Likewise.
(gimple_fold_stmt_to_constant): Likewise.
(fold_const_aggregate_ref): Likewise.
(gimple_get_virt_method_for_vtable): Likewise.
(rewrite_to_defined_unconditional): Likewise.
(gimple_build): Likewise.
(gimple_convert): Likewise.
* gimple-harden-control-flow.cc (pass_harden_control_flow_redundancy::execute): Likewise.
* gimple-loop-interchange.cc (loop_cand::can_interchange_p): Likewise.
(loop_cand::analyze_lcssa_phis): Likewise.
(should_interchange_loops): Likewise.
* gimple-loop-jam.cc (tree_loop_unroll_and_jam): Likewise.
* gimple-low.cc (find_assumption_locals_r): Likewise.
* gimple-match-exports.cc (try_conditional_simplification): Likewise.
* gimple-predicate-analysis.cc (find_matching_predicate_in_rest_chains): Likewise.
(uninit_analysis::func_t::phi_arg_set): Likewise.
(predicate::dump): Likewise.
* gimple-predicate-analysis.h (class uninit_analysis): Likewise.
* gimple-range-cache.cc (sbr_vector::bb_range_p): Likewise.
(block_range_cache::set_bb_range): Likewise.
* gimple-range-gori.cc (gori_compute::compute_operand_range): Likewise.
(gori_stmt_info::gori_stmt_info): Likewise.
(gori_calc_operands): Likewise.
(gori_on_edge): Likewise.
(gori_name_helper): Likewise.
* gimple-range-infer.h: Likewise.
* gimple-range-phi.cc (phi_group::phi_group): Likewise.
(phi_group::calculate_using_modifier): Likewise.
(phi_analyzer::operator[]): Likewise.
* gimple-range-phi.h: Likewise.
* gimple-range.cc (dom_ranger::range_of_stmt): Likewise.
* gimple-ssa-isolate-paths.cc (is_addr_local): Likewise.
(warn_return_addr_local): Likewise.
* gimple-ssa-pta-constraints.cc (get_constraint_for_ssa_var): Likewise.
(find_func_clobbers): Likewise.
(create_variable_info_for): Likewise.
(associate_varinfo_to_alias): Likewise.
* gimple-ssa-sccopy.cc: Likewise.
* gimple-ssa-split-paths.cc (count_stmts_in_block): Likewise.
(poor_ifcvt_pred): Likewise.
(is_feasible_trace): Likewise.
* gimple-ssa-sprintf.cc (get_int_range): Likewise.
(handle_printf_call): Likewise.
* gimple-ssa-store-merging.cc (get_location_for_stmts): Likewise.
* gimple-ssa-strength-reduction.cc: Likewise.
* gimple-ssa-warn-access.cc (call_arg): Likewise.
* gimple-ssa-warn-restrict.cc (builtin_memref::offset_out_of_bounds): Likewise.
(builtin_access::overlap_size): Likewise.
(maybe_diag_access_bounds): Likewise.
* gimple.def (GIMPLE_PHI): Likewise.
* gimple.h (gimple_goto_dest): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* genattrtab.cc (min_fn): Fix typos.
(get_attr_order): Likewise.
(optimize_attrs): Likewise.
* genautomata.cc (struct unit_usage): Likewise.
* gengtype-state.cc (s_expr_writer::write_any_indent): Likewise.
(write_state): Likewise.
* gengtype.cc (struct file_rule_st): Likewise.
(walk_type): Likewise.
(write_roots): Likewise.
* genmatch.cc (expr::gen_transform): Likewise.
(usage): Likewise.
* genopinit.cc (open_outfile): Likewise.
(handle_overloaded_code_for): Likewise.
(main): Likewise.
* genoutput.cc (operand_data_hasher::equal): Likewise.
* genpreds.cc (FOR_ALL_CONSTRAINTS): Likewise.
* genrecog.cc (prune_invalid_results): Likewise.
(split_out_patterns): Likewise.
* gensupport.cc (parse_section): Likewise.
(convert_syntax): Likewise.
(mark_operands_from_match_dup): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* sanopt.cc: Fix typos.
* sched-deps.cc (sched_analyze_2): Likewise.
* sel-sched-ir.cc (alloc_target_context): Likewise.
(av_set_union_and_live): Likewise.
(make_regions_from_loop_nest): Likewise.
* sel-sched-ir.h (struct _list_iterator): Likewise.
(struct succs_info): Likewise.
(SUCCS_ALL): Likewise.
* sel-sched.cc (moveup_expr): Likewise.
(moveup_expr_cached): Likewise.
(get_spec_check_type_for_insn): Likewise.
(get_expr_cost): Likewise.
(find_place_for_bookkeeping): Likewise.
(update_and_record_unavailable_insns): Likewise.
(move_op_at_first_insn): Likewise.
(calculate_new_fences): Likewise.
* shrink-wrap.cc (live_edge_for_reg): Likewise.
(try_shrink_wrapping): Likewise.
* simplify-rtx.cc
(simplify_context::simplify_logical_relational_operation): Likewise.
(simplify_const_vector_subreg): Likewise.
* spellcheck.cc (assert_not_suggested_for): Likewise.
* stringpool.h: Likewise.
* sym-exec/sym-exec-state.cc (state::do_shift_right): Likewise.
(state::get_parent_with_const_child): Likewise.
(state::add_numbers): Likewise.
(state::add_equal_cond): Likewise.
(state::add_not_equal_cond): Likewise.
* sym-exec/sym-exec-state.h (class state): Likewise.
* symbol-summary.h: Likewise.
* symtab.cc (symtab_node::noninterposable_alias): Likewise.
(symtab_node::equal_address_to): Likewise.
* system.h (gcc_stablesort_r): Likewise.
* target-hooks-macros.h: Likewise.
* target.def: Likewise.
* targhooks.cc (default_floatn_mode): Likewise.
(default_floatn_builtin_p): Likewise.
(default_builtin_vector_alignment_reachable): Likewise.
(default_addr_space_for_artificial_rodata): Likewise.
* text-art/ruler.cc (x_ruler::update_layout): Likewise.
* text-art/ruler.h (class x_ruler): Likewise.
* timevar.def (TV_ISOLATE_ERRONEOUS_PATHS): Likewise.
* trans-mem.cc (ipa_tm_scan_irr_block): Likewise.
(ipa_tm_execute): Likewise.
* typed-splay-tree.h (class typed_splay_tree): Likewise.
* ubsan.cc (instrument_bool_enum_load): Likewise.
* value-prof.cc: Likewise.
* value-range.cc (irange::union_append): Likewise.
(irange::snap): Likewise.
(irange::snap_subranges): Likewise.
(irange::get_bitmask): Likewise.
* value-range.h (irange_bitmask::get_precision): Likewise.
* value-relation.cc (dom_oracle::next_relation): Likewise.
(block_relation_iterator::block_relation_iterator): Likewise.
* var-tracking.cc (shared_hash_find): Likewise.
(emit_note_insn_var_location): Likewise.
* varasm.cc (mergeable_constant_section): Likewise.
(finish_tm_clone_pairs): Likewise.
(default_binds_local_p_3): Likewise.
* vr-values.cc (simplify_using_ranges::simplify): Likewise.
* vtable-verify.cc: Likewise.
* warning-control.cc (has_warning_spec): Likewise.
* wide-int.cc (wi::from_mpz): Likewise.
(wi::force_to_size): Likewise.
(wi::divmod_internal): Likewise.
* wide-int.h (wi::bitreverse): Likewise.
(wi::umin): Likewise.
(wi::mul_high): Likewise.
(wi::div_trunc): Likewise.
(wi::sdiv_trunc): Likewise.
(wi::udiv_trunc): Likewise.
(wi::div_floor): Likewise.
(wi::sdiv_floor): Likewise.
(wi::udiv_floor): Likewise.
(wi::div_ceil): Likewise.
(wi::udiv_ceil): Likewise.
(wi::div_round): Likewise.
(wi::gcd): Likewise.
(wi::mod_trunc): Likewise.
(wi::smod_trunc): Likewise.
(wi::umod_trunc): Likewise.
(wi::mod_floor): Likewise.
(wi::umod_floor): Likewise.
(wi::mod_ceil): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* omp-expand.cc (expand_oacc_collapse_vars): Likewise.
(expand_omp_for_init_vars): Likewise.
(expand_omp_for): Likewise.
(expand_omp_atomic_fetch_op): Likewise.
(build_omp_regions_1): Likewise.
* omp-general.cc (omp_is_allocatable_or_ptr): Likewise.
* omp-low.cc (lower_rec_input_clauses): Likewise.
(lower_omp): Likewise.
* omp-offload.cc (oacc_validate_dims): Likewise.
(oacc_loop_process): Likewise.
(oacc_loop_fixed_partitions): Likewise.
(oacc_loop_auto_partitions): Likewise.
(execute_oacc_device_lower): Likewise.
* omp-simd-clone.cc (simd_clone_clauses_extract): Likewise.
(ipa_simd_modify_stmt_ops): Likewise.
* optabs-query.cc (lshift_cheap_p): Likewise.
* optabs-query.h (trapv_binoptab_p): Likewise.
(get_vec_cmp_icode): Likewise.
* optabs.cc (expand_binop): Likewise.
(expand_vec_perm_var): Likewise.
(expand_compare_and_swap_loop): Likewise.
(expand_atomic_load): Likewise.
(maybe_optimize_fetch_op): Likewise.
(can_reuse_operands_p): Likewise.
* opts-global.cc (init_options_once): Likewise.
* opts.h (struct cl_option): Likewise.
* pair-fusion.cc (pair_fusion_bb_info::try_fuse_pair): Likewise.
* pair-fusion.h (enum class): Likewise.
* passes.cc (account_profile_1): Likewise.
* path-coverage.cc (instrument_prime_paths): Likewise.
* plugin.cc (get_event_last): Likewise.
* pointer-query.cc (handle_min_max_size): Likewise.
(handle_array_ref): Likewise.
(handle_ssa_name): Likewise.
* poly-int.h (struct if_lossless): Likewise.
(POLY_POLY_COEFF): Likewise.
* postreload-gcse.cc (gcse_after_reload_main): Likewise.
* predict.cc (expr_expected_value_1): Likewise.
(is_exit_with_zero_arg): Likewise.
(predict_paths_for_bb): Likewise.
(estimate_bb_frequencies): Likewise.
(rebuild_frequencies): Likewise.
(make_pass_rebuild_frequencies): Likewise.
* pretty-print-format-impl.h: Likewise.
* pretty-print.h: Likewise.
* prime-paths.cc (struct xpair): Likewise.
(edge_matrix): Likewise.
(test_build_ccfg): Likewise.
* print-rtl.cc (rtx_writer::print_rtx_operand_code_r): Likewise.
* profile-count.h (class profile_probability): Likewise.
* pta-andersen.cc (merge_node_constraints): Likewise.
(add_graph_edge): Likewise.
* range-op.cc (bool): Likewise.
(operator_cast::op1_range): Likewise.
(operator_bitwise_and::wi_fold): Likewise.
(operator_bitwise_and::op1_range): Likewise.
* range-op.h: Likewise.
* read-md.h (class md_reader): Likewise.
* read-rtl-function.cc (lookup_reg_by_dump_name): Likewise.
* real.cc: Likewise.
* recog.h: Likewise.
* ree.cc (find_and_remove_re): Likewise.
* reg-notes.def (REG_CFA_NOTE): Likewise.
* reginfo.cc (reg_allocno_class): Likewise.
* reload1.cc (will_delete_init_insn_p): Likewise.
(emit_reload_insns): Likewise.
* resource.cc (mark_referenced_resources): Likewise.
(mark_target_live_regs): Likewise.
* rtl.def (DEFINE_SPECIAL_PREDICATE): Likewise.
(COND): Likewise.
(DEFINE_SUBST): Likewise.
* rtl.h (const_vec_series_p_1): Likewise.
(const_vec_series_p): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* emit-rtl.h (struct rtl_data): Fix typos.
(struct address_reload_context): Likewise.
* explow.cc (anti_adjust_stack_and_probe): Likewise.
* explow.h (anti_adjust_stack_and_probe_stack_clash): Likewise.
* expmed.cc (store_bit_field_using_insv): Likewise.
(expand_mult): Likewise.
(emit_store_flag_force): Likewise.
(equivalent_cmp_code): Likewise.
* expr.cc (class op_by_pieces_d): Likewise.
(op_by_pieces_d::run): Likewise.
(use_group_regs): Likewise.
(get_def_for_expr): Likewise.
(emit_move_insn): Likewise.
(expand_expr_real): Likewise.
(expand_expr_real_gassign): Likewise.
* ext-dce.cc (ext_dce_process_uses): Likewise.
(ext_dce_process_bb): Likewise.
(ext_dce_rd_confluence_n): Likewise.
* fibonacci_heap.h (fibonacci_heap::cut): Likewise.
* fold-const.cc (combine_comparisons): Likewise.
(operand_compare::operand_equal_p): Likewise.
(fold_view_convert_vector_encoding): Likewise.
(fold_truth_andor): Likewise.
* fold-const.h: Likewise.
* function.cc (temp_address_hasher::equal): Likewise.
(gen_call_used_regs_seq): Likewise.
* gcc-diagnostic-spec.cc (GTY): Likewise.
(warning_suppressed_at): Likewise.
* gcc.cc (driver::maybe_run_linker): Likewise.
* gcov.cc (print_usage): Likewise.
(strip_extention): Likewise.
* gdbhooks.py: Likewise.
* gimplify.cc (gimplify_decl_expr): Likewise.
(gimplify_modify_expr): Likewise.
(oacc_default_clause): Likewise.
(omp_notice_variable): Likewise.
* graph.cc (draw_cfg_nodes): Likewise.
* graphite-dependences.cc (scop_get_reads_and_writes): Likewise.
* graphite-isl-ast-to-gimple.cc (graphite_copy_stmts_from_block): Likewise.
* haifa-sched.cc (model_set_excess_costs): Likewise.
(analyze_set_insn_for_autopref): Likewise.
(autopref_multipass_dfa_lookahead_guard): Likewise.
* hash-map-traits.h (HASH_MAP_TRAITS_H): Likewise.
* hosthooks.h (struct host_hooks): Likewise.
* ifcvt.cc (noce_try_sign_bit_splat): Likewise.
* input.cc (line_table_test::line_table_test): Likewise.
* internal-fn.def (PHI): Likewise.
* internal-fn.h (enum ifn_goacc_loop_kind): Likewise.
* ira-build.cc (create_insn_allocnos): Likewise.
* ira-color.cc (ira_mark_new_stack_slot): Likewise.
* ira-int.h: Likewise.
* ira.cc (struct sloc): Likewise.
* json-parsing.cc (parser::require_one_of): Likewise.
* langhooks.h (struct lang_hooks_for_decls): Likewise.
* libgdiagnostics.cc: Likewise.
* libgdiagnostics.h (diagnostic_manager_write_patch): Likewise.
* loop-invariant.cc (MAX_CANON_ADDR_PARTS): Likewise.
* lra-assigns.cc (reload_pseudo_compare_func): Likewise.
* lra-constraints.cc (match_reload): Likewise.
(process_alt_operands): Likewise.
(process_address_1): Likewise.
(lra_constraints): Likewise.
(inherit_in_ebb): Likewise.
* lra-eliminations.cc (init_elim_table): Likewise.
* lra-remat.cc: Likewise.
* machmode.h (struct int_n_data_t): Likewise.
* mem-stats.h (mem_alloc_description::register_descriptor): Likewise.
(mem_alloc_description::unregister_descriptor): Likewise.
* mode-switching.cc (optimize_mode_switching): Likewise.
* modulo-sched.cc (schedule_reg_moves): Likewise.
(optimize_sc): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* adjust-alignment.cc (pass_adjust_alignment::execute): Fix typos.
* alias.cc (alias_set_subset_of): Likewise.
(alias_ptr_types_compatible_p): Likewise.
(get_alias_set): Likewise.
(record_component_aliases): Likewise.
(base_alias_check): Likewise.
* alloc-pool.h: Likewise.
* asan.cc (insert_if_then_before_iter): Likewise.
(asan_expand_check_ifn): Likewise.
(hwasan_expand_check_ifn): Likewise.
* asan.h (sanitize_flags_p): Likewise.
* asm-toplevel.cc (analyze_toplevel_extended_asm): Likewise.
* attr-fnspec.h: Likewise.
* attribs.cc (decl_attributes): Likewise.
* auto-profile.cc (function_instance::match): Likewise.
(function_instance::remove_icall_target): Likewise.
(autofdo_source_profile::offline_external_functions): Likewise.
(afdo_set_bb_count): Likewise.
(scale_bbs): Likewise.
(afdo_adjust_guessed_profile): Likewise.
* basic-block.h (find_fallthru_edge): Likewise.
* bbitmap.h: Likewise.
* bitmap.cc (bitmap_list_find_element): Likewise.
* bitmap.h: Likewise.
* btfout.cc (BTF_INFO_SECTION_FLAGS): Likewise.
(btf_asm_type): Likewise.
(output_btf_vars): Likewise.
(btf_add_used_type_1): Likewise.
* builtins.cc (string_length): Likewise.
(expand_builtin_setjmp_setup): Likewise.
(inline_expand_builtin_bytecmp): Likewise.
* builtins.def: Likewise.
* ccmp.cc (get_compare_parts): Likewise.
(expand_ccmp_next): Likewise.
* ccmp.h: Likewise.
* cfg.cc (update_bb_profile_for_threading): Likewise.
* cfganal.cc (post_order_compute): Likewise.
* cfgbuild.cc (find_many_sub_basic_blocks): Likewise.
* cfgexpand.cc (vars_ssa_cache::dump): Likewise.
(add_scope_conflicts_1): Likewise.
(set_parm_rtl): Likewise.
(expand_one_ssa_partition): Likewise.
(expand_one_var): Likewise.
(discover_nonconstant_array_refs_r): Likewise.
(pass_expand::execute): Likewise.
* cfgloop.cc (get_estimated_loop_iterations): Likewise.
* cfgloopanal.cc (loop_count_in): Likewise.
* cfgloopmanip.cc (loop_exit_for_scaling): Likewise.
(update_loop_exit_probability_scale_dom_bbs): Likewise.
* cgraph.cc (add_detected_attribute_1): Likewise.
(cgraph_edge::maybe_hot_p): Likewise.
* cgraph.h (struct cgraph_node): Likewise.
* cif-code.def (ORIGINALLY_INDIRECT_CALL): Likewise.
* collect2.cc (main): Likewise.
* combine.cc (simplify_comparison): Likewise.
(distribute_notes): Likewise.
* configure.ac: Likewise.
* coretypes.h (enum pad_direction): Likewise.
* coroutine-passes.cc (make_pass_coroutine_lower_builtins): Likewise.
* coverage.cc (coverage_compute_profile_id): Likewise.
* cse.cc (struct set): Likewise.
(try_back_substitute_reg): Likewise.
(count_stores): Likewise.
* cselib.cc (struct cselib_hasher): Likewise.
* ctfc.cc (ctfc_get_num_ctf_vars): Likewise.
(ctf_add_string): Likewise.
(ctf_add_function_arg): Likewise.
* ctfc.h (GTY): Likewise.
(CTF_AUX_STRTAB): Likewise.
(ctfc_get_num_ctf_vars): Likewise.
* ctfout.cc (ctf_asm_sou_lmember): Likewise.
(output_ctf_header): Likewise.
* debug.h: Likewise.
* defaults.h: Likewise.
* df-problems.cc (df_simulate_fixup_sets): Likewise.
(df_simulate_finalize_backwards): Likewise.
* diagnostic-context-rich-location.cc
(lazy_diagnostic_context_path::make_inner_path): Likewise.
* diagnostics/color.cc (auto_enable_urls): Likewise.
* diagnostics/context.h: Likewise.
* diagnostics/sarif-sink.cc (get_message_from_result): Likewise.
* double-int.cc (double_int::lrotate): Likewise.
* dwarf2asm.cc (dw2_asm_output_delta_uleb128): Likewise.
* dwarf2cfi.cc (dwarf2out_frame_debug_expr): Likewise.
* dwarf2ctf.cc (ctf_get_AT_data_member_location): Likewise.
(handle_ctf_type_tags): Likewise.
* dwarf2out.cc (cst_pool_loc_descr): Likewise.
(loc_list_for_address_of_addr_expr_of_indirect_ref): Likewise.
(resolve_args_picking_1): Likewise.
(typed_binop_from_tree): Likewise.
(gen_array_type_die): Likewise.
* dwarf2out.h (struct dw_val_node): Likewise.
(dw_loc_dtprel): Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* doc/analyzer.texi: Fix typos.
* doc/cpp.texi: Likewise.
* doc/extend.texi: Likewise.
* doc/gcov.texi: Likewise.
* doc/gm2.texi: Likewise.
* doc/gty.texi: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/libgdiagnostics/topics/compatibility.rst: Likewise.
* doc/libgdiagnostics/topics/physical-locations.rst: Likewise.
* doc/libgdiagnostics/tutorial/07-execution-paths.rst: Likewise.
* doc/libgdiagnostics/tutorial/08-message-buffers.rst: Likewise.
* doc/match-and-simplify.texi: Likewise.
* doc/md.texi: Likewise.
* doc/optinfo.texi: Likewise.
* doc/params.texi: Likewise.
* doc/poly-int.texi: Likewise.
* doc/riscv-ext.texi: Likewise.
* doc/rtl.texi: Likewise.
* doc/sourcebuild.texi: Likewise.
* doc/tm.texi: Likewise.
* doc/tm.texi.in: Likewise.
* doc/tree-ssa.texi: Likewise.
2026-05-30 Dhruv Chawla <dhruvc@nvidia.com>
* Makefile.in: Fix typos.
2026-05-30 Jakub Jelinek <jakub@redhat.com>
* tree.h (BITINT_TYPE_P): Return true also for ENUMERAL_TYPE with
BITINT_TYPE as underlying type.
* stor-layout.cc (finish_bitfield_representative): Use BITINT_TYPE_P
macro.
(layout_type): Likewise. Lay out ENUMERAL_TYPEs with BITINT_TYPE as
underlying type the same as BITINT_TYPEs.
* gimple-lower-bitint.cc (maybe_cast_middle_bitint): Use BITINT_TYPE_P
macro.
(mergeable_op, optimizable_arith_overflow, comparison_op,
bitint_large_huge::handle_cast, bitint_large_huge::lower_shift_stmt,
bitint_large_huge::lower_muldiv_stmt,
bitint_large_huge::lower_mul_overflow,
bitint_large_huge::lower_bit_query,
bitint_large_huge::lower_call, bitint_large_huge::lower_asm,
bitint_large_huge::lower_stmt, build_bitint_stmt_ssa_conflicts,
arith_overflow_arg_kind, gimple_lower_bitint): Likewise.
* gimple-expr.cc (useless_type_conversion_p): Likewise.
* fold-const.cc (make_range_step): Likewise.
(range_check_type): For ENUMERAL_TYPEs with BITINT_TYPE as underlying
type use the underlying type.
(extract_muldiv_1): Use BITINT_TYPE_P macro.
(native_encode_wide_int): Likewise.
(native_interpret_int): Likewise.
* vr-values.cc
(simplify_using_ranges::simplify_float_conversion_using_ranges):
Likewise.
* cfgexpand.cc (expand_debug_expr): Likewise.
* convert.cc (convert_to_integer_1): Add special case for ENUMERAL_TYPE
with underlying BITINT_TYPE.
* tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
BITINT_TYPE_P macro.
(vn_reference_lookup_3): Likewise.
(eliminate_dom_walker::eliminate_stmt): Likewise.
* match.pd (ctz(ext(X)) == ctz(X), popcount(zext(X)) == popcount(X),
parity(zext(X)) == parity(X), a != 0 ? CLZ(a) : CST -> .CLZ(a),
a != 0 ? CTZ(a) : CST -> .CTZ(a), ffs(ext(X)) == ffs(X)): Likewise.
* builtins.cc (fold_builtin_bit_query): Likewise.
* explow.cc (promote_function_mode): Handle ENUMERAL_TYPE with
BITINT_TYPE as underlying type like BITINT_TYPE.
(promote_mode): Likewise.
* expr.cc (EXTEND_BITINT): Use BITINT_TYPE_P macro.
(expand_expr_real_1): Likewise.
* fold-const-call.cc (fold_const_call_ss): Likewise.
* gimple-fold.cc (gimple_fold_builtin_memset): Likewise.
(clear_padding_type_may_have_padding_p): Handle ENUMERAL_TYPE
with BITINT_TYPE as underlying type like BITINT_TYPE.
(type_has_padding_at_level_p): Likewise.
(clear_padding_type): Likewise.
* gimple-match-exports.cc (build_call_internal): Use BITINT_TYPE_P
macro.
* internal-fn.cc (expand_ubsan_result_store): Likewise.
* tree-sra.cc (create_access): Likewise.
(analyze_access_subtree): Likewise.
* tree-ssa-phiopt.cc (cond_removal_in_builtin_zero_pattern): Likewise.
* tree-ssa.cc (maybe_optimize_var): Likewise.
* tree-switch-conversion.cc (switch_conversion::array_value_type):
Likewise.
(switch_conversion::build_arrays): Likewise.
(jump_table_cluster::emit): Likewise.
* ubsan.cc (ubsan_encode_value): Likewise.
(ubsan_type_descriptor): Handle ENUMERAL_TYPE with BITINT_TYPE as
underlying type like BITINT_TYPE.
(instrument_si_overflow): Use BITINT_TYPE_P macro.
* varasm.cc (output_constant): Handle ENUMERAL_TYPE with BITINT_TYPE
as underlying type like BITINT_TYPE.
* config/aarch64/aarch64.cc (aarch64_return_in_memory_1): Use
BITINT_TYPE_P macro.
(bitint_or_aggr_of_bitint_p): Likewise.
(aarch64_composite_type_p): Likewise.
* config/arm/arm.cc (arm_return_in_memory): Likewise.
(arm_needs_doubleword_align): Likewise.
* config/i386/i386.cc (classify_argument): Handle ENUMERAL_TYPE with
BITINT_TYPE as underlying type like BITINT_TYPE.
* config/loongarch/loongarch.h: Use BITINT_TYPE_P macro.
2026-05-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-switch-conversion.cc (case_bit_test::cmp): Stability
based on the index of the target bb instead.
(bit_test_cluster::emit): Remove setting of the label field
of case_bit_test.
* tree-switch-conversion.h (case_bit_test): Remove the label
field.
2026-05-29 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125475
* gimple-range-fold.cc (fold_using_range::fold_stmt): Don't call
gimple_stmt_nonnegative_p. Instead set the varying range to
`[type_min, type_max]` if not the same as the precision.
2026-05-29 Georg-Johann Lay <avr@gjlay.de>
PR target/121343
* config/avr/avr.md (FMUL): New int iterator.
(fmul, fmul_X, fmul_1, fmul_2): New int attributes.
(fmul, fmuls, fmulsu): Turn from expander to insn_and_split.
(fmul_insn, fmuls_insn, fmulsu_insn): Remove.
2026-05-29 Tobias Burnus <tburnus@baylibre.com>
PR c/122892
* gimplify.cc (gimplify_scan_omp_clauses): Update for removed
plural -S in GOMP_OMP_PREDEF_ALLOC_THREAD.
2026-05-29 Nathan Sidwell <nathan@acm.org>
* config/riscv/sync.md: Move & rename atomic unspec enums to unspecv
enum. Use renamed UNSPECV_$NAME enums.
* config/riscv/sync-rvwmo.md: Use renamed UNSPECV_$NAME enums.
* config/riscv/sync-ztso.md: Use renamed UNSPECV_$NAME enums.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Emit definitions for __ARM_FEATURE_{SVE,SME}2p2.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve-builtins-sve2.def (svmul): Define new
SVE function variant.
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<optab><mode>): New
instruction pattern.
(@aarch64_sve_<optab><mode>_single): Likewise.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME2p2): New macro.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve-builtins-base.cc (class svexpand_impl):
Define new SVE function base.
* config/aarch64/aarch64-sve-builtins-base.def (svcompact): Allow
execution in streaming mode when SME2p2 is enabled.
* config/aarch64/aarch64-sve-builtins-base.h (svexpand): Declare
new SVE function base.
* config/aarch64/aarch64-sve-builtins-sve2.def (svcompact): Define
new SVE function.
(svexpand): Likewise.
* config/aarch64/aarch64-sve.md (@aarch64_sve_compact<mode>):
Enable 32- and 64-bit element variants under SME2p2. New
insn pattern for 8- and 16-bit elements.
(@aarch64_sve_expand<mode>): New insn pattern.
* config/aarch64/aarch64.h (TARGET_SVE_OR_SME2p2): New macro.
* config/aarch64/aarch64.md (UNSPEC_SVE_EXPAND): New UNSPEC.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve-builtins-sve2.cc
(class svfirst_lastp_impl): Define new SVE function base class.
(svfirstp): Define new SVE function base.
(svlastp): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def (svfirstp): Define
new SVE function.
(svlastp): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h (svfirstp): Declare
new SVE function base.
* config/aarch64/aarch64-sve2.md (@aarch64_pred_firstp<mode>): New
insn pattern.
(@aarch64_pred_lastp<mode>): Likewise.
* config/aarch64/iterators.md (UNSPEC_FIRSTP): New UNSPEC.
(UNSPEC_LASTP): Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve-builtins-sve2.cc (svrint32x): Define
new function base.
(svrint32z): Likewise.
(svrint64x): Likewise.
(svrint64z): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def (svrint32x):
Define new SVE function.
(svrint32z): Likewise.
(svrint64x): Likewise.
(svrint64z): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.h (svrint32x): Declare
new function base.
(svrint32z): Likewise.
(svrint64x): Likewise.
(svrint32z): Likewise.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_sd_float): New
type set.
(sd_float): New SVE type array.
* config/aarch64/aarch64-sve2.md (@cond_<frintnzs_op><mode>): New
insn pattern.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve-builtins-base.cc (class svcvtnt_impl):
Remove.
(svcvtnt): Redefine using narrowing_top_convert.
* config/aarch64/aarch64-sve-builtins-functions.h
(class narrowing_top_convert): New SVE function base class.
(NARROWING_TOP_CONVERT0): New function-like macro for specializing
narrowing_top_convert.
(NARROWING_TOP_CONVERT1): Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.cc (class svcvtxnt_impl):
Remove.
(svcvtxnt): Redefine using narrowing_top_convert.
* config/aarch64/aarch64-sve-builtins-sve2.def (svcvtlt): Allow
zeroing predication.
(svcvtnt): Likewise.
(svcvtxnt): Likewise.
* config/aarch64/aarch64-sve.md (@aarch64_sve_cvtnt<mode>):
Convert to compact syntax. Add operand 4 for values of
inactive lanes. New alternative for zeroing predication.
* config/aarch64/aarch64-sve2.md
(*cond_<sve_fp_op><mode>_relaxed): Convert to compact syntax.
New alternative for zeroing predication.
(*cond_<sve_fp_op><mode>_strict): Likewise.
(@aarch64_sve_cvtnt<mode>): Convert to compact syntax. Add
operand 4 for values of inactive lanes. New alternative for
zeroing predication.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md
(*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_relaxed):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
(*cond_<optab>_nonextend<SVE_HSDI:mode><SVE_PARTIAL_F:mode>_relaxed):
Likewise.
(*cond_<optab>_nonextend<SVE_FULL_HSDI:mode><SVE_FULL_F:mode>_strict):
Likewise.
(*cond_<optab>_extend<VNx4SI_ONLY:mode><VNx2DF_ONLY:mode>):
Likewise.
(*cond_<optab>_trunc<SVE_FULL_SDF:mode><SVE_FULL_HSF:mode>):
Likewise.
(*cond_<optab>_trunc<SVE_SDF:mode><SVE_PARTIAL_HSF:mode>):
Likewise.
(*cond_<optab>_trunc<VNx4SF_ONLY:mode><VNx8BF_ONLY:mode>):
Likewise.
(*cond_<optab>_nontrunc<SVE_FULL_HSF:mode><SVE_FULL_SDF:mode>):
Likewise.
(*cond_<optab>_nontrunc<SVE_PARTIAL_HSF:mode><SVE_SDF:mode>_relaxed):
Likewise.
* config/aarch64/aarch64-sve2.md
(*cond_<sve_fp_op><mode>_any_relaxed): Likewise.
(*cond_<sve_fp_op><mode>_any_strict): Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md
(*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_relaxed):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
(*cond_<optab>_nontrunc<SVE_PARTIAL_F:mode><SVE_HSDI:mode>_relaxed):
Likewise.
(*cond_<optab>_nontrunc<SVE_FULL_F:mode><SVE_FULL_HSDI:mode>_strict):
Likewise.
(*cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx4SI_ONLY:mode>):
Likewise.
(*cond_<optab>_trunc<VNx2DF_ONLY:mode><VNx2SI_ONLY:mode>_relaxed):
Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_any_relaxed):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
(*cond_<optab><mode>_any_strict): Likewise.
* config/aarch64/aarch64-sve2.md (*cond_<sve_fp_op><mode>):
Likewise.
(*cond_<sve_fp_op><mode>_strict): Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md (@cond_<optab><mode>):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
* config/aarch64/aarch64-sve2.md (@aarch64_pred_<optab><mode>):
Use zeroing predication variant for PRED_X.
(@cond_<optab><mode>): Accept constant zero as operand 3. New
alternative for zeroing predication. Add `arch` attribute to
every alternative.
* config/aarch64/predicates.md (aarch64_simd_reg_or_direct_zero):
New predicate.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md
(@aarch64_cond_sxt<SVE_FULL_HSDI:mode><SVE_PARTIAL_I:mode>):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
(*cond_uxt<mode>_any): Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md (*cond_<optab><mode>_any):
New alternative for zeroing predication. Add `arch` attribute
to every alternative.
(*cond_cnot<mode>_any): Likewise.
* config/aarch64/aarch64-sve2.md: (*cond_<sve_int_op><mode>):
Likewise.
2026-05-29 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64.h (TARGET_SVE2p2): New macro.
(TARGET_SME2p2): Likewise.
(TARGET_SVE2p2_OR_SME2p2): Likewise.
* config/aarch64/aarch64.md (arches): Add sve2p2_or_sme2p2 enum
constant.
(arch): Add test for sve2p2_or_sme2p2.
* doc/invoke.texi: Document sve2p2 and sme2p2 extensions.
2026-05-29 LIU Hao <lh_mouse@126.com>
* config/i386/i386.cc (ix86_decompose_address): Add a special case where
there's no base, there's an index, and the scale is 1.
2026-05-28 Roger Sayle <roger@nextmovesoftware.com>
* tree-ssa-loop-im.cc (ref_always_accessed_p): Rename to...
(ref_always_stored_p): New function specialized to determine if
REF is a store that is always executed in LOOP.
(execute_sm): Use ref_always_stored_p instead of
ref_always_accessed_p.
(class ref_always_accessed): Rename to..
(class ref_always_stored): Remove (always true) stored_p field.
(ref_always_stored::operator ()): Always check for a store.
Move hash table lookup, get_lim_data, after store test.
(can_sm_ref_p): Use ref_always_stored_p insead of
ref_always_accessed_p.
2026-05-28 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-features.cc (compute_convert_gain): Tweak
the cost of a 128-bit rotation to be 4 (or 5) instructions.
2026-05-28 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-features.cc (scalar_chain::add_insn): Don't
call analyze_register_chain if the USE is a SUBREG.
(scalar_chain::convert_op): Call gen_lowpart to convert
scalar (TImode) SUBREGs to vector (V1TImode) SUBREGs.
(convertible_comparison_p): We can now handle all general_operands
of *cmp<dwi>_doubleword.
(timode_remove_non_convertible_regs): We only need to check TImode
uses that aren't TImode SUBREGs of registers in other modes.
2026-05-28 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (inv_insn): New define_code_attr.
* config/i386/sse.md (<plusminus><mode>3): Accept a CONST_VECTOR
as the second operand. If the second operand is CONST1_RTX,
canonicalize to use CONSTM1_RTX instead.
(*add<mode>3_one): New define_insn_and_split to convert padd +1
to psub -1.
(*sub<mode>3_one): Likewise, a new define_insn_and_split to
convert psub +1 to padd -1.
2026-05-28 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_regno_to_class): Use the minimal
class containing each FP hard register: FP_REGS for f0-f7 and
f16-f31, RVC_FP_REGS for f8-f15.
(riscv_secondary_memory_needed): Use reg_class_subset_p to
detect FP classes.
2026-05-28 Zhongyao Chen <chen.zhongyao@zte.com.cn>
* config/riscv/riscv-vector-costs.cc (get_lmul_cost_scaling):
Enable scaling for all vector modes (VLA and VLS).
2026-05-28 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls (-masm-len-notes, -Wasm-len-notes): Add.
2026-05-28 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-sve.md
(*aarch64_vec_duplicate_subvector<vconsv><vconq><mode>):
New pattern.
* config/aarch64/iterators.md (VCONSV): New mode attribute.
(vconsv): Likewise.
2026-05-28 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_combine_internal<mode>):
New insn pattern.
(*aarch64_combine_internal_be<mode>): Likewise.
(*aarch64_combinez<mode>): Likewise.
(*aarch64_combinez_be<mode>): Likewise.
(@aarch64_vec_concat<mode>): Support smaller vector and scalar modes.
* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback):
Handle the case of two scalar elements.
* config/aarch64/iterators.md (SSUB64): New mode iterator.
(VSSUB64): Likewise.
(VSSUB32_I) : Likewise.
(VSSUB64_F): Likewise.
(VS32_I_SUB64_F): Likewise.
(single_wx): Define attribute for sub-64-bit vector and scalar modes.
(bitsize): Likewise.
(VDBL): Likewise.
(single_dwx): New mode attribute.
2026-05-28 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_dup_subvector<vconq><mode>):
New insn pattern.
(*aarch64_simd_dup_subvector<vcond><mode>): Likewise.
(@aarch64_simd_vec_set<mode>): Likewise.
(vec_set<mode>): Handle 16- and 32-bit vector modes in the expander.
* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Add
logic to initialize vector from starting subsequence. Make static.
(scalar_move_insn_p): Consider sub-64-bit vector moves scalar.
* config/aarch64/iterators.md (VDDUP): New iterator.
(VQDUP): Likewise.
(elem_bits): Define attribute for sub-64-bit vector modes.
(Vetype): Likewise.
(VEL): Likewise.
(single_wx): Define attribute for sub-64-bit vector and scalar modes.
(single_type): Likewise.
(VCOND): Likewise.
(VCONQ): Likewise.
(Vqduptype): New mode attribute.
(Vdduptype): Likewise.
(vcond): Likewise.
(vconq): Likewise.
(vstype): Define attribute for 64-bit vector and sub-128-bit scalar
modes.
2026-05-28 Artemiy Volkov <artemiy.volkov@arm.com>
* config/aarch64/aarch64-modes.def (VECTOR_MODE): Remove V2HF.
(VECTOR_MODES): Define V2QI, V4QI, V2HI, V2HF, V2BF.
* config/aarch64/aarch64-protos.h
(aarch64_advsimd_sub_dword_mode_p): Declare new predicate.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): New
define_insn_and_split pattern.
(mov<mode>): Add sub-64-bit vector modes to the VALL_F16 expander.
Forego const vector expansion for those modes.
* config/aarch64/aarch64.cc (aarch64_classify_vector_mode):
Handle 16- and 32-bit vector modes.
(aarch64_advsimd_sub_dword_mode_p): Define new predicate.
(aarch64_vectorize_vec_perm_const): Refuse for partial vector modes.
* config/aarch64/constraints.md (Da): New constraint.
* config/aarch64/iterators.md (VSUB64): New iterator.
(VALL_F16_SUB64): Likewise.
(size): Define attribute for sub-64-bit vector modes.
(VSC): New mode attribute.
(vstype): Likewise.
2026-05-28 Kewen Lin <linkewen@hygon.cn>
Xin Liu <liulxx@hygon.cn>
* config/i386/c86-4g-m7.md (c86_4g_m7_fpu): Remove automaton.
(c86_4g_m7_fpu02): New automaton.
(c86_4g_m7_fpu13): Ditto.
(c86-4g-m7-fpu0): Move to c86_4g_m7_fpu02 automaton.
(c86-4g-m7-fpu1): Move to c86_4g_m7_fpu13 automaton.
(c86-4g-m7-fpu2): Move to c86_4g_m7_fpu02 automaton.
(c86-4g-m7-fpu3): Move to c86_4g_m7_fpu13 automaton.
(c86-4g-m7-fdiv): Remove cpu unit.
(c86-4g-m7-fdiv1): New cpu unit.
(c86-4g-m7-fdiv3): Ditto.
(c86-4g-m7-fpu_0_3): New reservation.
(c86-4g-m7-fpu_1_3x2): Ditto.
(c86-4g-m7-fpu_1_3x3): Ditto.
(c86-4g-m7-fpu_1_3x6): Ditto.
(c86-4g-m7-fpux2): Ditto.
(c86-4g-m7-fpux4): Ditto.
(c86-4g-m7-fpux6): Ditto.
(c86-4g-m7-fpux8): Ditto.
(c86-4g-m7-fpux16): Ditto.
(c86-4g-m7-fp1fdiv1x4): Ditto.
(c86-4g-m7-fp3fdiv3x4): Ditto.
(c86-4g-m7-fdiv13): Ditto.
(c86-4g-m7-fp13div13): Ditto.
(c86-4g-m7-fp13div13x4): Ditto.
(c86-4g-m7-fp1div1_fp3div3_x4x8): Ditto.
(c86-4g-m7-fp1div1_fp3div3_x4x9): Ditto.
(c86-4g-m7-fp1div1_fp3div3_x4x11): Ditto.
(c86-4g-m7-fp1div1_fp3div3_x4x15): Ditto.
(c86-4g-m7-fp1div1_fp3div3_x4x18): Ditto.
(c86_4g_m7_idiv): New reservation.
(c86_4g_m7_idiv_QI): Adjust reservation latency and unit occupancy.
(c86_4g_m7_idiv_load): New reservation.
(c86_4g_m7_idiv_QI_load): Adjust reservation latency and unit
occupancy.
(c86_4g_m7_idiv_DI): Remove reservation.
(c86_4g_m7_idiv_SI): Ditto.
(c86_4g_m7_idiv_HI): Ditto.
(c86_4g_m7_idiv_DI_load): Ditto.
(c86_4g_m7_idiv_SI_load): Ditto.
(c86_4g_m7_idiv_HI_load): Ditto.
(c86_4g_m7_sse_insertimm): Adjust reservation units and unit
occupancy.
(c86_4g_m7_sse_insert): Ditto.
(c86_4g_m7_fp_sqrt): Adjust reservation.
(c86_4g_m7_fp_div): Ditto.
(c86_4g_m7_fp_div_load): Ditto.
(c86_4g_m7_fp_idiv_load): Ditto.
(c86_4g_m7_sse_pinsr_reg): Adjust reservation units and unit
occupancy.
(c86_4g_m7_sse_pinsr_reg_load): Ditto.
(c86_4g_m7_avx_vpinsr_reg): Ditto.
(c86_4g_m7_avx_vpinsr_reg_load): Ditto.
(c86_4g_m7_avx512_perm_xmm): Delete the prefix condition.
(c86_4g_m7_avx512_perm_xmm_opload): Ditto.
(c86_4g_m7_avx512_permi2_ymm): Adjust reservation units and unit
occupancy.
(c86_4g_m7_avx512_permi2_zmm): Ditto.
(c86_4g_m7_avx512_permi2_ymm_load): Ditto.
(c86_4g_m7_avx512_permi2_zmm_load): Ditto.
(c86_4g_m7_avx512_perm_zmm_imm): Ditto.
(c86_4g_m7_avx512_perm_zmm_imm_load): Ditto.
(c86_4g_m7_avx512_perm_zmm_noimm): Ditto.
(c86_4g_m7_sse_perm_zmm_noimm_load): Ditto.
(c86_4g_m7_avx_perm_ymm): Remove.
(c86_4g_m7_avx_perm_ymem): Ditto.
(c86_4g_m7_avx512_shuf_zmm): Adjust reservation units and unit
occupancy.
(c86_4g_m7_avx512_shuf_zmem): Ditto.
(c86_4g_m7_avx512_cmpestr): Ditto.
(c86_4g_m7_avx512_cmpestr_load): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto.
(c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto.
(c86_4g_m7_avx_ssecomi_comi): Ditto.
(c86_4g_m7_avx_ssecomi_comi_load): Ditto.
(c86_4g_m7_avx512_expand): Ditto.
(c86_4g_m7_avx512_expand_load): Ditto.
(c86_4g_m7_avx512_expand_z): Ditto.
(c86_4g_m7_avx512_expand_z_load): Ditto.
(c86_4g_m7_sse_movnt_xy): Rename to c86_4g_m7_sse_movnt.
(c86_4g_m7_avx512_sseadd_xy): Adjust reservation units.
(c86_4g_m7_avx512_sseadd_xy_load): Ditto.
(c86_4g_m7_sse_sseiadd_hplus): Adjust reservation units and unit
occupancy.
(c86_4g_m7_sse_sseiadd_hplus_load): Ditto.
(c86_4g_m7_avx512_ssemul): Adjust reservation units.
(c86_4g_m7_avx512_ssemul_load): Ditto.
(c86_4g_m7_avx512_ssediv): Remove.
(c86_4g_m7_avx512_ssediv_mem): Remove.
(c86_4g_m7_avx512_ssediv_x): New.
(c86_4g_m7_avx512_ssediv_xmem): New.
(c86_4g_m7_avx512_ssediv_y): New.
(c86_4g_m7_avx512_ssediv_ymem): New.
(c86_4g_m7_avx512_ssediv_z): Adjust reservation units.
(c86_4g_m7_avx512_ssediv_zmem): Ditto.
(c86_4g_m7_avx512_ssecmp_z): Add reservation units and unit
occupancy.
(c86_4g_m7_avx512_ssecmp_z_load): Ditto.
(c86_4g_m7_avx512_ssecmp_vp_z): New reservation.
(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
(c86_4g_m7_avx512_ssecmp_test_z): Remove reservation.
(c86_4g_m7_avx512_ssecmp_test_z_load): Ditto.
(c86_4g_m7_avx512_muladd): Broaden matching condition.
(c86_4g_m7_avx512_muladd_load): Ditto.
(c86_4g_m7_fma_muladd): Remove reservation.
(c86_4g_m7_fma_muladd_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_x): Add reservation units and unit
occupancy.
(c86_4g_m7_avx512_sse_conflict_x_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_y): Ditto.
(c86_4g_m7_avx512_sse_conflict_y_load): Ditto.
(c86_4g_m7_avx512_sse_conflict_z): Ditto.
(c86_4g_m7_avx512_sse_conflict_z_load): Ditto.
(c86_4g_m7_avx512_sse_class_z): Add reservation units and unit
occupancy.
(c86_4g_m7_avx512_sse_class_z_load): Ditto.
(c86_4g_m7_avx512_sse_sqrt): Remove.
(c86_4g_m7_avx512_sse_sqrt_load): Remove.
(c86_4g_m7_avx512_sse_sqrt_sf_x): New.
(c86_4g_m7_avx512_sse_sqrt_sf_xload): New.
(c86_4g_m7_avx512_sse_sqrt_sf_y): New.
(c86_4g_m7_avx512_sse_sqrt_sf_yload): New.
(c86_4g_m7_avx512_sse_sqrt_sf_z): New.
(c86_4g_m7_avx512_sse_sqrt_sf_zload): New.
(c86_4g_m7_avx512_sse_sqrt_df_x): New.
(c86_4g_m7_avx512_sse_sqrt_df_xload): New.
(c86_4g_m7_avx512_sse_sqrt_df_y): New.
(c86_4g_m7_avx512_sse_sqrt_df_yload): New.
(c86_4g_m7_avx512_sse_sqrt_df_z): New.
(c86_4g_m7_avx512_sse_sqrt_df_zload): New.
(c86_4g_m7_avx512_msklog_vector): Add reservation units and unit
occupancy.
(c86_4g_m7_avx512_mskmov_z_k): Ditto.
(c86_4g_m7_avx512_mskmov_k_reg): Ditto.
* config/i386/c86-4g.md (c86_4g_fp): Remove automaton.
(c86_4g_fp024): New automaton.
(c86_4g_fp1): Ditto.
(c86-4g-fp0): Move to c86_4g_fp024 automaton.
(c86-4g-fp1): Move to c86_4g_fp1 automaton.
(c86-4g-fp2): Move to c86_4g_fp024 automaton.
(c86-4g-fp3): Ditto.
(c86-4g-fp1fdivx4): New reservation.
(c86_4g_fp_sqrt): Adjust reservation.
(c86_4g_sse_sqrt_sf): Ditto.
(c86_4g_sse_sqrt_sf_mem): Ditto.
(c86_4g_sse_sqrt_df): Ditto.
(c86_4g_sse_sqrt_df_mem): Ditto.
(c86_4g_fp_op_div): Ditto.
(c86_4g_fp_op_div_load): Ditto.
(c86_4g_fp_op_idiv_load): Adjust reservation latency.
(c86_4g_ssediv_ss_ps): Adjust reservation.
(c86_4g_ssediv_ss_ps_load): Ditto.
(c86_4g_ssediv_sd_pd): Ditto.
(c86_4g_ssediv_sd_pd_load): Ditto.
(c86_4g_ssediv_avx256_ps): Ditto.
(c86_4g_ssediv_avx256_ps_load): Ditto.
(c86_4g_ssediv_avx256_pd): Ditto.
(c86_4g_ssediv_avx256_pd_load): Ditto.
2026-05-28 Zhongyao Chen <chen.zhongyao@zte.com.cn>
* config/riscv/riscv-vector-costs.cc
(estimated_loop_iters): New function.
(compare_loop_overhead): New function.
(costs::better_main_loop_than_p): Compare RVV loop overhead after
inside-loop cost.
2026-05-28 Alex Coplan <alex.coplan@arm.com>
* config/aarch64/aarch64.cc (aarch64_strip_extend): Replace
(unsigned HOST_WIDE_INT) INVAL (x) with UINTVAL (x).
* config/aarch64/predicates.md (aarch64_shift_imm_si): Likewise.
(aarch64_shift_imm_di): Likewise.
(aarch64_shift_imm64_di): Likewise.
(aarch64_imm3): Likewise.
2026-05-28 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_read_number, avr_length_of_asm)
(avr_maybe_length_of_asm): New static functions.
(avr_adjust_insn_length): Call avr_maybe_length_of_asm on
unrecognized insns.
* config/avr/avr.opt (-masm-len-notes, -Wasm-len-notes): New
options.
* doc/invoke.texi (AVR Options): Add -masm-len-notes,
-Wasm-len-notes.
* doc/extend.texi (Size of an asm): Add @subsubheading
"Specifying the size of an asm on AVR".
2026-05-28 Georg-Johann Lay <avr@gjlay.de>
PR target/121343
* config/avr/avr.md (divmod<mode>4, udivmod<mode>4): Use
hard-reg constraints instead of explicit hard-regs.
(*divmodqi4_call_split, *udivmodqi4_call_split): Remove.
(*divmodhi4_call_split, *udivmodhi4_call_split): Remove.
(*divmodpsi4_call_split, *udivmodpsi4_call_split): Remove.
(*divmodsi4_call_split, *udivmodsi4_call_split): Remove.
2026-05-28 Jakub Jelinek <jakub@redhat.com>
PR target/125469
* config/i386/i386.md (*add<mode>_1<nf_name>): Don't return "#" for
the lea non-TARGET_APX_NDD case, instead emit a lea directly.
2026-05-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* ext-dce.cc (ext_dce_try_optimize_extension): Handle
SIGN_EXTEND of MEM by replacing with ZERO_EXTEND of MEM
when upper bits are dead.
2026-05-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* ext-dce.cc (ext_dce_process_uses): Fix off-by-one: use
size > 32 instead of size >= 32 for group 3 liveness.
2026-05-27 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.md (movdi_aarch64): Use aarch64_output_move_imm
to select w-regs.
* config/aarch64/aarch64.cc (aarch64_output_move_imm): New function.
* config/aarch64/aarch64-protos.h (aarch64_output_move_imm): Add
declaration.
2026-05-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/120164
* tree-if-conv.cc (if_convertible_stmt_p): Detect prefetches.
(predicate_statements): Drop them during predication.
2026-05-27 oltolm <oleg.tolmatcev@gmail.com>
PR target/54412
* target.def (overaligned_stack_slot_required): New calls hook.
* calls.cc (allocate_call_dynamic_stack_space): New helper.
(initialize_argument_information): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
by-reference argument copies.
(expand_call): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
hidden return slots.
* function.cc (assign_stack_local_aligned): New helper.
(assign_parm_setup_block): Use
targetm.calls.overaligned_stack_slot_required for over-aligned
stack parm slots.
(assign_parm_setup_reg): Likewise.
* config/i386/i386.cc (ix86_overaligned_stack_slot_required): New.
(TARGET_OVERALIGNED_STACK_SLOT_REQUIRED): Define for i386.
* doc/tm.texi.in: Add hook placement.
* doc/tm.texi: Regenerate.
2026-05-27 oltolm <oleg.tolmatcev@gmail.com>
PR target/89597
* config/i386/i386.cc (function_value_ms_64): Handle 32-byte and
64-byte vector returns in registers when supported.
(ix86_return_in_memory): Do not force 32-byte/64-byte eligible
vector returns to memory for MS ABI.
2026-05-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/120352
* tree-vectorizer.h (LOOP_VINFO_EARLY_BRK_NEEDS_EPILOG): New.
(class _loop_vec_info): Add early_break_needs_epilogue.
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Detect
usage of stores.
* tree-vect-loop-manip.cc (vect_do_peeling): Use them.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Likewise.
(vect_create_loop_vinfo): Likewise.
(vect_update_ivs_after_vectorizer_for_early_breaks): Likewise.
* tree-vect-stmts.cc (vect_stmt_relevant_p): Likewise.
2026-05-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/120352
* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Add
redirect_exits.
(vect_do_peeling): Use it.
* tree-vectorizer.h (slpeel_tree_duplicate_loop_to_edge_cfg): Update
prototype.
2026-05-27 Tamar Christina <tamar.christina@arm.com>
PR target/125148
* config/aarch64/aarch64-sve.md
(*aarch64_vec_shl_insert_into_zero_<mode>,
*aarch64_vec_shl_insert_into_zero_vnx16qi,
*aarch64_vec_shl_insert_from_load_<mode>): New.
* config/aarch64/aarch64.cc (aarch64_emit_load_store_through_mode):
Replace paradoxical subreg with zero-extend.
2026-05-27 Evgeny Karpov <evgeny.karpov@arm.com>
* config/aarch64/aarch64-coff.h (SUPPORTS_INIT_PRIORITY):
Enable SUPPORTS_INIT_PRIORITY by default.
2026-05-27 liuhongt <hongtao.liu@intel.com>
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Disable
for m_DIAMONDRAPIDS.
(X86_TUNE_USE_GATHER_4PARTS): Likewise.
2026-05-26 Sergei Trofimovich <siarheit@google.com>
PR bootstrap/125318
* tree-vect-stmts.cc (vectorizable_load): Explicitly
initialize stride_step to work around
-Werror=maybe-uninitialized build failure.
2026-05-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125396
* tree-cfgcleanup.cc (bb_phis_references_abnormal_uses): New function.
(maybe_remove_forwarder_block): Check to make sure the
forwarder block does not have a phi that references ssa name that has
abnormal uses.
2026-05-26 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-fusion.cc (riscv_fusion_same_dest_p):
New function.
(riscv_set_is_add_p): Rename from riscv_set_is_add.
(riscv_set_is_addi_p): Rename from riscv_set_is_addi.
(riscv_set_is_adduw_p): Rename from riscv_set_is_adduw.
(riscv_set_is_shNadd_p): Rename from riscv_set_is_shNadd.
(riscv_set_is_shNadduw_p): Rename from riscv_set_is_shNadduw.
(riscv_fuse_zextws): New function.
(riscv_fuse_zexth): Likewise.
(riscv_fuse_ldindexed): Likewise.
(riscv_fuse_expanded_ld): Likewise.
(riscv_fuse_ldpreincrement): Likewise.
(riscv_fuse_lui_addi): Likewise.
(riscv_fuse_auipc_addi): Likewise.
(riscv_fuse_lui_ld): Likewise.
(riscv_fuse_auipc_ld): Likewise.
(riscv_fuse_cache_aligned_std): Likewise.
(riscv_fuse_aligned_std): Likewise.
(riscv_fuse_bfext): Likewise.
(riscv_fuse_b_alui): Likewise.
(struct riscv_fusion_entry): New struct.
(riscv_fusion_table): New table.
(riscv_macro_fusion_pair_p): Refactor to use table-driven
dispatch loop with simplified checker interface.
2026-05-26 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-fusion.cc (riscv_macro_fusion_pair_p):
Fix XINT to access SET_SRC (prev_set) in AUIPC_LD case.
Fix base register comparison from != to == in
CACHE_ALIGNED_STD case. Remove redundant CONST_INT_P
check in B_ALUI sub+smax case. Remove duplicate REG_P
check in LDINDEXED case. Fix typo in comment. Fix dump
output name for CACHE_ALIGNED_STD.
2026-05-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125453
* match.pd (`(smaller)a ==/!= (smaller) b`): Reject
non integral types.
2026-05-25 Georg-Johann Lay <avr@gjlay.de>
PR target/125409
* config/avr/avr-fixed.md (FIXED_A, FIXED_B): Add PSI to iterators.
2026-05-25 Georg-Johann Lay <avr@gjlay.de>
PR target/121343
* config/avr/avr.md (load_<mode>_libgcc): Rewrite to use
a hard-reg constraint for operand 0.
(gen_load<mode>_libgcc): Remove expander.
(mov<mode>): No more special handling needed for sources that
satisfy avr_load_libgcc_p.
2026-05-25 Tobias Burnus <tburnus@baylibre.com>
PR c/125377
* omp-general.cc (omp_check_for_duplicate_variant): Fix used
tree for 'inform' part of the error message.
2026-05-25 Eric Botcazou <ebotcazou@adacore.com>
* doc/invoke.texi (fstack-usage): Document new second field.
* toplev.cc (output_stack_usage_1): Revert latest changes and add
the mangled name as the second field.
2026-05-25 Richard Sandiford <rdsandiford@googlemail.com>
* bitmap.cc (bitmap_last_set_bit): Fix handling of index 0.
2026-05-25 liuhongt <hongtao.liu@intel.com>
PR middle-end/124630
* match.pd (popcount (x ^ (x - 1))): Fold to ctz (x) + 1 when
x is nonzero and CTZ is directly supported.
2026-05-24 Raven Hallsby <karl@hallsby.com>
PR tree-optimization/125104
* match.pd (`(~y & x) ^ y`): New Pattern.
2026-05-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* toplev.cc (output_stack_usage_1): Print out the human readable
name in quotes.
2026-05-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125419
* tree-if-conv.cc (factor_out_operators): Change
asserts about abnormals into a conditional to reject
it.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (fold_overflow_warning): Removed.
(pointer_may_wrap_p): Removed.
(fold_comparison): Removed fold_overflow_warning and
pointer_may_wrap_up calls.
(fold_binary_loc): Likewise.
* fold-const.h (fold_overflow_warning): Removed.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (fold_binary_loc): Likewise.
(tree_expr_nonnegative_warnv_p): Renamed to
tree_expr_nonnegative_p. Argument strict_overflow_p removed.
(tree_expr_nonnegative_p): Removed.
(RECURSE): Removed strict_overflow_p argument.
(tree_unary_nonnegative_p): Local strict_overflow_p variable
added to support the RECURSE() macro was removed.
(tree_binary_nonnegative_p): Likewise.
(tree_single_nonnegative_p): Likewise.
(tree_call_nonnegative_p): Likewise.
(tree_invalid_nonnegative_p): Likewise.
(tree_binary_nonzero_p): Removed sub_strict_overflow_p variable
from tree_expr_nonnegative_p call.
* fold-const.h (tree_expr_nonnegative_p): Removed.
(tree_expr_nonnegative_warnv_p): Renamed to
tree_expr_nonnegative_p, removed strict_overflow_p argument.
* tree-ssa-loop-manip.cc (create_iv): Removed ovf variable from
tree_expr_nonnegative_p call.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_call_nonnegative_warnv_p): Renamed to
tree_call_nonnegative_warnv_p.
(tree_call_nonnegative_p): Removed strict_overflow_p flag.
(tree_invalid_nonnegative_warnv_p): Renamed to
tree_invalid_nonnegative_p.
(tree_invalid_nonnegative_p): Removed strict_overflow_p flag.
(tree_expr_nonnegative_warnv_p): Added ATTRIBUTE_UNUSED tag in
the now unused strict_overflow_p argument. Removed
strict_overflow_p call from tree_invalid_nonnegative_p.
* fold-const.h (tree_call_nonnegative_warnv_p): Renamed to
tree_call_nonnegative_p.
(tree_call_nonnegative_p): Removed strict_overflow_p flag.
* gimple-fold.cc (gimple_call_nonnegative_warnv_p): Renamed to
gimple_call_nonnegative_p.
(gimple_call_nonnegative_p): Removed strict_overflow_p flag.
(gimple_stmt_nonnegative_warnv_p): Renamed to
gimple_stmt_nonnegative_p.
(gimple_stmt_nonnegative_p): Removed strict_overflow_p flag.
* gimple-fold.h (gimple_stmt_nonnegative_warnv_p): Renamed to
gimple_stmt_nonnegative_p.
(gimple_stmt_nonnegative_p): Removed strict_overflow_p flag.
* gimple-range-fold.cc (fold_using_range::fold_stmt): Removed
strict_overflow_p flag from gimple_stmt_nonnegative_p.
(fold_using_range::range_of_call): Likewise.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_single_nonnegative_warnv_p): Renamed to
tree_single_nonnegative_p.
(tree_single_nonnegative_p): Removed strict_overflow_p flag.
(tree_expr_nonnegative_warnv_p): Removed strict_overflow_p flag
from tree_single_nonnegative_p call.
* fold-const.h (tree_single_nonnegative_warnv_p): Renamed to
tree_single_nonnegative_p.
(tree_single_nonnegative_p): Removed strict_overflow_p flag.
* gimple-fold.cc (gimple_assign_nonnegative_warnv_p): Renamed to
gimple_assign_nonnegative_p.
(gimple_assign_nonnegative_p): Removed strict_overflow_p flag.
(gimple_phi_nonnegative_warnv_p): Renamed to
gimple_phi_nonnegative_p.
(gimple_phi_nonnegative_p): Removed strict_overflow_p flag.
(gimple_stmt_nonnegative_warnv_p): Removed strict_overflow_p
flag from gimple_phi_nonnegative_p and gimple_assign_nonnegative_p
calls.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_unary_nonnegative_warnv_p): Renamed to
tree_unary_nonnegative_p.
(tree_unary_nonnegative_p): Removed strict_overflow_p flag.
(tree_expr_nonnegative_warnv_p): Removed strict_overflow_flag
from tree_unary_nonnegative_p calls.
* fold-const.h (tree_unary_nonnegative_warnv_p): Renamed to
tree_unary_nonnegative_p.
(tree_unary_nonnegative_p): Removed strict_overflow_p flag.
* gimple-fold.cc (gimple_assign_nonnegative_warnv_p): Removed
strict_overflow_flag from tree_unary_nonnegative_p calls.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_binary_nonnegative_warnv_p): Renamed to
tree_binary_nonnegative_p.
(tree_binary_nonnegative_p): Removed strict_overflow_p flag. Add
a local variable with the same name for RECURSE() that we'll
remove later.
(tree_expr_nonnegative_warnv_p): Removed strict_overflow_p flag
from tree_binary_nonnegative_p call.
* fold-const.h (tree_binary_nonnegative_warnv_p): Renamed to
tree_binary_nonnegative_p.
(tree_binary_nonnegative_p): Removed strict_overflow_p flag.
* gimple-fold.cc (gimple_assign_nonnegative_warnv_p): Likewise.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (maybe_canonicalize_comparison_1): Removed
strict_overflow_p flag.
(maybe_canonicalize_comparison): Removed strict_overflow_p
flag and all fold_overflow_warning calls.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_expr_nonzero_warnv_p): Renamed to
tree_expr_nonzero_p and removed the strict_overflow_p flag.
(tree_expr_nonzero_p): Removed it since it's now redundant with
tree_expr_nonzero_warnv_p.
(tree_unary_nonzero_p): Removed the local sub_strict_overflow_p
flag from the tree_expr_nonzero_p call.
(tree_binary_nonzero_p): Likewise.
(tree_single_nonzero_p): Likewise.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_expr_nonzero_warnv_p): Removed
strict_overflow_p flag.
(tree_single_nonzero_warnv_p): Renamed to tree_single_nonzero_p.
(tree_single_nonzero_p): Removed strict_overflow_p flag.
* fold-const.h (tree_single_nonzero_warnv_p): Renamed to
tree_single_nonzero_p.
(tree_single_nonzero_p): Removed strict_overflow_p flag.
* gimple-range-fold.cc (fold_using_range::range_of_address):
Removed strict_overflow_p flag.
(range_from_readonly_load): Likewise.
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Likewise.
* tree-ssa-phiopt.cc (absorbing_element_p): Likewise.
* value-query.cc (range_query::get_tree_range): Likewise.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (tree_expr_nonzero_warnv_p): Removed
strict_overflow_p flag from tree_binary_nonzero_p call.
(tree_binary_nonzero_warnv_p): Renamed to tree_binary_nonzero_p.
(tree_binary_nonzero_p): Removed strict_overflow_p flag.
* fold-const.h (tree_binary_nonzero_warnv_p): Renamed to
tree_binary_nonzero_p.
(tree_binary_nonzero_p): Removed strict_overflow_p flag.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (mask_with_tz): Changed comment that describes
tree_expr_nonzero_warnv_p warn on overflow behavior.
(tree_expr_nonzero_warnv_p): Removed strict_overflow_p flag.
(tree_unary_nonzero_warnv_p): Renamed to tree_unary_nonzero_p.
(tree_unary_nonzero_p): Removed strict_overflow_p flag.
* fold-const.h (tree_unary_nonzero_warnv_p): Renamed to
tree_unary_nonzero_p.
(tree_unary_nonzero_p): Removed strict_overflow_p flag.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (extract_muldiv): Removed strict_overflow_p
references, including temporary variables and comments.
(extract_muldiv_1): Likewise.
(fold_binary_loc): Likewise.
2026-05-23 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* fold-const.cc (make_range_step): Likewise.
(make_range): Likewise.
(fold_range_test): Likewise.
* fold-const.h (make_range): Likewise.
(make_range_step): Likewise.
* tree-ssa-reassoc.cc (init_range_entry): Likewise.
2026-05-23 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/riscv/bitmanip.md (slli_slli_uw): New pattern.
(plus+and+ashift splitter): Turn into define_insn_and_split.
(riscv_slli_uw): Renamed from *slliuw.
2026-05-23 Dimitar Dimitrov <dimitar@dinux.eu>
* config/pru/constraints.md (MULDST_REGS): Remove constraint.
(MULSRC0_REGS): Ditto.
(MULSRC1_REGS): Ditto.
* config/pru/predicates.md (pru_muldst_operand): Compare
register number directly.
(pru_mulsrc0_operand): Ditto.
(pru_mulsrc1_operand): Ditto.
* config/pru/pru.h (enum reg_class): Remove single-reg classes.
(REG_CLASS_NAMES): Ditto.
(REGNO_REG_CLASS): Ditto.
* config/pru/pru.md (mulsi3): Switch to hard register constraints.
(umulsidi3): Ditto.
2026-05-23 Dimitar Dimitrov <dimitar@dinux.eu>
* config/pru/constraints.md: Prevent allocating r27 as
SImode destination for mulsi3 pattern.
* config/pru/pru.h (enum reg_class): Expand MULDST_REGS
to allow fitting DImode.
* config/pru/pru.md (umulsidi3): New pattern.
(muldi3): Ditto.
2026-05-22 Disservin <disservin.social@gmail.com>
PR target/50481
* config/aarch64/aarch64.md (bitreverse<mode>2, bitreverseqi2,
bitreversehi2): New expanders.
* config/aarch64/aarch64-simd.md (bitreverse<mode>2): New expander.
2026-05-22 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-protos.h (common_vector_cost): Add
reduc_i8_cost through reduc_f64_cost and
reduc_f{16,32,64}_ordered_cost.
* config/riscv/riscv.cc: Set costs in rvv_vls_vector_cost and
rvv_vla_vector_cost.
* config/riscv/riscv-vector-costs.cc (is_reduction): New helper.
(get_reduction_cost): New helper.
(costs::adjust_stmt_cost): Use them for vec_to_scalar kind.
2026-05-22 Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/125375
* cfgrtl.cc (flow_active_insn_p): Return true for clobbers.
2026-05-22 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/125399
* match.pd (BITREVERSE): Add BUILT_IN_BITREVERSE8.
2026-05-22 Steve Markgraf <steve@steve-m.de>
* config/rs6000/rs6000.h (TARGET_NO_LWSYNC): Add PROCESSOR_MPCCORE.
2026-05-22 Avinal Kumar <avinal.xlvii@gmail.com>
PR tree-optimization/125050
* match.pd: (X != C1 ? -X : C2): Handle C1 being INT_MIN
by emitting (signed)(-(unsigned)X) instead of bailing out.
2026-05-21 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* avoid-store-forwarding.cc
(store_forwarding_analyzer::avoid_store_forwarding): Replace
return with flush-and-continue for complex memory operations.
2026-05-21 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* avoid-store-forwarding.cc: Include regs.h.
(record_hard_reg_clobbers): New callback.
(store_forwarding_analyzer::m_bb_live_after): New cache.
(store_forwarding_analyzer::compute_bb_live_after): New helper.
(store_forwarding_analyzer::process_store_forwarding): Add
liveness check for hard registers clobbered by bit-insert
sequences, using the cached per-BB live-out information, and
evict the load_insn entry from the cache before delete_insn
in the load-elim path.
(store_forwarding_analyzer::avoid_store_forwarding): Clear the
per-BB liveness cache on entry.
2026-05-21 Konstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>
* avoid-store-forwarding.cc
(store_forwarding_analyzer::avoid_store_forwarding): Remove
store_exprs_del vector and all associated tracking. Remove the
same_range_as_removed check from the forwarding loop. Update
block comment.
2026-05-21 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Prerequisites): The C++ front end also does
not use extensions.
2026-05-21 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/123791
* config/aarch64/aarch64.cc (aarch64_cannot_force_const_mem): Remove
forcing symbol references to const mem.
(aarch64_can_use_per_function_literal_pools_p): Return false for
large model.
(aarch64_use_blocks_for_constant_p): Update comment.
(initialize_aarch64_code_model): Allow PIC/PIE.
(aarch64_classify_symbol): Use SYMBOL_SMALL_ABSOLUTE for constant
references and SYMBOL_SMALL_GOT_4G for writeable data.
2026-05-21 Xi Ruoyao <xry111@xry111.site>
PR target/125320
* config/riscv/riscv.md (stack_protect_test_<mode>): Call
riscv_output_move() instead of hard coding <load>.
(stack_protect_set_<mode>): Call riscv_output_move() instead of
hard coding <load> and <store>.
2026-05-21 Martin Jambor <mjambor@suse.cz>
* ipa-cp.cc (get_max_overall_size): Remove parameter CUR_SWEEP and
its use.
(decide_about_value): Adjust the call to get_max_overall_size.
(decide_whether_version_node): Likewise.
* params.opt (param_ipa_cp_eval_threshold): Initialize to 1100.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv.opt.urls: Regenerate.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* common/config/riscv/riscv-common.cc (riscv_handle_option):
Handle Zilsd alignment options and clear the Zilsd-specific
explicit marker for -mstrict-align.
* config/riscv/riscv-opts.h (riscv_zilsd_align_type): New enum.
* config/riscv/riscv-protos.h
(riscv_expand_zilsd_misaligned_move): Declare as void.
(riscv_zilsd_valid_mem_p): Declare.
* config/riscv/riscv.cc (riscv_zilsd_required_align): New
functions.
(riscv_zilsd_valid_mem_p): New function.
(riscv_rtx_costs): Honor Zilsd alignment policy.
(riscv_split_64bit_move_p): Split invalid Zilsd GPR accesses.
(riscv_expand_zilsd_misaligned_move): New function.
(riscv_can_inline_p): Check effective Zilsd alignment policy.
(riscv_override_options_internal): Reject explicit Zilsd
alignment options for RV64.
* config/riscv/riscv.md (movmisaligndi): New expander.
(movmisaligndf): New expander.
* config/riscv/riscv.opt: Add -mzilsd-word-align and
-mzilsd-strict-align.
* config/riscv/riscv.opt.urls: Regenerate.
* doc/invoke.texi: Document the new options.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/andes_vector.h: Define intrinsic detection macros.
* config/riscv/riscv_bitmanip.h: Likewise.
* config/riscv/riscv_crypto.h: Likewise.
* config/riscv/riscv_vector.h: Likewise.
* config/riscv/sifive_vector.h: Likewise.
* doc/extend.texi: Document RISC-V intrinsic detection macros.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* common/config/riscv/riscv-ext-bitmask.def: Add zicfiss.
* config/riscv/riscv-ext.def: Add C API bit position for
zicfiss.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* common/config/riscv/riscv-ext-bitmask.def: Add supm,
zicntr, zihpm, zfbfmin, zvfbfmin, zvfbfwma, zicbom,
zaamo, zalrsc, zabha, zalasr, zicbop, and zicfilp.
* config/riscv/riscv-ext.def: Add C API bit positions for
supm, zicntr, zihpm, zfbfmin, zvfbfmin, zvfbfwma,
zicbom, zaamo, zalrsc, zabha, zalasr, zicbop, and
zicfilp.
2026-05-21 Christoph Müllner <christoph.muellner@vrull.eu>
* common/config/riscv/riscv-ext-bitmask.def: Add b, e, h,
zilsd, zclsd, zcmp, zifencei, and zmmul.
2026-05-21 Georg-Johann Lay <avr@gjlay.de>
PR target/121343
* config/avr/avr.md (ctz_ffs, cxz_ffs): New code iterators.
(clzhi2, ctzhi2, ffshi2, clzsi2, ctzsi2, ffssi2, bswapsi2): New
insn-and-split's from former expanders.
2026-05-21 Xi Ruoyao <xry111@xry111.site>
PR target/50481
* config/loongarch/loongarch.md (@rbit<GPR:mode>2): Rename to
...
(@bitreverse<mode>2): ... this.
(rbithi2): Rename to ...
(bitreversehi2): ... this.
(rbitqi2): Rename to ...
(bitreverseqi2): ... this.
(rbitsi_extended): Rename to ...
(bitreversesi2_extended): ... this.
2026-05-20 Shivam Gupta <shivam98.tkg@gmail.com>
PR tree-optimization/112533
* match.pd: Add integral narrowing eq/ne to XOR-against-zero
rule for (T)(x) == (T)(y) where precision(T) < precision(x).
2026-05-20 Richard Sandiford <rdsandiford@googlemail.com>
* cselib.h (references_value_p): Remove only_useless parameter.
* cselib.cc (references_value_p): Likewise. Use rtx iterators.
(invariant_or_equiv_p): Update accordingly.
* postreload.cc (reload_cse_simplify_set): Likewise.
* var-tracking.cc (reverse_op): Likewise.
2026-05-20 Richard Sandiford <rdsandiford@googlemail.com>
* cselib.h (cselib_val::HASH_MASK): New static constant.
(cselib_val::hash): Turn into a 30-bit bitfield.
(cselib_val::in_preserved_table_p): New bitfield.
(cselib_val::all_locs_preserved_p): Likewise.
* cselib.cc: Include rtl-iter.h.
(cselib_preserved_prune_list): New variable.
(cselib_clear_all_locs_preserved): New function.
(new_elt_loc_list): Call it when modifying a value's location list.
(preserve_constants_and_equivs): Set in_preserved_table_p when
moving a value to the preserved hash table. Also push such values
onto cselib_preserved_prune_list.
(cselib_find_slot): Mask out the upper 2 bits of the hash.
(discard_useless_locs): New overload, split out from original
hash table traverse callback. Use an inline rtl iteration
instead of calling references_value_p. Record whether the
retained location only reference preserved value.
(remove_useless_values): Iterate over cselib_preserved_prune_list
instead of the hash table itself. Remove a value from the list
if all remaining locations only reference preserved value.
(new_cselib_val): Initialize the new bitfields.
(cselib_finish): Free cselib_preserved_prune_list.
2026-05-20 Richard Sandiford <rdsandiford@googlemail.com>
* cselib.cc (new_elt_loc_list): Cache CSELIB_VAL_PTR.
2026-05-20 Nathan Sidwell <nathan@acm.org>
* config/riscv/riscv-builtins.cc (enum riscv_builtin_type): Delete.
(struct riscv_builtin_description): Replace builtin_type by bool.
Reorder fields for better packing.
(RISCV_BUILTIN_NO_PREFIX): Remove BUILTIN_TYPE arg.
(RISCV_BUILTIN): Likewise, call RISCV_BUILTIN_NO_PREFIX.
(DIRECT_BUILTIN): Adjust RISCV_BUILTIN invocation.
(DIRECT_NO_TARGET_BUILTIN): Delete.
(riscv_builtins): Make non-constant. Adjust initializers.
(riscv_init_builtins): Compute no_target from function type.
(riscv_expand_builtin): Simplify.
* config/riscv/andes.def: Adjust.
* config/riscv/corev.def: Adjust.
* config/riscv/riscv-cmo.def: Adjust.
* config/riscv/riscv-scalar-crypto.def: Adjust.
2026-05-20 Uros Bizjak <ubizjak@gmail.com>
* config/i386/x86-tune.def (X86_TUNE_SHIFT1): Remove.
* config/i386/i386.h (TARGET_SHIFT1): Remove.
* config/i386/i386.md (*ashl<mode>3_1<nf_name>): Remove
TARGET_SHIFT1-gated implicit-1 encoding and simplify
length_immediate attribute.
(*ashlsi3_1_zext): Likewise.
(*ashlhi3_1<nf_name>): Likewise.
(*ashlqi3_1<nf_name>): Likewise.
(*ashl<mode>3_1_slp): Likewise.
(*ashl<mode>3_cmp): Likewise.
(*ashlsi3_cmp): Likewise.
(*<any_shiftrt:insn><mode>3_1<nf_name>): Likewise.
(*<any_shiftrt:insn>si3_1_zext): Likewise.
(*<any_shiftrt:insn><mode>3_1_slp): Likewise.
(*<any_shiftrt:insn><mode>3_cconly): Likewise.
(*<any_shiftrt:insn>qi_ext<mode>_1): Likewise.
(<any_shiftrt:insn><mode>3_carry): Likewise.
2026-05-20 Michiel Derhaeg <michiel@synopsys.com>
PR target/115650
* config/arc/arc.cc (legitimate_small_data_address_p): Check
offset size.
2026-05-20 Jakub Jelinek <jakub@redhat.com>
PR target/125373
* config/i386/i386.md
(Convert imul by three, five and nine into lea define_peephole2s): Use
index_reg_operand instead of register_operand.
2026-05-20 Jakub Jelinek <jakub@redhat.com>
PR target/125357
* config/i386/i386-expand.cc (ix86_expand_vec_perm): For TARGET_AVX
one_operand_shuffle handle also V2DImode and V2DFmode using
vpaddq and vpermilpd.
2026-05-20 liuhongt <hongtao.liu@intel.com>
* tree-ssa-loop-unswitch.cc (estimate_loop_insns): New function.
(init_loop_unswitch_info): Do not select an outer loop for
unswitching when the duplicated outer-body size exceeds
param_max_unswitch_insns.
2026-05-20 Zhou Qiankang <wszqkzqk@qq.com>
PR target/125362
* config/loongarch/t-loongarch (TM_H): Add
common/config/loongarch/cpu-features.h.
2026-05-19 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR target/123748
* config/aarch64/aarch64-simd.md (vec_packs_float_v2di): New pattern.
2026-05-19 Christopher Bazley <chris.bazley@arm.com>
* config/aarch64/aarch64.cc (aarch64_call_scalar_result_in_simd_reg_p):
New function to determine probabilistically whether a gcall
produces a scalar result in a SIMD/FP register.
(aarch64_scalar_op_to_vec_p): New function to determine
whether or not to add scalar_to_vec_cost per scalar operand
from which a vector is to be constructed.
(aarch64_external_adjust_stmt_cost): New function to adjust the
cost of an SLP tree node for a vec_construct that is fed by
values defined outside the vectorized region.
(aarch64_vector_costs::add_stmt_cost): Call the new
aarch64_external_adjust_stmt_cost function if we have an SLP
node and a vector type.
2026-05-19 Paul-Antoine Arras <parras@baylibre.com>
Chung-Lin Tang <cltang@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
* fold-const.cc (operand_compare::operand_equal_p): Handle
OMP_ARRAY_SECTION.
* gimplify.cc (gimplify_scan_omp_clauses): Call
omp_remove_duplicate_maps after partial clause expansion.
* omp-general.cc (omp_remove_duplicate_maps): New function.
* omp-general.h (omp_remove_duplicate_maps): Declare.
* omp-low.cc (install_var_field): Add new 'tree key_expr = NULL_TREE'
default parameter. Set splay-tree lookup key to key_expr instead of
var if key_expr is non-NULL. Adjust call to install_parm_decl.
Update comments.
(scan_sharing_clauses): Use clause tree expression as splay-tree key
for map/to/from and OpenACC firstprivate cases when installing the
variable field into the send/receive record type.
(lower_oacc_reductions): Adjust to find map-clause of reduction
variable, then create receiver-ref.
(lower_omp_target): Adjust to lookup var field using clause expression.
2026-05-19 Jakub Jelinek <jakub@redhat.com>
PR other/125348
* config/i386/i386-expand.cc (ix86_expand_builtin): Fix diagnostic
typo, forth -> fourth.
2026-05-19 Georg-Johann Lay <avr@gjlay.de>
PR target/50481
* config/avr/avr.md (bitreverseqi2): New insn-and-split.
(*bitreverseqi2): New insn.
2026-05-19 Roger Sayle <roger@nextmovesoftware.com>
PR target/90483
PR libstdc++/118416
* config/i386/i386-expand.cc (ix86_expand_sse_ptest): Refactor
with optimizations for PTESTZ*, PTESTC* and PTESTNZC*, including
transforming ptestz(x,-1) into ptestz(x,x).
2026-05-19 Christophe Lyon <christophe.lyon@arm.com>
PR target/124870
* config/arm/arm-mve-builtins-base.cc (vstrq_scatter_base_impl)
(vldrq_gather_base_impl): Fix call_properties.
2026-05-19 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cfgrtl.cc: Don't include gimplify.h or gimplify-me.h.
* cgraphbuild.cc: Likewise.
* emit-rtl.cc: Likewie.
* tree-ssa-dom.cc: Likewise.
* tree-ssa-dse.cc: Likewise.
* tree-ssa-loop-im.cc: Likewise.
* tree-ssa-loop-niter.cc: Likewise.
* tree-ssa-loop-unswitch.cc: Likewise.
* tree-ssa-math-opts.cc: Likewise.
* tree-ssa-phiopt.cc: Likewise.
* tree-ssa-phiprop.cc: Likewise.
* tree-ssa-pre.cc: Likewise.
* tree-ssa-propagate.cc: Likewise.
* tree-ssa-sccvn.cc: Likewise.
* gimplify.h (unshare_expr): Remove.
(unshare_expr_without_location): Remove.
(copy_if_shared): Remove.
* tree.h (unshare_expr): New decl.
(unshare_expr_without_location): Likewise.
(copy_if_shared): Likewise.
* gimplify.cc (mostly_copy_tree_r): Moved to tree.cc.
(copy_if_shared_r): Likewise.
(copy_if_shared): Likewise.
(unshare_expr): Likewise.
(prune_expr_location): Likewise.
(unshare_expr_without_location): Likewise.
* tree.cc (mostly_copy_tree_r): Moved from gimplify.cc
(copy_if_shared_r): Likewise.
(copy_if_shared): Likewise.
(unshare_expr): Likewise.
(prune_expr_location): Likewise.
(unshare_expr_without_location): Likewise.
2026-05-19 Jakub Jelinek <jakub@redhat.com>
PR target/125357
* config/i386/i386-expand.cc (ix86_expand_vec_perm): For
one_operand_shuffle if TARGET_AVX and not TARGET_AVX512F use
vpermilps for V4SImode/V4SFmode. Formatting fix.
2026-05-19 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (bitreversehi2, bitreversesi2): New insn_and_split.
(*bitreversehi2.libgcc, *bitreversesi2.libgcc): New insns.
2026-05-19 Jakub Jelinek <jakub@redhat.com>
PR target/50481
* optabs.cc (widen_bswap): Add UNOPTAB argument and use it instead
of hardcoded bswap_optab. Rename to ...
(widen_bswap_or_bitreverse): ... this.
(expand_doubleword_bswap): Add UNOPTAB argument and use it instead
of hardcoded bswap_optab. Rename to ...
(expand_doubleword_bswap_or_bitreverse): ... this.
(expand_bitreverse): Use widen_bswap_or_bitreverse and
expand_doubleword_bswap_or_bitreverse.
(expand_unop): Adjust widen_bswap and expand_doubleword_bswap callers
to use new names and add an extra bswap_optab argument.
2026-05-19 H.J. Lu <hjl.tools@gmail.com>
PR target/125355
* config/i386/i386-expand.cc (ix86_expand_movmem): Replace
optimize_function_for_size_p with optimize_insn_for_size_p.
2026-05-19 Robin Dapp <robin.dapp@oss.qualcomm.com>
PR target/125097
* config/riscv/riscv.cc (riscv_legitimize_move): Emit 32-bit
vec_extracts right away.
2026-05-19 Robin Dapp <rdapp@oss.qualcomm.com>
* config/riscv/autovec.md (<cbranch_optab><mode>): Remove.
* config/riscv/riscv-protos.h (expand_vec_cmp_float): Add mask
and else arguments.
* config/riscv/riscv-v.cc (expand_vec_cmp): Add mask and else
arguments.
(expand_vec_cmp_float): Ditto.
* config/riscv/vector-iterators.md: Remove iterators.
2026-05-19 Peter Bergner <bergner@linux.ibm.com>
Jeevitha Palanisamy <jeevitha@linux.ibm.com>
* config/rs6000/amo.h: Add missing atomic memory operations.
* doc/extend.texi (PowerPC Atomic Memory Operation Functions): Document
new functions.
2026-05-19 Andi Kleen <ak@gcc.gnu.org>
PR target/125351
* config/i386/i386.md: Use alternative to handle masm ptwrite
syntax.
2026-05-18 Xin Wang <yw987194828@gmail.com>
* tree-ssa-loop-split.cc (fix_loop_bb_probability): Rename
parameters from true_edge/false_edge to loop1_edge/loop2_edge
and scale both loops directly from their semantic edge
probabilities.
(split_loop): Derive loop1_edge and loop2_edge from initial_true.
Use them for loop1_prob, fix_loop_bb_probability, and iteration
estimate scaling.
2026-05-18 Wang Yaduo <wangyaduo@linux.alibaba.com>
* config/riscv/riscv-cores.def: Add xt-c9501fdvt tune and core.
* doc/riscv-mcpu.texi: Regenerated.
* doc/riscv-mtune.texi: Regenerated.
2026-05-18 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_rtx_costs): Properly cost pack insns
for Zbkb.
* config/riscv/riscv.md (zero_extendsidi2): Expand into shift pairs
when the appropriate instructions are not available.
(zero_extendhi<GPR:mode>2): Simlarly.
(*zero_extendsidi2_internal): Make a simple define_insn. Only handle
MEM sources.
(*zero_extendhi<GPR2:mode>2): Similarly.
(zero_extendsidi2_shifted): Turn into a define_split and generalize
to handle more constants.
* config/riscv/predicates.md (dimode_shift_operand): New predicate.
2026-05-18 Jeff Law <jeffrey.law@oss.qualcomm.com>
* ext-dce.cc (carry_backpropagate): Handle AND and IOR with a constant argument.
2026-05-18 David Malcolm <dmalcolm@redhat.com>
* doc/analyzer.texi: Update for change in param name.
* doc/params.texi: Likewise. Clarify wording.
2026-05-18 David Malcolm <dmalcolm@redhat.com>
* dump-context.h (dump_context::emit_optinfo): "info" is non-null,
so pass it by reference.
* dumpfile.cc (dump_context::end_any_optinfo): Update for above
change.
(dump_context::emit_optinfo): Likewise.
* optinfo-emit-json.cc: Update throughout to eliminate naked "new"
and "delete" in favor of std::make_unique and unique_ptr. Drop
redundant dtor. Use nullptr rather than NULL. Pass by
const-reference rather than by const-pointer in the places that
require non-null.
* optinfo-emit-json.h: Likewise.
* optinfo.cc (optinfo::emit_for_opt_problem): Update for above
changes.
2026-05-18 Yoshinori Sato <yoshinori.sato@nifty.com>
* config/rx/rx.cc (rx_gen_move_template): Select the mode with the smallest size
for the mov instruction.
2026-05-18 Kito Cheng <kito.cheng@sifive.com>
* expr.cc (calculate_reversed_crc): New function.
(assemble_reversed_crc_table): New function.
(generate_reversed_crc_table): New function.
(calculate_table_based_reversed_CRC): New function.
(expand_reversed_crc_table_based): Remove gen_reflecting_code
parameter. Use calculate_table_based_reversed_CRC.
* expr.h (expand_reversed_crc_table_based): Update prototype.
* builtins.cc (expand_builtin_crc_table_based): Update call.
* internal-fn.cc (expand_crc_optab_fn): Update call.
* config/aarch64/aarch64.md (crc_rev<ALLI:mode><ALLX:mode>4):
Update call.
* config/i386/i386.md (crc_rev<SWI124:mode>si4): Update call.
* config/loongarch/loongarch.md (crc_rev<mode>si4): Update call.
Remove local rbit lambda.
* config/riscv/bitmanip.md (crc_rev<ANYI1:mode><ANYI:mode>4):
Update call. Remove TARGET_ZBKB case.
* config/riscv/riscv.cc (generate_reflecting_code_using_brev):
Remove.
* config/riscv/riscv-protos.h (generate_reflecting_code_using_brev):
Remove declaration.
2026-05-18 Robin Dapp <rdapp@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Remove else.
2026-05-18 Robin Dapp <rdapp@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_check_target_clone_version): Fix
format specifier.
2026-05-18 Jakub Jelinek <jakub@redhat.com>
PR target/50481
* config/i386/i386-protos.h (ix86_expand_gfni_bitreverse): Declare.
* config/i386/i386-expand.cc (ix86_expand_gfni_bitreverse): New
function.
* config/i386/i386.md (bitreverse<mode>2): New expander.
2026-05-18 H.J. Lu <hjl.tools@gmail.com>
PR target/125355
* config/i386/i386-expand.cc (ix86_expand_movmem): Return false
for -Os.
2026-05-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-uncprop.cc (associate_equivalences_with_edges): For switches
info only store the case low value to be recorded as
the only value. Add comments.
2026-05-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* ipa-icf-gimple.cc (func_checker::compare_gimple_switch): Remove
the check on CASE_LABEL_EXPR since it is redundant.
2026-05-17 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-dom.cc (record_edge_info): For switches
info only store the case low value to be recorded as
the only value. Add comments.
2026-05-16 Jakub Jelinek <jakub@redhat.com>
PR target/50481
* match.pd (BITREVERSE): New define_operator_list. Use it next to
BSWAP for a subset of bswap simplifications.
2026-05-16 Jakub Jelinek <jakub@redhat.com>
PR target/50481
* doc/extend.texi (__builtin_bitreverse32, __builtin_bitreverse64):
Tweak wording for consistency with __builtin_bswap*.
(__builtin_bitreverse128): Document.
* builtins.def (BUILT_IN_BITREVERSE128): New.
* builtins.cc (expand_builtin): Handle also BUILT_IN_BITREVERSE128.
(is_inexpensive_builtin): Likewise.
* fold-const-call.cc (fold_const_call_ss): Handle also
CFN_BUILT_IN_BITREVERSE128.
* fold-const.cc (tree_call_nonnegative_warnv_p): Likewise.
* tree-ssa-ccp.cc (evaluate_stmt): Handle also BUILT_IN_BITREVERSE128.
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p): Handle also
CFN_BUILT_IN_BITREVERSE128.
(cond_removal_in_builtin_zero_pattern): Likewise.
2026-05-16 Jakub Jelinek <jakub@redhat.com>
PR target/50481
* tree-ssa-ccp.cc (evaluate_stmt): Fix up
BUILT_IN_BITREVERSE{8,16,32,64} handling.
2026-05-16 Roger Sayle <roger@nextmovesoftware.com>
Hongtao Liu <hongtao.liu@intel.com>
* config/i386/i386-features.cc (scalar_chain): If the chain
starts with a register-to-register move from a hard register,
then the hard register's defs don't need to converted.
(timode_scalar_chain::compute_convert_gain): Provide costs
for hard_reg-to-pseudo and pseudo-to-hard_reg moves.
Tweak speed cost of timode_concatdi_p moves.
(timode_scalar_chain::convert_insn): Add support for
hard_reg-to-pseudo and pseudo-to-hard_reg TImode transfers.
(timode_scalar_to_vector_candidate_p): Likewise.
2026-05-16 Shivam Gupta <shivam98.tkg@gmail.com>
PR tree-optimization/112095
* match.pd: Simplify ((~x) & y) ^ (x | y)
to x and ((~x) | y) ^ (x & y) to ~x.
2026-05-16 Timo Rothenpieler <timo@rothenpieler.org>
* config/i386/mingw-pthread.h:
rename to generic config/mingw/mingw-pthread.h
* config.gcc [aarch64-*-mingw*]:
Fix support for posix threading on aarch64 mingw targets.
* config/mingw/mingw-pthread.h: New file.
2026-05-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-operands.cc (operands_scanner::parse_ssa_operands):
Process index of the gswitch only.
2026-05-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125290
* tree-cfg.cc (group_case_labels_stmt): Remove code that was
added to remove `cases` that goto blocks of unreachable.
* tree-ssa-forwprop.cc (optimize_unreachable): Remove the
comment about switch cases being handled.
2026-05-15 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.h (ASM_PREFERRED_EH_DATA_FORMAT): Use
DW_EH_PE_aligned encoding on 64-bit HP-UX.
2026-05-15 H.J. Lu <hjl.tools@gmail.com>
PR rtl-optimization/125321
* function-abi.cc (function_abi_aggregator::caller_save_regs):
Return the enabled registers.
2026-05-15 Xi Ruoyao <xry111@xry111.site>
PR tree-optimization/125291
* tree-scalar-evolution.cc (simplify_peeled_chrec): Sign-extend
the step for peeled converted IV.
2026-05-15 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md (spaceship<mode>4): New
define_expand.
2026-05-15 Abhishek Kaushik <abhishek.kaushik@arm.com>
PR target/123924
* match.pd: Allow conversions in FMA-to-FNMA fold.
2026-05-15 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vector_costs::add_slp_cost): New.
* tree-vectorizer.cc (vector_costs::add_slp_cost): New
default version.
* tree-vect-slp.cc (add_slp_costs): Helper for dispatching
a cost vector in SLP chunks.
(vect_slp_analyze_operations): Adjust.
(li_cost_vec_cmp): Likewise.
(vect_bb_vectorization_profitable_p): Likewise.
2026-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/125296
* tree-ssa-forwprop.cc (forward_propagate_addr_expr_1):
Preserve alignment of the original access.
2026-05-15 Jakub Jelinek <jakub@redhat.com>
PR target/125308
* config/i386/sse.md (*minmax<mode>3_4): Force also
operands[2] into a REG.
2026-05-15 Disservin <disservin.social@gmail.com>
Jakub Jelinek <jakub@redhat.com>
PR target/50481
* builtin-types.def (BT_FN_UINT8_UINT8): New.
* builtins.def (BUILT_IN_BITREVERSE8, BUILT_IN_BITREVERSE16,
BUILT_IN_BITREVERSE32, BUILT_IN_BITREVERSE64): New builtins.
* builtins.cc (expand_builtin, is_inexpensive_builtin): Handle
bitreverse builtins.
* fold-const-call.cc (fold_const_call_ss): Fold bitreverse builtins.
* fold-const.cc (tree_call_nonnegative_warnv_p): Handle
bitreverse builtins.
* optabs.def (bitreverse_optab): New.
* optabs.cc (expand_bitreverse): New function.
(expand_unop): Use it for bitreverse_optab.
* tree-ssa-ccp.cc (evaluate_stmt): Handle bitreverse builtins.
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p,
cond_removal_in_builtin_zero_pattern): Likewise.
* doc/extend.texi: Document __builtin_bitreverse{8,16,32,64}.
* doc/md.texi (bitreverse<mode>2): Document.
2026-05-15 Jakub Jelinek <jakub@redhat.com>
PR c++/125081
* doc/invoke.texi (Wconstant-logical-operand): Document.
2026-05-14 Andi Kleen <ak@gcc.gnu.org>
PR target/124316
* config/i386/i386.md (ptwrite): Add explicit mode to
instruction.
2026-05-14 Xi Ruoyao <xry111@xry111.site>
PR rtl-optimization/96692
* config/loongarch/loongarch.md (define_split): New splitters
turning a ^ b ^ (a | c) => (c &~ a) ^ b.
2026-05-14 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv-v.cc (expand_const_vector_stepped): Drop unused
SRC parameter. All callers changed.
(expand_const_vector_interleaved_stepped_npatterns): Likewise.
(expand_const_vector): Corresponding changes.
2026-05-14 Alex Coplan <alex.coplan@arm.com>
* doc/rtl.texi (Machine Modes): Update description of
GET_MODE_MASK to use HOST_BITS_PER_WIDE_INT instead of
HOST_BITS_PER_INT as the upper limit of the input mode's bitsize.
2026-05-14 Tobias Burnus <tburnus@baylibre.com>
* langhooks.cc (lhd_omp_deep_mapping_p, lhd_omp_deep_mapping_cnt,
lhd_omp_deep_mapping): Improve interface comment.
* langhooks.h (lhd_omp_deep_mapping_p, lhd_omp_deep_mapping_cnt,
lhd_omp_deep_mapping): Likewise
2026-05-14 Georg-Johann Lay <avr@gjlay.de>
PR target/125194
* config/avr/avr.cc (avr_no_call_main_p): Remove variable...
(avr_file_end): ...and code that uses it.
(avr_insert_attributes): Same. Add "used" to main attributes
when -mno-call-main.
* config/avr/gen-avr-mmcu-specs.cc (print_mcu): Emit code
for link_no_call_main specs.
* config/avr/specs.h (LINK_SPEC): Add %(link_no_call_main).
2026-05-13 Zhongyao Chen <chen.zhongyao@zte.com.cn>
PR target/125215
* config/riscv/riscv-v.cc (expand_const_vector_interleaved_stepped_npatterns):
Remove hi/lo optimization and always use the merge fallback.
2026-05-13 Tamar Christina <tamar.christina@arm.com>
* tree-chrec.cc (chrec_convert_1): Fold unsigned CHREC converts.
2026-05-13 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
PR target/32803
* config/i386/i386.md (peephole2): Don't transform xorl;movb into
movzb with -Oz.
(peephole2): Convert movl into xorl;movb (strict_low_part) with -Oz.
(peephole2): Likewise, convert movl into xorl;movb [abcd]h with -Oz.
2026-05-13 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_store): Record ls_type
for VMAT_STRIDED_SLP.
(vectorizable_load): Likewise.
2026-05-13 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_store): Set slp_node->data
and SLP_TREE_TYPE only on success.
(vectorizable_load): Likewise. Move one validity check early.
2026-05-13 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/122665
* config/rs6000/vsx.md (smul<mode>3_highpart, umul<mode>3_highpart):
Replace shift-based patterns with smul_highpart and umul_highpart RTL
codes and use altivec_register_operand.
2026-05-13 Reshma Roy <Reshma.Roy@amd.com>
* match.pd: Add new popcount pattern variants from Hacker's Delight.
2026-05-13 H.J. Lu <hjl.tools@gmail.com>
Uros Bizjak <ubizjak@gmail.com>
PR target/120870
* config/i386/i386.cc (ix86_save_reg): Return true for DRAP
register early at entry.
(find_drap_reg): Use R11_REG in preserve_none functions in
64-bit mode.
2026-05-13 Tobias Burnus <tburnus@baylibre.com>
* omp-general.cc (omp_runtime_api_procname): Add omp_control_tool.
2026-05-12 Heiko Eißfeldt <heiko.Eissfeldt@hexco.de>
PR middle-end/124651
* gimple-warn-recursion.cc (find_function_exit):
replace recursive calls with iteration for lower stack usage
2026-05-12 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa64-hpux.h (MD_EXEC_PREFIX): Define to empty
string.
2026-05-12 Christopher Bazley <chris.bazley@arm.com>
* common.opt: Add Wzero-init-padding-bits=.
* common.opt.urls: Regenerated.
* doc/invoke.texi: Document Wzero-init-padding-bits=.
* expr.cc (categorize_ctor_elements_1): Update new struct type
ctor_completeness instead of an integer to indicate presence of
padding or missing fields in a constructor. Instead of setting -1
upon discovery of padding bits in both structs and unions,
set separate flags to indicate the type of padding bits.
(categorize_ctor_elements): Update the type and documentation of
the p_complete parameter.
(mostly_zeros_p): Use new struct type ctor_completeness when
calling categorize_ctor_elements.
(all_zeros_p): Use new struct type ctor_completeness when
calling categorize_ctor_elements.
* expr.h (struct ctor_completeness): New struct type to replace an
an integer that could take the value -1 ('all fields are
initialized, but there's padding'), 0 ('fields are missing') or
1 ('all fields are initialized, and there's no padding'). Named
bool members make the code easier to understand and make room to
disambiguate struct padding bits from union padding bits.
(categorize_ctor_elements): Update the function declaration to use
the new struct type in the last parameter declaration.
* gimplify.cc (gimplify_init_constructor): Replace use of
complete_p != 0 ('all fields are initialized') with !sparse,
replace use of complete == 0 ('fields are missing') with sparse, and
replace use of complete <= 0 ('fields are missing' or 'all fields are
initialized, but there's padding') with sparse || padded_union or
padded_non_union. Trigger new warnings if storage for the object
is not zeroed but padded_union or padded_non_union is set
(because this combination implies possible non-zero padding bits).
2026-05-12 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/124151
* tree-sra.cc (build_user_friendly_ref_for_offset): Added parameters
CUR_SIZE and EXP_SIZE. Added code passing the correct CUR_SIZE and
checking it against EXP_SIZE. Removed unused code for the case when
EXP_TYPE was NULL_TREE.
(create_artificial_child_access): Adjusted the call to
build_user_friendly_ref_for_offset.
(propagate_subaccesses_from_rhs): Likewise.
(propagate_subaccesses_from_rhs): Removed a check that the size of
lchild is a multiple of BITS_PER_UNIT.
(propagate_subaccesses_from_lhs): Likewise.
2026-05-12 Yoshinori Sato <yoshinori.sato@nifty.com>
PR target/113948
* config/rx/rx-protos.h (rx_split_double_move): New helper prototype.
(rx_relax_double_operands): Likewise.
* config/rx/rx.cc (rx_legitimize_address): Add expand complex case.
(rx_is_legitimate_address): Add double word case.
(rx_gen_move_template): Fix operation size in unsigned extend.
(rx_gen_move_template): Remove DImode and DFmode.
(rx_get_stack_layout): Fix for frame size calculation.
(rx_initial_elimination_offset): The calculation method has been
changed to one that supports LRA.
(rx_hard_regno_nregs): Use CEIL.
(rx_hard_regno_mode_ok): Add ATTRIBUTE_UNUSED.
(rx_get_subword): New. Double word move helper.
(rx_split_double_move): Likewise.
(rx_relax_double_operands): Likewise.
* config/rx/rx.h (reg_class): Add CC for all regsisters.
(CLASS_MAX_NREGS): Remove.
* config/rx/rx.md (mov<register_modes:mode>):
Replace copy_to_mode_reg to force_reg.
(movdi): Limit the arguments to make register allocation easier.
(movdf): Likewise.
(movdi_internal): New.
(movdf_internal): New.
(addsi3_pid): New. Handling UNSPEC_PID_ADDR.
(addsi3_lra): New. alternative addptrsi3.
(ashlsi3_lra): Likewise.
2026-05-12 Lili Cui <lili.cui@intel.com>
Hongtao Liu <hongtao.liu@intel.com>
* tree-vect-slp.cc (vect_analyze_slp_reduction): Don't bail out
early when SLP discovery limit is exhausted; only guard the chain
analysis which may build multi-lane trees. Single-lane fallback
does not consume limit and should always be attempted.
2026-05-12 Lili Cui <lili.cui@intel.com>
Hongtao Liu <hongtao.liu@intel.com>
* tree-vect-slp.cc (vect_build_slp_tree_1): Use unified
first_commutative_argument interface to allow commutative
operand swap for both tree codes and internal functions
(e.g. .COND_ADD) in SLP reduction matching.
2026-05-12 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (get_load_store_type): Pass
temporary to vect_use_grouped_gather, only set ls_type
when that succeeded.
2026-05-12 Artemiy Volkov <artemiy.volkov@arm.com>
PR middle-end/125259
* match.pd: Fix the view_convert (BIT_FIELD_REF) pattern.
2026-05-12 Alexandre Oliva <oliva@adacore.com>
* config.gcc [aarch64*-wrs-vxworks*] (tm_file): Add
aarch64/aarch64-errata.h.
* config/aarch64/aarch64-vxworks.h (LINK_SPEC): Add
AARCH64_ERRATA_LINK_SPEC.
(CC1_SPEC, CC1PLUS_SPEC): Add AARCH64_ERRATA_COMPILE_SPEC.
2026-05-12 Naveen <naveen.siddegowda@oss.qualcomm.com>
* fold-const-call.cc (fold_internal_fn_sat_add): New function.
(fold_const_call): Handle CFN_SAT_ADD.
* match.pd: Add simplifications for x SAT_ADD 0 == x.
* genmatch.cc (commutative_op): Add CFN_SAT_ADD.
2026-05-12 Naveen <naveen.siddegowda@oss.qualcomm.com>
* config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_imm_low):
Change return type to const char *.
* config/aarch64/aarch64.cc (aarch64_output_simd_mov_imm_low): Likewise.
2026-05-11 William D. Jones <thor0505@comcast.net>
PR target/120077
* config/lm32/lm32.cc: Enable LRA after diff testing showed minimal issues.
2026-05-11 Jerry DeLisle <jvdelisle@gcc.gnu.org>
* flag-types.h (gfc_fcoarray): Add GFC_FCOARRAY_SHARED.
2026-05-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc
(FPreg_neg_scaled_simm12b, convert_SF_const, constantsynth_pass1,
litpool_set_src_1, litpool_set_src):
Change each call to validate_change() and apply_change_group() to
trigger an ICE if the result is not true.
2026-05-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc
(xtensa_can_eliminate_callee_saved_reg_p):
Change the arguments that return values from being passed by pointer
to C++ reference.
(xtensa_expand_prologue):
Adjust the call to xtensa_can_eliminate_callee_saved_reg_p() to
match the above changes.
2026-05-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h (HONOR_REG_ALLOC_ORDER):
New macro definition.
2026-05-11 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-tuning-flags.def
(AARCH64_EXTRA_TUNE_BASE): Add AARCH64_EXTRA_TUNE_NARROW_GP_WRITES.
2026-05-11 Pan Li <pan2.li@intel.com>
* Makefile.in: Add match-sat-alu.pd as dependency.
* match.pd: Remove saturation alu related patterns.
* match-sat-alu.pd: Add new file for saturation alu patterns.
2026-05-11 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
* config/i386/cygming.h (TARGET_SEH): Keep SEH enabled for all
64-bit Windows functions when unwind tables are requested.
2026-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/125250
* tree-ssa-loop-im.cc (execute_sm): For modes that cannot
transfer bits, _Bool and bitfield accesses force the
multi-threaded model.
2026-05-11 LIU Hao <lh_mouse@126.com>
PR target/53929
* config/mingw/winnt.cc (mingw_pe_file_end): Use `ASM_OUTPUT_LABELREF`
to emit `name`.
2026-05-11 Richard Biener <rguenther@suse.de>
PR target/125174
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Cost calls as 10 times FMA.
2026-05-11 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR rtl-optimization/121426
* combine.cc (recog_for_combine_1): Reject insns which make use
of hard register constraints.
2026-05-11 Naveen <naveen.siddegowda@oss.qualcomm.com>
* config/aarch64/aarch64-protos.h
(aarch64_output_simd_mov_imm_low): New.
(aarch64_const_vec_fmov_p): New.
* config/aarch64/aarch64-simd.md (mov<mode>): Do not expand constant
vectors handled by aarch64_const_vec_fmov_p into VDUP.
(*aarch64_simd_mov<VDMOV:mode>): Add Dc alternatives for FMOV based
SIMD constant moves.
(*aarch64_simd_mov<VQMOV:mode>): Likewise.
* config/aarch64/aarch64.cc (aarch64_const_vec_fmov_p): New function.
(aarch64_output_simd_mov_imm_low): New function.
* config/aarch64/constraints.md (Dc): New constraint.
2026-05-11 Boudewijn van der Heide <boudewijn@delta-utec.com>
PR rtl-optimization/125209
* combine.cc (make_compound_operation_int): Return NULL_RTX if we got CLOBBER.
2026-05-11 Shreya Munnangi <smunnang@qti.qualcomm.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/80770
* rtl.h (simplify_context::simplify_ior_with_common_term): Add
new method.
(simplify_context::simplify_binary_operation_1): Use new method.
* simplify-rtx.cc (simplify_context::simplify_ior_with_common_term):
New method.
2026-05-10 Jørgen Kvalsvik <j@lambda.is>
* gcov.cc (json_set_prime_path_coverage): Read arc.true_value.
2026-05-10 H.J. Lu <hjl.tools@gmail.com>
PR target/125238
* config/i386/i386-features.cc (ix86_broadcast_inner): Set kind
to X86_CSE_CONST_VECTOR if the vector load can be converted to
constant integer load.
2026-05-09 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
PR target/125217
* config/riscv/riscv.cc (riscv_gen_multi_pop_insn): Rename variable.
(riscv_expand_epilogue): Don't emit cm.popret with shadow stack.
2026-05-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/117871
* cfghooks.cc (cfg_hooks): Change the type
to be a pointer to a const struct cfg_hooks.
(get_cfg_hooks): Return the current pointer
rather the struct.
(set_cfg_hooks): Change the argument type and
set the cfg_hooks directly to it.
* cfghooks.h (gimple_cfg_hooks): Constify.
(rtl_cfg_hooks): Likewise.
(cfg_layout_rtl_cfg_hooks): Likewise.
(get_cfg_hooks): Update declration.
(set_cfg_hooks): Likewise.
* cfgrtl.cc (rtl_cfg_hooks): Constify.
(cfg_layout_rtl_cfg_hooks): Likewise.
* sel-sched-ir.cc (orig_cfg_hooks): Change to a pointer.
(sel_create_basic_block): Update
for orig_cfg_hooks being a pointer.
(sel_register_cfg_hooks): Update for the constification
of cfg_hooks.
* tree-cfg.cc (gimple_cfg_hooks): Constify.
2026-05-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cfghooks.cc (current_ir_name): New function.
(dump_bb_for_graph): Use current_ir_name
instead of accessing the name field.
(dump_bb_as_sarif_properties): Likewise.
(redirect_edge_and_branch): Likewise.
(can_remove_branch_p): Likewise.
(redirect_edge_and_branch_force): Likewise.
(split_block_1): Likewise.
(move_block_after): Likewise.
(delete_basic_block): Likewise.
(split_edge): Likewise.
(create_basic_block_1): Likewise.
(can_merge_blocks_p): Likewise.
(predict_edge): Likewise.
(predicted_by_p): Likewise.
(merge_blocks): Likewise.
(make_forwarder_block): Likewise.
(force_nonfallthru): Likewise.
(can_duplicate_block_p): Likewise.
(duplicate_block): Likewise.
(block_ends_with_call_p): Likewise.
(block_ends_with_condjump_p): Likewise.
(flow_call_edges_add): Likewise.
* cfghooks.h (struct cfg_hooks): Remove the name
field.
* cfgrtl.cc (rtl_cfg_hooks): Update for the removal
of the name field.
(cfg_layout_rtl_cfg_hooks): Likewise.
* tree-cfg.cc (struct cfg_hooks): Likewise.
2026-05-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cfghooks.cc (current_ir_type): Return cfghooks' ir field.
* cfghooks.h (struct cfg_hooks): Add ir field.
* cfgrtl.cc (rtl_cfg_hooks): Update for new ir field.
(cfg_layout_rtl_cfg_hooks): Likewise.
* tree-cfg.cc (gimple_cfg_hooks): Likewise.
2026-05-09 H.J. Lu <hjl.tools@gmail.com>
PR target/125239
* config/i386/i386-features.cc (ix86_place_single_vector_set):
For CONST_VECTOR source, check CONST0_RTX with
X86_CSE_CONST0_VECTOR and CONSTM1_RTX with X86_CSE_CONSTM1_VECTOR.
(ix86_broadcast_inner): Set x86_cse kind to X86_CSE_CONST0_VECTOR
for CONST0_RTX and X86_CSE_CONSTM1_VECTOR for CONSTM1_RTX.
2026-05-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125234
* match.pd (`(a !=/== b) &\| ((a|b) ==/!= 0)`): Fix
resulting constant form.
2026-05-08 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/124637
* calls.cc (load_register_parameters): If using store_constructor
to place a constant structure in a register, use a right shift to
align the structure/padding if required on big-endian targets.
2026-05-08 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/119422
* match.pd(`(bool >= A) >= A -> bool >= A`): New pattern.
2026-05-08 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124955
* config/riscv/riscv.md (masked shifted bitfield extraction): New
splitter to utilize slliw to eliminate the need for sign extnesion.
2026-05-08 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/93504
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Generalize existing code for (X & C) | ((X|Y) & ~C) to handle
(X & C) | ((X^Y) & ~C) as well.
2026-05-08 Roger Sayle <roger@nextmovesoftware.com>
* expmed.cc (synth_mult): Add more constraints to recent change
to avoid "false positive" array bounds warnings during bootstrap.
2026-05-08 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.cc (loongarch_print_operand): Print
the symbol name for SYMBOL_REF with %c.
2026-05-08 Xi Ruoyao <xry111@xry111.site>
PR target/125049
* config/loongarch/predicates.md (ssp_operand): New
define_predicate.
(ssp_normal_operand): New define_predicate.
* config/loongarch/constraints.md (ZE): New define_constraint.
(ZF): New define_constraint.
* config/loongarch/loongarch.md (UNSPEC_SSP): New unspec.
(cbranch4): Add "@" to create gen_cbranch4(machine_mode, ...).
(@stack_protect_combined_set_normal_<mode>): New define_insn.
(@stack_protect_combined_set_extreme_<mode>): New define_insn.
(@stack_protect_combined_test_internal_<mode>): New define_insn.
(stack_protect_combined_set): New define_expand.
(stack_protect_combined_test): New define_expand.
* config/loongarch/loongarch-protos.h
(loongarch_output_asm_load_canary): Declare.
* config/loongarch/loongarch.cc (loongarch_print_operand): Allow
'v' to print d/w for DImode/SImode.
(loongarch_output_asm_load_canary): Implement.
2026-05-08 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md (*ctzsi2_extend): New
define_insn.
2026-05-08 Vijay Shankar <vijay@linux.ibm.com>
PR target/113353
* config/rs6000/rs6000.cc (rs6000_builtin_vectorized_function):
Emit xvrdpic/xvrspic.
* config/rs6000/rs6000-overload.def (__builtin_vec_nearbyint):
Modified bif-id and overload-id.
2026-05-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/125174
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Cost
the number of OMP SIMD calls number of vector stmts.
2026-05-08 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv-v.cc (shuffle_even_odd_patterns): Use vnsrl
when possible.
2026-05-08 Soumya AR <soumyaa@nvidia.com>
PR target/124895
* config/aarch64/aarch64-passes.def (pass_narrow_gp_writes): Move pass
before pass_free_cfg.
2026-05-08 H.J. Lu <hjl.tools@gmail.com>
PR target/125100
* config/i386/i386-features.cc (x86_cse_kind): Add
X86_CSE_CONST_VECTOR.
(redundant_pattern): Add dest_mode.
(ix86_place_single_vector_set): Handle X86_CSE_CONST_VECTOR.
Generate SUBREG for constant integer source.
(ix86_broadcast_inner): Add an INSN argument. Use CONST_VECTOR
in REG_EQUAL note. Set load kind to X86_CSE_CONST_VECTOR for
native and converted CONST_VECTORs. Return CONST_VECTOR if it
can be converted to constant integer load.
(pass_x86_cse::candidate_vector_p): Add an INSN argument and
pass the insn to ix86_broadcast_inner.
(pass_x86_cse::x86_cse): Add a basic block bitmap for calls.
Pass the insn to candidate_vector_p. Handle X86_CSE_CONST_VECTOR.
Set dest_mode. Keep constant integer load when crossing a
function call. Convert CONST_VECTOR load no larger than integer
register to constant integer load even if there are no redundant
CONST_VECTOR loads.
2026-05-07 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/109878
* match.pd(min/max (a & CST0, a & CST1)): New pattern.
(min/max (a, a & CST)): New pattern.
2026-05-07 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/106244
* config/riscv/riscv.md ((and (ashift X Y) const_int 1)): New splitter.
2026-05-07 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/123514
* match.pd ((x - (x<0)) ^ -(x<0) into ABS_EXPR<x>): New pattern.
2026-05-07 Richard Sandiford <rdsandiford@googlemail.com>
* rtlanal.cc (commutative_operand_precedence): Bump the precedence
of non-commutative binary arithmetic to 3. Give comparisons a
precedence of 2.
2026-05-07 Richard Sandiford <rdsandiford@googlemail.com>
* combine.cc (make_compound_operation_int): Remove PLUS and MINUS
simplifications and PLUS operand order swapping. Delegate those
tasks to simplify_gen_binary instead.
2026-05-07 Richard Sandiford <rdsandiford@googlemail.com>
* alloc-pool.h (object_allocator::allocate): Generalize to handle
non-default constructors.
2026-05-07 Richard Sandiford <rdsandiford@googlemail.com>
* rtl.h (post_ra_split_completed): Declare.
* final.cc (rest_of_clean_state): Set it to false.
* recog.cc (post_ra_split_completed): New variable.
(split_insn): Temporarily set post_ra_split_completed while walking
the new instructions.
(split_all_insns, split_all_insns_noflow): Set post_ra_split_completed
after completing a post-reload split.
* config/rx/rx.md (*cmpsi, *tstsi, *cmpsf, *conditional_branch)
(*sccc, *stcc, *stcc_reg, *abssi2_flags, *addsi3_flags, adc_internal)
(*adc_flags, *andsi3_flags, *negsi2_flags, *one_cmplsi2_flags)
(*iorsi3_flags, *rotlsi3_flags, *rotrsi3_flags, *ashrsi3_flags)
(*lshrsi3_flags, *ashlsi3_flags, *sat, *subsi3_flags, sbb_internal)
(*sbb_flags, *xorsi3_flags, *bmcc): Require post_ra_split_completed
rather than reload_completed.
(comparesi3_<extend_types:code><small_int_modes:mode>, addsi3_flags)
(subsi3_flags): Require post_ra_split_completed.
2026-05-07 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/125214
* match.pd (min|max(a+|-c,b+|-c)): Add integral type check.
2026-05-07 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/122871
* expmed.cc (synth_mult): Handle doubleword left shifts by
BITS_PER_WORD bits or more, for scalar modes.
* optabs.cc (expand_doubleword_mult): Avoid generating multiply
instructions by immediate constants 0, 1 or 2.
2026-05-07 Avinash Jayakar <avinashd@linux.ibm.com>
* config/rs6000/crypto.md (UNSPEC_XXAESENCP): New unspec entry.
(UNSPEC_XXAES128ENCP): Likewise.
(UNSPEC_XXAES192ENCP): Likewise.
(UNSPEC_XXAES256ENCP): Likewise.
(UNSPEC_XXAESDECP): Likewise.
(UNSPEC_XXAES128DECP): Likewise.
(UNSPEC_XXAES192DECP): Likewise.
(UNSPEC_XXAES256DECP): Likewise.
(UNSPEC_XXAESGENLKP): Likewise.
(UNSPEC_XXAES128GENLKP): Likewise.
(UNSPEC_XXAES192GENLKP): Likewise.
(UNSPEC_XXAES256GENLKP): Likewise.
(UNSPEC_XXGFMUL128): Likewise.
(UNSPEC_XXGFMUL128GCM): Likewise.
(UNSPEC_XXGFMUL128XTS): Likewise.
(AESACC_base_code): New iterator for xxaesencp and xxaesdecp base
mnemonics.
(AESACC_code): New iterator for xxaesencp and xxaesdecp extended
mnemonics.
(AESGENLKP_code): New iterator for xxaesgenlkp extended mnemonics.
(AESGF_code): New iterator for xxgfmul128 extended mnemonics.
(AESACC_base_insn): New attribute iterator for xxaesencp and xxaesdecp
base mnemonics.
(AESACC_insn): New attribute iterator for xxaesencp and xxaesdecp
extended mnemonics.
(AESGENLKP_insn): New attribute iterator for xxaesgenlkp extended
mnemonics.
(AESGF_insn): New attribute iterator for xxgfmul128 extended mnemonics.
(<AESACC_base_insn>): New define_insn for xxaesencp and xxaesdecp base
mnemonics.
(<AESACC_insn>): New define_insn for xxaesencp and xxaesdecp extended
mnemonics.
(<AESGENLKP_insn>): New define_insn for xxaesgenlkp extended mnemonics.
(xxaesgenlkp): New define_insn for genlkp base mnemonic.
(<AESGF_insn>): New define_insn for xxgfmul128 extended mnemonics.
(xxgfmul128): New define_insn for xxgfmul128 base mnemonic.
* config/rs6000/rs6000-builtins.def: Added new builtin definitions for
AES acceleration.
* doc/extend.texi: Add new section for AES acceleration builtins
for Future ISA.
2026-05-07 Pan Li <pan2.li@intel.com>
* config/riscv/predicates.md: Add lt to swapped operator.
* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle
the rtl as well.
2026-05-07 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/116008
PR tree-optimization/124560
* match.pd (min|max(a+|-c,b+|-c)): New patterns.
2026-05-06 Jason Merrill <jason@redhat.com>
* Makefile.in (TAGS): Add diagnostics/ and text-art/.
2026-05-06 David Malcolm <dmalcolm@redhat.com>
* range-op-float.cc (fop_unordered): Make static and const.
(fop_ordered): Likewise.
(fop_unordered_lt): Likewise.
(fop_unordered_le): Likewise.
(fop_unordered_gt): Likewise.
(fop_unordered_ge): Likewise.
(fop_unordered_equal): Likewise.
(fop_ltgt): Likewise.
(fop_div): Likewise.
* range-op-ptr.cc (op_pointer_plus): Likewise.
(op_pointer_diff): Likewise.
* range-op.cc (op_equal): Likewise.
(op_not_equal): Likewise.
(op_lt): Likewise.
(op_le): Likewise.
(op_gt): Likewise.
(op_ge): Likewise.
(op_ident): Likewise.
(op_cst): Likewise.
(op_cast): Likewise.
(op_view): Likewise.
(op_plus): Likewise.
(op_abs): Likewise.
(op_minus): Likewise.
(op_negate): Likewise.
(op_mult): Likewise.
(op_addr): Likewise.
(op_bitwise_not): Likewise.
(op_bitwise_xor): Likewise.
(op_bitwise_and): Likewise.
(op_bitwise_or): Likewise.
(op_min): Likewise.
(op_max): Likewise.
(operator_table): Make static. Fix typo in comment.
(range_op_handler::range_op_handler): Fix typo in leading comment.
(range_op_handler::range_op): Make returned ptr const. Use
nullptr.
(RO_III): Make static.
(RO_IFI): Likewise.
(RO_IFF): Likewise.
(RO_FFF): Likewise.
(RO_FIF): Likewise.
(RO_FII): Likewise.
(RO_PPP): Likewise.
(RO_PPI): Likewise.
(RO_IPP): Likewise.
(RO_IPI): Likewise.
(RO_PIP): Likewise.
(RO_PII): Likewise.
(op_trunc_div): Make const.
(op_floor_div): Likewise.
(op_round_div): Likewise.
(op_ceil_div): Likewise.
* range-op.h (range_op_handler::range_op): Make returned ptr
const.
(range_op_handler::m_operator): Make const.
(range_op_table::operator[]): Make const. Make returned ptr
const.
(range_op_table::set): Make range_operator const.
(range_op_table::m_range_tree): Make ptrs const.
2026-05-06 David Malcolm <dmalcolm@redhat.com>
* value-range.cc (value_range::print): New, based on
value_range::dump.
* value-range.h (value_range::print): New decl.
2026-05-06 David Malcolm <dmalcolm@redhat.com>
* value-range.h: Remove stray slash in comment.
2026-05-06 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (ANALYZER_OBJS): Add analyzer/state-transition.o.
* digraph.cc (test_path::append_edge): New.
(test_path::reverse): New.
* shortest-paths.h (get_shortest_path): Use append_edge and
reverse.
* tree-diagnostic.h
(tree_dump_pretty_printer::~tree_dump_pretty_printer): Only flush
when the buffer's stream is non-null.
2026-05-06 Andrew MacLeod <amacleod@redhat.com>
* value-range-storage.cc (prange_storage::alloc): Use prange_format.
(prange_storage::prange_storage): Likewise.
(prange_format::prange_format): New.
(prange_storage::set_prange): Use prange_foramt and only write
required words to storage.
(prange_storage::get_prange): Only read required words.
(prange_storage::equal_p): Adjust for new enum.
(prange_storage::fits_p): Use prange_format to determine size.
* value-range-storage.h (enum prange_kind): New.
(class prange_format): New.
(get_low, get_high, get_value, get_mask): Replace with get_word.
(set_low, set_high, set_value, set_mask): Replace with set_word.
(get_word): New.
(set_word): New.
2026-05-06 Andrew MacLeod <amacleod@redhat.com>
* gimple-fold.cc (get_maxval_strlen): Return the same value if
passed a constant.
2026-05-06 Zhongyao Chen <chenzhongyao.hit@gmail.com>
PR target/122558
* config/riscv/riscv-vector-costs.cc (get_lmul_cost_scaling):
New function to calculate multiplicative scaling factors.
(costs::adjust_stmt_cost): Apply LMUL scaling uniformly to all
vector statements.
2026-05-06 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch.cc (loongarch_rtx_costs): Add
RTX cost handling for the ORDERED RTX code.
2026-05-06 Lulu Cheng <chenglulu@loongson.cn>
PR target/125057
* config/loongarch/loongarch.cc
(loongarch_split_vector_move): Complete the split condition.
* config/loongarch/loongarch.h (LSX_REG_RTX_P): Delete.
(LASX_REG_RTX_P): Delete.
(GP_REG_RTX_P): Define macro.
2026-05-06 Robin Dapp <rdapp@oss.qualcomm.com>
* config/riscv/riscv-protos.h (whole_reg_to_reg_move_p):
Rename from this...
(whole_reg_move_p): ...to this.
(whole_reg_loadstore_p): Declare.
* config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
(whole_reg_move_p): Ditto.
(whole_reg_loadstore_p): New function.
* config/riscv/thead-vector.md: Use renamed function.
* config/riscv/vector.md (@pred_store<mode>): Use new function.
2026-05-06 Richard Biener <rguenther@suse.de>
* config/i386/x86-tune.def (avx512_two_epilogues): Enable
for m_ZNVER6.
(avx512_masked_epilogues): Likewise.
2026-05-05 H.J. Lu <hjl.tools@gmail.com>
PR target/120587
PR target/125155
* config/or1k/or1k.cc (or1k_hard_regno_mode_ok): Allow condition
condition flag register in SImode.
2026-05-05 wangzicong <wangzicong@masscore.cn>
* config/riscv/riscv.cc (riscv_modes_tieable_p): Make tuple modes
not tieable to some modes.
2026-05-05 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/120189
* doc/gm2.texi (Building a shared library): Rewrite the
description of the shared library and include complete code into
the example.
2026-05-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/125185
* tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Guard
first vect_slp_linearize_chain call.
2026-05-05 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_legitimize_address):
Modify to extend the upper limit of the coverable offset if the
address displacement of the corresponding machine instruction is
greater than 255.
2026-05-05 Jakub Jelinek <jakub@redhat.com>
PR target/125180
* config/i386/i386.md (HI/SI test -> QI test splitter): Punt if
operands[2] is a volatile MEM.
2026-05-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/125124
* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Disable
BB SLP partitioning sanity-check.
2026-05-04 H.J. Lu <hjl.tools@gmail.com>
PR c/121911
* target.def (stack_protect_guard_symbol_p): New target hook.
* targhooks.cc (default_stack_protect_guard): Use the type of
uintptr_t, instead of ptr_type_node, if the
stack_protect_guard_symbol_p hook returns true.
* config/i386/i386.cc (ix86_stack_protect_guard_symbol_p): New.
(TARGET_STACK_PROTECT_GUARD_SYMBOL_P): Likewise.
* doc/tm.texi: Regenerated.
* doc/tm.texi.in (TARGET_STACK_PROTECT_GUARD_SYMBOL_P): New.
2026-05-04 Iain Buclaw <ibuclaw@gdcproject.org>
* config/m32c/*: Delete entire directory.
* attr-urls.def: Remove references to m32c.
* config.gcc: Likewise.
* config/msp430/msp430.cc (msp430_expand_epilogue): Likewise.
* configure: Regenerate.
* configure.ac: Remove references to m32c.
* doc/extend.texi: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: Likewise.
* explow.cc (promote_mode): Likewise.
* regenerate-opt-urls.py: Likewise.
* config/microblaze/microblaze.opt.urls: Regenerate.
* config/msp430/msp430.opt.urls: Regenerate.
* config/nds32/nds32.opt.urls: Regenerate.
* config/rl78/rl78.opt.urls: Regenerate.
* config/rs6000/sysv4.opt.urls: Regenerate.
* config/rx/elf.opt.urls: Regenerate.
* config/stormy16/stormy16.opt.urls: Regenerate.
* config/visium/visium.opt.urls: Regenerate.
2026-05-04 Richard Sandiford <rdsandiford@googlemail.com>
* config/aarch64/aarch64.cc (aarch64_expand_sve_vec_perm): Check
whether all indices of a variable selector refer to the first
values vector.
2026-05-04 Mark Wielaard <mark@klomp.org>
* config/xtensa/xtensa.opt.urls: Regenerated.
2026-05-04 Nathan Myers <ncm@cantrip.org>
* doc/invoke.texi: insert "result" in comment text
2026-05-04 Artemiy Volkov <artemiy.volkov@arm.com>
PR tree-optimization/122679
* tree-ssa-forwprop.cc (simplify_vector_constructor): Check the
PROP_gimple_lvec property before returning false.
2026-05-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/116823
* tree-ssa-phiprop.cc (can_handle_load): Skip past
clobbers for !aggregate.
2026-05-04 David Malcolm <dmalcolm@redhat.com>
* data-streamer-in.cc (streamer_read_value_range): Update for
renaming of value_range::set_type to value_range::set_range_class.
* gimple-range-gori.cc (gori_compute::compute_operand_range):
Likewise.
(gori_compute::compute_operand1_and_operand2_range): Likewise.
(gori_stmt_info::gori_stmt_info): Likewise.
(gori_calc_operands): Likewise.
(gori_name_helper): Likewise.
* ipa-cp.cc (ipcp_vr_lattice::set_to_bottom): Likewise.
* ipa-cp.h (ipcp_vr_lattice::init): Likewise.
* ipa-fnsummary.cc (evaluate_properties_for_edge): Likewise.
* ipa-prop.cc (ipa_vr::get_vrange): Likewise.
* range-op.h (range_cast): Likewise.
* value-range.h (value_range::set_type): Rename to...
(value_range::set_range_class): ...this, and add a note to the
leading comment that it doesn't set the type of the underlying
vrange.
(value_range::init): Add a similar note to the leading comment.
2026-05-04 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ranger_cache::range_of_expr): Handle
NULL statement.
2026-05-04 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-fold.cc (fold_using_range::fold_stmt): Move
range_of_address call into nested 'if' with other routines.
2026-05-04 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ranger_cache::ranger_cache): Allocate bitmap.
(ranger_cache::~ranger_cache): Free bitmap.
(ranger_cache::mark_stale): New.
(ranger_cache::get_global_range): Check if NAME is marked stale.
* gimple-range-cache.h (ranger_cache::mark_stale): New.
* gimple-range.cc (gimple_ranger::update_range_info): New variant.
* gimple-range.h (update_range_info): New prototype.
* gimple.h (gimple_set_modified): Call update_range_info.
* value-query.cc (range_query::update_range_info): New variant.
* value-query.h (range_query::update_range_info): New prototype.
2026-05-04 Andrew MacLeod <amacleod@redhat.com>
* value-range.cc (irange::intersect): Snap bounds as they are created.
2026-05-04 Andrew MacLeod <amacleod@redhat.com>
* value-query.cc (range_query::get_tree_range): Check if return
range R supports the expression type.
2026-05-04 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*bt<SWI48:mode>_mask): Use
int248_register_operand for operand 1 predicate.
(*jcc_bt<mode>_mask): Use nonimmediate_operand for operand 1 predicate.
(*jcc_bt<SWI48:mode>_mask_1): Use nonimmediate_operand for operand 1
predicate and int248_register_operand for operand 2 predicate.
(BT followed by CMOV splitter): Use nonimmediate_operand
for operand 1 predicate.
(*bt<mode>_setcqi): Ditto.
(*bt<mode>_setncqi): Ditto.
(*bt<mode>_setnc<mode>): Ditto.
(*bt<mode>_setncqi_2): Ditto.
(*bt<mode>_setc<mode>_mask): Use nonimmediate_operand for operand 1
predicate and int248_register_operand for operand 2 predicate.
2026-05-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123120
PR tree-optimization/116823
* tree-ssa-phiprop.cc (phiprop_insert_phi): Add other_vuse
argument, use it instead of the vuse on the use_stmt.
(can_handle_load): Add aggregate argument. Also return the vuse
of the load/store when the insert is allowed.
Skipping over one non-modifying store for !aggregate.
(propagate_with_phi): Update call to can_handle_load
and phiprop_insert_phi.
2026-05-04 Richard Biener <rguenther@suse.de>
Revert:
2025-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/120003
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Allow block re-use but do not enlarge the path beyond such a
re-use.
2026-05-04 Richard Biener <rguenther@suse.de>
PR middle-end/125156
* tree-cfgcleanup.cc (cleanup_control_expr_graph): Clear
EDGE_TRUE_VALUE and EDGE_FALSE_VALUE edge flags only.
2026-05-04 Richard Biener <rguenther@suse.de>
PR middle-end/125146
* gimple-fold.cc (fold_stmt_1): Discard stmts in seq
after failed gimple_simplify as well.
2026-05-04 Kishan Parmar <kishan@linux.ibm.com>
* config.gcc (powerpc*-*-*): Add support for supporting
--with-cpu=future.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
if the user used the -mcpu=future option.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Handle
ENB_FUTURE and issue diagnostic requiring -mcpu=future.
(rs6000_builtin_is_supported): Return TARGET_FUTURE for
ENB_FUTURE built-ins.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): New macro.
(POWERPC_MASKS): Add OPTION_MASK_FUTURE.
(rs6000_cpu_opt_value): New entry for 'future' via the RS6000_CPU macro.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
BSTZ_FUTURE for future.
(write_decls): Add ENB_FUTURE in bif_enable enum of generated header
file.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New macro.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_machine_from_flags) If -mcpu=future,
set the .machine directive to "future".
(rs6000_opt_masks): Add entry for -mfuture.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mfuture to the assembler
if the user used the -mcpu=future option.
* config/rs6000/rs6000.opt (-mfuture): New option.
* doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document
-mcpu=future.
2026-05-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* doc/extend.texi (Xtensa Named Address Spaces):
Document '__force_l32'.
(Xtensa Attributes): Document 'force_l32'.
* doc/invoke.texi (Xtensa Options):
Document '-m[no-]force-l32'.
2026-05-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_expand_load_force_l32_2):
New sub-function for inspecting pseudos that clearly point to the
function's stack frame.
(xtensa_expand_load_force_l32):
Add handling for loading from the generic address space when the
"-mforce-l32" option is enabled, however, obvious references to
function stack frames are excluded.
* config/xtensa/xtensa.opt (mforce-l32):
New target-specific option definition.
2026-05-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_attribute_table,
TARGET_ATTRIBUTE_TABLE):
New definitions for target-specific attributes.
(xtensa_expand_load_force_l32_1): New sub-function for inspecting
the attribute from the specified MEM rtx.
(xtensa_expand_load_force_l32): Add handlings for for addresses
with offsets.
(xtensa_handle_force_l32_attribute_1,
xtensa_handle_force_l32_attribute):
New functions for handling the attribute.
2026-05-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h
(xtensa_expand_load_force_l32): New function prototype.
* config/xtensa/xtensa.cc (#include): Add "expmed.h".
(TARGET_LEGITIMATE_ADDRESS_P):
Change a whitespace delimiter from HTAB to SPACE.
(TARGET_ADDR_SPACE_SUBSET_P, TARGET_ADDR_SPACE_CONVERT,
TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P):
New macro definitions for named address space.
(xtensa_addr_space_subset_p, xtensa_addr_space_convert,
xtensa_addr_space_legitimate_address_p):
New hook function prototypes and definitions required for
implementing the named address space.
(xtensa_expand_load_force_l32): New function that generates RTXes
that perform loads from memory belonging to the named address
space.
* config/xtensa/xtensa.h (ADDR_SPACE_FORCE_L32):
New macro for the ID# of the named address space.
(REGISTER_TARGET_PRAGMAS): New hook for registering C language
identifier for the named address space.
* config/xtensa/xtensa.md
(zero_extend<mode>si2_internal): Rename from zero_extend<mode>si2.
(zero_extend<mode>si2): New RTL generation pattern that calls
xtensa_expand_load_force_l32().
(extendhisi2, extendqisi2, movhi, movqi):
Change to call xtensa_expand_load_force_l32() first.
(*shift_per_byte): Delete the insn condition.
2026-05-04 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/124766
* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
Simplify x + y == y constructs.
2026-05-04 Avinal Kumar <avinal.xlvii@gmail.com>
PR tree-optimization/116700
* match.pd: (A > B ? ABS(A) : B -> MAX(A, B)): New pattern
for non-negative B.
2026-05-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-chrec.cc (chrec_fold_plus_poly_poly): Move
rtype definition to right before the use.
2026-05-03 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR tree-optimization/122569
* tree-ssa-forwprop.cc (simplify_count_zeroes): Avoid
shift-by-HOST_BITS_PER_WIDE_INT UB when computing the all-ones
value for the CLZ validator.
2026-05-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124009
* config/riscv/iterators.md (scc_0): Add any_lt.
* config/riscv/zicond.md: Add splitters to select between 2^n and 0.
2026-05-03 Collin Funk <collin.funk1@gmail.com>
* glimits.h (__STDC_VERSION_LIMITS_H__): Only define the macro
if it was not already defined.
2026-05-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/125152
* config/riscv/riscv.cc (riscv_expand_conditional_move): Extract the
mode after operand canonicalization.
2026-05-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiopt.cc (pass_phiopt::execute): Set cfgcleanup
if cselim_limited returns true.
2026-05-02 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/109038
* config/riscv/bitmanip.md (rotate_with_masking_to_shift): New pattern.
2026-05-02 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
* config/riscv/riscv.opt.urls: Add temp fix for -mmpy-option.
2026-05-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125139
* match.pd (`(A>>bool) EQ 0 -> (unsigned)A LE bool`): Enable
only for INTEGRAL_TYPE_P types.
2026-05-01 Sam James <sam@gentoo.org>
* Makefile.in (MOSTLYCLEANFILES): Fix typo of '$(exeext)'.
2026-05-01 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/119420
* match.pd(`(A>>bool) EQ 0 -> (unsigned)A LE bool`): New
pattern.
2026-05-01 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR rtl-optimization/123967
* match.pd(`if (cond) (A | CST1) : (A & ~CST1)`)`: New pattern.
2026-05-01 Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/110010
* match.pd (`(A>>C) NE|EQ (B>>C) -> (A^B) GE|LT (1<<C)`): New
pattern.
2026-05-01 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
* config.gcc: Added riscv-fusion.o
* config/riscv/riscv-protos.h (enum riscv_fusion_pairs):
(riscv_macro_fusion_p): Added declaration.
(riscv_macro_fusion_pair_p): Idem.
(riscv_get_fusible_ops): Idem.
* config/riscv/riscv.cc (enum riscv_fusion_pairs):
(riscv_macro_fusion_p): Moved to riscv-fusion.cc
(riscv_fusion_enabled_p): Idem.
(riscv_set_is_add): Idem.
(riscv_set_is_addi): Idem.
(riscv_set_is_adduw): Idem.
(riscv_set_is_shNadd): Idem.
(riscv_set_is_shNadduw): Idem.
(riscv_macro_fusion_pair_p): Idem.
(riscv_get_fusible_ops): New function to access tune_param->fusible_ops
from riscv-fusion.cc.
* config/riscv/t-riscv: Added riscv-fusion.cc
* config/riscv/riscv-fusion.cc: New file.
2026-05-01 Kewen Lin <linkewen@hygon.cn>
* config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.
(c86_4g_m7_fdiv): Ditto.
(c86-4g-m7-idiv): New unit.
(c86-4g-m7-fdiv): Ditto.
(c86_4g_m7_idiv_DI): Adjust unit in the reservation.
(c86_4g_m7_idiv_SI): Ditto.
(c86_4g_m7_idiv_HI): Ditto.
(c86_4g_m7_idiv_QI): Ditto.
(c86_4g_m7_idiv_DI_load): Ditto.
(c86_4g_m7_idiv_SI_load): Ditto.
(c86_4g_m7_idiv_HI_load): Ditto.
(c86_4g_m7_idiv_QI_load): Ditto.
(c86_4g_m7_fp_div): Ditto.
(c86_4g_m7_fp_div_load): Ditto.
(c86_4g_m7_fp_idiv_load): Ditto.
(c86_4g_m7_avx512_ssediv): Ditto.
(c86_4g_m7_avx512_ssediv_mem): Ditto.
(c86_4g_m7_avx512_ssediv_z): Ditto.
(c86_4g_m7_avx512_ssediv_zmem): Ditto.
(c86_4g_m7_avx512_sse_sqrt): Ditto.
(c86_4g_m7_avx512_sse_sqrt_load): Ditto.
(c86_4g_m7_fp_sqrt): Ditto. Rename from ...
(c86_4g_m7fp_sqrt): ... here.
* config/i386/c86-4g.md (c86_4g_idiv): New automaton.
(c86_4g_fdiv): Ditto.
(c86-4g-idiv): New unit.
(c86-4g-fdiv): Ditto.
(c86_4g_idiv_DI): Ditto.
(c86_4g_idiv_SI): Ditto.
(c86_4g_idiv_HI): Ditto.
(c86_4g_idiv_QI): Ditto.
(c86_4g_idiv_mem_DI): Ditto.
(c86_4g_idiv_mem_SI): Ditto.
(c86_4g_idiv_mem_HI): Ditto.
(c86_4g_idiv_mem_QI): Ditto.
(c86_4g_fp_sqrt): Ditto.
(c86_4g_sse_sqrt_sf): Ditto.
(c86_4g_sse_sqrt_sf_mem): Ditto.
(c86_4g_sse_sqrt_df): Ditto.
(c86_4g_sse_sqrt_df_mem): Ditto.
(c86_4g_fp_op_div): Ditto.
(c86_4g_fp_op_div_load): Ditto.
(c86_4g_fp_op_idiv_load): Ditto.
(c86_4g_ssediv_ss_ps): Ditto.
(c86_4g_ssediv_ss_ps_load): Ditto.
(c86_4g_ssediv_ss_pd): Ditto.
(c86_4g_ssediv_ss_pd_load): Ditto.
(c86_4g_ssediv_avx256_ps): Ditto.
(c86_4g_ssediv_avx256_ps_load): Ditto.
(c86_4g_ssediv_avx256_pd): Ditto.
(c86_4g_ssediv_avx256_pd_load): Ditto.
2026-05-01 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
Artemiy Volkov <artemiyv@acm.org>
Luis Silva <luiss@synopsys.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rmx-100-series.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
Add arcv_rmx100.
(enum arcv_mpy_option_enum): New enum for ARC-V multiply options.
* config/riscv/riscv-protos.h (arcv_mpy_1c_bypass_p): New declaration.
(arcv_mpy_2c_bypass_p): New declaration.
(arcv_mpy_10c_bypass_p): New declaration.
* config/riscv/riscv.cc (arcv_mpy_1c_bypass_p): New function.
(arcv_mpy_2c_bypass_p): New function.
(arcv_mpy_10c_bypass_p): New function.
* config/riscv/riscv.md: Add arcv_rmx100.
* config/riscv/riscv.opt: New option for RMX-100 multiply unit
configuration.
* doc/riscv-mtune.texi: Document arc-v-rmx-100-series.
* config/riscv/arcv-rmx100.md: New file.
2026-05-01 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
Artemiy Volkov <artemiyv@acm.org>
Luis Silva <luiss@synopsys.com>
* config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rhx-100-series.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add
arcv_rhx100.
* config/riscv/riscv.cc (arcv_rhx100_tune_info): New riscv_tune_param.
* config/riscv/riscv.md: Add arcv_rhx100 to tune attribute.
* doc/riscv-mtune.texi: Add RHX-100 documentation.
* config/riscv/arcv-rhx100.md: New file.
2026-05-01 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/riscv/riscv.cc (riscv_expand_conditional_move):
Convert unsigned comparisons against power-of-2 boundaries
to shift-based equality tests.
2026-05-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac: Test solaris_as, solaris_ld instead of gas, gnu_ld.
(gcc_cv_as_working_gdwarf_n_flag): Escape '.' in filename.
* acinclude.m4 (gcc_cv_initfini_array): Test solaris_as,
solaris_ld instead of gas, gnu_ld.
* configure: Regenerate.
2026-05-01 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces
around the if body for the slli.uw pattern in the AND case.
2026-05-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/125079
* tree-ssa-strlen.cc (get_string_length): Transform
__strcat_chk (x, y, z) when we need strlen (x) afterwards into
l1 = strlen (x); l = __stpcpy_chk (x + l1, y, z - l1) - x;
where l is the strlen (x), instead of using z as last __stpcpy_chk
argument.
2026-05-01 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124559
* config/riscv/riscv-protos.h (riscv_move_integer): Drop mode argument.
* config/riscv/riscv.cc (riscv_move_integer): Pass mode after promotions
to riscv_build_integer. All callers changed.
* config/riscv/riscv.md: Corresponding changes.
* cse.cc (cse_insn): Try to derive one constant from another using NOT/NEG.
2026-05-01 H.J. Lu <hjl.tools@gmail.com>
PR target/125117
* config/i386/i386-expand.cc (ix86_expand_movmem): Generate
last_4x_vec_label when min_size <= 4 * MOVE_MAX.
2026-05-01 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (s390_secondary_reload): Add cases for HF
vector modes.
* config/s390/s390.md: Add modes V{1,2,4,8}HF to mode iterator
ALL.
2026-05-01 Jakub Jelinek <jakub@redhat.com>
* tree-vect-loop.cc (vectorizable_reduction): Remove pointless
&& 1.
2026-05-01 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/96692
* config/riscv/bitmanip.md (xor+xor+ior splitters): New splitters
that ultimately generate andn+xor when possible.
2026-04-30 H.J. Lu <hjl.tools@gmail.com>
PR target/124878
* config/i386/i386.cc (x86_64_int_return_registers): Remove
DI_REG and SI_REG.
(ix86_function_value_regno_p): Remove DI_REG and SI_REG cases.
(function_value_64): Replace X86_64_REGPARM_MAX and
X86_64_SSE_REGPARM_MAX with X86_64_MAX_RETURN_NREGS and
X86_64_MAX_SSE_RETURN_NREGS for the number of registers used
in return values.
* config/i386/i386.h (X86_64_MAX_RETURN_NREGS): New. Defined
to 2.
(X86_64_MAX_SSE_RETURN_NREGS): Likewise.
2026-04-30 H.J. Lu <hjl.tools@gmail.com>
PR target/125102
* config/i386/mmx.md (V_16_32_64:*mov<mode>_imm): Disable
16-bit immediate integer store if TARGET_LCP_STALL is true.
2026-04-30 Eric Botcazou <ebotcazou@adacore.com>
* Makefile.in (COVERAGE_FLAGS): Remove obsolete comment.
2026-04-30 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-costs.cc (record_reg_classes): Process correctly case
op_class == NO_REGS.
2026-04-30 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-color.cc (assign_hard_reg): Use the right allocno mode to
call note_conflict.
2026-04-30 Heiko Eißfeldt <heiko.Eissfeldt@hexco.de>
PR middle-end/124805
* tree-ssa.cc (verify_vssa):
replace recursive calls with iteration for lower stack usage
2026-04-30 Tomas Härdin <git@haerdin.se>
* toplev.cc (output_stack_usage_1): Pass RINT_DECL_UNIQUE_NAME
instead of PRINT_DECL_NAME to print_decl_identifier.
2026-04-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (`(a !=/== b) &\| ((a|b) ==/!= 0)`):
Simplify patterns using for loop and remove the `:c`
on the inner ne/eq.
2026-04-30 Christopher Bazley <chris.bazley@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_pragma_target_parse):
Pass &global_options_set as an argument to
aarch64_override_options_internal.
* config/aarch64/aarch64-protos.h (aarch64_override_options_internal):
Add a parameter declaration for opts_set.
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Add a parameter declaration for opts_set and use the argument
when invoking SET_OPTION_IF_UNSET.
(aarch64_override_options): Pass &global_options_set as an argument to
aarch64_override_options_internal.
(aarch64_option_restore): As above.
(aarch64_set_current_function): As above.
(aarch64_option_valid_attribute_p): As above.
(aarch64_option_valid_version_attribute_p): As above.
2026-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/125088
* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Refactor and
simplify.
* tree-vect-stmts.cc (vect_nop_conversion_p): Exclude
copies with memory accesses.
2026-04-30 H.J. Lu <hjl.tools@gmail.com>
PR target/125026
PR target/125032
* config/i386/i386-features.cc (ix86_place_single_vector_set):
Don't check CONST_VECTOR load size.
(replace_vector_const): Handle constant integer load.
(x86_cse::x86_cse): Convert CONST_VECTOR load no larger than
integer to constant integer load and keep redundant constant
integer load. Generate zero CONST_VECTOR load.
2026-04-30 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
* doc/params.texi: Added --param=max-niter-dominators-walk.
* params.opt: Added --param=max-niter-dominators-walk.
* tree-ssa-loop-niter.cc (MAX_DOMINATORS_TO_WALK): Removed.
(determine_value_range): Updated.
(bound_difference): Updated.
(simplify_using_initial_conditions): Updated.
2026-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/120398
PR tree-optimization/123603
* config/i386/i386.opt (ix86-vect-compare-costs): Default to 1.
2026-04-30 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::better_epilogue_loop_than_p):
New. If the other loop suggests this as epilog prefer other.
2026-04-30 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vector_costs::vinfo): New accessor.
* config/i386/i386.cc (ix86_vector_costs::better_main_loop_than_p):
Prefer a masked main loop if we can elide enough of (vector)
epilog loop iterations.
2026-04-29 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/113379
* match.pd (min(a,b) {<=,>,<,>=} max(a,b)): New patterns.
2026-04-29 John David Anglin <danglin@gcc.gnu.org>
* doc/install.texi (hppa64-hp-hpux11*): Remove incorrect
statement.
2026-04-29 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.opt (mpc-relative-literal-loads):
Deprecate.
* config/aarch64/aarch64.cc (aarch64_override_options):
Add deprecated warning for -mpc-relative-literal-loads.
* doc/invoke.texi (mpc-relative-literal-loads): Update docs.
2026-04-29 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.h (HAS_LONG_COND_BRANCH): Unused, remove.
(HAS_LONG_UNCOND_BRANCH): unused, remove.
* config/aarch64/aarch64.cc (aarch64_use_pseudo_pic_reg): Declare.
(aarch64_rtx_costs): Update.
(aarch64_override_options_after_change_1): Likewise.
(initialize_aarch64_code_model): Simplify.
(aarch64_classify_tls_symbol): Likewise.
(aarch64_classify_symbol): Simplify, remove duplicated code.
(aarch64_asm_preferred_eh_data_format): Update.
(aarch64_use_pseudo_pic_reg): Update.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Remove uses of AARCH64_CMODEL_TINY_PIC, AARCH64_CMODEL_SMALL_PIC,
and AARCH64_CMODEL_SMALL_SPIC.
* config/aarch64/aarch64-opts.h (aarch64_code_model):
Remove AARCH64_CMODEL_TINY_PIC, AARCH64_CMODEL_SMALL_PIC and
AARCH64_CMODEL_SMALL_SPIC.
2026-04-29 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-remat.cc (do_remat): Use the right nregs for pseudo hard reg
when updating live hard regs.
2026-04-29 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-remat.cc (reg_overlap_for_remat_p): Use the right mode for
regno2.
2026-04-29 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-conflicts.cc (build_object_conflicts): Use the right
conflicting allocno.
2026-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/125080
* tree-vect-slp.cc (vect_bb_slp_mark_stmts_vectorized): Only
add instance root stmts to scalar coverage if they do not
appear in externs.
2026-04-29 Xin Liu <liulxx@hygon.cn>
Zhaoling Bao <baozhaoling@hygon.cn>
* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect the specific
type of HYGON CPU and return HYGON CPU name.
(cpu_indicator_init): Handle HYGON CPU.
* common/config/i386/i386-common.cc (processor_names): Add HYGON
C86-4G processors c86-4g-m{4,6,7}.
(processor_alias_table): Add hygon, hygonfam18h and c86-4g-m{4,6,7}
entries.
(ARRAY_SIZE): Update as new entries added.
* common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add
VENDOR_HYGON.
(enum processor_types): Add HYGONFAM18H.
(enum processor_subtypes): Add HYGONFAM18H_C86_4G_M{4,6,7}.
* config.gcc: Add support for c86_4g_m{4,6,7}.
* config/i386/cpuid.h (signature_HYGON_ebx): Add signature for HYGON.
(signature_HYGON_ecx): Ditto.
(signature_HYGON_edx): Ditto.
* config/i386/driver-i386.cc (host_detect_local_cpu): Support HYGON
c86-4g-m4{4,6,7} processors.
* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
* config/i386/i386-options.cc (m_C86_4G_M4): New definition.
(m_C86_4G_M6): Ditto.
(m_C86_4G_M7): Ditto.
(m_C86_4G): Ditto.
(processor_cost_table): Add cost entries for c86-4g-m4{4,6,7}.
* config/i386/i386.cc (ix86_reassociation_width): Add handlings for
PROCESSOR_C86_4G_M{4,6,7}.
* config/i386/i386.h (enum processor_type): Define
PROCESSOR_C86_4G_M{4,6,7}.
(PTA_C86_4G_M4): New define.
(PTA_C86_4G_M6): Ditto.
(PTA_C86_4G_M7): Ditto.
* config/i386/x86-tune-costs.h (c86_4g_m4_memcpy): New stringop_algs.
(c86_4g_m4_cost): New processor_costs.
(c86_4g_m6_cost): Ditto.
(c86_4g_m7_cost): Ditto.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle
PROCESSOR_C86_4G_M{4,6,7}.
(ix86_adjust_cost): Ditto.
* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Handle m_C86_4G.
(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
(X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
(X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
(X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
(X86_TUNE_USE_LEAVE): Ditto.
(X86_TUNE_PUSH_MEMORY): Ditto.
(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
(X86_TUNE_USE_SAHF): Ditto.
(X86_TUNE_USE_BT): Ditto.
(X86_TUNE_AVOID_MFENCE): Ditto.
(X86_TUNE_USE_FFREEP): Ditto.
(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
(X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL): Ditto.
(X86_TUNE_SSE_TYPELESS_STORES): Ditto.
(X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
(X86_TUNE_USE_GATHER_2PARTS): Ditto.
(X86_TUNE_USE_GATHER_4PARTS): Ditto.
(X86_TUNE_USE_GATHER_8PARTS): Ditto.
(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.
(X86_TUNE_USE_RCR): Ditto.
(X86_TUNE_AVX256_MOVE_BY_PIECES): Handle m_C86_4G_M{4,6}.
(X86_TUNE_USE_SCATTER_2PARTS): Handle m_C86_4G_M7.
(X86_TUNE_USE_SCATTER_4PARTS): Ditto.
(X86_TUNE_USE_SCATTER_8PARTS): Ditto.
(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Ditto.
(X86_TUNE_AVX512_SPLIT_REGS): Ditto.
(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.
(X86_TUNE_AVX512_MASKED_EPILOGUES): Ditto.
* doc/extend.texi: Document about hygonfam18h and c86-4g-m{4,6,7}.
* doc/invoke.texi: Document about c86-4g-m{4,6,7}.
* config/i386/c86-4g-m7.md: New file for c86-4g-m7 scheduling model
information.
* config/i386/c86-4g.md: New file for c86-4g-m{4,6} scheduling model
information.
* config/i386/i386.md (cpu attr): Add c86_4g_m{4,6,7}.
(c86-4g.md): New include.
(c86-4g-m7.md): Ditto.
(*cmpi<unord>xf_i387): Set attr c86_decode.
(*cmpi<unord><MODEF:mode>): Ditto.
(swap<mode>): Ditto.
(*swap<mode>): Ditto.
(extendhisi2): Ditto.
(floathi<mode>2): Ditto.
(float<SWI48x:mode>xf2): Ditto.
(*float<SWI48:mode><MODEF:mode>2): Ditto.
(*floatdi<MODEF:mode>2_i387): Ditto.
(*anddi_1_bt): Ditto.
(*iordi_1_bts): Ditto.
(*xordi_1_btc): Ditto.
(*<btsc><mode>): Ditto.
(*btr<mode>): Ditto.
(*btsq_imm): Ditto.
(*btrq_imm): Ditto.
(*btcq_imm): Ditto.
(*tzcnt<mode>_1): Ditto.
(*tzcnt<mode>_1_falsedep): Ditto.
(*bsf<mode>_1): Ditto.
(*ctz<mode>2_falsedep): Ditto.
(*ctzsi2_zext): Ditto.
(*ctzsi2_zext_falsedep): Ditto.
(bsr_rex64): Ditto.
(bsr_rex64_1): Ditto.
(bsr_rex64_1_zext): Ditto.
(bsr): Ditto.
(bsr_1): Ditto.
(bsr_zext_1): Ditto.
(*bswaphi2_movbe): Ditto.
(*bswaphi2): Ditto.
(bswaphisi2_lowpart): Ditto.
(fpremxf4_i387): Ditto.
(fprem1xf4_i387): Ditto.
(<sincos>xf2): Ditto.
(sincosxf3): Ditto.
(fptanxf4_i387): Ditto.
(atan2xf3): Ditto.
(fyl2xxf3_i387): Ditto.
(fyl2xp1xf3_i387): Ditto.
(fxtractxf3_i387): Ditto.
(*f2xm1xf2_i387): Ditto.
(fscalexf4_i387): Ditto.
(rintxf2): Ditto.
(*movxi_internal_avx512f): Set attr c86_attr.
(*movoi_internal_avx): Ditto.
(*movti_internal): Ditto.
(*movdi_internal): Ditto.
(*movsi_internal): Ditto.
(*movhi_internal): Ditto.
(*movtf_internal): Ditto.
(*movdf_internal): Ditto.
(*movsf_internal): Ditto.
(*zero_extendsidi2): Ditto.
(sqrtxf2): Ditto.
(<smaxmin:code><mode>3): Ditto.
(*ieee_s<ieee_maxmin><mode>3): Ditto.
* config/i386/mmx.md (*mmx_maskmovq): Set attr c86_decode.
(*mmx_maskmovq): Ditto.
(sse_movntq): Set attr c86_attr.
(*mmx_blendps): Ditto.
(mmx_blendvps): Ditto.
(*mmx_pmaddwd): Ditto.
(mmx_pblendvb_v8qi): Ditto.
(mmx_pblendvb_<mode>): Ditto.
(sse4_1_<code>v4qiv4hi2): Ditto.
(sse4_1_<code>v2hiv2si2): Ditto.
(sse4_1_<code>v2qiv2si2): Ditto.
(sse4_1_<code>v2qiv2hi2): Ditto.
(*mmx_pinsrd): Ditto.
(*mmx_pinsrw): Ditto.
(*mmx_pinsrb): Ditto.
(*mmx_pextrw): Ditto.
(*mmx_pextrw<mode>): Ditto.
(*mmx_pextrw_zext): Ditto.
(*mmx_pextrb): Ditto.
(*mmx_pextrb_zext): Ditto.
(*mmx_pblendw64): Ditto.
(*mmx_pblendw32): Ditto.
(*vec_extractv2si_1): Ditto.
(*vec_extractv2si_1_zext): Ditto.
(*pinsrw): Ditto.
(*pinsrb): Ditto.
(*pextrw): Ditto.
(*pextrw<mode>): Ditto.
(*pextrw_zext): Ditto.
(*pextrb): Ditto.
(*pextrb_zext): Ditto.
(*mmx_psadbw): Ditto.
* config/i386/sse.md (ktest<mode>): Set attr c86_decode.
(*kortest<mode>): Ditto.
(sse_cvtsi2ss<rex64namesuffix><round_name>): Ditto.
(sse2_cvtsi2sd): Ditto.
(sse2_maskmovdqu): Ditto.
(*<sse>_dp<ssemodesuffix><avxsizesuffix>): Ditto.
(*<sse4_1_avx2>_mpsadbw): Ditto.
(pclmulqdq): Ditto.
(<mask_codefor>conflict<mode><mask_name>): Ditto.
(<avx512>_blendm<mode>): Set attr c86_attr.
(sse2_movnti<mode>): Ditto.
(<sse>_movnt<mode>): Ditto.
(<sse2>_movnt<mode>): Ditto.
(<sse>_rcp<mode>2): Ditto.
(sse_vmrcpv4sf2): Ditto.
(<mask_codefor>rcp14<mode><mask_name>): Ditto.
(srcp14<mode>): Ditto.
(srcp14<mode>_mask): Ditto.
(<sse>_sqrt<mode>2<mask_name><round_name>): Ditto.
(<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
(*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
(<mask_codefor>rsqrt14<mode><mask_name>): Ditto.
(rsqrt14<mode>): Ditto.
(rsqrt14_<mode>_mask"): Ditto.
(*<code><mode>3<mask_name><round_saeonly_name>): Ditto.
(ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>): Ditto.
(*<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name>):
Ditto.
(<sse>_ieee_vm<ieee_maxmin><mode>3<mask_scalar_name>
<round_saeonly_scalar_name>): Ditto.
(*ieee_<ieee_maxmin><mode>3): Ditto.
(avx_h<insn>v4df3): Ditto.
(*sse3_haddv2df3): Ditto.
(sse3_hsubv2df3): Ditto.
(*sse3_haddv2df3_low): Ditto.
(*sse3_hsubv2df3_low): Ditto.
(avx_h<insn>v8sf3): Ditto.
(sse3_h<insn>v4sf3): Ditto.
(*<mask_codefor>reducep<mode><mask_name><round_saeonly_name>): Ditto.
(reduces<mode><mask_scalar_name><round_saeonly_scalar_name>): Ditto.
(*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto.
(<sse>_andnot<mode>3<mask_name>): Ditto.
(*<code><mode>3<mask_name>): Ditto.
(*andnot<mode>3): Ditto.
(<code><mode>3): Ditto.
(*<code>tf3): Ditto.
(vec_set<mode>_0): Ditto.
(@vec_set<mode>_0): Ditto.
(*sse4_1_extractps): Ditto.
(vec_extract<mode>): Ditto.
(<mask_codefor><avx512>_align<mode><mask_name>): Ditto.
(avx512bw_pmaddwd512<mode><mask_name>): Ditto.
(*avx2_pmaddw): Ditto.
(*sse2_pmaddwd): Ditto.
(*avx2_<code><mode>3): Ditto.
(*avx512f_<code><mode>3<mask_name>): Ditto.
(*avx512bw_<code><mode>3<mask_name>): Ditto.
(*sse4_1_<code><mode>3<mask_name>): Ditto.
(*<code>v8hi3): Ditto.
(*<code>v16qi3): Ditto.
(*andnot<mode>3_mask): Ditto.
(*<code><mode>3): Ditto.
(<code>v1ti3): Ditto.
(<sse2p4_1>_pinsr<ssemodesuffix>): Ditto.
(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Ditto.
(<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>
_1<mask_name>): Ditto.
(vec_set_lo_<mode><mask_name>): Ditto.
(vec_set_hi_<mode><mask_name>): Ditto.
(<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
(avx512f_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
(*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1): Ditto.
(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
(avx512f_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
(*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): Ditto.
(*vec_extract<mode>): Ditto.
(*vec_extract<PEXTR_MODE12:mode>_zext): Ditto.
(*vec_extractv16qi_zext): Ditto.
(*vec_extractv4si): Ditto.
(*vec_extractv4si_zext): Ditto.
(*vec_extractv2di_1): Ditto.
(*vec_concatv2si_sse4_1): Ditto.
(vec_concatv2di): Ditto.
(*<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
(*<sse2_avx2>_psadbw): Ditto.
(<sse>_movmsk<ssemodesuffix><avxsizesuffix>): Ditto.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Ditto.
(<sse2_avx2>_pmovmskb): Ditto.
(*<sse2_avx2>_pmovmskb_zext): Ditto.
(*sse2_maskmovdqu): Ditto.
(avx2_ph<plusminus_mnemonic>wv16hi3): Ditto.
(ssse3_ph<plusminus_mnemonic>wv8hi3): Ditto.
(ssse3_ph<plusminus_mnemonic>dv4si3): Ditto.
(avx2_ph<plusminus_mnemonic>dv8si3): Ditto.
(avx2_pmaddubsw256): Ditto.
(avx512bw_pmaddubsw512<mode><mask_name>): Ditto.
(ssse3_pmaddubsw128): Ditto.
(<ssse3_avx2>_psign<mode>3): Ditto.
(ssse3_psign<mode>3): Ditto.
(*abs<mode>2): Ditto.
(abs<mode>2_mask): Ditto.
(abs<mode>2_mask): Ditto.
(sse4a_movnt<mode>): Ditto.
(sse4a_vmmovnt<mode>): Ditto.
(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Ditto.
(<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Ditto.
(sse4_1_blendv<ssemodesuffix>): Ditto.
(<vi8_sse4_1_avx2_avx512>_movntdqa): Ditto.
(<sse4_1_avx2>_pblendvb): Ditto.
(sse4_1_pblend<ssemodesuffix>): Ditto.
(*avx2_pblend<ssemodesuffix>): Ditto.
(avx2_pblendd<mode>): Ditto.
(avx2_<code>v16qiv16hi2<mask_name>): Ditto.
(avx512bw_<code>v32qiv32hi2<mask_name>): Ditto.
(sse4_1_<code>v8qiv8hi2<mask_name>): Ditto.
(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Ditto.
(<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): Ditto.
(avx2_<code>v8qiv8si2<mask_name>): Ditto.
(*avx2_<code>v8qiv8si2<mask_name>_1): Ditto.
(sse4_1_<code>v4qiv4si2<mask_name>): Ditto.
(*sse4_1_<code>v4qiv4si2<mask_name>_1): Ditto.
(avx512f_<code>v16hiv16si2<mask_name>): Ditto.
(avx2_<code>v8hiv8si2<mask_name>): Ditto.
(sse4_1_<code>v4hiv4si2<mask_name>): Ditto.
(*sse4_1_<code>v4hiv4si2<mask_name>_1): Ditto.
(avx512f_<code>v8qiv8di2<mask_name>): Ditto.
(*avx512f_<code>v8qiv8di2<mask_name>_1): Ditto.
(avx2_<code>v4qiv4di2<mask_name>): Ditto.
(*avx2_<code>v4qiv4di2<mask_name>_1): Ditto.
(sse4_1_<code>v2qiv2di2<mask_name>): Ditto.
(*sse4_1_<code>v2qiv2di2<mask_name>_1): Ditto.
(avx512f_<code>v8hiv8di2<mask_name>): Ditto.
(avx2_<code>v4hiv4di2<mask_name>): Ditto.
(*avx2_<code>v4hiv4di2<mask_name>_1): Ditto.
(sse4_1_<code>v2hiv2di2<mask_name>): Ditto.
(*sse4_1_<code>v2hiv2di2<mask_name>_1): Ditto.
(avx512f_<code>v8siv8di2<mask_name>): Ditto.
(avx2_<code>v4siv4di2<mask_name>): Ditto.
(sse4_1_<code>v2siv2di2<mask_name>): Ditto.
(*sse4_1_<code>v2siv2di2<mask_name>_1): Ditto.
(sse4_1_round<ssescalarmodesuffix>): Ditto.
(*sse4_1_round<ssescalarmodesuffix>"): Ditto.
(sse4_2_pcmpestri): Ditto.
(sse4_2_pcmpestrm): Ditto.
(sse4_2_pcmpestr_cconly): Ditto.
(sse4_2_pcmpistri): Ditto.
(sse4_2_pcmpistrm): Ditto.
(sse4_2_pcmpistr_cconly): Ditto.
(xop_phadd<u>bw): Ditto.
(xop_phadd<u>bd): Ditto.
(xop_phadd<u>bq): Ditto.
(xop_phadd<u>wd): Ditto.
(xop_phadd<u>wq): Ditto.
(xop_phadd<u>dq): Ditto.
(xop_phsubbw): Ditto.
(xop_phsubwd): Ditto.
(xop_phsubdq): Ditto.
(aesenc): Ditto.
(aesenclast): Ditto.
(aesdec): Ditto.
(aesdeclast): Ditto.
(aesimc): Ditto.
(aeskeygenassist): Ditto.
(<avx2_avx512>_permvar<mode><mask_name>): Ditto.
(avx2_perm<mode>_1<mask_name>): Ditto.
(<avx512>_permvar<mode><mask_name>): Ditto.
(avx512f_perm<mode>_1<mask_name>): Ditto.
(<mask_codefor>avx512f_broadcast<mode><mask_name>): Ditto.
(avx_vbroadcastf128_<mode>): Ditto.
(<mask_codefor>avx512vl_broadcast<mode><mask_name>_1): Ditto.
(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Ditto.
(*<avx512>_vpermi2var<mode>3_mask): Ditto.
(<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto.
(<avx512>_vpermt2var<mode>3_mask): Ditto.
(*avx_vperm2f128<mode>_nozero): Ditto.
(vec_set_lo_<mode><mask_name>): Ditto.
(vec_set_hi_<mode><mask_name>): Ditto.
(vec_set_lo_<mode>): Ditto.
(vec_set_hi_<mode>): Ditto.
(vec_set_lo_v32qi): Ditto.
(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Ditto.
(<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
(avx_vec_concat<mode>): Ditto.
(<avx512>_compress<mode>_mask): Ditto.
(compress<mode>_mask): Ditto.
(<avx512>_compressstore<mode>_mask): Ditto.
(compressstore<mode>_mask): Ditto.
(expand<mode>_mask): Ditto.
(<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>): Ditto.
(clz<mode>2<mask_name>): Ditto.
(vpmadd52<vpmadd52type>v8di): Ditto.
(vpmadd52<vpmadd52type><mode>): Ditto.
(vpmadd52<vpmadd52type><mode>_maskz_1): Ditto.
(vpmadd52<vpmadd52type><mode>_mask): Ditto.
(vaesdec_<mode>): Ditto.
(vaesdeclast_<mode>): Ditto.
(vaesenc_<mode>): Ditto.
(vaesenclast_<mode>): Ditto.
2026-04-29 Pan Li <pan2.li@intel.com>
* config/riscv/predicates.md: Add ltu to swappable
cmp operator.
* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle
the swapped rtx code as well.
2026-04-29 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
Move obj_nelts/atype computation before bitint_extended handling. For
bitint_big_endian in the bitint_extended handling use size_zero_node
only for limb_access_type calls, otherwise use
size_int (nelts - obj_nelts) and pass NULL_TREE as first argument to
limb_access calls.
2026-04-29 Raghesh Aloor <Raghesh.Aloor@amd.com>
* tree-vect-slp.cc (vect_slp_linearize_chain): Optional parameter
allow_alt_code added (default true), check added not to follow
MINUS_EXPR, when false.
(vect_slp_check_for_roots): Calls vect_slp_linearize_chain with
parameter allow_alt_code set to false.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
PR analyzer/124217
* doc/invoke.texi: Add -Wanalyzer-div-by-zero.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (ANALYZER_OBJS): Add analyzer/exploded-path.o.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (ANALYZER_OBJS): Add analyzer/setjmp-longjmp.o.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (ANALYZER_OBJS): Add
analyzer/poisoned-value-diagnostic.o,
analyzer/shift-diagnostics.o, and
analyzer/write-to-const-diagnostics.o.
2026-04-28 Tomás Ortín Fernández <quanrong@mailbox.org>
PR analyzer/105890
* doc/invoke.texi: Rename -Wanalyzer-mkstemp-missing-suffix to
-Wanalyzer-mktemp-missing-placeholder and
-Wanalyzer-mkstemp-of-string-literal to
-Wanalyzer-mktemp-of-string-literal. Add
-Wanalyzer-mkostemp-redundant-flags. Fix alphabetical ordering
of detailed descriptions.
2026-04-28 Tomás Ortín Fernández <quanrong@mailbox.org>
PR analyzer/105890
* doc/invoke.texi: Add -Wanalyzer-mkstemp-missing-suffix and
-Wanalyzer-mkstemp-of-string-literal.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* diagnostics/html-sink.cc: Update status comment.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* doc/libgdiagnostics/topics/execution-paths.rst
(diagnostic_execution_path_add_event_via_msg_buf): Fix
indentation.
* doc/libgdiagnostics/topics/message-buffers.rst: Replace
duplicate entry for diagnostic_message_buffer_end_url with entry
for diagnostic_message_buffer_end_quote.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* diagnostics/context.h (diagnostics::context::make_option_name):
Convert return type from char * to label_text, and rename to...
(diagnostics::context::get_option_name): ...this.
(diagnostics::context::make_option_url): Likewise, renaming to...
(diagnostics::context::get_option_url): ...this.
* diagnostics/html-sink.cc
(html_builder::make_element_for_diagnostic): Update for above
changes.
* diagnostics/lazy-paths.cc (selftest::all_warnings_disabled):
Update for above changes.
* diagnostics/option-id-manager.h
(diagnostics::option_id_manager::make_option_name): Convert return
type from char * to label_text, and rename to...
(diagnostics::option_id_manager::get_option_name): ...this.
(diagnostics::option_id_manager::make_option_url): Likewise,
renaming to...
(diagnostics::option_id_manager::get_option_url): ...this.
* diagnostics/sarif-sink.cc: Add #define INCLUDE_SET.
(sarif_builder::m_rule_id_set): Convert from
hash_set <free_string_hash> to std::set<std::string>.
(sarif_builder::make_result_object): Update for above changes,
removing manual memory management.
(sarif_builder::make_reporting_descriptor_object_for_warning):
Likewise.
* diagnostics/text-sink.cc (text_sink::print_option_information):
Likewise.
* lto-wrapper.cc (print_lto_docs_link): Likewise.
(lto_diagnostic_option_id_manager::make_option_name): Convert
return type from char * to label_text, and rename to...
(lto_diagnostic_option_id_manager::get_option_name): ...this.
* opts-diagnostic.h (gcc_diagnostic_option_id_manager): Update for
above changes.
* opts.cc
(compiler_diagnostic_option_id_manager::make_option_name): Update
as above, renaming to...
(compiler_diagnostic_option_id_manager::get_option_name): ...this.
(gcc_diagnostic_option_id_manager::make_option_url): Likewise,
renaming to...
(gcc_diagnostic_option_id_manager::get_option_url): ...this.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
PR sarif-replay/123056
* libsarifreplay.cc: Include "json-pointer-parsing.h".
(sarif_replayer::sarif_replayer): Initialize m_root_val.
(sarif_replayer::m_root_val): New field.
(sarif_replayer::replay_file): Store m_root_val.
(sarif_replayer::append_embeddded_link): Add message_obj param.
Attempt to decode intra-sarif links, turning them into event IDs.
(sarif_replayer::decode_link_within_sarif): New.
(sarif_replayer::make_plain_text_within_result_message): Pass
message_obj to append_embeddded_link.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon): Add json-pointer-parsing.o.
* json-pointer-parsing.cc: New file.
* json-pointer-parsing.h: New file.
* json.cc (json::object::set_string): Return a borrowed pointer to
the new json::value.
(json::object::set_integer): Likewise.
(json::array::append_string): Likewise.
* json.h (json::object::set_string): Likewise.
(json::object::set_integer): Likewise.
(json::array::append_string): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::json_pointer_parsing_cc_tests.
* selftest.h (selftest::json_pointer_parsing_cc_tests): New decl.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon): Add pretty-print-token-buffer.o.
* libgdiagnostics.cc: Drop include of "auto-obstack.h".
Include "pretty-print-token-buffer.h".
(class copying_token_printer): Move to
pretty-print-token-buffer.cc.
(struct diagnostic_message_buffer): Reimplement as a subclass of
pretty_print_token_buffer.
(diagnostic_message_buffer::to_string): Rename to
pretty_print_token_buffer::to_string and move to
pretty-print-token-buffer.cc.
* pretty-print-token-buffer.cc: New file, based on material from
libgdiagnostics.cc.
* pretty-print-token-buffer.h: New file, based on material from
libgdiagnostics.h.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::pretty_print_token_buffer_cc_tests.
* selftest.h (selftest::pretty_print_token_buffer_cc_tests): New
decl.
2026-04-28 David Malcolm <dmalcolm@redhat.com>
* json-diagnostic.cc: Include "pretty-print-markup-json.h".
(class pp_markup::quoted_json_pointer): Move to...
* pretty-print-markup-json.h: ...this new file.
2026-04-28 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124760
* config/riscv/bitmanip.md (SI->DI promoting shadd pattern): Promote
intermediate SI ops to DI ops when there's a final extending op.
2026-04-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125067
* tree-ssa-phiprop.cc (can_handle_load): Fix copy and pasto
on dominated_by_p.
2026-04-28 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-eliminations.cc (mark_not_eliminable): Fix condition to
consider hard regs instead of pseudos for INC/DEC/MODIFY operands.
2026-04-28 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc (curr_insn_transform): When recreating subreg
of a const put in pool, use the original subreg mode.
2026-04-28 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-lives.cc (ira_implicitly_set_insn_hard_regs): Use the same
start prefered for all operand.
2026-04-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiprop.cc (propagate_with_phi): Move vuse variable
declaration right before its use.
2026-04-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiprop.cc (propagate_with_phi): Move vuse checks
before the dominator tests.
2026-04-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiprop.cc (propagate_with_phi): Factor out
checking the load for vdef to ....
(can_move_into_conditional): Here.
2026-04-28 Philipp Tomsich <philipp.tomsich@vrull.eu>
* fold-mem-offsets.cc (pass_fold_mem_offsets::execute): Remove
optimize_bb_for_size_p check.
* config/riscv/riscv.cc (riscv_option_override): Disable
flag_fold_mem_offsets when optimizing for size with compressed
instructions.
2026-04-28 Jiawei <jiawei@iscas.ac.cn>
Edwin Lu <ewlu@rivosinc.com>
* config/riscv/riscv-ext.def: New extension.
* config/riscv/riscv-ext.opt: Ditto.
* config/riscv/sync-rvwmo.md: Add check for zalasr.
* config/riscv/sync-ztso.md: Ditto.
* doc/riscv-ext.texi: New extension.
2026-04-28 Maximilian Ciric <max.ciric@gmail.com>
* config/riscv/riscv.cc (riscv_can_tag_addresses): New function.
(RISCV_HWASAN_TAG_SIZE): New definition.
(riscv_memtag_tag_bitsize): New function.
(TARGET_MEMTAG_CAN_TAG_ADDRESSES): New definition.
(TARGET_MEMTAG_TAG_BITSIZE): Likewise.
2026-04-28 Dimitar Dimitrov <dimitar@dinux.eu>
* config/pru/pru.h (ASM_SPEC): Define.
2026-04-28 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/94892
* config/riscv/riscv.md (sign_bit_splat_equality_test): New pattern.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Do not
attempt to live code-generate defs that are kept in scalar
form anyway.
* tree-vect-loop.cc (vectorizable_live_operation): Update
comment.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_slp_tree::live_lanes): New vector.
(SLP_TREE_LIVE_LANES): New.
* tree-vect-loop.cc (vectorizable_live_operation): Append
to SLP_TREE_LIVE_LANES.
* tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize
SLP_TREE_LIVE_LANES.
(_slp_tree::~_slp_tree): Release SLP_TREE_LIVE_LANES.
(vect_print_slp_tree): Adjust live lane dumping, indicating
the SLP node a lane is code generated from.
(vect_bb_slp_mark_live_stmts): No longer verify we can
code-generate from all SLP nodes but at least one, picking
the first.
* tree-vect-stmts.cc (vect_transform_stmt): Iterate over
SLP_TREE_LIVE_LANES.
(vect_analyze_stmt): Also analyze reductions for live
lanes.
2026-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/124222
* tree-vect-slp.cc (vect_slp_gather_vectorized_scalar_stmts): Remove.
(vect_bb_slp_scalar_cost): Simplify by using SLP_TREE_TYPE and
a use-def walk of the scalar stmts SSA uses.
(vect_bb_vectorization_profitable_p): Simplify.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vec_slp_has_scalar_use): Remove.
(vect_bb_slp_mark_live_stmts): Simplify.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_slp_analyze_bb_1): Split out pure_slp
marking into ...
(vect_bb_slp_mark_stmts_vectorized): ... new function. Compute
full scalar stmt coverage of the SLP graph.
(vect_slp_gather_extern_scalar_stmts): New helper.
(vect_bb_slp_mark_live_stmts): Adjust.
* tree-vect-loop.cc (vectorizable_live_operation): Likewise.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (struct slp_oprnds): New.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_slp_analyze_operations): Move
vect_bb_slp_mark_live_stmts call ...
(vect_slp_analyze_bb_1): ... here. Move SLP stmt marking
right before it.
(vect_mark_slp_stmts): Remove unused overload.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_slp_child_index_for_operand): Get
a stmt_vec_info, elide gather-scatter flag.
* tree-vect-stmts.cc (vect_check_store_rhs): Adjust.
(vectorizable_simd_clone_call): Likewise.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
* tree-vect-slp.cc (vect_get_operand_map): New overload
with a stmt_vec_info argument.
(vect_slp_child_index_for_operand): Adjust.
(vect_get_and_check_slp_defs): Likewise.
(compatible_calls_p): Likewise.
(vect_build_slp_tree_2): Likewise.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_get_operand_map): Put operand map
data here. Handle VIEW_CONVERT_EXPR, use else if, factor
out assertion.
(vect_get_and_check_slp_defs): Remove explicit VIEW_CONVERT_EXPR
handling here.
2026-04-28 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (construct_container): Remove redundant
early call to classify_argument. Recompute the classification
only when needed and assert that it succeeds.
(examine_argument): Change in_return parameter type to bool.
(function_arg_advance_64): Update call to examine_argument.
(function_arg_64): Update call to construct_container.
(function_value_64): Likewise.
(ix86_return_in_memory): Update call to examine_argument.
(ix86_gimplify_va_arg): Update calls to construct_container
and examine_argument.
2026-04-28 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv.h (OPTION_DEFAULT_SPECS): Specify -mcpu
instead of -march when --with-cpu is used.
2026-04-28 Bohan Lei <garthlei@linux.alibaba.com>
* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
Add simplifications for `(cmp (and/ior x C1) C2)`.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vect_estimate_min_profitable_iters):
Add comment about costing of prologue/epilogue.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vect_get_known_peeling_cost): Use
scalar_costs instead of guesstimating it.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vect_compute_single_scalar_iteration_cost):
Record stmt cost to vect_body.
2026-04-28 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_get_known_peeling_cost): Simplify API.
* tree-vect-loop.cc (vect_get_known_peeling_cost): Avoid
all the overhead of record_stmt_cost as we only are interested
in the overall sum of the included builtin_vectorization_cost
calls.
* tree-vect-data-refs.cc (vect_peeling_hash_get_lowest_cost):
Adjust.
(vect_enhance_data_refs_alignment): Likewise.
2026-04-28 Netanel Komm <netanelkomm@gmail.com>
PR tree-optimization/112659
PR tree-optimization/122996
* match.pd: Extend conditional addition pattern to handle
a third constant and uniform vectors.
2026-04-28 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.md (length attribute): Check CROSSING_JUMP_P
for jump instructions and use length 8 for crossing jumps.
(jump): Update comment to explain when long form is used.
2026-04-28 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/125039
* range-op-float.cc (operator_not_equal::fold_range): Call
empty_range_varying when not calling frelop_early_resolve.
2026-04-28 Jakub Jelinek <jakub@redhat.com>
* tree.cc (build_bitint_type): Allow build_bitint_type (1, 0).
(signed_or_unsigned_type_for): Call that for !unsignedp case
of BITINT_TYPE with bits 1.
2026-04-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/125036
* tree-ssa-loop-ivopts.cc (add_iv_candidate_for_doloop): Don't
assert on niniter being integer type. Convert to a full mode
integer type if non integer or non-full mode integer type.
2026-04-27 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/57650
* config/riscv/zicond.md: Generalize patterns which identify
a logical AND of an equality test and some other sCC insn to
handle more cases.
2026-04-27 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/aarch64-narrow-gp-writes.cc
(narrow_gp_writes::narrow_gp_writes): Remove redundant m_curr_insn
initialization.
(narrow_gp_writes::~narrow_gp_writes): Remove redundant m_curr_insn
de-initialization.
2026-04-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
* ext-dce.cc (promotion_candidate_info): New struct.
(copy_info): New struct.
(promotion_candidates, promotable_dests): New file-scope variables.
(consumed_by_candidate, promotion_copies): Likewise.
(ext_dce_try_promote_operation): New function to promote
sign/zero-extended arithmetic to wider mode.
(ext_dce_record_promotion_candidate): New function to record
promotion candidates for deferred chain analysis.
(ext_dce_promote_chained_candidates): New function to promote
only chained candidates.
(ext_dce_process_uses): Record candidates instead of promoting
immediately; propagate chain info through optimized copies.
(ext_dce_process_bb): Call ext_dce_promote_chained_candidates
after processing all insns in a block.
(ext_dce_init): Allocate chain detection bitmaps.
(ext_dce_finish): Free chain detection data structures.
2026-04-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
* ext-dce.cc (ext_dce_try_optimize_extension): Only remove
REG_EQUAL/EQUIV notes when validate_change succeeds.
2026-04-27 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/tuning_models/generic.h: Update br_mispredict_factor
to 7.
2026-04-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
* match.pd: Relax single_use for eq/ne when folded constant
is zero.
2026-04-27 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-lives.cc (clear_sparseset_regnos, regnos_in_sparseset_p):
Use set instead of dead_set.
2026-04-27 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-costs.cc (record_reg_classes): When calculating alt_cost use
the right cost of memory-reg move.
* ira-emit.cc (emit_move_list): Use load cost instead of store for
moving memory to reg.
2026-04-27 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-build.cc (add_to_conflicts): Use sizeof(ira_object_p)
instead of sizeof(ira_allocno_t) for allocations.
* ira-color.cc (print_hard_reg_set): Fix printing hard reg set.
* ira-emit.cc (allocno_last_set, allocno_last_set_check): Remove
unused static variables.
* ira.cc (combine_and_move_insns): Fix dead note recognition.
(ira_remove_insn_scratches): Use dump_file instead of
ira_dump_file.
* lra-constraints.cc (match_reload): Remove always true condition.
(undo_optional_reloads): Fix recognition of clobber for assertion.
2026-04-27 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/124886
* match.pd ((X * C1) + (X << C2) -> X * (C1 + (1 << C2))): New pattern.
2026-04-27 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/121268
* config/riscv/bitmanip.md: Add splitters to exploit identities
that relate subtraction and bitwise negation on 2's complement
arithmetic.
2026-04-27 Muhammad Kamran <muhammad.kamran@arm.com>
* doc/sourcebuild.texi (Scan object metadata with readelf): Document
object-readelf-attributes, object-readelf-attributes-not,
object-readelf-notes, and object-readelf-notes-not as regex-based
checks with optional target/xfail selectors.
2026-04-27 Netanel Komm <netanelkomm@gmail.com>
PR tree-optimization/93556
* gimple-fold.cc (gimple_fold_builtin_mempcpy): New function.
(gimple_fold_builtin): Handle BUILT_IN_MEMPCPY.
2026-04-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/125025
* tree-ssa-loop-niter.cc (number_of_iterations_ne): Avoid
negation of most negative signed integer.
(number_of_iterations_lt): Likewise.
2026-04-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/125019
* tree-vect-loop.cc (vectorizable_recurr): Properly guard
against hitting last stmt when searching for the insertion
place.
2026-04-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/110262
* match.pd (`signed < 0 ? positive : min<signed, positive>`): New
pattern.
2026-04-26 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Prerequisites): Use Binutils over binutils to
refer to that project.
(Downloading the source): Ditto.
(Configuration): Ditto.
(Building): Ditto.
(Specific): Ditto.
2026-04-26 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case VEC_SELECT>: Simplify a (non-identity) vec_select of a
vec_select.
2026-04-26 Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/124715
* match.pd (simpify pows): Check flag_errno_math before simplifying
pow(x,-1) -> 1/x when x could be zero.
2026-04-26 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/sse.md
(<avx512>_cmp<mode>3<mask_scalar_merge_name><round_saeonly_name>):
Change mode iterator from V48H_AVX512VL to VFH_AVX512VL and op3's
predicate from <cmp_imm_predicate> to const_0_to_31_operand.
(<avx512>_cmp<mode>3<mask_scalar_merge_name>): Change mode
iterator from VI12_AVX512VL to VI1248_AVX512VLBW.
(<avx512>_ucmp<mode>3<mask_scalar_merge_name>): Likewise.
2026-04-26 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/56096
* config/riscv/riscv.md: Add new patterns to optimize certain cases with
a logical AND feeding an equality test against zero.
2026-04-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124061
* tree-scalar-evolution.cc (interpret_rhs_expr): Use
INTEGRAL_NB_TYPE_P instead of comparing the code to INTEGER_TYPE.
* tree-ssa-loop-niter.cc (number_of_iterations_ne): Likewise.
(number_of_iterations_cltz): Likewise.
(number_of_iterations_exit_assumptions): Likewise.
* tree.h (INTEGRAL_NB_TYPE_P): New macro.
2026-04-25 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123904
* config/riscv/riscv.md (masking shifted value): New splitter to
optimize certain masking operations on shifted values.
2026-04-25 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123838
* config/riscv/riscv.md: Use splitters to simplify shifts where
the shift count is 31-N or 63-N.
2026-04-25 Pan Li <pan2.li@intel.com>
* config/riscv/predicates.md: Add ge to the swappable
cmp operator iterator.
* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Take
care of the swapped rtx code as well.
2026-04-25 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/64567
* match.pd (`cond (bit_and A IMM) (bit_or A IMM) A`): New
pattern.
(`cond (bit_and A IMM) (bit_and A ~IMM) A`): New pattern.
2026-04-25 Avinal Kumar <avinal.xlvii@gmail.com>
PR tree-optimization/122989
* tree-ssa-strlen.cc (get_string_length): Use
gimple_convert_to_ptrofftype and gimple_build instead of
convert_to_ptrofftype/force_gimple_operand_gsi/gimple_build_assign.
2026-04-25 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124984
* config/riscv/thead.cc (th_memidx_classify_address_index): Extract
constant multiplicand value from the right object.
2026-04-24 Hans-Peter Nilsson <hp@axis.com>
* doc/sourcebuild.texi (Effective-Target Keywords): Document 'sleep'.
2026-04-24 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/80770
* config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2): Always extend
out to a word and use a subreg lowpart extraction to get the right bits.
(extend<SHORT:mode><SUPERQI:mode>2): Similarly.
2026-04-24 Carter Rennick <carter.rennick@gmail.com>
PR target/120144
* config/mips/mips.h (MAX_FIXED_MODE_SIZE): Remove.
2026-04-24 Eikansh Gupta <eikansh.gupta@oss.qualcomm.com>
PR tree-optimization/123966
* tree-ssa-dce.cc (mark_stmt_if_obviously_necessary):
Don't mark a relaxed atomic load with no LHS as necessary.
2026-04-24 Milan Tripkovic <Milan.Tripkovic@rt-rk.com>
* config/riscv/riscv.cc (riscv_sched_adjust_cost):Enable
TARGET_ADJUST_LMUL_COST for spacemit_x60.
* config/riscv/spacemit-x60.md: Add vector pipeline model
for Spacemit-X60.
Co-authored-by: Dusan Stojkovic <Dusan.Stojkovic@rt-rk.com>
Co-authored-by: Nikola Ratkovac <Nikola.Ratkovac@rt-rk.com>
2026-04-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_create_new_slp_node): Assert that 'code'
is either ERROR_MARK or VEC_PERM_EXPR. Document properly.
* tree-vect-slp-patterns.cc (vect_build_swap_evenodd_node):
Use lane_permutation_t.
(vect_build_combine_node): Likewise. Pass VEC_PERM_EXPR
as code.
2026-04-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Do not pass
vector type to costing.
2026-04-24 Raphael Zinsly <rzinsly@qti.qualcomm.com>
PR target/123839
* config/riscv/riscv-v.cc (shuffle_slide_patterns): Use a
vslideup+vslidedown pair rather than a vcompressed based
sequence.
2026-04-24 Jakub Jelinek <jakub@redhat.com>
PR target/124133
* config/rs6000/rs6000-c.cc (c_fold_convert): New function.
(c_fold_build2_loc): Likewise.
(fully_fold_convert): Use c_fold_convert instead of fold_convert.
(altivec_build_resolved_builtin): Likewise. Use c_fold_build2_loc
instead of fold_build2.
(resolve_vec_mul, resolve_vec_adde_sube, resolve_vec_addec_subec):
Use c_fold_build2_loc instead of fold_build2_loc.
(resolve_vec_splats, resolve_vec_extract): Use c_fold_convert instead
of fold_convert.
(resolve_vec_insert): Use c_fold_build2_loc instead of fold_build2.
(altivec_resolve_overloaded_builtin): Use c_fold_convert instead
of fold_convert.
2026-04-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
PR tree-optimization/124988
* gimple-lower-bitint.cc (bitint_large_huge::finish_arith_overflow):
Handle bitint_extend.
(bitint_large_huge::lower_addsub_overflow): Fix up comment spelling.
For bitint_extended extend the partial limb if any.
2026-04-24 H.J. Lu <hjl.tools@gmail.com>
PR target/125009
* config/i386/i386-features.cc (ix86_place_single_vector_set):
Support CONST_VECTOR load no larger than integer register.
(ix86_broadcast_inner): Use inner mode as the scalar mode for
CONST_VECTOR load source.
(pass_x86_cse::x86_cse): Generate CONST_VECTOR broadcast source
for CONST_VECTOR load no larger than integer register.
2026-04-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/124843
* tree-vect-patterns.cc (vect_recog_bool_pattern): Recognize
BIT_NOT_EXPR of scalar bools and rewrite with BIT_XOR_EXPR.
2026-04-24 Richard Biener <rguenther@suse.de>
* tree-vect-data-refs.cc (vect_duplicate_ssa_name_ptr_info):
Create points-to info from decl-based accesses.
(vect_create_addr_base_for_vector_ref): Adjust.
(vect_create_data_ref_ptr): Likewise.
(bump_vector_ptr): Likewise.
2026-04-24 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (_stmt_vec_info::slp_vect_pattern_only_p):
Remove.
(STMT_VINFO_SLP_VECT_ONLY_PATTERN): Likewise.
* tree-vectorizer.cc (vec_info::new_stmt_vec_info): Do not
initialize STMT_VINFO_SLP_VECT_ONLY_PATTERN.
* tree-vect-loop.cc (vect_analyze_loop_2): Nothing to do
for SLP pattern stmts that are not reachable from scalar
stmts anyway. Remove dead code.
* tree-vect-slp-patterns.cc (complex_pattern::build): Do not
set STMT_VINFO_SLP_VECT_ONLY_PATTERN.
(addsub_pattern::build): Likewise.
* tree-vect-slp.cc (vect_free_slp_tree): Remove dead code.
2026-04-24 Richard Biener <rguenther@suse.de>
* tree-vect-slp-patterns.cc (complex_pattern::build):
Add pattern for the original stmt, do not set
STMT_VINFO_REDUC_DEF.
(addsub_pattern::build): Likewise.
2026-04-24 Netanel Komm <netanelkomm@gmail.com>
PR tree-optimization/122996
* match.pd (x != CST1 ? x + CST2 : 0 -> x + CST2): New pattern.
2026-04-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/124947
* tree-ssa-loop-ivopts.cc (may_eliminate_iv): Do not use
a candidate that involves undefs.
2026-04-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/124946
* tree-vect-loop.cc (vect_emulate_mixed_dot_prod): Perform the
constant biasing in an unsigned type.
2026-04-23 Michiel Derhaeg <Michiel.Derhaeg@synopsys.com>
* config/riscv/pipeline-checker: Filter tuneless insn types.
2026-04-23 Yuxuan Chen <i@yuxuan.ch>
PR c++/107187
* doc/extend.texi: Document __attribute__((trivial_abi)).
2026-04-23 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/riscv/bitmanip.md (<bitmanip_optab>si3): Add
SUBREG_PROMOTED annotation to lowpart result.
2026-04-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/124029
* config/riscv/riscv.cc (riscv_rtx_costs): Improve costing of COMPARE
nodes.
2026-04-23 Eric Botcazou <ebotcazou@adacore.com>
* config/i386/cygming.h (STACK_CHECK_PROTECT): Define.
2026-04-23 H.J. Lu <hjl.tools@gmail.com>
PR target/124994
* config/i386/i386-features.cc (x86_cse::gate): Drop TARGET_SSE2.
2026-04-23 Bohan Lei <garthlei@linux.alibaba.com>
* config/riscv/riscv.cc (vxrm_unknown_p): Remove `CALL_P` check
2026-04-22 Sam James <sam@gentoo.org>
* ipa-prop.cc (param_type_may_change_p): Fix comment typo.
2026-04-22 Sam James <sam@gentoo.org>
* config/i386/i386.cc (ix86_get_callcvt): Say 'regparm' in comment,
not 'regparam'.
2026-04-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cfghooks.cc (make_forwarder_block): New data argument,
pass it down to redirect_edge_p.
* cfghooks.h (make_forwarder_block): Add void* argument.
* cfgloop.cc (mfb_reis_set): Remove.
(mfb_redirect_edges_in_set): Add new data argument.
Use it instead of mfb_reis_set.
(form_subloop): Create a local variable instead of
mfb_areis_set. Update call to make_forwarder_block.
(merge_latch_edges): Likewise.
* cfgloopmanip.cc (mfb_kj_edge): Remove.
(mfb_keep_just): Add new data argument.
Use it instead of mfb_kj_edge.
(create_preheader): Use local variable instead of
mfb_kj_edge. Update call to make_forwarder_block.
* cfgloopmanip.h (mfb_keep_just): Add void* argument.
* tree-cfgcleanup.cc (mfb_keep_latches): Add unused void* arugment.
(cleanup_tree_cfg_noloop): Update call to make_forwarder_block.
* tree-ssa-threadupdate.cc
(fwd_jt_path_registry::thread_through_loop_header): Use local
variable instead of mfb_kj_edge. Update call to make_forwarder_block.
2026-04-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cfghooks.cc (make_forwarder_block): Remove new_bb_cbk argument.
* cfghooks.h (make_forwarder_block): Remove last argument.
* cfgloop.cc (form_subloop): Update call to make_forwarder_block.
(merge_latch_edges): Likewise.
* cfgloopmanip.cc (create_preheader): Likewise.
* tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Likewise.
* tree-ssa-threadupdate.cc
(fwd_jt_path_registry::thread_through_loop_header): Likewise.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi (-ffunction-cse): Add missing full stop.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi (-Wduplicate-decl-specifier): Say 'a duplicate'.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi (-Waddress): Drop unnecessary 'warning'.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi: Fix whitespace.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi: Write 'In C,' and 'In C++,' with a comma
consistently.
2026-04-22 Sam James <sam@gentoo.org>
* doc/invoke.texi (-Walloca): Simplify phrasing.
(-Walloca-larger-than=-): Ditto.
2026-04-22 Alice Carlotti <alice.carlotti@arm.com>
* mode-switching.cc (optimize_mode_switching): Add dump output.
2026-04-22 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64.cc (aarch64_start_call_args): Extend
comment.
2026-04-22 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64.cc (aarch64_mode_confluence): Fix
comment typo.
* target.def (mode_switching): Fix incorrect variable names in
documentation.
* doc/tm.texi: Regenerate.
2026-04-22 Alice Carlotti <alice.carlotti@arm.com>
PR target/119210
* config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
Add PSTATE.ZA enablement, and zero it if already enabled.
2026-04-22 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sme.md (aarch64_sme_write_zt): Add
ZTO_REGNUM use and make unspec non-volatile.
2026-04-22 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/124908
* config/aarch64/aarch64-sve-builtins-base.cc
(svld1rq_impl::fold): When the SVE vector length equals the
quadword width, emit VIEW_CONVERT_EXPR instead of VEC_PERM_EXPR.
2026-04-22 Richard Earnshaw <rearnsha@arm.com>
PR target/124933
* config/arm/constraints.md (Uj): Allow offset addressing for
all targets, only allow Neon addressing when we have both Neon
and FP16INST.
* config/arm/vfp.md (mov<mode>_vfp_<mode>16): Only use vld1/vst1
when the pattern needs address write-back.
2026-04-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/124971
* gensupport.cc (convert_syntax): Fix up // comment handling.
2026-04-21 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/120189
* doc/gm2.texi (Building a shared library): Replace
constant string with DEFAULT_RUNTIME_MODULE_OVERRIDE.
2026-04-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* gimple-lower-bitint.cc (bitint_large_huge::lower_muldiv_stmt):
Extend the padding bits not just for unsigned MULT_EXPR but for any
TYPE_OVERFLOW_WRAPS MULT_EXPR and signed TYPE_OVERFLOW_WRAPS division.
2026-04-21 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124941
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Use build_bitint_type
rather than build_nonstandard_integer_type for
maxsizei larger than MAX_FIXED_MODE_SIZE.
2026-04-21 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/120189
* doc/gm2.texi (Building a shared library): Rewrite.
2026-04-20 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* gimple-lower-bitint.cc (bitint_large_huge::lower_shift_stmt): In the
RSHIFT_EXPR case, use p2 in two LE_EXPR conditions rather than just
one. In LSHIFT_EXPR case, use signed RSHIFT_EXPR instead of unsigned.
(bitint_large_huge::lower_muldiv_stmt): For unsigned MULT_EXPR with
bitint_extended if prec is not multiple of limb_prec, clear padding
bits after libgcc call.
(bitint_large_huge::lower_float_conv_stmt): Use signed RSHIFT_EXPR
instead of unsigned.
2026-04-20 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* gimple-lower-bitint.cc (bitint_precision_kind): Assert the current
assumptions, that bitint_ext_full for abi_limb_prec > limb_prec is
supported only when abi_limb_prec is limb_Prec * 2 and it is not
big endian in that case.
(bitint_large_huge::lower_mergeable_stmt): Don't set separate_ext
fir bitint_ext_full for bit-field stores. Guard the condition
on an extra limb of padding bits to be extended rather than including
earlier extensions in that too. If already sign extending before
and type is unsigned, set zero_ms_limb instead and later handle it.
(bitint_large_huge::lower_shift_stmt): Handle bitint_ext_full.
2026-04-20 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/aarch64-narrow-gp-writes.cc (narrow_dimode_src): Remove
redundant checks. Don't recurse when an operand remains DImode.
(narrow_gp_writes::optimize_compare_arith_insn): Use
HOST_WIDE_INT_PRINT_HEX.
(narrow_gp_writes::optimize_single_set_insn): Likewise.
2026-04-19 Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/124643
* cse.cc (canon_reg): Handle and canonicalize subregs.
2026-04-18 Richard Sandiford <rdsandiford@googlemail.com>
* config/aarch64/aarch64.md (SME_STATE_REGNUM): Fix a comment typo.
2026-04-18 Gopi Kumar Bulusu <gopi@sankhya.com>
PR target/103383
* config/microblaze/microblaze.md: bswaphi2: (set_attr length 8)
2026-04-17 Jonathan Wakely <jwakely@redhat.com>
PR c/84717
* doc/extend.texi (Decimal Float): Document d and D suffixes.
Fix index entries for decimal float suffixes.
2026-04-17 Jan Hubicka <hubicka@ucw.cz>
PR ipa/120098
* ipa-polymorphic-call.cc (polymorphic_ctor_dtor_p): Remove
check for pure/const flags
2026-04-17 Jan Hubicka <hubicka@ucw.cz>
PR ipa/120098
* ipa-devirt.cc (odr_type_p): Add no_derived_construction_vtables
(odr_types_ptr): Move ahead in file.
(odr_types): Move ahead in file.
(anonymous_construction_vtable_p): New function.
(mark_derived_construction_vtables): New function.
(construction_vtable_hook): New function.
(type_possibly_instantiated_p): Watch for construction vtables.
2026-04-17 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx-sm.def: Add '50'.
* config/nvptx/nvptx-gen.h: Regenerate.
* config/nvptx/nvptx-gen.opt: Likewise.
* config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): Adjust.
* config/nvptx/nvptx.opt (-march-map=sm_50): Likewise.
* config.gcc: Likewise.
* doc/invoke.texi (Nvidia PTX Options): Document '-march=sm_50'.
* config/nvptx/gen-multilib-matches-tests: Extend.
2026-04-17 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx-opts.h (enum ptx_version): Add
'PTX_VERSION_4_0'.
* config/nvptx/nvptx.cc (ptx_version_to_string)
(ptx_version_to_number): Adjust.
* config/nvptx/nvptx.h (TARGET_PTX_4_0): New.
* config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue'
'4.0' for 'PTX_VERSION_4_0'.
* doc/invoke.texi (Nvidia PTX Options): Document '-mptx=4.0'.
2026-04-17 Tamar Christina <tamar.christina@arm.com>
PR middle-end/124900
* gimple-crc-optimization.cc (crc_optimization::optimize_crc_loop): Do
not expand to table when compiling for size.
(class crc_optimization): Update prototype of optimize_crc_loop to
include loop.
(crc_optimization::execute): Pass loop to optimize_crc_loop.
2026-04-16 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm-cpus.in (cortex-m85): Allow +cdecp<n>.
* doc/invoke.texi: Document this
2026-04-16 Jakub Jelinek <jakub@redhat.com>
PR target/124565
* config/stormy16/stormy16.cc (xstormy16_build_builtin_va_list): Set
TREE_PUBLIC on type_decl.
* config/xtensa/xtensa.cc (xtensa_build_builtin_va_list): Likewise.
2026-04-16 Tobias Burnus <tburnus@baylibre.com>
PR target/124897
* doc/install.texi (amdgcn-amdhsa): Fix required LLVM version for
default multilib.
2026-04-16 Richard Biener <rguenther@suse.de>
PR middle-end/124877
* calls.cc (initialize_argument_information): Compute
signedness of the formal argument type before applying
PROMOTE_PROTOTYPES promotion. Also apply promotion to
a smaller than int integer first member type of a
transparent union.
* target.def (promote_prototypes): Update documentation.
* doc/tm.texi: Re-generate.
2026-04-16 Jakub Jelinek <jakub@redhat.com>
PR target/124892
* config/i386/i386.md (clz<mode>2_lzcnt_nf,
<lt_zcnt>_<mode>_nf, popcount<mode>2_nf): Emit explicit
set of (match_dup 0) to (const_int 0) without flags clobber instead of
using ix86_expand_clear.
2026-04-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124891
* tree-ssa-propagate.cc
(substitute_and_fold_dom_walker::before_dom_children): Call update_stmt
in the did_replace case before calling fold_stmt.
2026-04-15 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/122976
* tree-sra.cc (path_comparable_for_same_access): Return false if the
base is a MEM_REF with a different underlying type.
2026-04-15 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123635
* target.h (enum bitint_ext): New.
(struct bitint_info): Change extend type from bool to enum bitint_ext
and document it.
* gimple-lower-bitint.cc (bitint_extended): Change type from bool
to enum bitint_ext.
(bitint_precision_kind): Change bitint_extended to bitint_ext_partial
from bitint_ext_full if limb_mode is the same as abi_limb_mode.
(bitint_large_huge::limb_access_type): For
bitint_extended == bitint_ext_full allow access to the most
significant limb solely with padding bits if present.
(bitint_large_huge::lower_mergeable_stmt): Handle
bitint_extended == bitint_ext_full extension if needed.
(bitint_large_huge::lower_muldiv_stmt): Likewise.
(bitint_large_huge::lower_float_conv_stmt): Likewise.
* config/aarch64/aarch64.cc (aarch64_bitint_type_info): Set
info->extended to bitint_ext_undef rather than false.
* config/arm/arm.cc (arm_bitint_type_info): Set
info->extended to bitint_ext_full rather than true.
* config/i386/i386.cc (ix86_bitint_type_info): Set
info->extended to bitint_ext_undef rather than false.
* config/loongarch/loongarch.cc (loongarch_bitint_type_info): Set
info->extended to bitint_ext_partial rather than true.
* config/riscv/riscv.cc (riscv_bitint_type_info): Set
info->extended to bitint_ext_full rather than true.
* config/s390/s390.cc (s390_bitint_type_info): Likewise.
2026-04-15 Jason Merrill <jason@redhat.com>
PR c++/117133
PR c++/124768
PR c++/124773
* doc/trouble.texi (Linkage in Anonymous Namespaces): Remove.
2026-04-15 H.J. Lu <hjl.tools@gmail.com>
* config/i386/i386.cc
(x86_64_preserve_none_int_parameter_registers): Replace
ix86_function_value_regno_p with ix86_function_arg_regno_p in
comments.
2026-04-14 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-cores.def (armagicpu): New.
* config/aarch64/aarch64-tune.md: Renegerate
* doc/invoke.texi: Document it.
2026-04-14 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/124809
* value-relation.cc (equiv_oracle::equiv_oracle): Allocate lhs
equivalence bitmap.
(relation_oracle::record): Check if LHS has already created an
equivalence record.
* value-relation.h (relation_oracle::relation_oracle): New.
(relation_oracle::m_lhs_equiv_set_p): New.
2026-04-14 Richard Earnshaw <rearnsha@arm.com>
PR target/123102
* config/arm/arm.md (*cmp_ite0): Apply stricter checks on the
comparison mode.
(*cmp_ite1, *cmp_and, *cmp_ior): Likewise.
2026-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/124777
* ipa-cp.h (ipacp_value_safe_for_type): Declare.
* ipa-cp.cc (ipacp_value_safe_for_type): Make public.
* ipa-prop.cc (ipa_set_jf_cst_copy): Fix comment.
(ipa_convert_prop_cst_jf): New function.
(update_jump_functions_after_inlining): Handle the constant to
pass-through case by calling ipa_convert_prop_cst_jf.
2026-04-14 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/aarch64.opt.urls: Regenerate.
2026-04-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/124875
* tree-ssa-pre.cc (prefer): Also compare TBAA set and base_set.
Refactor computing the final prefered expression, do early outs
and allow same prefered expressions.
(sorted_array_from_bitmap_set): Fix thinko that prevented
the last expression in the set of being excluded.
2026-04-14 Soumya AR <soumyaa@nvidia.com>
Kyrylo Tkachov <ktkachov@nvidia.com>
* config.gcc: Add aarch64-narrow-gp-writes.o.
* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert
pass_narrow_gp_writes before pass_cleanup_barriers.
* config/aarch64/aarch64-protos.h (make_pass_narrow_gp_writes): Declare.
* config/aarch64/aarch64-tuning-flags.def
(AARCH64_EXTRA_TUNING_OPTION): Add NARROW_GP_WRITES.
* config/aarch64/aarch64.opt (mnarrow-gp-writes): New option.
* config/aarch64/t-aarch64: Add aarch64-narrow-gp-writes.o rule.
* config/aarch64/tuning_models/olympus.h: Add
AARCH64_EXTRA_TUNE_NARROW_GP_WRITES to tune_flags.
* doc/invoke.texi: Document -mnarrow-gp-writes.
* config/aarch64/aarch64-narrow-gp-writes.cc: New file.
2026-04-14 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124826
* gimple-lower-bitint.cc (bitint_large_huge::handle_load): Look through
BIT_FIELD_REF with zero bit offset.
2026-04-14 Jakub Jelinek <jakub@redhat.com>
* cgraphunit.cc (process_symver_attribute): Fix comment typo,
bintuils -> binutils.
2026-04-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/124868
* gimple-ssa-isolate-paths.cc (handle_return_addr_local_phi_arg):
Do not diagnose returns in blocks not dominated by the PHI.
(find_implicit_erroneous_behavior): Do two sweeps over PHIs,
first for NULL dereferences and then for local address returns.
2026-04-14 Avinash Jayakar <avinashd@linux.ibm.com>
Revert:
2026-04-07 Avinash Jayakar <avinashd@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add
logic to handle __builtin_ppc_atomic_cas_local.
* config/rs6000/rs6000-builtins.def: New builtins for
__builtin_ppc_atomic_cas_local with types.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin):
Handle builtins with up to 6 arguments.
* config/rs6000/rs6000-overload.def: Overload builtin for
signed/unsiged char, short, int, long, __int128.
* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap):
Add additional parameter 'local' to the prototype.
* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass
new parameter to generate load-locked instruction.
(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
emit_load_locked() with additional parameter value of EH bit.
(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL
template. Specify EH bit in the larx instruction.
(load_locked<QHI:mode>_si): Likewise.
(load_lockedpti): Likewise.
(load_lockedti): Add new operand in RTL template. Pass EH bit to
gen_load_lockedpti().
(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
rs6000_expand_atomic_compare_and_swap.
(atomic_compare_and_swap_local<mode>): New define_expand.
2026-04-14 H.J. Lu <hjl.tools@gmail.com>
PR target/124876
* config/i386/i386.cc (ix86_zero_call_used_regs): Zero ZMM16-31
if needed.
2026-04-13 Surya Kumari Jangala <jskumari@linux.ibm.com>
Revert:
2025-06-30 Peter Bergner <bergner@linux.ibm.com>
PR target/109116
* config/rs6000/mma.md (unspec): Delete UNSPEC_MMA_EXTRACT.
(vsx_disassemble_pair): Expand into a vector register sized subreg.
(mma_disassemble_acc): Likewise.
(*vsx_disassemble_pair): Delete.
(*mma_disassemble_acc): Likewise.
2026-04-13 Josef Melcr <josef.melcr@suse.com>
PR ipa/124700
* cgraph.cc (cgraph_node::is_clone_of): New method, determines
whether a node is a descendant of another in the clone tree.
* cgraph.h (struct cgraph_node): Add decl of is_clone_of.
* cgraphbuild.cc (mark_address): Fix reference creation for
cloned callback functions.
2026-04-13 Hu, Lin1 <lin1.hu@intel.com>
PR target/124710
* config/i386/sse.md (iptrps2qq): New mode attribute for
ps2qq Intel syntax memory operand size override.
(avx10_2_vcvttps2<sat_cvt_sign_prefix>qqs<mode><mask_name><round_saeonly_name>):
Use %<iptrps2qq>1 in Intel syntax to emit qword ptr for V2DI (128-bit)
memory operands.
(avx10_2_vcvttsd2<sat_cvt_sign_prefix>sis<mode><round_saeonly_name>):
Use %q1 in Intel syntax to emit qword ptr for scalar double memory
operands.
(avx10_2_vcvttss2<sat_cvt_sign_prefix>sis<mode><round_saeonly_name>):
Use %k1 in Intel syntax to emit dword ptr for scalar single memory
operands.
2026-04-11 Christopher Albert <albert@tugraz.at>
PR fortran/93554
* omp-expand.cc (expand_oacc_for): Relax entry_bb and cont_bb
assertions to allow intermediate blocks from finalization code.
Remove exit_bb predecessor count assertion.
2026-04-10 Jakub Jelinek <jakub@redhat.com>
PR middle-end/124827
* gimple-ssa-warn-access.cc (xchg_models): Remove.
(pass_waccess::check_atomic_builtin): Fix up sucs_arg for
BUILT_IN_ATOMIC_EXCHAGE_* and use all_models instead of xchg_models.
Handle BUILT_IN_TSAN_ATOMIC*. Formatting fixes.
2026-04-10 Dhruv Chawla <dhruvc@nvidia.com>
* configure: Regenerate.
2026-04-10 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Set
__riscv_v_intrinsic to v1.0.
* doc/extend.texi (RISC-V Vector Intrinsics): Document the
ratified v1.0 RVV intrinsic specification and update the link.
2026-04-09 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/124773
* doc/trouble.texi (Linkage in Anonymous Namespaces): New section.
2026-04-09 Alex Coplan <alex.coplan@arm.com>
PR target/122483
* config/aarch64/t-aarch64: Replace instances of TM_H with
TARGET_H where appropriate, add missing dependency on TARGET_H
for aarch64-early-ra.cc.
2026-04-09 Dhruv Chawla <dhruvc@nvidia.com>
* Makefile.in (AFDO_PROFILER): New variable.
(PERF): Likewise.
* config/aarch64/gcc-auto-profile: Detect and use ARM SPE events when
invoking perf record.
* configure: Regenerate.
* configure.ac: Detect whether build has perf utility available and
check for ARM SPE-based profiling support when building on AArch64.
2026-04-09 Richard Biener <rguenther@suse.de>
* coverage.cc (coverage_init): Do not call read_counts_file
if flag_auto_profile.
2026-04-09 Christoph Müllner <christoph.muellner@vrull.eu>
PR target/124818
* config/riscv/riscv.cc (synthesize_ior_xor): Do not treat
TARGET_ZBKB as sufficient for single-bit immediate IOR/XOR.
2026-04-09 Tamar Christina <tamar.christina@arm.com>
* doc/params.texi: Replace param_vect_scalar_cost_multiplier with
param_vect_allow_possibly_not_worthwhile_vectorizations
* params.opt: Likewise.
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Likewise.
* config/riscv/riscv.cc (riscv_override_options_internal): Likewise.
* tree-vect-loop.cc (vect_estimate_min_profitable_iters): Likewise.
* tree-vect-slp.cc (vect_bb_vectorization_profitable_p): Likewise.
(vect_slp_region): Likewise.
2026-04-09 Xi Ruoyao <xry111@xry111.site>
PR target/105192
* ifcvt.cc (find_if_header): Don't attempt to use ctrap expander
after reload.
2026-04-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/124810
* cfgloopmanip.cc (fix_loop_placements): Do not stop
iterating when an inner loop didn't get re-parented.
Compute the outermost loop we have to consider re-parenting.
2026-04-08 Prathamesh Kulkarni <prathameshk@nvidia.com>
* auto-profile.cc (function_instance::merge): Set other->timestamp() if it's
lesser than timestamp() and greater than zero or if timestamp() is zero.
2026-04-07 H.J. Lu <hjl.tools@gmail.com>
PR target/124759
PR target/124789
* config/i386/i386.cc (ix86_need_alignment_p_2): New function.
Exclude memory with SYMBOLIC_CONST.
(ix86_need_alignment_p_1): Call ix86_need_alignment_p_2.
(ix86_find_max_used_stack_alignment): Restore
hard_stack_slot_access handling.
2026-04-07 H.J. Lu <hjl.tools@gmail.com>
* config/i386/i386.cc (ix86_need_alignment_p_1): Replace
GET_MODE_ALIGNMENT with MEM_ALIGN.
2026-04-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/124802
* tree-vect-slp-patterns.cc (vect_match_expression_p): Fail
for SLP_TREE_PERMUTE_P.
2026-04-07 Sandra Loosemore <sloosemore@baylibre.com>
PR sanitizer/124170
* doc/invoke.texi (Option Summary) <Linker Options>: Add
-static-libhwasan and fix alphabetization of similar options.
(Link Options): Likewise.
* common.opt.urls: Regenerated.
2026-04-07 Sandra Loosemore <sloosemore@baylibre.com>
PR other/124784
* regenerate-opt-urls.py (canonicalize_option_name): Remove one
of the dashes from option names starting with two dashes.
(test_parse_option_index): Add a self-test for this.
* common.opt.urls: Regenerated.
* config/picolibc.opt.urls: Regenerated.
2026-04-07 Peter Damianov <peter0x44@disroot.org>
* config/mingw/t-cygming: Remove obsolete STMP_FIXINC
override.
2026-04-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/124743
* tree-vect-slp.cc (vect_schedule_slp_node): Schedule
loop invariant operations in the loop preheader.
2026-04-07 Avinash Jayakar <avinashd@linux.ibm.com>
Surya Kumari Jangala <jskumari@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add
logic to handle __builtin_ppc_atomic_cas_local.
* config/rs6000/rs6000-builtins.def: New builtins for
__builtin_ppc_atomic_cas_local with types.
* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin):
Handle builtins with up to 6 arguments.
* config/rs6000/rs6000-overload.def: Overload builtin for
signed/unsiged char, short, int, long, __int128.
* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap):
Add additional parameter 'local' to the prototype.
* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass
new parameter to generate load-locked instruction.
(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
emit_load_locked() with additional parameter value of EH bit.
(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL
template. Specify EH bit in the larx instruction.
(load_locked<QHI:mode>_si): Likewise.
(load_lockedpti): Likewise.
(load_lockedti): Add new operand in RTL template. Pass EH bit to
gen_load_lockedpti().
(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
rs6000_expand_atomic_compare_and_swap.
(atomic_compare_and_swap_local<mode>): New define_expand.
2026-04-06 Nathaniel Shead <nathanieloshead@gmail.com>
PR libstdc++/124268
* doc/invoke.texi: Note that -Wexpose-global-module-tu-local
also applies to 'export using' declarations.
2026-04-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* doc/install.texi (Specific, amd64-*-solaris2*, i?86-*-solaris2*)
(sparc-sun-solaris2*, sparc64-*-solaris2*, sparcv9-*-solaris2*)
(x86_64-*-solaris2*): Remove. Fold into ...
(Specific, *-*-solaris2*): ... this.
Rewrite.
2026-04-04 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Picolibc Options): Copy-edit for markup, use
of proper names, etc.
2026-04-04 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (GCC Command Options): Move Picolibc Options
section to Target-Specific Options.
(Option Summary): Likewise.
2026-04-04 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Common Attributes): Fix cross-reference for
renamed "Submodel Options" -> "Target-Specific Options".
* doc/invoke.texi (Invoking GCC): Likewise for the menu.
(Option Summary): Likewise for the use here.
(Submodel Options): Rename to Target-Specific Options. Leave
an anchor with the old name. Add better index entries. Rewrite
introductory text.
(Precompiled Headers): Fix another cross-reference.
2026-04-04 Sandra Loosemore <sloosemore@baylibre.com>
PR target/107337
* doc/invoke.texi (x86 Options): Add CX16 feature to nocona,
alderlake, arrowlake, arrowlake-s, pantherlake, novalake,
bonnell, sierraforest, grandridge, clearwaterforest, and amdfam10
family processors.
2026-04-04 Richard Biener <rguenther@suse.de>
* doc/gccint.texi: Add named pattern index with @mdindex.
* doc/md.texi (Standard Pattern Names For Generation): Split
table into two using subsections, splitting out vectorizer
related standard patterns. Use @mdindex for all standard
pattern names.
2026-04-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_legitimize_address):
Add code to legitimize the displacement of 64 kilobytes before and
after using two ADDMI instructions.
2026-04-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (negsf2):
Change define_insn to define_insn_and_split, and replace the
corresponding output template with the split pattern.
2026-04-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (TARGET_DIFFERENT_ADDR_DISPLACEMENT_P):
Remove.
2026-04-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (smalloffset_mem_p):
Rename it to smalloffset_address_p and remove the result check
of MEM_P().
(constantpool_address_p): Change from static scope to global.
* config/xtensa/xtensa-protos.h (smalloffset_mem_p):
Rename it to smalloffset_address_p.
(constantpool_address_p): New function prototype.
* config/xtensa/constraints.md (R):
Change the call in (match_test "...") from smalloffset_mem_p()
to smalloffset_address_p().
(T, U): Change the call in (match_test "...") from
constantpool_mem_p() to constantpool_address_p().
2026-04-03 Sandra Loosemore <sloosemore@baylibre.com>
PR c/123234
* doc/extend.texi (Decimal Float): Clarify that GCC really does
support only the older N1312 draft as documented here, not the
standard C23 functionality yet.
2026-04-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124754
* tree-ssa-strlen.cc (strlen_pass::handle_builtin_strcpy): Make
sure both get_stridx calls are done before first get_strinfo call.
(strlen_pass::handle_builtin_memcpy): Likewise.
(strlen_pass::handle_builtin_strcat): Likewise.
2026-04-03 Sandra Loosemore <sloosemore@baylibre.com>
PR debug/94491
* doc/invoke.texi (Debugging Options): Explicitly document what
-g2 does instead of just saying it's the default.
2026-04-03 Sandra Loosemore <sloosemore@baylibre.com>
PR other/94182
* doc/implement-c.texi (Characters implementation): Add
cross-reference to more detailed discussion about signedness.
* doc/invoke.texi (C Dialect Options): Combine -fsigned-char
and -funsigned-char table entries since the following discussion
applies to both. Add an anchor so other things can point at it.
(Warning Options): Add cross-references to the above two places.
Clarify that the warning is given regardless of whether char is
signed or unsigned.
2026-04-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124746
* tree-ssa-phiprop.cc (propagate_with_phi): Treat
and aggregate copy as it is a trapping load.
2026-04-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-phiprop.cc (propagate_with_phi): Move the
check for load from ptr before the checks of domination.
2026-04-02 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-protos.h
(loongarch_parse_fmv_features): Modify parameter type.
* config/loongarch/loongarch-target-attr.cc
(loongarch_parse_fmv_features): Some errors have been
changed to warnings.
* config/loongarch/loongarch.cc
(loongarch_process_target_version_attr): Update parameters.
(loongarch_check_target_clone_version): Likewise.
(loongarch_option_same_function_versions): Likewise.
(TARGET_CHECK_TARGET_CLONE_VERSION): Define.
2026-04-01 Tamar Christina <tamar.christina@arm.com>
Roger Sayle <roger@nextmovesoftware.com>
PR target/123238
* config/aarch64/aarch64.cc (aarch64_rtx_costs) <case NE/EQ>:
Provide improved costs for scalar and vector comparisons.
2026-04-01 Roger Sayle <roger@nextmovesoftware.com>
PR target/123238
* expr.cc (convert_tree_comp_to_rtx): Make global.
* expr.h (convert_tree_comp_to_rtx): Prototype here.
* internal-fn.cc (expand_vec_cond_mask_optab_fn): Use rtx_costs
to determine whether swapping operands would result in better
code.
* config/i386/i386-expand.cc (ix86_expand_int_vec_cmp): On
AVX512 targets use a ternlog instead of a comparison to negate
the mask (requires one instruction instead of two).
* config/i386/i386.cc (ix86_rtx_costs): Refactor code for UNSPEC.
Provide costs for UNSPEC_BLENDV and UNSPEC_MOVMSK. Provide
costs for comparison operators of integer vector modes.
2026-04-01 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/124696
* lra-constraints.cc (simplify_operand_subreg): Reload
paradoxical subreg only if it requires more than one hard reg.
2026-04-01 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (print_operand): Use fputs instead of
fprintf.
2026-04-01 Sandra Loosemore <sloosemore@baylibre.com>
PR preprocessor/70917
* doc/invoke.texi (Environment Variables): Clarify that LC_ALL,
LC_CTYPE, LC_MESSAGES, and LANG affect only diagnostics and
informational output from GCC, not the encodings of input and
output files. Remove separate bit-rotten entry for LANG.
2026-04-01 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124742
* tree-ssa-forwprop.cc (optimize_aggr_zeroprop): Exit
if the vdef on the stmt is NULL.
2026-04-01 H.J. Lu <hjl.tools@gmail.com>
PR middle-end/124697
* function.cc (assign_parm_adjust_stack_rtl): Force a local copy
if the current alignment is less than the minimum of
BIGGEST_ALIGNMENT and MAX_SUPPORTED_STACK_ALIGNMENT.
2026-04-01 Richard Biener <rguenther@suse.de>
Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/124634
* doc/ifn.texi: New file.
* doc/gccint.texi: Include ifn.texi.
* Makefile.in (TEXI_GCCINT_FILES): Add ifn.texi.
2026-04-01 Sandra Loosemore <sloosemore@baylibre.com>
PR c/61896
* doc/cppopts.texi (-finput-charset=): Remove long-obsolete
locale discussion. Document behavior about ill-formed inputs.
2026-04-01 Sandra Loosemore <sloosemore@baylibre.com>
* doc/poly-int.texi: Add copyright notice.
* doc/specs.texi: Likewise.
2026-03-31 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa-dse.cc (compute_trims): Bail out if ref->size is not
byte aligned either.
2026-03-31 Mikael Morin <mikael@gcc.gnu.org>
Christopher Albert <albert@tugraz.at>
PR fortran/121185
PR fortran/124661
* tree-inline.cc (debug_find_tree, debug_find_tree_1): Move
and rename functions...
* tree.cc (find_tree, find_tree_1): ... here.
* tree-inline.h (debug_find_tree): Move renamed declaration...
* tree.h (find_tree): ... here.
2026-03-31 H.J. Lu <hjl.tools@gmail.com>
PR target/124165
PR target/124684
* config/i386/i386.cc (ix86_symbolic_const_load_p_1): Renamed to
...
(ix86_need_alignment_p_1): This.
(ix86_symbolic_const_load_p): Renamed to ...
(ix86_need_alignment_p): This.
(ix86_find_max_used_stack_alignment): Call ix86_access_stack_p
only if the INSN needs alignment > stack alignment.
2026-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
2026-03-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/aarch64/aarch64-option-extensions.def (poe2):
New CLI extension option.
(tev): Likewise.
(tlbid): Likewise.
(gcie): Likewise.
(mpamv2): Likewise.
(lscp): Likewise.
(mops-go): Likewise.
(sve2p3): Likewise.
(sme2p3): Likewise.
(f16f32dot): Likewise.
(sve-b16mm): Likewise.
(mtetc): Likewise.
(f16f32mm): Likewise.
(f16mm): Likewise.
* doc/invoke.texi (poe2): Document option.
(tev): Likewise.
(tlbid): Likewise.
(gcie): Likewise.
(mpamv2): Likewise.
(lscp): Likewise.
(mops-go): Likewise.
(sve2p3): Likewise.
(sme2p3): Likewise.
(f16f32dot): Likewise.
(sve-b16mm): Likewise.
(mtetc): Likewise.
(f16f32mm): Likewise.
(f16mm): Likewise.
2026-03-31 Wu Haotian <rigoligo03@gmail.com>
* config.gcc: removed linux.h and t-linux for loongarch*-*-elf* targets
2026-03-30 H.J. Lu <hjl.tools@gmail.com>
Richard Biener <rguenther@suse.de>
PR target/120839
PR middle-end/124671
* function.cc (assign_parm_adjust_stack_rtl): Get the parameter
as argument. Adjust alignment check forcing a local copy.
(assign_parms): Adjust.
* config/i386/i386.cc (ix86_argument_passed_on_stack_p): New.
(ix86_update_stack_alignment): Ignore argument passed on stack.
2026-03-30 Vineet Gupta <vineet.gupta@linux.dev>
* config/bpf/bpf.md (zero_extendhidi2): Add alternates for
alu32 and use 'W' for reg operands.
(zero_extendqidi2): Ditto.
2026-03-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/124692
* tree-cfg.cc (replace_uses_by): Call update_stmt after
substitution and before folding.
2026-03-30 Saurabh Jha <saurabh.jha@arm.com>
Evgeny Karpov <evgeny.karpov@arm.com>
* config/aarch64/aarch64.cc
(aarch64_scalar_mode_supported_p): Only return true on TFmode if
TARGET_LONG_DOUBLE_128 is set.
2026-03-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/88576
* tree-ssa-alias.cc (check_fnspec): Remove flag_errno_math check.
* ipa-modref.cc (modref_access_analysis::process_fnspec):
Likewise.
2026-03-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/124677
* tree-vect-loop.cc (vectorizable_recurr): Skip vector
stmts for the def.
2026-03-30 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Apple M5
cores.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Add apple-m5 core to the ones listed
for arch and tune selections.
2026-03-30 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR target/102309
* config/arm/arm.cc (arm_constant_limit): Allways allow at least
one insn when loading a constant.
2026-03-29 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124674
* config/riscv/riscv-modes.def: Create OImode.
2026-03-27 Vineet Gupta <vineet.gupta@linux.dev>
PR target/124670
* config/bpf/bpf.md (zero_extendsidi2): Use 'W' in asm template.
2026-03-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/124649
* regcprop.cc (maybe_mode_change): Return early
for unordered modes.
2026-03-27 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/124613
* config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher):
Add riscv_registering_builtins.
(rvv_switcher::~rvv_switcher): Set riscv_registering_builtins to
false.
* config/riscv/riscv.cc (riscv_vector_mode_supported_p): Use
riscv_registering_builtins.
* config/riscv/riscv.h: Declare.
2026-03-27 Richard Biener <rguenther@suse.de>
PR debug/124644
* dwarf2out.cc (dwarf2out_abstract_function): Only
add DW_AT_artificial if the decl isn't DECL_ARTIFICIAL.
2026-03-27 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
* Makefile.in: (PLUGIN_HEADERS): Add $(srcdir)/topics/*.h.
(install-plugin): Preserve directory structure for topics
headers.
2026-03-25 Richard Biener <rguenther@suse.de>
PR gcov-profile/121074
* coverage.h (coverage_init_file): Declare.
(coverage_finish_file): Likewise.
* coverage.cc (coverage_init_file): New function, split
out actual file opening and writing from ...
(coverage_init): ... here.
(coverage_finish_file): Likewise for file closing, from ...
(coverage_finish): ... here.
* tree-profile.cc (tree_profiling): Call coverage_init_file
and coverage_finish_file here.
2026-03-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/124627
* tree-inline.cc (copy_debug_stmts): Only copy debug
stmts that are still in the IL.
2026-03-25 Alexandre Oliva <oliva@adacore.com>
* gcc-diagnostic-spec.cc (nowarn_spec_t::nowarn_spec_t): Map
OPT_Wuse_after_free like OPT_Wuse_after_free_.
2026-03-25 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/i386/i386.cc (ix86_in_large_data_p): Check for .lbss etc.
(x86_64_elf_section_type_flags): Clear SECTION_NOTYPE for .lbss etc.
* config/i386/x86-64.h (MACH_DEP_SECTION_ASM_FLAG): Define.
* config/i386/sol2.h [HAVE_SOLARIS_AS]
(MACH_DEP_SECTION_ASM_FLAG): Redefine as 'h'.
2026-03-25 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* cgraph.cc (cgraph_edge::get_next_speculative_id): Use
next_speculative_call_target in get_next_speculative_id.
2026-03-24 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/124572
* lra-eliminations.cc (lra_eliminate): Push new reload insns for
eliminations in insns.
2026-03-24 Christopher Bazley <chris.bazley@arm.com>
* doc/rtl.texi: Fix example of the SSA form.
2026-03-24 Alfie Richards <alfie.richards@arm.com>
* tree-vect-stmts.cc (vectorizable_load): Swap order of failure
message checks.
2026-03-23 Stefan Weigl-Bosker <stefan@s00.xyz>
* omp-general.h: Fix typos.
2026-03-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/124599
* tree-ssa-pre.cc (compute_avail): Make the VUSE in the
PRE reference expression part of the value again.
(phi_translate_1): Likewise.
2026-03-23 Jakub Jelinek <jakub@redhat.com>
PR bootstrap/124547
* configure.ac: After config.gcc inclusion use or set only gas instead
of gas_flag and gnu_ld instead of gnu_ld_flag.
* config.gcc: Document possibility of gas_flag or gnu_ld_flag being
empty.
* acinclude.m4 (gcc_GAS_FLAGS): Use gas instead of gas_flag.
(gcc_AC_INITFINI_ARRAY): Likewise. Use gnu_ld instead of gnu_ld_flag.
* configure: Regenerate.
2026-03-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/124597
* config/i386/i386-builtins.cc (ix86_init_builtins_va_builtins_abi):
Also add nothrow and leaf attributes to the va builtins.
2026-03-22 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124597
* gimple-fold.cc (gimple_fold_builtin_stdarg): Correct the
eh_update argument to gsi_replace for the VA_END case.
2026-03-21 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/123852
* config/sh/sh.md (movsicc_t_false): Add the SImode
on the if_then_else.
(movsicc_t_true): Likewise.
(negsi_cond): Likewise.
(negdi_cond): Add the DImode on the if_then_else.
(bst_m2a): Add the QImode on the if_then_else.
2026-03-20 Tobias Burnus <tburnus@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
PR c/122866
* gimplify.cc (omp_instantiate_mapper): Give a sorry if there are
iterators.
2026-03-20 Kwok Cheung Yeung <kcyeung@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
* gimplify.cc (gimplify_omp_workshare): Handle iterators in
"target data".
2026-03-20 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/tuning_models/olympus.h (olympus_tunings): Set
loop_align to 64:16.
2026-03-20 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (gen_int_relational):
Specify the table array "info" and the pointer to its elements
as const.
2026-03-20 Jakub Jelinek <jakub@redhat.com>
PR target/124565
* config/i386/i386.cc (ix86_build_builtin_va_list_64): Set TREE_PUBLIC
on type_decl.
2026-03-20 Jakub Jelinek <jakub@redhat.com>
PR target/124566
* config/sh/sh.cc (sh_build_builtin_va_list): Set TREE_PUBLIC
on type_decl.
2026-03-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/124578
* tree-ssa-sccvn.cc (vn_reference_eq): Consistently check
fields from vro2.
2026-03-20 Yangyu Chen <cyy@cyyself.name>
* config/aarch64/aarch64.cc (aarch64_generate_version_dispatcher_body):
Check DECL_VIRTUAL_P for virtual functions for LTO handling.
* config/i386/i386-features.cc (ix86_generate_version_dispatcher_body):
Ditto.
* config/riscv/riscv.cc (riscv_generate_version_dispatcher_body): Ditto.
* config/rs6000/rs6000.cc (rs6000_generate_version_dispatcher_body):
Ditto.
* config/loongarch/loongarch.cc
(loongarch_generate_version_dispatcher_body): Ditto.
2026-03-19 Jakub Jelinek <jakub@redhat.com>
PR target/124565
* config/alpha/alpha.cc (alpha_build_builtin_va_list): Set TREE_PUBLIC
on type_decl.
2026-03-19 Dhruv Chawla <dhruvc@nvidia.com>
* common.opt.urls: Added missing entry.
2026-03-18 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/124041
PR rtl-optimization/124439
* lra-constraints.cc (process_alt_operands): Check hard reg subreg
mode by hard_regno_mode_ok.
(curr_insn_transform): Always subsitute equivalence for hard reg
subreg.
2026-03-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/124555
* match.pd ((A - B) >=/> 0 ? (A - B) : (B - A) -> abs (A - B)):
Guard the vector case with target_supports_op_p checks.
((A - B) <=/< 0 ? (A - B) : (B - A) -> -abs (A - B)): Likewise.
((type)A >=/> 0 ? A : -A -> abs (A)): Likewise.
((type)A <=/< 0 ? A : -A -> -abs (A)): Likewise.
2026-03-18 Dhruv Chawla <dhruvc@nvidia.com>
* Makefile.in (all.fda): Add `--print-autofdo-gcov-version` to
profile_merger invocation.
* auto-profile.cc (AUTO_PROFILE_VERSION): Move from here ...
* auto-profile.h (AUTO_PROFILE_VERSION): ... to here.
* common.opt: Add -print-autofdo-gcov-version and
--print-autofdo-gcov-version.
* doc/invoke.texi: Document the options.
* gcc.cc: Add include for auto-profile.h.
(driver_handle_option): Add OPT_print_autofdo_gcov_version.
(driver::maybe_print_and_exit): Handle the option.
2026-03-18 Richard Biener <rguenther@suse.de>
PR middle-end/124552
* function.cc (free_after_compilation): Free the copyid
allocator.
2026-03-18 Jakub Jelinek <jakub@redhat.com>
PR bootstrap/124547
* configure.ac (--with-gnu-ld): Set gnu_ld_flag= instead of
gnu_ld_flag=no if not explicitly specified.
(--with-gnu-as): Similarly for gas_flag.
(DEFAULT_ASSEMBLER): Use wording without GNU as whenever gas_flag
is not yes rather than when it is no.
* configure: Regenerate.
2026-03-18 Richard Biener <rguenther@suse.de>
* common.opt (fpost-ipa-mem-report): Fix typo.
2026-03-18 Richard Biener <rguenther@suse.de>
* ipa-cp.cc (gather_edges_for_value): Return an auto_vec.
(decide_about_value): Simplify, fixing leak of callers.
2026-03-18 Prachi Godbole <pgodbole@nvidia.com>
PR target/123749
* ipa-locality-cloning.cc (partition_callchain): Start new partition
if no. of insns exceeds size and if there are nodes to process.
2026-03-18 Sebastian Huber <sebastian.huber@embedded-brains.de>
* config/sparc/t-rtems: Add leon5 multilibs.
2026-03-17 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sve2.md (@aarch64_pred_revd<mode>):
Remove movprfx alternative.
(@cond_revd<mode>): Likewise.
2026-03-17 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR rtl-optimization/124476
* avoid-store-forwarding.cc
(store_forwarding_analyzer::process_store_forwarding): Replace
bitmap_all_bits_in_range_p with bitmap_any_bit_in_range_p and
return false on partial overlap. Remove redundant-store vectors
and their associated removal, dump, and deletion logic.
2026-03-17 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_analyze_slp): Release BST map when
returning.
2026-03-17 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info):
Initialize loop_iv_cond given it's no longer always
initialized ...
(vect_create_loop_vinfo): ... here. Fix formatting.
2026-03-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/122380
* tree-ssa-sccvn.h (copy_reference_ops_from_ref): Declare.
(vn_reference_compute_hash): Likewise.
(vn_reference_eq): Add parameter indicating lexical equivalence,
defaulted to false.
* tree-ssa-sccvn.cc (vn_reference_eq): Likewise.
(print_vn_reference_ops): Print alias type and alignment.
(vn_reference_compute_hash): Export.
(copy_reference_ops_from_ref): Likewise.
* tree-ssa-pre.cc (pre_expr_d::equal): Use lexical equivalence.
(get_or_alloc_expr_for_reference): Also get value-id, upon
zero assign a new value-id if the expression is unknown.
(expr_cmp): New helper.
(prefer): Likewise.
(pre_expr_DFS): Get expression exclusion bitmap and honor it.
(sorted_array_from_bitmap_set): If done for insertion, do limited
canonexpr() via pairwise prefer on expression pairs with the same
value, populating an exclution bitmap.
(phi_translate_1): Do not use the VN hashtable expressions
or insert there. Instead maintain a PRE view of expressions.
(clean): Adjust.
(do_hoist_insertion): Likewise.
(insert): Likewise.
(compute_avail): Use gimple_could_trap_p_1
on the original stmt rather than vn_reference_may_trap on
the VN leader. Use the original stmt operands for the PRE
view of reference expressions, only use the value number from the VN
tables. Remove no longer effective workarounds for semantically
different references with same value.
(fini_pre): Release operand vectors for PRE IL reference
expressions.
2026-03-17 Yangyu Chen <cyy@cyyself.name>
* config/i386/i386-features.cc (make_resolver_func): Use
symtab->change_decl_assembler_name instead of
SET_DECL_ASSEMBLER_NAME to properly update the symbol table.
2026-03-16 Jose E. Marchesi <jemarch@gnu.org>
* doc/install.texi (Configuration): Fix copy pasto
--enable-objc-gc to --enable-algol68-gc.
2026-03-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/124528
* tree-scalar-evolution.cc (scev_dfs::add_to_evolution):
Perform the negation in an unsigned type if we cannot make
sure it will not cause UB.
2026-03-16 Kito Cheng <kito.cheng@sifive.com>
* doc/invoke.texi: Add experimental warning for RISC-V
big-endian support.
2026-03-16 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc
(constantsynth_method_lshr_mi12b): New.
(constantsynth_methods): Add constantsynth_method_lshr_mi12b.
2026-03-14 Jakub Jelinek <jakub@redhat.com>
PR other/124508
* config/loongarch/genopts/gen-evolution.awk: Rename copyright_header
routine so that update-copyright.py isn't upset about it.
2026-03-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/124454
* regcprop.cc (pass_cprop_hardreg::execute): If something
changed and non-call exceptions is on, call purge_all_dead_edges
and cleanup_cfg.
2026-03-13 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/117182
* lra-constraints.cc (curr_insn_transform): Don't change an output
operand by constant or invariant equivalence.
2026-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.cc (TARGET_C_BITINT_TYPE_INFO): New Macro.
(arm_return_in_memory): Return true for any _BitInt(N) where N > 64.
(arm_needs_doubleword_align): Return true for any _BitInt(N) where N > 32.
(arm_bitint_type_info): New.
* config/arm/arm-protos.h (arm_bitint_type_info): New declaration.
2026-03-13 Saurabh Jha <saurabh.jha@arm.com>
PR target/122953
* config/aarch64/aarch64-c.cc
(TARGET_AARCH64_MS_ABI): Explicitly set it to 0 if not on mingw.
(aarch64_define_unconditional_macros): Remove __ARM_PCS_AAPCS64
from here.
(aarch64_update_cpp_builtins): Define __ARM_PCS_AAPCS64 if not
on Windows ABI.
---
Hey,
Regression tested on aarch64-linux-gnu and found no regressions.
Built for arch64-w64-mingw32, ran target dependent tests, and
found no regressions.
Ok for master?
Thanks,
Saurabh
2026-03-13 Jakub Jelinek <jakub@redhat.com>
* tree-profile.cc (struct conds_ctx): Formatting fixes.
Rename B1, B2, G1, G2 and G3 members to b1, b2, g1, g2 and g3.
Adjust all uses.
(topological_cmp, topological_src_cmp, index_of, single_p,
single_edge, contract_edge_up): Formatting fixes.
(struct outcomes): Likewise.
(conditional_succs, condition_index, condition_uid,
masking_vectors, emit_assign, emit_bitwise_op): Likewise.
(make_top_index_visit, make_top_index): Likewise. Rename
L argument to l.
(paths_between): Formatting fixes.
(struct condcov): Likewise.
(cov_length, cov_blocks, cov_masks, cov_maps, cov_free): Likewise.
(find_conditions): Likewise. Don't start warning_at message with
uppercase letter.
(struct counters): Formatting fixes.
(find_counters, resolve_counter, resolve_counters,
instrument_decisions): Likewise.
(init_ic_make_global_vars): Comment formatting fixes.
(gimple_init_gcov_profiler): Formatting fixes.
2026-03-13 Jørgen Kvalsvik <j@lambda.is>
PR ipa/124462
* tree-profile.cc (masking_vectors): Skip blocks with less than
2 non-complex incoming edges.
2026-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (constantsynth_pass1):
Change the comparison between src and SET_SRC(pat) to be performed
using rtx_equal_p rather than between references (pointer values)
directly, and adjust the destination of changes in validate_change
to eliminate the need to call gen_rtx_SET.
(constantsynth_pass2):
Fill in missing spacing in one place and changes dump file output
slightly.
2026-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_split_operand_pair)
Move the common code from the split part of movd[if]_internal
MD patterns into this function, since this function is only
called from the split part of that patterns.
Also, during non-debug optimization, re-register new literal
pool entries with the split values themselves instead of
splitting the memory reference of the source numeric constant
placed in the pool.
(split_DI_SF_DF_const):
Rename to convert_SF_const and remove the split function of
D[IF]mode constant assignment.
(do_largeconst2):
Change the call from split_DI_SF_DF_const to convert_SF_const.
* config/xtensa/xtensa.md (movdi_internal, movdf_internal):
Reduce their split parts to just a call to xtensa_split_operand_pair.
2026-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (FPreg_neg_scaled_simm12b_1):
Change the test to determine whether REAL_VALUE_TYPE is a non-
zero finite value to whether it is normal.
(FPreg_neg_scaled_simm12b):
Place the call to FPreg_neg_scaled_simm12b_1 last in the
expression to improve performance, and change the dump file
output slightly.
2026-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-passes.def (pass_xtensa_largeconst):
Rename to pass_xtensa_largeconst1.
(pass_xtensa_largeconst2): New target-specific pass.
* config/xtensa/xtensa-protos.h (make_pass_xtensa_largeconst):
Rename to make_pass_xtensa_largeconst1.
(make_pass_xtensa_largeconst2): New function prototype.
* config/xtensa/xtensa.cc (litpool_set_src_1):
Change to process large numeric constant assignments to DImode
as well as [SH]Imode.
(do_largeconst):
Rename it to do_largeconst1 and leave only the mandatory insn
transformation process.
(do_largeconst2): New function that inherits the optional insn
transformation processes from the old do_largeconst.
(rest_of_handle_largeconst):
Rename to rest_of_handle_largeconst1 and change to call
do_largeconst1.
(rest_of_handle_largeconst2): New function that calls
do_largeconst2.
(pass_data_xtensa_largeconst)
Rename to pass_data_xtensa_largeconst1.
(pass_xtensa_largeconst):
Rename to pass_xtensa_largeconst1 and change to call
rest_of_handle_largeconst1.
(pass_data_xtensa_largeconst2): New opt_pass data.
(pass_xtensa_largeconst2):
New rtl_opt_pass that runs rest_of_handle_largeconst2 when non-
debug optimizations are enabled.
(make_pass_xtensa_largeconst):
Rename to make_pass_xtensa_largeconst1.
(make_pass_xtensa_largeconst2): New function definition.
2026-03-13 Jakub Jelinek <jakub@redhat.com>
PR target/124461
* config/i386/i386.md (movrs<mode>): Use <imodesuffix> only for
-masm=att, not for -masm=intel.
2026-03-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/123822
* simplify-rtx.cc (simplify_context::simplify_subreg): Check the
mode of the part to be non-VOIDmode before calling gen_rtx_SUBREG.
2026-03-12 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/124452
* lra-constraints.cc (curr_insn_transform): Move return on the
postponed insn before any reload generation.
2026-03-12 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
Revert:
2026-02-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gnu_ld_flag): Move $gcc_cv_ld --version check into
AC_ARG_WITH(gnu-ld).
(gcc_cv_ld): Set before gnu_ld_flag.
(gas_flag): Move $gcc_cv_ld --version check into AC_ARG_WITH(gnu-ld).
(gcc_cv_as): Set before gas_flag.
* configure: Regenerate.
2026-03-12 Martin Jambor <mjambor@suse.cz>
PR objc/124260
* ipa-prop.cc (ipa_analyze_var_static_initializer): Skip a constructor
entry if its index is NULL.
2026-03-12 Richard Biener <rguenther@suse.de>
PR bootstrap/124406
* ipa-pure-const.cc (skip_function_for_local_pure_const):
Do not analyze interposable functions when LTO is enabled.
2026-03-12 H.J. Lu <hjl.tools@gmail.com>
PR target/122925
PR target/119979
* config/sh/sh.cc (TARGET_PROMOTE_PROTOTYPES): Removed.
2026-03-12 Philipp Tomsich <philipp.tomsich@vrull.eu>
* fold-mem-offsets.cc (do_analysis): Revise comment.
2026-03-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/120030
* symtab.cc (symtab_node::set_init_priority): Better
handle the case of setting the priority back to default.
(cgraph_node::set_fini_priority): Likewise.
2026-03-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* doc/extend.texi (constructor/destructor): Add documentation
about multiple attributes here.
2026-03-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* doc/extend.texi (constructor/destructor): Document
the priority when none is supplied.
2026-03-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/124409
* doc/install.texi: Increment the required binutils for
riscv to 2.40.
2026-03-12 Marek Polacek <polacek@redhat.com>
PR c++/124397
* diagnostic.h (emitting_diagnostic_p): New.
* diagnostics/context.h (context::emitting_diagnostic_p): New.
2026-03-11 Jakub Jelinek <jakub@redhat.com>
PR target/124436
* genautomata.cc (output_dfa_insn_code_func): Use
MIN (INT_MAX, 2U * uid) instead of 2 * uid in dfa_insn_code_enlarge.
2026-03-11 H.J. Lu <hjl.tools@gmail.com>
PR target/124407
* config/i386/i386-features.cc (ix86_place_single_vector_set):
Handle non-int load with integer constant.
(ix86_broadcast_inner): Convert const0_rtx to non-int mode.
2026-03-11 Richard Sandiford <rdsandiford@googlemail.com>
PR middle-end/124435
* expr.cc (store_field_updates_msb_p): Use GET_MODE_BITSIZE
instead of GET_MODE_SIZE. Handle the two endiannesses separately.
2026-03-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
Revert:
2026-02-27 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/90036
* tree-ssa-scopedtables.cc (avail_exprs_stack::record_cond): Always
record the new hash table entry.
2026-03-11 Jeff Law <jeffrey.law@oss.qualcomm.com>
Revert:
2026-02-28 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/90036
* tree-ssa-dom.cc (back_propagate_equivalences): Accept new
argument for available expression stack. Lookup equivalences
in the expression hash table too. If an expression hash a
known constant value, record it and recurse.
(record_temporary_equivalences): Back propagate for a subset of
edge equivalences.
2026-03-11 Richard Earnshaw <rearnsha@arm.com>
PR target/123271
* config/arm/arm.md (subvsi3_intmin): Renamed to ...
(sub_cmpVsi3_intmin): ... this.
(subvsi3): Renamed to ...
(sub_cmpVsi3): ... this.
(subvsi3_imm1): Renamed to ...
(sub_cmpVsi3_imm1): ... this.
(usubvsi3_borrow): Renamed to ...
(usub_cmpVsi3_borrow): ... this.
(usubvsi3_borrow_imm): Renamed to ...
(usub_cmpVsi3_borrow_imm): ... this.
(subvsi3_borrow): Renamed to ...
(sub_cmpVsi3_borrow): ... this.
(subvsi3_borrow_imm): Renamed to ...
(sub_cmpVsi3_borrow_imm): ... this.
2026-03-11 Arsen Arsenović <aarsenovic@baylibre.com>
* config/gcn/gcn.cc (gcn_addr_space_convert): Use
SHARED_BASE_REG to find flat address space base of LDS.
2026-03-11 Arsen Arsenović <aarsenovic@baylibre.com>
PR target/124044
* config/gcn/gcn.cc (gcn_addr_space_resolve_default): New
function. Converts from ADDR_SPACE_DEFAULT to
DEFAULT_ADDR_SPACE.
(gcn_addr_space_convert): Resolve from_type and to_type address
spaces.
2026-03-11 Arsen Arsenović <aarsenovic@baylibre.com>
* config/gcn/gcn.cc (gcn_regno_reg_class): Handle
MEMORY_APERTURE_REGS.
(gcn_hard_regno_rename_ok): Return false for memory aperture
regs.
(gcn_memory_move_cost): Handle memory aperture regs the same as
general registers.
(gcn_hard_regno_nregs): Handle MEMORY_APERTURE_REGS.
* config/gcn/gcn.h (SHARED_BASE_REG): Define.
(SHARED_LIMT_REG): Ditto.
(PRIVATE_BASE_REG): Ditto.
(PRIVATE_LIMT_REG): Ditto.
(MEMORY_APERTURE_REG_P): New macro. Evaluates to non-zero if
parameter is one of the above registers.
(SSRC_REGNO_P): Also evaluate to non-zero for aperture regs, as
they can be sources to scalar instructions.
(enum reg_class): New class: MEMORY_APERTURE_REGS.
(REG_CLASS_NAMES): Provide name for that class.
(MEMORY_APERTURE_REGS_MASK): New helper macro. Value of
NAMED_REG_MASK2 for each of the memory aperture regs.
(REG_CLASS_CONTENTS): Add the above registers to
MEMORY_APERTURE_REGS, SGPR_VOP_SRC_REGS, and SGPR_SRC_REGS.
2026-03-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
* fold-mem-offsets.cc (do_check_validity): fix wrong mode
and rename arguments to avoid future confusion
2026-03-10 Yangyu Chen <cyy@cyyself.name>
* config/riscv/riscv.cc (riscv_check_target_clone_version):
Fix TARGET_CHECK_TARGET_CLONE_VERSION implementation.
2026-03-10 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vect_get_datarefs_in_loop): Add function
level comment.
(vect_analyze_loop_2): Fix comment.
2026-03-10 Jan Hubicka <jh@suse.cz>
Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/120987
* ipa-modref.cc (ipa_merge_modref_summary_after_inlining): Mask
off non const/pure/novops related flags when combining of outer
functions.
2026-03-09 Jonathan Wakely <jwakely@redhat.com>
PR translation/124422
* config/loongarch/loongarch-target-attr.cc
(loongarch_parse_fmv_features): Fix spelling in diagnostics.
* params.opt (max-devirt-targets): Fix typo in description.
2026-03-09 Martin Jambor <mjambor@suse.cz>
PR ipa/124291
* ipa-cp.cc (ipcp_val_replacement_ok_p): Allow more precise
contexts that what the clone was originally intended for.
2026-03-09 Dhruv Chawla <dhruvc@nvidia.com>
PR gcov-profile/124075
* config/aarch64/gcc-auto-profile: Add "-o perf.data" to perf
record invocation.
* config/i386/gcc-auto-profile: Likewise.
2026-03-09 Dhruv Chawla <dhruvc@nvidia.com>
PR gcov-profile/123923
* config/aarch64/gcc-auto-profile: Add --inherit to perf record flags.
* config/i386/gcc-auto-profile: Likewise.
2026-03-09 Richard Sandiford <rdsandiford@googlemail.com>
PR middle-end/118608
* rtlanal.cc (truncated_to_mode): Revert a change made on 2026-02-03.
* config/mips/mips.md (*extenddi_truncate<mode>): Likewise.
2026-03-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (movdi_internal, movdf_internal, *btrue,
*ubtrue, movsicc_internal0, movsicc_internal1, movsfcc_internal0,
movsfcc_internal1):
Rewrite in compact syntax.
2026-03-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/124403
* config/riscv/riscv.cc (riscv_get_vls_cc_attr): Fix formating
of the diagnostic.
2026-03-07 Sandra Loosemore <sloosemore@baylibre.com>
PR driver/69367
PR driver/69849
* Makefile.in (TEXI_GCCINT_FILES): Add specs.texi.
* doc/gccint.texi: Include it.
* doc/install.texi: Fix cross-references.
* doc/invoke.texi: Likewise.
(Option Summary): Reclassify -specs/--specs as a developer option.
(Overall Options): Move -specs= documentation to...
(Developer Options): ...here.
(Spec Files): Move entire section to....
* doc/specs.texi: ....new file.
* common.opt.urls: Regenerated.
2026-03-07 Jørgen Kvalsvik <j@lambda.is>
* tree-profile.cc (struct conds_ctx): Add edges.
(topological_src_cmp): New function.
(masking_vectors): New search strategy.
2026-03-07 Robin Dapp <rdapp@oss.qualcomm.com>
PR rtl-optimization/121649
* cse.cc (find_sets_in_insn): Only use non-reg vec_select
simplifications.
2026-03-06 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/124126
* config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types): Copy
the array type before setting the mode.
2026-03-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124135
* tree-inline.cc (expand_call_inline): If both gimple_call_lhs (stmt)
and use_retvar aren't gimple regs but have gimple reg type, use
separate load of use_retva into SSA_NAME and then store of it
into gimple_call_lhs (stmt).
2026-03-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/124358
* match.pd ((ptr) (x p+ y) p+ z -> (ptr) (x p+ (y + z))): Simplify
into (ptr) x p+ (y + z) instead.
2026-03-05 Victor Do Nascimento <victor.donascimento@arm.com>
PR tree-optimization/124037
* tree-vect-stmts.cc (get_load_store_type): Fix
alignment_support_scheme categorization for early
break VMAT_ELEMENTWISE accesses.
2026-03-05 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vectorizable_live_operation): Fix typo.
2026-03-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/98064
* tree-vect-loop.cc (vectorizable_live_operation): Do
not restrict replacing uses in a LC PHI.
2026-03-05 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.md (swap<mode>): Swap operand order for
-masm=intel.
2026-03-05 Xi Ruoyao <xry111@xry111.site>
PR target/123807
PR middle-end/124250
* config/loongarch/loongarch.cc
(loongarch_expand_vector_init_same): Revert r16-7163 change.
2026-03-05 Jakub Jelinek <jakub@redhat.com>
PR target/124349
* config/i386/sse.md (iptrssebvec_2): New define_mode_attr.
(cvthf82ph<mode><mask_name>): Use it for -masm=intel input
operand.
2026-03-05 Jakub Jelinek <jakub@redhat.com>
PR target/124367
* config/i386/sse.md (*andnot<mode>3): Use 0x44 rather than $0x44
for -masm=intel.
2026-03-05 Jakub Jelinek <jakub@redhat.com>
PR target/124366
* config/i386/i386.md (@wrss<mode>, @wruss<mode>): Swap operand
order for -masm=intel.
2026-03-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/119568
* tree-ssa-math-opts.cc (convert_plusminus_to_widen): Reject different
mode classes.
2026-03-04 Robin Dapp <rdapp@oss.qualcomm.com>
PR rtl-optimization/124041
* lra-constraints.cc (curr_insn_transform): Check if hardreg is
valid in subreg context.
2026-03-04 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR rtl-optimization/124351
* avoid-store-forwarding.cc (process_store_forwarding): Add
bitmap_clear after allocating forwarded_bytes.
2026-03-04 Jakub Jelinek <jakub@redhat.com>
PR target/124341
* config/i386/sse.md (vcvt<convertfp8_pack><mode><mask_name>): Use
<mask_operand3> rather than <mask_operand2> for -masm=intel.
2026-03-04 Jakub Jelinek <jakub@redhat.com>
PR target/124349
* config/i386/sse.md (avx10_2_comisbf16_v8bf): Use %w1 instead of %1
for -masm=intel.
2026-03-03 H.J. Lu <hjl.tools@gmail.com>
PR target/124165
* config/i386/i386-protos.h (symbolic_reference_mentioned_p):
Change the argument type from rtx to const_rtx.
* config/i386/i386.cc (symbolic_reference_mentioned_p): Likewise.
(ix86_access_stack_p): Add 2 auto_bitmap[] arguments. Cache
the register BB domination result.
(ix86_symbolic_const_load_p_1): New.
(ix86_symbolic_const_load_p): Likewise.
(ix86_find_max_used_stack_alignment): If there is no symbolic
constant load into the register, don't call ix86_access_stack_p.
2026-03-03 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/115042
* lra-int.h (lra_postponed_insns): New.
* lra.cc (lra_set_insn_deleted, lra_asm_insn_error): Clear
postponed insn flag.
(lra_process_new_insns): Propagate postponed insn flag for asm
gotos.
(lra_postponed_insns): New.
(lra): Initialize lra_postponed_insns. Push postponed insns on
the stack.
* lra-constraints.cc (postpone_insns): New function.
(curr_insn_transform): Use it to postpone processing reload insn
constraints. Skip processing postponed insns.
2026-03-03 Richard Biener <rguenther@suse.de>
PR middle-end/45273
* predict.cc (combine_predictions_for_insn): Use int64_t
math instead of double.
2026-03-03 Jakub Jelinek <jakub@redhat.com>
PR target/124336
* config/i386/i386.cc (output_adjust_stack_and_probe): Use
or{b} rather than or%z0 and BYTE PTR rather than DWORD PTR.
(output_probe_stack_range): Likewise.
* config/i386/i386.md (probe_stack): Pass just 2 arguments
to gen_probe_stack_1, first adjust_address to QImode, second
const0_rtx.
(@probe_stack_1_<mode>): Remove.
(probe_stack_1): New define_insn.
2026-03-03 Jonathan Wakely <jwakely@redhat.com>
* fold-const.cc: Fix "Conveinece" typo in comment.
2026-03-03 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_make_slp_decision): Do not call
vect_mark_slp_stmts.
* tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
We are always doing SLP.
(vect_supportable_dr_alignment): Likewise.
* tree-vect-loop.cc (vect_analyze_loop_2): No need to reset
STMT_SLP_TYPE.
2026-03-03 Jonathan Yong <10walls@gmail.com>
* Makefile.in: the libgdiagnostics shared object for mingw
should be based on host name, not target name.
2026-03-03 Richard Sandiford <rdsandiford@googlemail.com>
Artemiy Volkov <artemiy.volkov@arm.com>
PR rtl-optimization/123786
* rtl-ssa/functions.h (function_info::live_out_value): Delete.
(function_info::create_degenerate_phi): New overload.
* rtl-ssa/blocks.cc (all_uses_are_live_out_uses): Delete.
(function_info::live_out_value): Likewise.
(function_info::replace_phi): Keep live-out uses if they are followed
by a definition in the same EBB.
(function_info::create_degenerate_phi): New overload, extracted
from create_reg_use.
(function_info::add_phi_nodes): Ensure that there is a phi for
every live input that is redefined by a second or subsequent
block in the EBB. Record that such phis need live-out uses.
(function_info::record_block_live_out): Use look_through_degenerate_phi
rather than live_out_value when setting phi inputs. Remove use of
live_out_value for live-out uses. Inline the old handling of
bb_mem_live_out.
(function_info::start_block): Move append_bb call to...
(function_info::create_ebbs): ...here.
* rtl-ssa/insns.cc (function_info::create_reg_use): Use the new
create_degenerate_phi overload.
2026-03-03 Jakub Jelinek <jakub@redhat.com>
PR target/124315
* config/i386/sse.md (avx512f_vmfmadd_<mode>_mask3<round_name>,
avx512f_vmfmsub_<mode>_mask3<round_name>,
avx512f_vmfnmadd_<mode>_mask3<round_name>,
avx512f_vmfnmsub_<mode>_mask3<round_name>): Use %<iptr>1 instead of
%<iptr>3 in -masm=intel syntax.
2026-03-03 Jakub Jelinek <jakub@redhat.com>
PR target/124335
* config/i386/sse.md (*avx512f_load<mode>_mask): Use %{%3%} instead of
%{3%} for -masm=intel syntax.
2026-03-03 Jakub Jelinek <jakub@redhat.com>
* config/i386/sse.md (avx512fp16_mov<mode>): Rename pattern to...
(*avx512fp16_mov<mode>): ... this.
2026-03-02 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/102397
* doc/extend.texi (Attributes): Explicitly say that all attributes
work in both syntaxes and examples may show either form.
(Common Attributes): Convert some examples to use the new syntax.
2026-03-02 Filip Kastl <fkastl@suse.cz>
PR target/123926
* config/sparc/sparc.h (HAVE_AS_TLS): Default to 0.
2026-03-02 Alfie Richards <alfie.richards@arm.com>
PR target/124167
* attribs.cc (make_dispatcher_decl): Change node->definition
to inherit from the node its called on.
* ipa.cc (remote_unreachable_nodes): Move FMV logic out of
(!in_boundary_p) if block.
2026-03-02 Cupertino Miranda <cupertino.miranda@oracle.com>
PR target/113453
* config/bpf/bpf-protos.h (bpf_output_call): Change prototype.
* config/bpf/bpf.cc (bpf_output_call): Change to adapt operands
and return
the instruction template instead of immediately emit asm and
not allow proper final expected execution flow.
(bpf_output_line_info): Add function to introduce line info
entries in respective structures
(bpf_asm_out_unwind_emit): Add function as hook to
TARGET_ASM_UNWIND_EMIT. This hook is called before any
instruction is emitted.
* config/bpf/bpf.md: Change calls to bpf_output_call.
* config/bpf/btfext-out.cc (struct btf_ext_lineinfo): Add fields
to struct.
(bpf_create_lineinfo, btf_add_line_info_for): Add support
function to insert line_info data in respective structures.
(output_btfext_line_info): Function to emit line_info data in
.BTF.ext section.
(btf_ext_output): Call output_btfext_line_info.
* config/bpf/btfext-out.h: Add prototype for
btf_add_line_info_for.
2026-03-02 Jakub Jelinek <jakub@redhat.com>
PR target/124294
* config/i386/sse.md (avx512fp16_mov<mode>): Fix ordering of operands
for -masm=intel for the avx10_2 alternative. Fix up indentation in
the insn condition.
(vec_set<mode>_0): Fix comment typo, higer -> higher.
2026-03-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR target/57261
* configure.ac (gcc_cv_ld_as_needed) <i?86-*-solaris2* |
x86_64-*-solaris2*>: Don't disable.
* configure: Regenerate.
2026-03-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (solaris_ld): New check.
Test solaris_ld instead of gnu_ld_flag.
* configure: Regenerate.
* config.in: Regenerate.
* config/i386/sol2.h: Switch to HAVE_SOLARIS_LD.
* config/sol2.h: Likewise.
* config/sparc/sol2.h: Likewise.
* config/sparc/sparc.md: Likewise.
2026-03-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (solaris_as): New check.
* configure: Regenerate.
* config.in: Regenerate.
* config/i386/i386.cc: Switch to HAVE_SOLARIS_AS.
* config/i386/sol2.h: Likewise.
* config/sol2.h: Likewise.
* config/sparc/sol2.h: Likewise.
* config/sparc/sparc.cc: Likewise.
* config/sparc/sparc.md: Likewise.
2026-02-28 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/90036
* tree-ssa-dom.cc (back_propagate_equivalences): Accept new
argument for available expression stack. Lookup equivalences
in the expression hash table too. If an expression hash a
known constant value, record it and recurse.
(record_temporary_equivalences): Back propagate for a subset of
edge equivalences.
2026-02-28 David Malcolm <dmalcolm@redhat.com>
PR target/124094
* config/aarch64/aarch64-generate-json-tuning-routines.py
(generate_field_code): Add "ctxt, " arg to function call when
operation is "parse".
(generate_function): Add "gcc_json_context &ctxt, " param to
function decl when operation is "parse".
* config/aarch64/aarch64-json-tunings-parser-generated.inc:
Regenerate, passing around a gcc_json_context &.
* config/aarch64/aarch64-json-tunings-parser.cc: Include
"json-diagnostic.h".
(WARNING_OPT) New macro.
(PARSE_INTEGER_FIELD): Add "ctxt" param and pass it around.
(PARSE_UNSIGNED_INTEGER_FIELD): Likewise.
(PARSE_BOOLEAN_FIELD): Likewise.
(PARSE_STRING_FIELD): Likewise.
(PARSE_OBJECT): Likewise.
(PARSE_ARRAY_FIELD): Likewise.
(PARSE_ENUM_FIELD): Likewise.
(parse_func_type): Likewise.
(parse_object_helper): Likewise. Use json_error rather than error.
(inform_about_wrong_kind_of_json_value): New.
(extract_string): Add "ctxt" param. Replace "warning" with a pair
of calls to json_warning and
inform_about_wrong_kind_of_json_value, tweaking wording
accordingly.
(extract_integer): Likewise.
(extract_unsigned_integer): Likewise.
(parse_enum_field): Likewise.
(validate_and_traverse): Replace "warning" and "error" with
"json_warning" and "json_error".
(check_version_compatibility): Use WARNING_OPT. Add
auto_diagnostic_group to group the error and note.
(aarch64_load_tuning_params_from_json_string): Add "js_filename"
param. Use gcc_json_context to capture location info. Use it
when reporting errors to get file/line/column info. Replace check
on root being non-null with assertion, as this is guaranteed if
error is non-null. Replace warning with json_warning.
(aarch64_load_tuning_params_from_json): Pass data_filename to
aarch64_load_tuning_params_from_json_string for use when reporting
diagnostics.
(selftest::test_json_integers): Add a placeholder filename.
(selftest::test_json_boolean): Likewise.
(selftest::test_json_strings): Likewise.
(selftest::test_json_enums): Likewise.
2026-02-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon): Add json-diagnostic.o.
* diagnostics/client-data-hooks.h
(class client_data_hooks_decorator): New.
* diagnostics/context.cc (context::set_client_data_hooks): Return
the old hooks.
* diagnostics/context.h (context::set_client_data_hooks): Update
decl likewise.
* json-diagnostic.cc: New file.
* json-diagnostic.h: New file.
2026-02-28 David Malcolm <dmalcolm@redhat.com>
* config/aarch64/aarch64-json-tunings-parser.cc: Define
INCLUDE_MAP.
* json-parsing.cc: Likewise.
* json-parsing.h (class simple_location_map): New class, moved and
renamed from...
* libsarifreplay.cc (class replayer_location_map): ...here.
(sarif_replayer::m_json_location_map): Update for renaming of
class.
2026-02-28 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon):
Add diagnostics/physical-location-maker.o.
* diagnostics/physical-location-maker.cc: New file, adapted from
material in libgdiagnostics.cc.
* diagnostics/physical-location-maker.h: New file, adapted from
material in libgdiagnostics.cc.
* libgdiagnostics.cc: Include
"diagnostics/physical-location-maker.h".
(diagnostic_manager::diagnostic_manager): Initialize
m_phys_loc_maker.
(diagnostic_manager::new_location_from_file_and_line): Split out
into physical_location_maker.
(diagnostic_manager::new_location_from_file_line_column):
Likewise.
(diagnostic_manager::ensure_linemap_for_file_and_line): Likewise.
(diagnostic_manager::m_phys_loc_maker): New field.
2026-02-28 David Malcolm <dmalcolm@redhat.com>
* diagnostics/html-sink.cc
(html_builder::make_element_for_diagnostic): Update for logical
location strings being returned as label_text rather than
const char *.
* diagnostics/logical-locations.h
(logical_locations::manager::get_short_name): Return label_text
rather than const char *.
(logical_locations::manager::get_name_with_scope): Likewise.
(logical_locations::manager::get_internal_name): Likewise.
* diagnostics/sarif-sink.cc
(sarif_builder::ensure_sarif_logical_location_for): Update for
logical location strings being returned as label_text rather than
const char *.
(sarif_builder::make_minimal_sarif_logical_location): Likewise.
* diagnostics/selftest-logical-locations.cc
(test_manager::get_short_name): Likewise.
(test_manager::get_name_with_scope): Likewise.
(test_manager::get_internal_name): Likewise.
(selftest_logical_locations_cc_tests): Likewise.
* diagnostics/selftest-logical-locations.h
(test_manager::get_short_name): Likewise.
(test_manager::get_name_with_scope): Likewise.
(test_manager::get_internal_name): Likewise.
* diagnostics/state-graphs-to-dot.cc
(state_diagram::on_node_in_table): Likewise.
* libgdiagnostics.cc
(impl_logical_location_manager::get_short_name): Likewise.
(impl_logical_location_manager::get_name_with_scope): Likewise.
(impl_logical_location_manager::get_internal_name): Likewise.
* tree-logical-location.cc
(tree_logical_location_manager::get_short_name): Likewise.
(tree_logical_location_manager::get_name_with_scope): Likewise.
(tree_logical_location_manager::get_internal_name): Likewise.
* tree-logical-location.h
(tree_logical_location_manager::get_short_name): Likewise.
(tree_logical_location_manager::get_name_with_scope): Likewise.
(tree_logical_location_manager::get_internal_name): Likewise.
2026-02-28 Sandra Loosemore <sloosemore@baylibre.com>
PR c/87591
* doc/extend.texi (Attributes): Document __attribute keyword.
(Attribute Syntax): Here too.
2026-02-28 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Attributes): Rename the node "GNU Attribute
Syntax" node back to "Attribute Syntax"; fix references. Add
@anchor for sections recently merged away at the new location of
the material they used to contain.
2026-02-28 Kwok Cheung Yeung <kcyeung@baylibre.com>
PR middle-end/113436
* omp-low.cc (lower_omp_target): Merge branches for allocating memory
for private clauses. Add handling for references when allocator
clause not specified.
2026-02-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/124142
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
For early break require masking when operation can trap.
2026-02-27 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/90036
* tree-ssa-scopedtables.cc (avail_exprs_stack::record_cond): Always
record the new hash table entry.
2026-02-27 Xi Ruoyao <xry111@xry111.site>
PR middle-end/124280
* optabs.cc (expand_vector_broadcast): Allow broadcasting QImode
to BImode vector.
2026-02-27 Vladimir N. Makarov <vmakarov@redhat.com>
Revert:
2026-02-26 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/115042
* lra-int.h (lra_constraint_insn_stack_clear): New prototype.
* lra.cc (lra_constraint_insn_stack2): New vector.
(lra_constraint_insn_stack_clear): New function.
(lra): Initialize/finalize lra_constraint_insn_stack2.
* lra-constraints.cc (lra_constraints): Use
lra_constraint_insn_stack_clear to postpone processing new reload
insns.
2026-02-27 Martin Jambor <mjambor@suse.cz>
PR ipa/123229
* ipa-prop.cc (update_indirect_edges_after_inlining): Reset parameter
index associated with an indirect edge if the inlined edge does not
have any jump functions.
2026-02-27 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/aarch64-json-tunings-parser.cc (parse_object_helper):
Zero-initialize objects that are NULL in the base tunings, if provided
in JSON tunings.
* config/aarch64/aarch64-protos.h (struct sve_vec_cost): Add default
constructor.
(struct aarch64_simd_vec_issue_info): Likewise.
(struct aarch64_sve_vec_issue_info): Likewise.
2026-02-27 Martin Jambor <mjambor@suse.cz>
PR ipa/123629
* ipa-polymorphic-call.cc
(ipa_polymorphic_call_context::meet_with): When an outer context is
NULL, call make_speculative on the other one.
2026-02-27 Tamar Christina <tamar.christina@arm.com>
PR target/124162
* config/aarch64/aarch64-sve.md (cond_vec_cbranch_any,
cond_vec_cbranch_all): Drop partial vectors support.
2026-02-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/117935
* tree-ssa-phiopt.cc (contains_hot_cold_predict): New function.
(match_simplify_replacement): Return early if early_p and one of
the middle bb(s) have a hot/cold predict statement.
2026-02-26 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/115042
* lra-int.h (lra_constraint_insn_stack_clear): New prototype.
* lra.cc (lra_constraint_insn_stack2): New vector.
(lra_constraint_insn_stack_clear): New function.
(lra): Initialize/finalize lra_constraint_insn_stack2.
* lra-constraints.cc (lra_constraints): Use
lra_constraint_insn_stack_clear to postpone processing new reload
insns.
2026-02-26 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/122448
* config/riscv/riscv-vsetvl.cc (compute_reaching_defintion):
Rename...
(compute_reaching_definition): ...To this.
(pre_vsetvl::compute_vsetvl_def_data): Compute reaching
definitions for vsetvl VL -> vsetvl AVL.
(pre_vsetvl::compute_transparent): Include VL uses.
(pre_vsetvl::fuse_local_vsetvl_info): Initialize m_reg_use_loc.
(pre_vsetvl::earliest_fuse_vsetvl_info): Don't hoist if any
successor would use VL.
2026-02-26 Xi Ruoyao <xry111@xry111.site>
PR middle-end/124250
PR target/123807
* optabs.cc (expand_vector_broadcast): Add a checking assert to
verify the precondition about the input modes.
(expand_binop): Extend the shift amount if it's narrower than
the element of the shifted vector.
2026-02-26 Roger Sayle <roger@nextmovesoftware.com>
PR target/124194
* config/i386/sse.md (*<avx512>_cmp<mode>3_dup_op): Also return
CONSTM1_RTX for the case cmp_imm == 7 (predicate TRUE).
2026-02-26 Roger Sayle <roger@nextmovesoftware.com>
PR c/119651
PR c/123472
* fold-const.cc (tree_nonzero_bits): Rename the original as a
static function taking an additional precision parameter. Make
this implementation robust to error_mark_node. Preserve the
original API by checking for error_operand_p before invoking the
static helper function.
2026-02-26 H.J. Lu <hjl.tools@gmail.com>
PR target/119979
PR target/120888
* targhooks.cc (default_promote_function_mode_sign_extend): New.
* targhooks.h (default_promote_function_mode_sign_extend):
Likewise.
* config/mcore/mcore.cc (TARGET_PROMOTE_FUNCTION_MODE): Use
default_promote_function_mode_sign_extend.
(TARGET_PROMOTE_PROTOTYPES): Removed.
* config/xtensa/xtensa.cc (xtensa_promote_function_mode): Removed.
(TARGET_PROMOTE_FUNCTION_MODE): Use
default_promote_function_mode_sign_extend.
2026-02-25 Philipp Tomsich <philipp.tomsich@vrull.eu>
* avoid-store-forwarding.cc
(store_forwarding_analyzer::process_store_forwarding): Use
auto_sbitmap for forwarded_bytes to ensure it is freed on all
return paths.
2026-02-25 Philipp Tomsich <philipp.tomsich@vrull.eu>
* avoid-store-forwarding.cc
(store_forwarding_analyzer::update_stats): Use stats_sf_avoided
for the "avoided" counter.
2026-02-25 Philipp Tomsich <philipp.tomsich@vrull.eu>
* avoid-store-forwarding.cc: Move config.h before
avoid-store-forwarding.h; place avoid-store-forwarding.h
after rtl.h; remove unused cselib.h include.
* avoid-store-forwarding.h: Remove includes of config.h,
system.h, coretypes.h, backend.h, rtl.h.
2026-02-25 Cupertino Miranda <cupertino.miranda@oracle.com>
PR target/120241
* config/bpf/core-builtins.cc
(is_attr_preserve_access): Correct for pointer types.
(maybe_get_base_for_field_expr, core_access_index_map,
core_access_clean, core_is_access_index, core_mark_as_access_index):
Remove.
(make_gimple_core_safe_access_index): Remove function.
(struct walker_data): New struct to pass data to tree walker.
(callback_should_do_core_access, should_do_core_access): Add
function to identify expressions that should not be converted to
CO-RE.
(core_make_builtins): Add callback tree walker function to
convert expressions to CO-RE.
(callback_find_next_split_location, core_should_split_expr,
find_next_split_location, gimple_core_early_split_expr): Add
function to split expressions in CO-RE and non-CO-RE
expressions.
(execute_lower_bpf_core): Adapt to new code.
* config/bpf/bpf.opt: Add option Wco-re.
* doc/invoke.texi: Add documentation for Wco-re.
2026-02-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/110091
* ipa-split.cc (split_function): Find the bb
which is used for return in the outlined function.
Move the clobbers that are at the end of that bb
to be after the new call.
2026-02-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/110091
* ipa-split.cc (split_function): Split after
the clobbers/debug stmts rather than after the labels.
2026-02-25 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (spaceshipsi4):
New RTL generation pattern.
2026-02-25 Richard Biener <rguenther@suse.de>
PR target/120234
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
For constructor elements always look through a conversion.
Rewrite load and vector extraction matching to be more obvious.
Allow arbitrary conversions from the vector extract to elide
costing of a gpr<->xmm move.
2026-02-25 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/123285
* config/aarch64/aarch64-early-ra.cc (early_ra::form_chains): Process clobbers
and ABI clobbers before starting to form the chain.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* Makefile.in (ATTR_URLS_HTML_DEPS): Point at new index file.
* attr-urls.def: Regenerated.
* gcc-attribute-urlifier.cc (test_attribute_urlifier): Adjust
URLs to match formatting in the new index.
* regenerate-attr-urls.py (parse_html_line_attribute_index):
Update pattern to match formatting in the new combined index.
Don't segregate entries into separate function/variable/etc
arrays.
(INDEX_REL_PATH): Point at the new index file.
(class TestParsingIndex): Update patterns in self-tests to match
the current formatting.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* doc/extend.texi (Common Attributes): Change @cindex entries for
attributes to @atindex. Add some additional @cindex entries.
(AArch64 Attributes): Likewise.
(AMD GCN Attributes): Likewise.
(ARC Attributes): Likewise.
(ARM Attributes): Likewise.
(AVR Attributes): Likewise.
(Blackfin Attributes): Likewise.
(BPF Attributes): Likewise.
(C-SKY Attributes): Likewise.
(Epiphany Attributes): Likewise.
(H8/300 Attributes): Likewise.
(IA-64 Attributes): Likewise.
(LoongArch Attributes): Likewise.
(M32C Attributes): Likewise.
(M32R/D Attributes): Likewise.
(m68k Attributes): Likewise.
(MicroBlaze Attributes): Likewise.
(Microsoft Windows Attributes): Likewise.
(MIPS Attributes): Likewise.
(MSP430 Attributes): Likewise.
(NDS32 Attributes): Likewise.
(Nvidia PTX Attributes): Likewise.
(PowerPC Attributes): Likewise.
(RISC-V Attributes): Likewise.
(RL78 Attributes): Likewise.
(RX Attributes): Likewise.
(S/390 Attributes): Likewise.
(SH Attributes): Likewise.
(Symbian OS Attributes): Likewise.
(V850 Attributes): Likewise.
(Visium Attributes): Likewise.
(x86 Attributes): Likewise.
(Xstormy16 Attributes): Likewise.
(C++ Attributes): Likewise.
* doc/gcc.texi: Define a new "at" index for attributes.
(Attribute Index): New appendix.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* doc/extend.texi (Common Attributes): Document the "naked"
attribute here.
(ARC Attributes): Delete entry for "naked".
(ARM Attributes): Likewise.
(AVR Attributes): Likewise.
(BPF Attributes): Likewise.
(C-SKY Attributes): Likewise.
(MCORE Attributes): Delete entire section since "naked" was
the only thing listed.
(MSP430 Attributes): Delete entry for "naked".
(NDS32 Attributes): Likewise.
(RISC-V Attributes): Likewise.
(RL78 Attributes): Likewise.
(RX Attributes): Likewise.
(x86 Attributes): Likewise.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* doc/extend.texi (Common Attributes): Consolidate documentation
for "cold" and "hot" attributes, including the C++-specific
behavior.
(C++ Attributes): Likewise, just point to the main entry.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (RISC-V Attributes): Format and index options
for the "target" attribute consistently with the documentation
for other back ends.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Common Attributes): Add LoongArch to lists of
targets supporting target_clones and target_version.
(LoongArch Attributes): Copy-edit for grammar and markup. Wrap
excessively long lines. Rearrange the introductory material for
the target attribute. Correct index entries for target attribute
options.
(Function Multiversioning): Add LoongArch to list of targets
supporting this feature. Fix nearby typo.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (AArch64 Attributes): Reorganize material in this
section, correct terminology and formatting.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Attributes): General copy-editing.
(C++ Attributes): Likewise.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* doc/extend.texi (Attributes): Start each attribute's
documentation with a short paragraph describing what it applies to.
(C++ Attributes): Likewise.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR other/88472
* doc/extend.texi (Attributes): Merge respective subsections of
Function Attributes, Variable Attributes, Type Attributes,
Label Attributes, Enumerator Attributes, and Statement Attributes
into new sections Common Attributes and Target-Specific Attributes.
Fix cross-references.
* doc/invoke.texi: Fix cross-references.
* doc/trouble.texi: Likewise.
2026-02-24 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/102397
* doc/extend.texi (Attributes): Rewrite and expand discussion
of standard vs legacy syntax, with several examples.
(Attribute Syntax): Rename section to...
(GNU Attribute Syntax): ...this. Prune discussion of standard
attribute syntax. Fix cross-references.
2026-02-24 Robin Dapp <rdapp@oss.qualcomm.com>
* config/riscv/vector.md: Change 'X' to 'r' in _lra insns.
2026-02-24 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/124147
* config/riscv/autovec.md: Work around fractional-LMUL modes for
TARGET_XTHEADVECTOR.
* config/riscv/riscv-protos.h (get_m1_mode): Export.
* config/riscv/riscv-v.cc (get_m1_mode): Allow to get a VLS m1
vector.
2026-02-24 Robin Dapp <rdapp@oss.qualcomm.com>
PR rtl-optimization/123381
* lra-constraints.cc (process_alt_operands): Detect cycles in
three-operand moves with clobber.
(curr_insn_transform): Don't write back a scratch operand.
2026-02-24 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/121240
* config/aarch64/aarch64-simd.md (mov<mode>): Expand vector constants
early.
* config/aarch64/aarch64.cc (aarch64_select_rtx_section): Force
vector immediates <= 16 bytes to constdata.
2026-02-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/123117
PR target/120234
* tree-ssa-forwprop.cc (simplify_vector_constructor): Fix
sign conversion check guarding unpacking.
2026-02-24 Martin Jambor <mjambor@suse.cz>
PR ipa/123629
* ipa-cp.cc (ipcp_val_replacement_ok_p): Also verify that the
vector of known contexts has sufficient length.
2026-02-23 Sandra Loosemore <sloosemore@baylibre.com>
PR translation/118988
* params.opt (-param=cycle-accurate-model=): Fix wording of help
string.
(-param=phiopt-factor-max-stmts-live=): Likewise.
2026-02-23 Sandra Loosemore <sloosemore@baylibre.com>
* config/gcn/gcn.md (addsi3): Disparage vector alternative.
(addptrdi3): Reverse order of vector and scalar alternatives
to prefer the latter.
(subsi3): Disparage vector alternatives.
(mulsi3): Likewise.
(muldi3): Likewise.
(bitunop <expander>si2): Likewise.
(vec_and_scalar_com <expander>si3): Likewise.
(vec_and_scalar_nocom <expander>si3): Likewise.
(one_cmpldi2): Likewise.
(vec_and_scalar64_com <expander>di3): Likwise.
(vec_and_scalar64_nocom <expander>di3): Likwise.
2026-02-23 Paul-Antoine Arras <parras@baylibre.com>
PR fortran/120505
* gimplify.cc (omp_accumulate_sibling_list): When the containing struct
is a Fortran array descriptor, sort mapped components by offset.
2026-02-23 Paul-Antoine Arras <parras@baylibre.com>
PR fortran/120505
* gimplify.cc (omp_mapped_by_containing_struct): Handle Fortran array
descriptors.
(omp_build_struct_sibling_lists): Allow attach_detach bias to be
adjusted on non-target regions.
(gimplify_adjust_omp_clauses): Remove GIMPLE-only nodes.
* tree-pretty-print.cc (dump_omp_clause): Handle
OMP_CLAUSE_MAP_SIZE_NEEDS_ADJUSTMENT and OMP_CLAUSE_MAP_GIMPLE_ONLY.
* tree.h (OMP_CLAUSE_MAP_SIZE_NEEDS_ADJUSTMENT,
OMP_CLAUSE_MAP_GIMPLE_ONLY): Define.
2026-02-23 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Remove +sme+nosve sorry, and remove SVE from nosme workaround.
* doc/invoke.texi: Remove SVE2 requirement from +sme.
2026-02-23 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Replace TARGET_SVE{2} with explicit feature flag checks.
* config/aarch64/aarch64.cc
(aarch64_adjust_generic_arch_tuning): Add SME to SVE2 check.
* config/aarch64/aarch64.h (TARGET_SVE): Adjust condition.
(TARGET_SVE2): Ditto.
2026-02-23 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sme.md (UNSPEC_GET_CURRENT_VG): New
enum value.
(aarch64_get_current_vg): New insn.
* config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
__arm_get_current_vg if cntd is unavailable.
2026-02-22 Roger Sayle <roger@nextmovesoftware.com>
PR c/123716
* tree.cc (tree_nop_conversion_p): Move sanity checks on
inner_type to here...
(tree_nop_conversion): ... from here.
2026-02-22 Nathaniel Shead <nathanieloshead@gmail.com>
PR c++/120974
* gcc.cc (join_spec_func): Escape special characters.
2026-02-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (constantsynth_pass1):
Add the case where the assignment destination is a stack pointer
to the exclusion criteria for processing.
2026-02-21 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/123994
* rtl-ssa/changes.cc (function_info::verify_insn_changes): Bullet
proof loop to not fault if we run off the end of the insn chain.
2026-02-21 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124147
* config/riscv/riscv.cc (riscv_same_function_versions): Use nullptr_t rather
than UNKNOWN_LOCATION for pointer argument.
2026-02-20 Kwok Cheung Yeung <kcyeung@baylibre.com>
PR middle-end/113436
* omp-low.cc (omp_lower_target): Do not check for variable-length
variables in private clauses by reference when allocating memory.
2026-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/124068
* tree-vect-patterns.cc (target_has_vecop_for_code): Move
earlier, add defaulted optab_subtype parameter.
(vect_recog_over_widening_pattern): Check that the target
supports the narrowed operation before committing to the
pattern.
2026-02-20 Martin Jambor <mjambor@suse.cz>
PR ipa/122856
* ipa-cp.cc (self_recursive_pass_through_p): Test jump function type first.
(self_recursive_ancestor_p): New function.
(find_scalar_values_for_callers_subset): Test also for self-recursive
ancestor jump functions.
(push_agg_values_for_index_from_edge): Likewise.
2026-02-20 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/121103
* gimple-fold.cc (gimple_fold_call): Don't simplify
noreturn functions.
* tree-ssa-dse.cc (dse_optimize_stmt): Don't handle
calls to noreturn functions.
2026-02-19 jlaw <jeffreyalaw@gmail.com>
PR tree-optimization/124108
* match.pd (reassociating XOR to expose rotations): Check
type_has_mode_precision_p before simplifying.
2026-02-19 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.cc (avx_vpermilp_parallel): Use IN_RANGE
macro.
2026-02-19 Pan Li <pan2.li@intel.com>
* config/riscv/autovec-opt.md (*literal_v<ieee_fmaxmin_op>_vf_<mode>):
Add new pattern for vfmax/min combine to fx.
2026-02-18 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/116053
* regcprop.cc (copyprop_hardreg_forward_1): Use delete_insn_and_edges
instead of delete_insn.
2026-02-18 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/120169
* lra-int.h (lra_process_new_insns): Modify the prototype.
* lra.cc (lra_process_new_insns): Add arg fixup_reg_args_size with
implicit value. Move REG_ARGS_SIZE note if necessary.
* lra-constraints.cc (curr_insn_transform): Pass the new arg value.
2026-02-18 Richard Biener <rguenther@suse.de>
PR target/123137
* config/i386/i386-features.cc (ix86_emit_tls_call): Improve
local FLAGS_REG liveness calculation.
2026-02-18 Jakub Jelinek <jakub@redhat.com>
PR target/124138
* config/i386/i386.cc (avx_vpermilp_parallel): Verify
ipar[2] and ipar[3] aren't larger than 3.
2026-02-18 H.J. Lu <hjl.tools@gmail.com>
PR target/124098
* config/i386/i386.cc (ix86_access_stack_p): New.
(ix86_find_max_used_stack_alignment): Update stack alignment only
if stack is used.
2026-02-17 H.J. Lu <hjl.tools@gmail.com>
PR target/124136
* config/i386/i386-features.cc (ix86_check_flags_reg): Don't
mark clobbered FLAGS_REG as live.
2026-02-17 Richard Earnshaw <rearnsha@arm.com>
PR target/124134
* config/arm/arm.md (movsfcc): FAIL if using restricted IT
blocks and we lack VSEL.
(movdfcc): Likewise.
2026-02-17 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/124048
* config/riscv/zicond.md (conditional AND patterns): Fix missed
flipping the condition's test in RTL output.
2026-02-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/124130
* tree-inline.cc (copy_edges_for_bb): Fixup noreturn calls
with abnormal edge source.
2026-02-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/124132
* tree-ssa-loop-split.cc (compute_new_first_bound): Fix
bound difference computation.
2026-02-17 Jakub Jelinek <jakub@redhat.com>
PR target/120233
* gimple-ssa-store-merging.cc (find_bswap_or_nop_2): New function.
(find_bswap_or_nop): Move CONSTRUCTOR handling to above function,
call it instead of find_bswap_or_nop_1.
(bswap_replace): Handle VEC_PACK_TRUNC_EXPR like CONSTRUCTOR.
(maybe_optimize_vector_constructor): Likewise.
(pass_optimize_bswap::execute): Likewise.
(get_status_for_store_merging): Likewise.
(pass_store_merging::execute): Likewise.
2026-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR libstdc++/113450
PR libstdc++/123176
* config/sol2.h (INT8_TYPE): Change to signed char.
(INT_LEAST8_TYPE): Likewise.
(INT_FAST8_TYPE): Likewise.
2026-02-15 Iain Sandoe <iain@sandoe.co.uk>
* json.cc (pointer::token::print): Cast the value to pp_scalar
with (fmt_size_t).
2026-02-15 Jan Hubicka <hubicka@ucw.cz>
* ipa-devirt.cc (ipa_devirt): Improve statistics for multi-target
devirtualization; do not simple-call devirtualize already devirtualized calls.
2026-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac <sparc*-*-*> (gcc_cv_as_sparc_fmaf): Remove.
(gcc_cv_as_sparc_sparc4): Remove.
(gcc_cv_as_sparc_sparc): Remove.
(gcc_cv_as_sparc_sparc6): Remove.
* configure: Regenerate.
* config.in: Regenerate.
* config/sparc/sparc.h (AS_NIAGARA3_FLAG) Remove. Replace uses by
definition.
(AS_NIAGARA4_FLAG): Likewise.
(AS_NIAGARA7_FLAG): Likewise.
(AS_M8_FLAG): Likewise.
* config/sparc/sol2.h [!HAVE_AS_SPARC4]: Remove.
(AS_SPARC32_FLAG): Remove.
(AS_SPARC64_FLAG): Remove.
(AS_NIAGARA3_FLAG) Replace uses by definition.
(AS_NIAGARA4_FLAG): Likewise.
(AS_NIAGARA7_FLAG): Likewise.
(AS_M8_FLAG): Likewise.
* config/sparc/sparc.cc (sparc_option_override):
[!HAVE_AS_FMAF_HPC_VIS3]: Remove.
[!HAVE_AS_SPARC4]: Likewise.
[!HAVE_AS_SPARC5_VIS4]: Likewise.
[!HAVE_AS_SPARC6]: Likewise.
2026-02-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124099
* tree-ssa-forwprop.cc (optimize_agr_copyprop_return): Don't do anything
if the return is already result decl or a deference of result decl.
Also reject non local var decls.
2026-02-14 Jakub Jelinek <jakub@redhat.com>
PR cobol/122839
* doc/install.texi (COBOL-Specific Options): New.
2026-02-14 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac <sparc*-*-*> (gcc_cv_as_sparc_gotdata_op): Remove.
* configure: Regenerate.
* config.in: Regenerate.
* config/sparc/sparc.md [!HAVE_AS_SPARC_GOTDATA_OP]: Remove.
2026-02-14 Kalvis Duckmanton <kalvisd@gmail.com>
PR target/112400
* config/vax/vax.md (casesi1): Wrap naked operand 1 with a USE
where used with the insn split to.
(*casesi1): Likewise naked incoming operand 1.
2026-02-14 Maciej W. Rozycki <macro@orcam.me.uk>
* config/vax/vax.cc (nonindexed_address_p): Move incoming RTX's
operand 0 access to the actual use places.
2026-02-14 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/124086
* tree-complex.cc (extract_component): Extend the check
for ssa names for VCE to include invariants.
2026-02-13 David Malcolm <dmalcolm@redhat.com>
* json-parsing.cc (selftest::assert_json_pointer_eq): New.
(ASSERT_JSON_POINTER_EQ): New.
(selftest::test_parse_object): Add tests of JSON pointer.
(selftest::test_pointer_escaping): New test.
(selftest::json_parser_cc_tests): Call it.
* json.cc (json::pointer::token::print): New.
(json::value::print_pointer): New.
* json.h (json::pointer::token::print): New decl.
(json::value::print_pointer): New decl.
* libsarifreplay.cc: Include pretty-print.h.
(make_logical_location_from_jv): Use
json::pointer::token::print for short_name.
2026-02-13 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/124079
* lra-constraints.cc (get_matching_reload_reg_subreg): Add new arg
rclass. Use another condition to use lowpart_subreg. Use lra_constraint_offset
to calculate the subreg offset.
(get_reload_reg, match_reload): Pass the new arg.
2026-02-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/95825
* tree-ssa-forwprop.cc (optimize_agr_copyprop_return): New function.
(optimize_agr_copyprop): Call optimize_agr_copyprop_return
for return statements.
2026-02-13 David Malcolm <dmalcolm@redhat.com>
PR diagnostics/124014
* diagnostics/html-sink.cc (html_builder::get_logical_loc_mgr):
New.
(html_builder::m_logical_loc_mgr): Drop field.
(html_builder::html_builder): Drop initialization of
m_logical_loc_mgr.
(html_builder::maybe_make_state_diagram): Use get_logical_loc_mgr
rather than m_logical_loc_mgr.
(html_builder::make_element_for_diagnostic): Likewise.
2026-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/99959
* tree-sra.cc (create_access_replacement): Guard DECL_NONLOCAL_FRAME
access.
2026-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/99959
* tree-sra.cc (create_access_replacement): Always create
debug expressions for DECL_NONLOCAL_FRAME bases.
2026-02-13 Dhruv Chawla <dhruvc@nvidia.com>
* Makefile.in (all.fda): Bump profile_merger gcov_version to 3.
2026-02-12 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_reduce_compare): Add forcing the first
operand to be a register, unless the second operand is 0, to scope.
* config/cris/cris.md ("*cstore<mode><code>4")
("*cbranch<mode><code>4"): Add guards to condition, for either operand
to be a register unless the last operand is zero.
2026-02-12 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (BWDSF): New mode_iterator replacing SISF.
All callers changed.
("*movhi_internal<setcc><setnz><setnzvc>"): Anonymized from
"<acc><anz><anzvc>movhi<setcc><setnz><setnzvc>" to make it a
match-only pattern. Add conditions to guard from source and
destination both being memory operands.
("*movstricthi_internal", "*movstrictqi_internal"): Similarly
for "movstricthi" and "movstrictqi".
("movstrict<mode>"): Add common expander for BW, forcing one operand
to be a register or source being zero.
2026-02-12 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (SISF): New mode_iterator for SI and SF.
("mov<mode>"): Make "movsi" a define_expand to include SFmode by
means of the SISF iterator and adjust to also handle SFmode.
("*movsf_internal"): Anonymize "movsf"; make it a match-only pattern.
Add conditions to guard from source and destination both being memory
operands.
2026-02-12 Kwok Cheung Yeung <kcyeung@baylibre.com>
PR middle-end/113436
* omp-low.cc (is_variable_sized): Add extra is_ref argument. Check
referenced type if true.
(lower_omp_target): Call lower_private_allocate to generate code to
allocate memory for firstprivate/private clauses with allocators, and
insert code after dependent variables have been initialized.
Construct calls to free allocate memory and insert after target block.
Adjust decl values for clause variables. Copy value of firstprivate
variables to allocated memory.
2026-02-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/124062
* ifcvt.cc (noce_try_cond_arith): Check the conditional code
for UNKNOWN.
2026-02-12 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/aarch64-json-schema.h: Include inherited members for
SVE vector costs.
* config/aarch64/aarch64-json-tunings-parser-generated.inc
(parse_vec_costs_sve): Regenerate.
* config/aarch64/aarch64-json-tunings-parser.cc
(aarch64_load_tuning_params_from_json_string): Clear dispatch scheduling
flag if dispatch_constraints is NULL.
* config/aarch64/aarch64-json-tunings-printer-generated.inc
(serialize_vec_costs_sve): Regenerate.
2026-02-11 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/121191
* lra-constraints.cc (get_matching_reload_reg_subreg): New.
(get_reload_reg, match_reload): Use it.
2026-02-11 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/124038
* tree-ssa-math-opts.cc (strip_nop_view_converts): Remove.
(convert_mult_to_fma): Undo stripping.
2026-02-11 Jakub Jelinek <jakub@redhat.com>
PR middle-end/124056
* cfgexpand.cc (expand_asm_stmt): If after_md_seq is non-NULL, emit
it at the start of after_rtl_seq instead of after fallthru_label.
2026-02-11 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/116600
PR middle-end/123386
* cfgrtl.cc (force_nonfallthru_and_redirect): Don't do any
asm goto adjustments early, only note in asm_goto_edge if
any labels point originally to e->dest head. After jumpblock
creation don't add an extra edge for asm_goto_edge, instead
adjust those labels pointing to former e->dest head to point
to jumpblock instead.
2026-02-10 Dimitry Andric <dimitry@andric.com>
PR libfortran/123366
* configure.ac: Move restoring of CXXFLAGS/LDFLAGS for zstd test to
the correct place.
* configure: Regenerate.
2026-02-10 Alice Carlotti <alice.carlotti@arm.com>
PR target/123624
* config/aarch64/aarch64-protos.h
(aarch64_use_simple_return_insn_p): New.
* config/aarch64/aarch64.cc
(aarch64_use_simple_return_insn_p): New, used...
* config/aarch64/aarch64.md (simple_return): ...here.
2026-02-10 Alice Carlotti <alice.carlotti@arm.com>
* config.gcc: Improve aarch64 --with-arch checks.
2026-02-10 Alfie Richards <alfie.richards@arm.com>
* tree-vect-data-refs.cc (vect_analyze_data_refs_alignment):
Update signature and comment.
* tree-vect-loop.cc (vect_analyze_loop_2): Update comment for
vect_analyze_data_refs_alignment and remove control flow.
* tree-vectorizer.h (vect_analyze_data_refs_alignment): Update
signature.
2026-02-10 Juergen Christ <jchrist@linux.ibm.com>
PR tree-optimization/122297
* tree-vect-loop.cc (vectorize_fold_left_reduction): Adjust.
(vectorizable_induction): Adjust.
(vectorizable_live_operation_1): Adjust.
(vect_get_loop_len): Provide parameter to select bias-adjusted
length.
(vect_gen_loop_len_mask): Adjust.
(vect_update_ivs_after_vectorizer_for_early_breaks): Adjust.
* tree-vect-stmts.cc (vect_get_strided_load_store_ops): Adjust.
(vectorizable_call): Adjust.
(vectorizable_operation): Adjust.
(vectorizable_store): Adjust.
(vectorizable_load): Adjust.
(vectorizable_condition): Adjust.
* tree-vectorizer.h (vect_get_loop_len): Add parameter.
2026-02-10 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/tuning_models/olympus.h (olympus_sve_vector_cost):
Set align_load_cost to 6.
2026-02-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/107690
* tree-ssa-ifcombine.cc (ifcombine_ifandif): Do not merge
possibly analyzable exit conditions.
2026-02-09 David Malcolm <dmalcolm@redhat.com>
PR diagnostics/124014
* diagnostics/sarif-sink.cc
(sarif_builder::get_logical_location_manager): Reimplement, to
eliminate m_logical_loc_mgr.
(sarif_builder::m_logical_loc_mgr): Drop field.
(sarif_builder::sarif_builder): Update for removed field.
(sarif_builder::set_any_logical_locs_arr): Likewise.
(sarif_builder::ensure_sarif_logical_location_for): Likewise.
(sarif_builder::make_minimal_sarif_logical_location): Likewise.
2026-02-09 David Faust <david.faust@oracle.com>
PR target/123556
* config/bpf/bpf.h (SLOW_BYTE_ACCESS): Set to 0, update comment.
2026-02-09 Eric Botcazou <ebotcazou@adacore.com>
PR target/80881
* attribs.cc (handle_dll_attribute): If TARGET_WIN32_TLS is 1,
issue an error if either attribute is set on a TLS variable.
2026-02-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR other/123841
PR target/123926
* acinclude.m4 (gcc_GAS_FLAGS): Handle non-Darwin/Solaris as cases
alike on x86 and SPARC.
* configure: Regenerate.
2026-02-09 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/123796
* lra-int.h (lra_pointer_equiv_set_add): Add prototype.
(lra_pointer_equiv_set_in, lra_finish_equiv): Ditto.
* lra.cc (lra_emit_move): Set up pointer flag of the destination
if necessary.
(lra): Call lra_finish_equiv.
* lra-constraints.cc: Include hash-set.h.
(pointer_equiv_set, lra_pointer_equiv_set_add): New.
(lra_pointer_equiv_set_in, lra_finish_equiv): New.
(get_equiv_with_elimination): Propagate pointer flag by adding to
pointer_equiv_set.
(process_addr_reg, curr_insn_transform): Ditto.
2026-02-09 Richard Biener <rguenther@suse.de>
* doc/analyzer.texi (State Tracking): Fix typo.
2026-02-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/123225
* tree-vect-loop.cc (vect_analyze_loop_costing): For uncounted
loops reject not trivially profitable loops that have no
estimate on the number of scalar iterations.
2026-02-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/124034
* tree-vect-stmts.cc (process_use): Never force induction
latch defs relevant when doing early break vectorization.
2026-02-09 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* doc/invoke.texi (-mconst16/-mno-const16):
Remove the clause "The CONST16 instruction is currently not a
standard option from Tensilica."
2026-02-09 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/117217
* tree-sra.cc (propagate_subaccesses_from_rhs): Do not propagate
bit-field children.
(propagate_subaccesses_from_lhs): Likewise.
2026-02-09 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123911
* config/riscv/riscv.cc (riscv_legitimize_move): Elide nop moves to
avoid infinite recursion.
2026-02-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123672
* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq): Use std::swap
instead of fetching gimple_assign_rhs{1,2} again. Change type of lanes
vector from auto_vec<unsigned int> to auto_vec<bool> and store true
instead of 1 into it. Fix comment typo and formatting fix.
(can_blend_vec_perm_simplify_seqs_p): Put end of comment on the same
line as the last sentence in it.
(calc_perm_vec_perm_simplify_seqs): Change lane_assignment type from
auto_vec<int> to auto_vec<unsigned> and store 2 + l_orig into it
instead of true. Fix comment typo and formatting fix. Set use_seq1
to line_assignment[i] < 2 instead of line_assignment[i] != 2. Replace
bogus computation of index for !use_seq with using
line_assignment[i] - 2. Set l1 to l1 % nelts and similarly for l2.
2026-02-07 Jakub Jelinek <jakub@redhat.com>
* optabs.cc (expand_vec_perm_const): Comment spelling fix,
permuation -> permutation.
* config/arm/arm.cc (arm_evpc_neon_vtbl): Likewise.
* config/loongarch/loongarch.cc (loongarch_try_expand_lsx_vshuf_const):
Comment spelling fix, permuatation -> permutation.
(loongarch_is_elem_duplicate): Likewise. Comment spelling fix,
permuation -> permutation.
2026-02-07 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Remove double and triple accounting of GPR -> XMM moves
in construction of AVX and AVX512 vectors.
2026-02-07 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* cse.cc (invalidate_from_sets_and_clobbers): Consider any hard
register referred to by any single register constraint
potentially being clobbered.
2026-02-07 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/123826
PR tree-optimization/123958
PR c++/124002
* tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children):
Delete code that (mis)handled conversion of pow(x,2.0) to x*x.
2026-02-07 Roger Sayle <roger@nextmovesoftware.com>
Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/123833
* recog.cc (cancel_changes): Update the recog_data cache if it
holds the instruction being changed.
2026-02-06 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): Add ptr and generic variants.
(aarch64_init_pcdphint_builtins): Likewise.
(aarch64_general_expand_builtin): Add ptr variant.
(aarch64_resolve_overloaded_builtin_stshh): Function to handle
overloaded atomic_store_with_stshh.
(aarch64_resolve_overloaded_builtin_general): Add call to stshh function.
* config/aarch64/aarch64-c.cc
(aarch64_resolve_overloaded_builtin): Allow fndecl to return.
* config/aarch64/arm_acle.h
(__atomic_store_with_stshh): Remove __Generic.
2026-02-06 Martin Jambor <mjambor@suse.cz>
PR ipa/106260
* ipa-cp.cc (initialize_node_lattices): Replace assert that there are
callers with handling that situation when -fno-toplevel_reorder.
2026-02-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gnu_ld_flag): Move $gcc_cv_ld --version check into
AC_ARG_WITH(gnu-ld).
(gcc_cv_ld): Set before gnu_ld_flag.
(gas_flag): Move $gcc_cv_ld --version check into AC_ARG_WITH(gnu-ld).
(gcc_cv_as): Set before gas_flag.
* configure: Regenerate.
2026-02-06 Jakub Jelinek <jakub@redhat.com>
PR c/101312
* alias.cc (get_alias_set): Allow TYPE_CANONICAL (mv) to be
not its own TYPE_MAIN_VARIANT, as long as its TYPE_MAIN_VARIANT
has TYPE_CANONICAL equal to itself.
* tree.cc (verify_type): Likewise.
2026-02-06 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/114969
* match.pd (`(A | (convert?)(A != 0)) EQ|NE 0`): New pattern.
2026-02-06 Andrew Stubbs <ams@baylibre.com>
* config/gcn/gcn-valu.md (*mov<mode>_exec_match): Delete.
(*mov<mode>_exec_match): Likewise.
(*mov<mode>): Delete unaligned register support, and convert to new
constraint syntax.
(mov<mode>_exec): Likewise.
(@mov<mode>_sgprbase): Likewise.
* config/gcn/gcn.md (*movbi): Likewise.
2026-02-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/114274
* tree-switch-conversion.cc (switch_conversion::build_one_array):
Use UNKNOWN_LOCATION for the CSWTCH decl.
2026-02-06 Jakub Jelinek <jakub@redhat.com>
PR c++/123977
* tree.cc (build_function_type): Pass no_named_args_stdarg_p
as last argument to recursive call.
2026-02-06 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123940
* tree-ssa-math-opts.cc (convert_mult_to_fma): Check
multiplication result is an addend.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* attribs.cc: Replace CONST_CAST with const_cast<>.
* builtins.cc: Likewise.
* collect2.cc: Likewise.
* config/bpf/core-builtins.cc: Likewise.
* config/gcn/mkoffload.cc: Likewise.
* config/nvptx/mkoffload.cc: Likewise.
* config/nvptx/nvptx.cc: Likewise.
* ctfc.cc: Likewise.
* dumpfile.cc: Likewise.
* gcc.cc: Likewise.
* gcov.cc: Likewise.
* gengtype-parse.cc: Likewise.
* gengtype-state.cc: Likewise.
* gengtype.cc: Likewise.
* genoutput.cc: Likewise.
* ggc-page.cc: Likewise.
* godump.cc: Likewise.
* lto-section-in.cc: Likewise.
* lto-wrapper.cc: Likewise.
* omp-offload.cc: Likewise.
* passes.cc: Likewise.
* plugin.cc: Likewise.
* prefix.cc: Likewise.
* pretty-print.cc: Likewise.
* selftest.cc: Likewise.
* statistics.cc: Likewise.
* stringpool.cc: Likewise.
* tree.h: Likewise.
* tree-profile.cc: Likewise.
* vec.h: Likewise.
* system.h (CONST_CAST2): Remove.
(CONST_CAST): Likewise.
* tsystem.h (CONST_CAST2): Remove.
(CONST_CAST): Likewise.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* tree.h: Replace CONST_CAST2 with const_cast<>.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* attribs.cc: Replace CONST_CAST_TREE with const_cast<tree>.
* config/aarch64/aarch64.cc: Likewise.
* config/arm/arm.cc: Likewise.
* config/darwin.cc: Likewise.
* fold-const.cc: Likewise.
* gimple-expr.cc: Likewise.
* print-rtl.cc: Likewise.
* tree-object-size.cc: Likewise.
* tree.cc: Likewise.
* varasm.cc: Likewise.
* tree.h: Likewise.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* gimple.h: Replace CONST_CAST_GIMPLE with const_cast<gimple *>.
* system.h (CONST_CAST_GIMPLE): Remove.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* system.h: Remove.
* tracer.cc: Replace CONST_CAST_BB with
const_cast<basic_block>.
* tree-cfg.cc: Likewise.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* alias.cc: Replace CONST_CAST_RTX with const_cast<rtx>.
* config/i386/x86-tune-sched-bd.cc: Likewise.
* config/rs6000/rs6000.cc: Likewise.
* recog.cc: Likewise.
* sel-sched-ir.cc: Likewise.
* var-tracking.cc: Likewise.
* varasm.cc: Likewise.
* system.h (CONST_CAST_RTX): Remove.
2026-02-06 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* config/aarch64/aarch64.cc: Replace CONST_CAST_RTX_INSN with
const_cast<struct rtx_insn *>.
* rtlanal.cc: Likewise.
* sched-deps.cc: Likewise.
* system.h (CONST_CAST_RTX_INSN): Remove.
2026-02-05 David Malcolm <dmalcolm@redhat.com>
* value-range.cc (irange_bitmask::irange_bitmask): Fix typo in
comment.
* value-range.h (class vrange): Update leading comment to refer
to "subsets" rather than "ranges". Allude to the available
subclasses. Warn that the classes can be over-approximations and
thus can introduce imprecision.
(class irange_bitmask): Updating leading comment to refer to
knowledge about a "value", rather than a "range". Reword
description of MASK and VALUE to clarify implementation, and
add an example.
(class irange): Update leading comment to refer to a
"subset of possible values" rather than a "range", and
that subclasses have responsibility for storage.
(class nan_state): Rewrite leading comment.
(class frange final): Update leading comment to refer to
subsets of possible values, rather than ranges, and to
consistently use "Nan" when capitalizing.
2026-02-05 Michal Jires <mjires@suse.cz>
PR testsuite/123559
* cgraphunit.cc (check_global_declaration): Suppress OPT_Wunused.
2026-02-05 Jakub Jelinek <jakub@redhat.com>
Revert:
2026-01-28 Jakub Jelinek <jakub@redhat.com>
PR c/101312
* langhooks.h (struct lang_hooks_for_types): Remove
copy_lang_qualifiers. Add build_lang_qualified_type.
* langhooks.cc (lhd_build_lang_qualified_type): New function.
* langhooks-def.h (lhd_build_lang_qualified_type): Declare.
(LANG_HOOKS_COPY_LANG_QUALIFIERS): Remove.
(LANG_HOOKS_BUILD_LANG_QUALIFIED_TYPE): Add.
(LANG_HOOKS_FOR_TYPES_INITIALIZER): Use
LANG_HOOKS_BUILD_LANG_QUALIFIED_TYPE instead of
LANG_HOOKS_COPY_LANG_QUALIFIERS.
* attribs.cc (build_type_attribute_qual_variant): Use
lang_hooks.types.build_lang_qualified_type instead of
build_qualified_type and/or build_qualified_type with
optional lang_hooks.types.copy_lang_qualifiers call.
(attr_access::array_as_string): Use "array " attribute instead of
"array". If attribute has been created or intended quals differ
from quals of build_array_type, use copy_node and adjust quals and
attributes on the copy, print and then ggc_free.
2026-02-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/123986
* tree-vect-slp.cc (vect_slp_analyze_operations): When
rolling back analyzed nodes, release node specific data
and reset SLP_TREE_TYPE.
2026-02-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/123983
* tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer):
Only update the PHI argument on the requested edge.
2026-02-05 Richard Earnshaw <rearnsha@arm.com>
PR target/123604
* compare-elim.cc (find_flags_uses_in_insn): Handle COND_EXEC.
* config/arm/arm.cc (TARGET_FLAGS_REGNUM): Define.
2026-02-05 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123978
* range-op.h (OP_WIDEN_MULT_SIGNED_UNSIGNED): Define.
(OP_WIDEN_PLUS_SIGNED, OP_WIDEN_PLUS_UNSIGNED,
RANGE_OP_TABLE_SIZE): Renumber.
* gimple-range-op.cc (imple_range_op_handler::maybe_non_standard):
Use 3 different classes instead of 2 for WIDEN_MULT_EXPR, one
for both operands signed, one for both operands unsigned and
one for operands with different signedness. In the last case
canonicalize to first operand signed second unsigned.
* range-op.cc (operator_widen_mult_signed::wi_fold): Use
TYPE_PRECISION (type) rather than wi::get_precision (whatever) * 2,
use SIGNED for all wide_int::from calls.
(operator_widen_mult_unsigned::wi_fold): Similarly but use UNSIGNED
for all wide_int::from calls.
(class operator_widen_mult_signed_unsigned): New type.
(operator_widen_mult_signed_unsigned::wi_fold): Define.
2026-02-05 Jan Hubicka <hubicka@ucw.cz>
PR ipa/123226
* cgraph.cc (cgraph_update_edges_for_call_stmt_node): Fix handling
of multi-target speculations resolved at clone materialization time
2026-02-05 xiezhiheng <xiezhiheng@huawei.com>
liyunfei <liyunfei33@huawei.com>
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add hip12 core
* config/aarch64/aarch64-cost-tables.h: Add hip12_extra_costs
* config/aarch64/aarch64-tune.md: Regenerate
* config/aarch64/aarch64.cc: Include hip12 tuning model
* doc/invoke.texi: Document -mcpu=hip12
* config/aarch64/tuning_models/hip12.h: New file.
2026-02-05 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123870
PR target/123969
* config/riscv/vector.md: Add vlds to "no ratio" for
theadvector.
2026-02-05 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123971
* config/riscv/riscv.cc (riscv_vector_mode_supported_any_target_p):
Remove TARGET_XTHEADVECTOR.
2026-02-05 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123925
* tree-ssa-forwprop.cc (simplify_vector_constructor):
Add nop-conversion handling for maybe_ident.
2026-02-05 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123910
* config/riscv/riscv-string.cc (riscv_expand_block_move):
Remove !xtheadvector guard.
(use_vector_stringop_p): Guard small LMULs.
(check_vectorise_memory_operation): Ditto.
2026-02-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/121726
* tree-sra.cc (build_ref_for_offset): Add force_ref_all
parameter and use ptr_type_node as alias pointer type in
that case.
(build_ref_for_model): Add force_ref_all parameter and
pass it through, forcing build_ref_for_offset.
(generate_subtree_copies): Likewise.
(sra_modify_call_arg): Force ref-all accesses.
2026-02-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/123898
* tree-ssa-math-opts.cc (strip_nop_view_converts): New.
(convert_mult_to_fma): Use it.
2026-02-05 Alexandre Oliva <oliva@adacore.com>
* simplify-rtx.cc (negated_ops_p): New.
(simplify_context::simplify_binary_operation_1): Use it.
2026-02-05 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-opts.h (VR2FPR_COST_UNPROVIDED): Add new
sentinel for unprovided cost.
* config/riscv/riscv-protos.h (get_vr2fr_cost): Add new func
decl.
* config/riscv/riscv-vector-costs.cc (costs::adjust_stmt_cost):
Leverage new func to get cost of vr2fpr.
* config/riscv/riscv.cc (riscv_register_move_cost): Ditto.
(get_vr2fr_cost): Add new func to wrap access to the cost
of the vr2fpr.
* config/riscv/riscv.opt: Add new param vr2fpr-cost.
2026-02-05 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-opts.h (GPR2VR_COST_UNPROVIDED): Depend on
default unprovided value.
(FPR2VR_COST_UNPROVIDED): Ditto.
(VR2GPR_COST_UNPROVIDED): Ditto.
(COST_UNPROVIDED): Add new default unprovided value.
* config/riscv/riscv-protos.h (get_vr2gr_cost): Add new func
decl.
* config/riscv/riscv-vector-costs.cc (costs::adjust_stmt_cost):
Leverage new func to get cost of vr2gpr.
* config/riscv/riscv.cc (riscv_register_move_cost): Ditto.
(get_vr2gr_cost): Add new func to wrap access to the cost
of the vr2gpr.
* config/riscv/riscv.opt: Add new param vr2gpr-cost.
2026-02-04 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/123922
* lra-assigns.cc (lra_split_hard_reg_for): Allocate and free
update_hard_regno_preference_check. Clear non_reload_pseudos for
successful spilling too.
2026-02-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/121661
* tree-complex.cc (extract_component): Create gimple
assign statements directly rather than call force_gimple_operand_gsi.
2026-02-04 Sandra Loosemore <sloosemore@baylibre.com>
PR translation/89915
* doc/params.texi: Copy-edit text throughout the file.
* params.opt: Likewise in documentation strings.
2026-02-04 Sandra Loosemore <sloosemore@baylibre.com>
PR target/123245
PR translation/89915
* doc/invoke.texi (Warning Options): Remove discussion of parameters
from -Winterference-size documentation.
(Static Analyzer Options): Ditto for -Wanalyzer-symbol-too-complex,
the list of things the analyzer has specific knowledge of, and
-fanalyzer-call-summaries.
(Optimize Options): Ditto for -finline-limit and fipa-cp-clone.
(Instrumentation Options): Likewise for -fsanitize=kernel-hwaddress
and -fharden-control-flow-redundancy.
(C++ Compiled Module Interface): Likewise for discussion of limits
on number of open files.
2026-02-04 Sandra Loosemore <sloosemore@baylibre.com>
PR target/123245
PR translation/89915
* Makefile.in (TEXI_GCCINT_FILES): Add params.texi.
* doc/gccint.texi (pa): New index.
(Top): Add new Parameters and Parameters Index nodes to menu.
Include params.texi.
(Parameter Index): New.
* doc/invoke.texi (Option Summary): Move --param from Optimization
Options to Developer Options.
(Optimization Options): Move parameter documentation to params.texi.
(Developer Options): Add abbreviated discussion of --param here.
(LoongArch Options): Move parameter documentation to params.texi.
(RISC-V Options): Likewise.
(RS/6000 and PowerPC Options): Likewise.
* doc/params.texi: New file.
2026-02-04 Yangyu Chen <cyy@cyyself.name>
* config/riscv/riscv-target-attr.cc
(riscv_target_attr_parser::parse_arch): Fix nullptr dereference
when parsing invalid arch string.
2026-02-04 Jakub Jelinek <jakub@redhat.com>
PR c++/123818
* tree.cc (simple_cst_equal) <case CONSTRUCTOR>: Return -1 if some
recursive call returns -1. Also compare indexes.
2026-02-04 Jakub Jelinek <jakub@redhat.com>
PR middle-end/122689
* gimple-lower-bitint.cc (gimple_lower_bitint): For the PHI handling
if min_prec == prec, break after emitting assignment from c.
2026-02-04 Prachi Godbole <pgodbole@nvidia.com>
* params.opt: Change default param value.
2026-02-03 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR other/123841
* acinclude.m4 (gcc_GAS_FLAGS): Check $gas_flag, $gnu_ld_flag
instead of $gas, $gnu_ld.
* configure.ac: Likewise.
(gas_flag): Determine if not already set.
(gnu_ld_flag): Likewise.
(ld_32_opt): Only set after gnu_ld_flag is set.
(ld_64_opt): Likewise.
* configure: Regenerate.
2026-02-03 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR other/123841
* acinclude.m4 (gcc_GAS_FLAGS): Handle Darwin as cases separately.
* configure: Regenerate.
2026-02-03 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/118608
* expr.cc (store_field_updates_msb_p): New helper function that
now also handles BYTES_BIG_ENDIAN targets.
(expand_assignment): Use the above function when deciding to emit
a required sign/zero extension.
* rtlanal.cc (truncated_to_mode): Call targetm.mode_rep_extended
to check whether an explicit TRUNCATE is required (i.e. performs
an extension) on this target.
* config/mips/mips.md (*extenddi_truncate<mode>): Handle all
SUBDI modes, not just SHORT modes.
2026-02-03 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/123826
* tree-ssa-math-opts.cc (gimple_expand_builtin_pow): Add test
for flag_errno_math.
* fold-const-call.cc (fold_const_pow): Reorganize, eliminating
call to real_powi, and letting do_mpfr_arg2 do all the heavy
lifting.
2026-02-03 Alfie Richards <alfie.richards@arm.com>
PR target/123548
* config/aarch64/aarch64-builtins.cc
(aarch64_builtins): Rename AARCH64_PL<X> to
AARCH64_PREFETCH_PL<X>.
(aarch64_init_prefetch_builtin): Rename to...
(aarch64_init_prefetch_builtins): ...this and change builtin
names.
(AARCH64_INIT_PREFETCH_BUILTIN): Change to not add
"__builtin_aarch64__" prefix and to register builtins.
(handle_arm_acle_h): Add call to aarch64_init_prefetch_builtins.
(aarch64_init_pcdphint_builtins): Move __pldir code to init
prefetch builtins.
(aarch64_general_init_builtins): Remove call to
aarch64_init_prefetch_builtin.
(aarch64_expand_prefetch_builtin): Update names of PL<X>
builtins.`
* config/aarch64/arm_acle.h
(__pld): Remove
(__pli): Likewise.
(__plix): Likewise.
(__pldx): Likewise.
(__pldir): Likewise.
2026-02-03 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/123322
* combine.cc (try_combine): Consider an IF_THEN_ELSE "good" when
evaluating if 4 insn combinations should be tried.
* config/riscv/iterators.md (zero_is_neutral_op): New iterator.
(zero_is_neutral_op_c): Likewise.
(any_shift_rotate): Likewise.
* config/riscv/riscv.cc (riscv_rtx_costs): Recognize the conditional
AND RTL and cost is appropriately.
* config/riscv/zicond.md: Add patterns to rewrite general conditional
move sequences into simpler forms.
2026-02-03 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac (gcc_cv_header_afunix_h): New test.
(HAVE_AFUNIX_H): New AC_DEFINE.
* diagnostics/sarif-sink.cc: Conditionally include afunix.h
if it's available, else fall back to internal definition.
2026-02-03 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
PR middle-end/123892
* collect2.cc: Migrate from CONST_CAST2() macro to
const_cast<>() C++ expression.
* config/sparc/driver-sparc.cc: Likewise.
* gcc-ar.cc: Likewise.
* gcc.cc: Likewise.
* toplev.cc: Likewise.
* tree-nested.cc: Likewise.
2026-02-03 Richard Biener <rguenther@suse.de>
PR ipa/123416
* ipa-modref.cc (ipa_merge_modref_summary_after_inlining):
Fix typo in condtion for load merging when no callee summary.
2026-02-03 Xi Ruoyao <xry111@xry111.site>
Revert:
2025-11-08 Lulu Cheng <chenglulu@loongson.cn>
PR target/122097
* config/loongarch/loongarch.cc
(loongarch_const_vector_same_bytes_p): Add processing for
floating-point vector data.
2026-02-03 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/predicates.md (const_vector_neg_fp_operand):
New define_predicate.
(reg_or_vector_neg_fp_operand): New define_predicate.
* config/loongarch/lasx.md (copysign<mode>3): Remove.
(xorsign<mode>3): Remove.
* config/loongarch/lsx.md (copysign<mode>3): Remove.
(@xorsign<mode>3): Remove.
* config/loongarch/simd.md (copysign<mode>3): New define_expand.
(@xorsign<mode>3): New define_expand.
(and<mode>3): Only allow IVEC instead of ALLVEC.
(ior<mode>3): Likewise.
(xor<mode>3): Likewise.
* config/loongarch/loongarch.cc (loongarch_print_operand): No
longer allow floating-point vector constants for %V.
(loongarch_const_vector_bitimm_set_p): Always return false for
floating-point vector constants.
(loongarch_build_signbit_mask): Factor out force_reg.
(loongarch_emit_swrsqrtsf): Use integer vector mode instead of
floating-point vector mode when masking zero inputs.
2026-02-02 David Malcolm <dmalcolm@redhat.com>
PR diagnostics/110522
* gcc.cc (driver_handle_option): Use
get_diagnostic_file_output_basename for
OPT_fdiagnostics_format_.
* opts-diagnostic.cc (get_base_filename): Likewise.
(get_diagnostic_file_output_basename): New.
* opts-diagnostic.h (get_diagnostic_file_output_basename): New
decl.
* opts.cc (maybe_prepend_dump_dir_name): New, based on code in
finish_options.
(finish_options): Move code for determining prepended
dump_base_name to maybe_prepend_dump_dir_name and call it.
(common_handle_option): Use get_diagnostic_file_output_basename
for OPT_fdiagnostics_format_.
* opts.h (maybe_prepend_dump_dir_name): New decl.
2026-02-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/123294
* ifcvt.cc (noce_emit_store_flag): Reject modes
greater than MAX_FIXED_MODE_SIZE.
2026-02-02 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/123897
* tree-ssa-math-opts.cc (convert_mult_to_fma_1): Use type of variable
being folded.
2026-02-02 Tamar Christina <tamar.christina@arm.com>
PR target/121290
* config/aarch64/aarch64.cc (aarch64_vector_costs::add_stmt_cost):
Remove else.
2026-02-02 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121104
* tree-ssa-math-opts.cc (match_uaddc_usubc): Punt if
lhs of ovf1 or ovf2 doesn't have element type compatible with type.
2026-02-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/123755
* tree-vect-stmts.cc (vectorizable_call): Adjust len-masking
condition. Simplify code generation.
2026-01-31 Keith Packard <keithp@keithp.com>
* config/picolibc-spec.h (LIBC_LINK_SPEC): Use find-file for test
and access to picolibc.ld.
2026-01-31 Richard Biener <rguenther@suse.de>
PR middle-end/123887
* match.pd ((a ? x : y) !=/== (b ? x : y)): Make sure
x and y have no side-effects before evaluating them
unconditionally.
2026-01-31 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Binaries): Switch delorie.com to https.
2026-01-30 Richard Biener <rguenther@suse.de>
PR middle-end/123887
* match.pd ((zero_one ==/!= 0) ? .. z <op> y .. -> zero_one * z ..):
Check evaluating z unconditionally has no side-effects, like
trapping.
2026-01-30 Richard Biener <rguenther@suse.de>
PR debug/123886
* dwarf2out.cc (sym_off_pair::sym): Remove GTY((skip)).
2026-01-30 Michal Jires <mjires@suse.cz>
* doc/extend.texi: Mention flto-toplevel-asm-heuristics.
* doc/invoke.texi: Add flto-toplevel-asm-heuristics.
2026-01-30 Richard Biener <rguenther@suse.de>
PR debug/110885
* dwarf2out.cc (generate_skeleton_bottom_up): Generate the
skeleton ancestor tree when moving a new child to the parent
even for template instantiations.
2026-01-30 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123864
* match.pd (__builtin_mul_overflow_p (x, cst, (stype) 0) ->
x > stype_max / cst || x < stype_min / cst): Only check
integer_minus_onep for signed types.
2026-01-30 Jakub Jelinek <jakub@redhat.com>
PR c++/123790
* fold-const.cc (fold_convert_const): Handle conversion of
integer_zerop to NULLPTR_TYPE.
(fold_convert_loc): Likewise.
2026-01-30 Jørgen Kvalsvik <j@lambda.is>
PR gcov-profile/123855
* path-coverage.cc (flush_on_edges): Only look up SSA name def
stmt when counter is non-const.
2026-01-30 Jørgen Kvalsvik <j@lambda.is>
* gcov-dump.cc (tag_paths): New function.
2026-01-30 Jørgen Kvalsvik <j@lambda.is>
* common.opt: ftest-coverage enabled by fpath-coverage or
fcondition-coverage
2026-01-30 Jørgen Kvalsvik <j@lambda.is>
* gcov-dump.cc (tag_conditions): Read position before blocks,
terms.
2026-01-30 Jørgen Kvalsvik <j@lambda.is>
PR gcov-profile/121084
PR gcov-profile/121123
PR gcov-profile/121409
* profile.cc (branch_prob): Record seen_locations without
discriminators.
2026-01-30 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123876
* omp-low.cc (diagnose_sb_2): Handle GIMPLE_ASM.
2026-01-30 Alex Coplan <alex.coplan@arm.com>
PR target/123206
* config/aarch64/aarch64-builtins.cc (struct aarch64_pragma_builtins_data):
Declare array as CONSTEXPR.
* config/aarch64/aarch64-simd-pragma-builtins.def: Update
incorrect uses of TARGET_SIMD to use AARCH64_FL_SIMD instead.
2026-01-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/109410
* tree-ssa-reassoc.cc (build_and_add_sum): Use
gsi_start_nondebug_after_labels_bb to look for a possible
returns-twice call.
2026-01-30 Iain Buclaw <ibuclaw@gdcproject.org>
* config/darwin-d.cc (darwin_d_os_builtins): Add Apple.
2026-01-30 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/122170
* ifcvt.cc (noce_can_force_operand): Don't only check if
there is an optab for the code check the entry for the
mode is non-null. Handle non integral div by checking
optab like force_operand does.
2026-01-30 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-ftypes.def: Remove unused type.
2026-01-30 Lulu Cheng <chenglulu@loongson.cn>
PR target/123766
* config/loongarch/loongarch-builtins.cc
(loongarch_build_vpointer_type): New function. Return a type
for 'volatile void *'.
(LARCH_ATYPE_VPOINTER): New macro.
* config/loongarch/loongarch-ftypes.def: Change the pointer
type of the store class function from CVPOINTER to VPOINTER.
2026-01-30 Lulu Cheng <chenglulu@loongson.cn>
PR target/123807
* config/loongarch/loongarch.cc
(loongarch_expand_vector_init_same): When same is MEM and
GET_MODE(same) != imode, first load the data from memory
and then process it further.
2026-01-30 mengqinggang <mengqinggang@loongson.cn>
* config/loongarch/loongarch.md: Delete movsf TARGET_HARD_FLOAT
condition.
2026-01-29 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/123869
* optabs.cc (expand_unop): Move the NEG optab
handling before the widening code.
Move the ABS bitwise expansion from expand_abs_nojump
to before the widening code.
(expand_abs_nojump): Remove the bitwise expansion trial
since expand_unop is called right above.
2026-01-29 Roger Sayle <roger@nextmovesoftware.com>
* expr.cc (emit_group_load_1): Don't call force_reg if orig_src
is already a CONCAT.
2026-01-29 Sandra Loosemore <sloosemore@baylibre.com>
* doc/options.texi (Options): Point to the "user experience"
documentation.
* doc/ux.texi (Guidelines for Options): Add some.
2026-01-29 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123806
* config/riscv/riscv-string.cc (expand_rawmemchr): Use unified
vl_read.
(expand_strcmp): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc:
* config/riscv/riscv-vector-builtins.cc (function_expander::use_fof_load_insn):
Only emit the store and not the VL read.
* config/riscv/riscv-vsetvl.cc (get_fof_set_vl_reg): New
function.
(init_rtl_ssa): New wrapper.
(finish_rtl_ssa): Ditto.
(emit_fof_read_vls): Emit read_vl after each fault-only-first
load.
(pass_vsetvl::simple_vsetvl): Call emit_fof_read_vls ().
(pass_vsetvl::lazy_vsetvl): Ditto.
* config/riscv/vector-iterators.md: Add read_vl unspec.
* config/riscv/vector.md (read_vlsi): Unify.
(@read_vl<mode>): Ditto.
(read_vldi_zero_extend): Ditto.
(@pred_fault_load_set_vl<V_VLS:mode><P:mode>): New FoF variant
that saves VL in a register.
(@pred_fault_load_set_vl<VT:mode><P:mode>): Ditto.
2026-01-29 Filip Kastl <fkastl@suse.cz>
* gimple-ssa-pta-constraints.cc (make_param_constraints): Adjust
comment: The function only creates varinfos for the parameters,
the return value and the static chain.
2026-01-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/122537
* tree-ssa-loop-niter.cc (number_of_iterations_lt_to_ne): Register
may_be_zero condition when the IV may overflow.
2026-01-29 Sangamesh Mallayya <swamy.sangamesh@gmail.com>
* diagnostics/sarif-sink.cc: Move config.h at the begining.
2026-01-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/123596
* tree-eh.cc (sink_clobbers): Create a virtual PHI when
one is required but not present, queuing arguments
for renaming.
2026-01-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/116747
* tree-ssa-phiopt.cc (cond_if_else_store_replacement): Avoid
duplicate stmts in the set of store pairs to process.
2026-01-28 Uros Bizjak <ubizjak@gmail.com>
PR target/36503
* config/i386/i386.md (*<insn:any_shift><mode:SWI48>3_sub):
Also allow operands[3] & (<mode_bitsize>-1) == (<mode_bitsize>-1)
in insn condition. Emit NOT RTX instead of NEG RTX in this case.
(*<insn:any_shift><mode:SWI48>3_sub_1): Ditto.
2026-01-28 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123824
* config/riscv/riscv.cc (riscv_vls_mode_fits_in_gprs_p): New
helper.
(riscv_pass_vls_aggregate_in_gpr): Use helper and distribute
half-fitting vector to GPR and stack.
(riscv_pass_aggregate_in_vr): Reformat comment.
(riscv_get_arg_info): Use helper.
(riscv_pass_by_reference): Ditto.
2026-01-28 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/121571
* lra-constraints.cc (process_alt_operands): Reprocess asm insn
when there are no enough regs for the asm-insn.
2026-01-28 Richard Biener <rguenther@suse.de>
PR middle-end/123575
* match.pd (abs ((T)x) -> absu (x)): For vector type
arguments require the resulting operation is supported.
2026-01-28 Richard Biener <rguenther@suse.de>
PR ipa/111036
* match.pd (__builtin_constant_p ((T)x)): Strip nop-conversions
from __builtin_constant_p arguments.
2026-01-28 Richard Biener <rguenther@suse.de>
PR rtl-optimization/106859
* var-tracking.cc (val_store): Dump -1 as UID if setting_insn
is NULL.
2026-01-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/123537
* match.pd (REDUC (@0 & @1) -> @0[I] & @1[I]): Restrict
allowed conversions.
2026-01-28 Karl Meakin <karl.meakin@arm.com>
* doc/invoke.texi: Document `+sve-bfscale` flag.
* config/aarch64/aarch64.h (TARGET_SVE_BFSCALE): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Define `__AARCH64_FEATURE_SVE_BFSCALE`.
* config/aarch64/aarch64-sve-builtins-base.cc: Skip constant
folding for floating-point or unpredicated multiplications.
* config/aarch64/aarch64-sve-builtins-sve2.def: New `SVE_FUNCTION`s.
* config/aarch64/aarch64-sve.md: Modify insns for
`SVE_COND_FP_BINARY_INT` to handle BF16 modes.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve_<optab><mode>, @aarch64_sve_<optab><mode>_single): New insn for `BFSCALE`.
Modify insns for `UNSPEC_FSCALE` to handle BF16 modes.
* config/aarch64/iterators.md (SVE_FULL_F_SCALAR): Add `VNx8BF` to iterator.
(SVE_FULL_F_BFSCALE): New iterator.
(SVE_Fx24_BFSCALE): New iterator.
(SVE_BFx24): New iterator.
(UNSPEC_FMUL): New unspec.
(V_INT_EQUIV): Add entries for BF16 modes.
(b): Add entries for scalar float modes.
(is_bf16): Add entries for BF16 modes and reformat.
(SVSCALE_SINGLE_INTARG): Likewise.
(SVSCALE_INTARG): Likewise.
(SVE_FP_MULL): New iterator.
2026-01-28 Pengfei Li <Pengfei.Li2@arm.com>
PR middle-end/123447
* expr.cc (expand_expr_real_1): Increase stack slot alignment
for STRICT_ALIGNMENT targets.
2026-01-28 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/123016
* tree-vect-stmts.cc (vectorizable_simd_clone_call): use
'build_truth_vector_type_for_mode' to reconstruct mask's vectype for
non-scalar masks.
2026-01-28 Jakub Jelinek <jakub@redhat.com>
PR c/101312
* langhooks.h (struct lang_hooks_for_types): Remove
copy_lang_qualifiers. Add build_lang_qualified_type.
* langhooks.cc (lhd_build_lang_qualified_type): New function.
* langhooks-def.h (lhd_build_lang_qualified_type): Declare.
(LANG_HOOKS_COPY_LANG_QUALIFIERS): Remove.
(LANG_HOOKS_BUILD_LANG_QUALIFIED_TYPE): Add.
(LANG_HOOKS_FOR_TYPES_INITIALIZER): Use
LANG_HOOKS_BUILD_LANG_QUALIFIED_TYPE instead of
LANG_HOOKS_COPY_LANG_QUALIFIERS.
* attribs.cc (build_type_attribute_qual_variant): Use
lang_hooks.types.build_lang_qualified_type instead of
build_qualified_type and/or build_qualified_type with
optional lang_hooks.types.copy_lang_qualifiers call.
(attr_access::array_as_string): Use "array " attribute instead of
"array". If attribute has been created or intended quals differ
from quals of build_array_type, use copy_node and adjust quals and
attributes on the copy, print and then ggc_free.
2026-01-28 Jakub Jelinek <jakub@redhat.com>
PR c++/123837
* ipa-free-lang-data.cc (find_decls_types_r): Remove C++ annotations
from {DECL,TYPE}_ATRIBUTES.
2026-01-28 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123849
* gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
DEMANGLE_COMPONENT_EXTENDED_BUILTIN_TYPE like DEMANGLE_COMPONENT_BUILTIN_TYPE.
2026-01-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/110043
* pointer-query.cc (get_offset_range): Fail for integer
types with precision larger than ptrdiff_type_node.
2026-01-28 Hongyu Wang <hongyu.wang@intel.com>
PR target/123779
* config/i386/sse.md (*sse4_1_<code>v8qiv8hi2<mask_name>_2):
Rename to ...
(*sse4_1_<code>v8qiv8hi2_2): ... this, and drop mask conditions.
(*avx2_<code>v8qiv8si2<mask_name>_2): Rename to ...
(*avx2_<code>v8qiv8si2_2): ... this, and likewise.
(*sse4_1_<code>v4qiv4si2<mask_name>_2): Rename to ...
(*sse4_1_<code>v4qiv4si2_2): ... this, and likewise.
(*sse4_1_<code>v4hiv4si2<mask_name>_2): Rename to ...
(*sse4_1_<code>v4hiv4si2_2): ... this, and likewise.
(*avx2_<code>v4qiv4di2<mask_name>_2): Rename to ...
(*avx2_<code>v4qiv4di2_2): ... this, and likewise.
(*avx2_<code>v4hiv4di2<mask_name>_2): Rename to ...
(*avx2_<code>v4hiv4di2_2): ... this, and likewise.
(*sse4_1_<code>v2hiv2di2<mask_name>_2): Rename to ...
(*sse4_1_<code>v2hiv2di2_2): ... this, and likewise.
(*sse4_1_<code>v2siv2di2<mask_name>_2): Rename to ...
(*sse4_1_<code>v2siv2di2_2): ... this, and likewise.
(*avx512f_<code>v8qiv8di2<mask_name>_2): Rename to ...
(*avx512f_<code>v8qiv8di2_2): ... this.
(*avx512vl_<code>v8qiv8hi2_mask_2): New define_insn_and_split.
(*avx512vl_<code>v8qiv8si2_mask_2): Likewise.
(*avx512vl_<code>v4qiv4si2_mask_2): Likewise.
(*avx512vl_<code>v4hiv4si2_mask_2): Likewise.
(*avx512f_<code>v8qiv8di2_mask_2): Likewise.
(*avx512vl_<code>v4qiv4di2_mask_2): Likewise.
(*avx512vl_<code>v4hiv4di2_mask_2): Likewise.
(*avx512vl_<code>v2hiv2di2_mask_2): Likewise.
(*avx512vl_<code>v2siv2di2_mask_2): Likewise.
2026-01-28 Nina Ranns <dinka.ranns@gmail.com>
Iain Sandoe <iain@sandoe.co.uk>
Ville Voutilainen <ville.voutilainen@gmail.com>
* doc/invoke.texi: Document -fcontracts-client-check= and
-fcontracts-definition-check=.
2026-01-28 Nina Ranns <dinka.ranns@gmail.com>
Iain Sandoe <iain@sandoe.co.uk>
Ville Voutilainen <ville.voutilainen@gmail.com>
* doc/invoke.texi: Document -fcontract-checks-outlined and
-fcontract-disable-optimized-checks.
2026-01-28 Nina Ranns <dinka.ranns@gmail.com>
Iain Sandoe <iain@sandoe.co.uk>
* tree-core.h (struct tree_base): Update tree flag usage comment.
2026-01-28 Nina Ranns <dinka.ranns@gmail.com>
Iain Sandoe <iain@sandoe.co.uk>
* tree.h (CONST_WRAPPER_P): New.
2026-01-28 Nina Ranns <dinka.ranns@gmail.com>
Iain Sandoe <iain@sandoe.co.uk>
* doc/invoke.texi: Document -fcontracts-conservative-ipa.
2026-01-28 Iain Sandoe <iain@sandoe.co.uk>
Nina Ranns <dinka.ranns@gmail.com>
Ville Voutilainen <ville.voutilainen@gmail.com>
* config/darwin.h (ASM_GENERATE_INTERNAL_LABEL): Add cases for contract
constant data that need to be in independent link-time 'atoms'.
* doc/invoke.texi: Document -fcontracts and
-fcontract-evaluation-semantic=.
2026-01-28 Iain Sandoe <iain@sandoe.co.uk>
Nina Ranns <dinka.ranns@gmail.com>
* doc/invoke.texi: Remove documentation of contracts options.
2026-01-27 Jakub Jelinek <jakub@redhat.com>
PR other/123841
* acinclude.m4 (gcc_GAS_FLAGS) <i?86-*-* | x86_64-*-*>: Set
gcc_cv_as_flags irrespective of $gas_flag.
* configure: Regenerate.
2026-01-27 David Malcolm <dmalcolm@redhat.com>
PR analyzer/122623
* doc/invoke.texi (-fanalyzer-assume-nothrow): New option.
2026-01-27 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/97898
* omp-expand.cc (expand_omp_for_static_chunk): Don't
conditionalize the call to force_gimple_operand_gsi on DECL_P/TREE_ADDRESSABLE
but rather pass that as the 3rd argument.
2026-01-27 Jan Hubicka <hubicka@ucw.cz>
PR ipa/123619
* ipa-polymorphic-call.cc
(ipa_polymorphic_call_context::possible_dynamic_type_change): Remove impossible
speuculation.
2026-01-27 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (ld_32_opt, ld_64_opt): Set.
(ld_ix86_gld_32_opt): Replace by ld_32_opt.
(ld_ix86_gld_64_opt): Replace by ld_64_opt.
Replace -melf_x86_64 by ld_64_opt.
* configure: Regenerate.
2026-01-27 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* acinclude.m4 (gcc_cv_as_flags) Provide Solaris settings.
Apply Linux/x86 gas settings on all x86 gas targets, too.
(as_32_opt, as_64_opt): Set on all x86 gas targets.
* configure.ac: Consistenly use as_32_opt, as_64_opt instead of
as_ix86_gas_{32,64}_opt or hardcoded --64.
<sparc*-*-*>: Simplify setting TLS test code.
* configure: Regenerate.
2026-01-27 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (fw_as_opt): Set.
Replace --fatal-warnings by $fw_as_opt.
(tls_as_opt): Remove --fatal-warnings.
(gcc_cv_as_tls): Use $fw_as_opt.
* configure: Regenerate.
2026-01-27 Richard Biener <rguenther@suse.de>
PR ipa/116296
* ipa-modref-tree.cc (modref_access_node::contains): Use
poly_offset_int for the param offset difference and the
overlap computation.
2026-01-27 Richard Biener <rguenther@suse.de>
PR debug/123376
* dwarf2out.cc (tree_add_const_value_attribute): Walk all
initializers for early mangling of referenced decls.
(mangle_referenced_decls): Also walk subtrees of CONSTRUCTORS.
2026-01-27 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123799
* tree-ssa-forwprop.cc (simplify_vector_constructor): Pun
conversion element type with integer type.
2026-01-27 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/123791
* config/aarch64/aarch64.cc (aarch64_cannot_force_const_mem):
Always return true for symbols and labels except for large model.
(aarch64_select_rtx_section): Force .rodata for constants only.
2026-01-27 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/123792
* config/aarch64/aarch64.md (aarch64_<optab>_reg_minus<mode>3):
Add support for invert in shift count.
2026-01-27 Tobias Burnus <tburnus@baylibre.com>
* doc/install.texi (gcn): Require Newlib 4.6.0+, replacing 4.3.0+
requirement with long list of recommended fixes up to post-4.5.0.
2026-01-27 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122749
* tree-ssa-math-opts.cc (convert_mult_to_fma_1, convert_mult_to_fma):
Unwrap converts around addend.
2026-01-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123820
* gimple-ssa-strength-reduction.cc (create_add_on_incoming_edge): Use
the correct type for the stride (lhs if non-pointer).
2026-01-26 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR middle-end/123709
* final.cc (output_asm_operand_names): Skip over
opnum which is MAX_RECOG_OPERANDS (invalid).
(output_asm_insn): Increase opoutput and oporder size
by 1. For out of range operands, set the opnum to
MAX_RECOG_OPERANDS.
2026-01-26 Filip Kastl <fkastl@suse.cz>
* doc/invoke.texi: Document --param auto-profile-reorder-only.
* params.opt: Fix spelling.
2026-01-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/122474
* tree-vectorizer.h (vect_reduc_info_s::neutral_op): New.
(VECT_REDUC_INFO_NEUTRAL_OP): New.
* tree-vect-loop.cc (vectorizable_reduction): Adjust condition
guarding the check for .VEC_SHL_INSERT.
2026-01-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/123755
* tree-vect-stmts.cc (vectorizable_call): Fixup LEN masking
of unconditional but possibly trapping calls.
2026-01-26 Victor Do Nascimento <victor.donascimento@arm.com>
PR tree-optimization/123657
* tree-vect-loop.cc (vect_analyze_loop_form): Add
chrec_dont_know check.
2026-01-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/123794
* tree-vect-slp.cc (vect_remove_slp_scalar_calls): Unlink
VOPs for all calls.
2026-01-26 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
PR tree-optimization/123628
* tree-if-conv.cc (if_convertible_simdclone_stmt_p): New.
(if_convertible_stmt_p, predicate_statements): Use it.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
* gcc-urlifier.cc (test_gcc_urlifier): Match either positive
or negative option URLS.
2026-01-25 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/122348
* expr.cc (store_constructor): Ignore fields where DECL_SIZE
is NULL_TREE, i.e. flexible array members.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
* common.opt.urls: Regenerated.
* config/alpha/alpha.opt.urls: Regenerated.
* config/arc/arc.opt.urls: Regenerated.
* config/arm/arm.opt.urls: Regenerated.
* config/avr/avr.opt.urls: Regenerated.
* config/bpf/bpf.opt.urls: Regenerated.
* config/cris/cris.opt.urls: Regenerated.
* config/lynx.opt.urls: Regenerated.
* config/m68k/m68k.opt.urls: Regenerated.
* config/mcore/mcore.opt.urls: Regenerated.
* config/mingw/cygming.opt.urls: Regenerated.
* config/mips/mips.opt.urls: Regenerated.
* config/mips/sde.opt.urls: Regenerated.
* config/mmix/mmix.opt.urls: Regenerated.
* config/nvptx/nvptx.opt.urls: Regenerated.
* config/rs6000/linux64.opt.urls: Regenerated.
* config/rs6000/rs6000.opt.urls: Regenerated.
* config/rs6000/sysv4.opt.urls: Regenerated.
* config/sh/sh.opt.urls: Regenerated.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Option Summary): Fix whitespace in @gccoptlist
tables.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/cppopts.texi: Add missing @opindex entries for
-fno-* options.
* doc/invoke.texi: Likewise.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/cppwarnopts.texi: Add missing @opindex entries for
-Wno-* options.
* doc/invoke.texi: Likewise.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/cppdiropts.texi: Document -imultiarch.
* doc/invoke.texi (Option Summary) <Optimization Options>: Add
-flto-toplevel-asm-heuristics.
<Program Instrumentation Options>: Remove -fbounds-check.
<Directory Options>: Add -imultiarch.
<ARC Options>: Add -mbitops, -mcmem, -munaligned-access.
<ARM Options>: Add -mvectorize-with-neon-quad and
-mvectorize-with-neon-double.
<AVR Options>: Add -mrmw and -mstrict-X.
<CRIS Options>: Fix typo in -mmax-stackframe.
<Cygwin and MinGW Options>: Add -muse-libstdc-wrappers.
<M680x0 Options>: Add several missing CPU options, plus -mxtls.
<MIPS Options>: Add -mno-data-in-code and -mcode-xonly.
<MMIX Options>: Add mset-data-start, -mset-program-start, and
-mno-set-program-start.
<Nvidia PTX Options>: Add -msoft-stack-reserve-local.
<RS/6000 and PowerPC Options>: Add -mprofile-kernel, -mbit-word,
-mno-splat-word-constant, -mno-splat-float-constant,
-mno-ieee128-constant, and -mno-warn-altivec-long.
(Optimization Options): Document -flto-toplevel-asm-heuristics.
(ARC Options): Document -mbitops and -mcmem.
(ARM Options): Add index entries for mbe32,
m[no-]fix-cortex-a57-aes-1742098, m[no-]fix-cortex-a72-aes-1655431.
Document -mvectorize-with-neon-quad and -mvectorize-with-neon-double.
(AVR Options): Document -mpmem-wrap-around.
(CRIS Options): Fix typo in -mmax-stackframe.
(Cygwin and MinGW Options): Document -muse-libstdc-wrappers.
(DEC Alpha Options): Fix typo in -mfp-regs.
(eBPF Options): Add @opindex for -mframe-limit.
(HPPA Options): Fix typos in -mno-disable-fpregs and -mno-gas
index entries.
(m680x0 Options): Document -m68302, -m68332, -m68851, and -mfidoa.
Document -mnoshort and -mnortd aliases. Document -mxtls.
(MCore Options): Fix typos in -m[no-]relax-immediates.
(MIPS Options): Document -mno-data-in-code and -mcode-xonly.
(MMIX Options): Document -mset-data-start, -mset-program-start, and
-mno-set-program-start.
(Nvidia PTX Options): Document -msoft-stack-reserve-local.
(RS/6000 and PowerPC Options): Document -mprofile-kernel,
-mbit-word, -msplat-word-constant, -msplat-float-constant,
-mieee128-constant, and -mwarn-altivec-long.
(SH Options): Add index entry for -m2e. Document -m4-400.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* common.opt (fbounds-check): Mark as Undocumented, expand comments
to explain why.
* config/frv/frv.opt (msched-lookahead=): Mark unused option as
Undocumented.
* config/m68k/m68k.opt (m68851): Add RejectNegative.
* config/nvptx/nvptx.opt (minit-regs=): Mark as Undocumented. It's
not currently documented and seems to have been introduced as a
stopgap to experiment with different implementation strategies.
* config/rs6000/476.opt (mpreserve-link-stack): Mark as Undocumented.
It seems to be an internal option that is enabled by default on the
cpu that can benefit from it.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* common.opt (gtoggle): Mark RejectNegative.
* doc/invoke.texi (Option Summary) <Debugging Options>: Remove
redundant -gno- forms from the list.
(Debugging Options): Add @opindex for -gno- option forms.
Copy-edit option descriptions to avoid future tense and use of
implementor jargon.
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/67300
* common.opt (foffload-abi, foffload-abi-host-opts): Mark
"Undocumented".
2026-01-25 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/invoke.texi (Option Summary) <LynxOS Options>: New.
(LynxOS Options): New section.
2026-01-24 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123803
* gimple-ssa-strength-reduction.cc (replace_rhs_if_not_dup): For
pointer lhs use sizetype.
2026-01-23 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123780
* config/riscv/vector.md: Correct output template.
2026-01-23 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123767
* tree-vect-stmts.cc (vectorizable_store): Only scale offset
once.
(vectorizable_load): Ditto.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123778
* genmatch.cc (parser::parse_expr): Peek on the next
token after eating the `!` or `^`.
* match.pd (`(op (cnd @0 @1 @2) @3)`, `(op @3 (cnd @0 @1 @2))`):
Add the type to resulting op.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/120258
PR tree-optimization/106883
* gimple-ssa-strength-reduction.cc (replace_mult_candidate): Allow for
basis_name and bump_tree not to be the same type as the lhs.
Rewrite added multiply for undefined overflow.
(create_add_on_incoming_edge): Allow for init
to be a different type from the wanted type.
Rewrite added add for undefined overflow.
(replace_rhs_if_not_dup): Rewrite replaced stmts
for undefined overflow.
(replace_one_candidate): Allow for basis_name and
rhs2 to be a different type from lhs.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/106883
* gimple-ssa-strength-reduction.cc (create_add_on_incoming_edge): Rewrite
the new addition on the edge too.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* gimple-ssa-strength-reduction.cc (introduce_cast_before_cand): Use
gimple_convert instead of manually creating the gimple_assign.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/121347
PR tree-optimization/106883
* gimple-ssa-strength-reduction.cc (insert_initializers): Rewrite
newly inserted statements for undefinedness (overflow).
2026-01-23 Peter Bergner <bergner@tenstorrent.com>
PR target/123492
* config/riscv/riscv-cores.def (RISCV_CORE): Add zvfbfmin to
tt-ascalon-d8.
2026-01-23 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123776
* gimple-fold.cc (gimple_fold_partial_load_store): Copy
the vdef from the old statement to the new statement of a
load that is also a store to non gimple_reg.
2026-01-23 Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/80357
PR rtl-optimization/94014
PR rtl-optimization/123144
* haifa-sched.cc (model_recompute): Ignore dying uses of registers
that are not assumed to be live.
2026-01-23 Richard Biener <rguenther@suse.de>
* match.pd ((convert (vec_cond ...))): Make sure the
resulting vec_cond can be expanded.
2026-01-23 Richard Biener <rguenther@suse.de>
PR middle-end/123775
* match.pd ((view_convert (vec_cond ...))): Make sure the
resulting vec_cond can be expanded.
2026-01-23 Kyrylo Tkachov <ktkachov@nvidia.com>
Revert:
2026-01-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/123584
* config/aarch64/aarch64-sve2.md (@aarch64_sve2_xar<mode>): Use
aarch64_simd_rshift_imm predicate for rotate amount.
2026-01-23 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123703
* builtins.cc (fold_builtin_abs): Return NULL_TREE if type is not
integral.
2026-01-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/123771
* tree-vect-loop.cc (vectorizable_induction): Convert step
also for VLA vectors.
2026-01-23 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::finish_cost):
Avoid selecting masked epilogs for in-order reductions.
2026-01-23 Hongyu Wang <hongyu.wang@intel.com>
* config/i386/sse.md (avx2_vbroadcasti128_<mode>): Constraint
alternative 0 with jm and add gpr16 attr to avoid egpr usage.
2026-01-22 Richard Earnshaw <rearnsha@arm.com>
PR target/123742
* config/arm/neon.md (*smin<mode>3_neon): Renamed to ...
(*smin<VDQWH:mode>3_neon): ... this. Add HFmode support.
(*smax<mode>3_neon): Renamed to ...
(*smax<VDQWH:mode>3_neon): ... this. Add HFmode support.
2026-01-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/123741
* tree-vect-stmts.cc (vectorizable_store): Add missing check
on loop vectorization.
2026-01-22 Jonathan Wakely <jwakely@redhat.com>
* tree-vrp.cc (remove_unreachable::fully_replaceable): Fix typo
in comment.
2026-01-22 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123731
* tree-ssa-forwprop.cc (simplify_vector_constructor): Handle nop
conversion between during extraction.
2026-01-22 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/122869
* config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load):
Remove
* config/riscv/riscv-vector-builtins.cc (function_expander::use_contiguous_load_insn):
Use new helper.
(function_expander::prepare_contiguous_load_insn): New helper.
(function_expander::use_fof_load_insn): New function to emit FoF
loads.
* config/riscv/riscv-vector-builtins.h: Declare new functions.
2026-01-22 Robin Dapp <rdapp@oss.qualcomm.com>
PR target/123279
* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
Add VECTOR_EXT_NO_XTHEAD.
(vlm): Move to VECTOR_EXT_NO_XTHEAD.
(vsm): Ditto.
(vzext): Ditto.
(vsext): Ditto.
(vaaddu): Ditto.
(vaadd): Ditto.
(vasubu): Ditto.
(vasub): Ditto.
(vfrsqrt7): Ditto.
(vfrec7): Ditto.
(vfrec7_frm): Ditto.
(vfslide1up): Ditto.
(vfslide1down): Ditto.
(vluxei8): Ditto.
(vluxei16): Ditto.
(vluxei32): Ditto.
(vluxei64): Ditto.
(vsuxei8): Ditto.
(vsuxei16): Ditto.
(vsuxei32): Ditto.
(vsuxei64): Ditto.
(vluxseg): Ditto.
(vsuxseg): Ditto.
(vrgatherei16): Ditto.
(vlseg): Keep.
(vsseg): Keep.
(vlsseg): Keep.
(vssseg): Keep.
(vloxseg): Keep.
(vsoxseg): Keep.
(vlsegff): Keep.
* config/riscv/riscv-vector-builtins.cc (GTY): Split
registered_functions into multiple partitions.
(is_fractional_lmul): New function.
(xthvector_unsupported_p): Ditto.
(get_builtin_partition): Ditto.
(function_builder::add_function): Use new functions.
(lookup_registered_function): Ditto.
(builtin_decl): Use lookup_registered_function.
(gimple_fold_builtin): Ditto.
(expand_builtin): Ditto.
(check_builtin_call): Ditto.
(resolve_overloaded_builtin): Ditto.
* config/riscv/riscv-vector-builtins.h (enum required_ext):
(enum rvv_builtin_partition): New enum.
(required_ext_to_isa_name): Add NO_XTHEAD.
(required_extensions_specified): Ditto.
* config/riscv/riscv-vector-switch.def (ENTRY): Remove
XTheadVector.
(TUPLE_ENTRY): Ditto.
* config/riscv/riscv.cc (riscv_expand_mult_with_const_int): Fix
whitespace.
(riscv_legitimize_poly_move): Ditto.
(riscv_vector_fractional_lmul_p): New function.
(riscv_validate_vector_type): Use new function.
2026-01-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/123755
* tree-vect-stmts.cc (vectorizable_call): Register mask when
the call could trap.
2026-01-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/123756
* tree-vect-loop.cc (vect_transform_reduction): Remove
bogus assert.
2026-01-22 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123736
* tree-ssa-loop-unswitch.cc (hoist_guard): Guard dump message
on dump_file && (dump_flags & TDF_DETAILS) condition.
2026-01-22 David Malcolm <dmalcolm@redhat.com>
PR diagnostics/122622
* diagnostics/paths-output.cc: Include "diagnostics/file-cache.h".
(event_range::print_as_text): Generalize the fallback logic for
special locations to also cover the case where source-printing
will fail, and show the location for that case.
(event_range::print_as_html): Likewise.
(event_range::can_print_source_p): New.
2026-01-22 liuhongt <hongtao.liu@intel.com>
PR target/123631
* config/i386/i386-expand.cc (ix86_vector_duplicate_value):
Don't force CONST_INT to reg !TARGET_PREFER_BCST_FROM_INTEGER,
force it to mem instead.
* config/i386/i386.h (TARGET_PREFER_BCST_FROM_INTEGER): New macro.
* config/i386/x86-tune.def
(X86_TUNE_PREFER_BCST_FROM_INTEGER): New tune.
2026-01-21 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/122781
* config/s390/vector.md: Don't emulate vec_cmpgtu for 128-bit
integers for VXE3.
2026-01-20 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/123380
* combine.cc (gen_lowpart_for_combine): Don't try to create a
paradoxical SUBREG if it's going to be rejected by validate_subreg.
2026-01-20 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123626
* config/riscv/vector.md (vxrm_mode): Handle CALL_INSNs, which set
the attribute to the new VXRM_MODE_CLOBBER state.
* config/riscv/riscv.cc (riscv_emit_mode_set): Don't emit code when
VXRM's state changes to VXRM_MODE_CLOBBER.
2026-01-20 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/123314
* gimple-range.cc (gimple_ranger::range_on_entry): Do not check
ranger cache for an SSA_NAME with no BB.
(gimple_ranger::prefill_stmt_dependencies): Stop filling
dependencies when an out-of IL name is encountered.
2026-01-20 supers1ngular <supers1ngular@baylibre.com>
* doc/extend.texi: Swap samp fields to fix overfull hbox.
* doc/invoke.texi: Ditto.
2026-01-20 Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
PR c++/123639
* doc/invoke.texi: Add @item for -Wsfinae-incomplete.
2026-01-20 Nathan Sidwell <nathan@acm.org>
* diagnostics/context.cc (context::action_after_output): Print
invocation on ICE.
2026-01-20 David Malcolm <dmalcolm@redhat.com>
PR sarif-replay/123056
* libsarifreplay.cc (struct embedded_link): Move decl earlier.
(sarif_replayer::append_embeddded_link): New.
(sarif_replayer::make_plain_text_within_result_message): Move the
link-replay logic to the above, and skip the link part of
intra-sarif links.
2026-01-20 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P):
Return true when WITH_AVRLIBC.
2026-01-20 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.md: Update comment.
* config/aarch64/aarch64-simd.md: Change comment to refer to
aarch64.md.
* config/aarch64/aarch64-sme.md: Likewise.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/aarch64-sve-builtins.def: Update comment.
* config/aarch64/aarch64-sve-builtins-base.def: Update to refer
to aarch64-sve-builtins.def.
* config/aarch64/aarch64-sve-builtins-sme.def: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
2026-01-20 Jakub Jelinek <jakub@redhat.com>
PR target/123724
* config/aarch64/aarch64.cc (aarch64_possible_by_lane_insn_p): Ignore
debug stmts.
2026-01-20 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/123585
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case VEC_SELECT>: Correct gcc_assert when optimizing a vec_select
of a vec_select with differing vector lengths.
2026-01-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/123584
* config/aarch64/aarch64-sve2.md (@aarch64_sve2_xar<mode>): Use
aarch64_simd_rshift_imm predicate for rotate amount.
2026-01-20 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/123584
* config/aarch64/aarch64-simd.md (aarch64_xarqv2di): Leave zero
rotate amounts as zero during expansion.
(*aarch64_xarqv2di_insn): Account for zero rotate amounts. Print #
in rotate immediate.
2026-01-20 Prachi Godbole <pgodbole@nvidia.com>
* flag-types.h (enum lto_locality_heuristics): New enum.
* ipa-locality-cloning.cc (struct templ_info): New struct.
(struct locality_info): Add templ_info field.
(templ_hash_map): New hash_map.
(callee_templ_cmp): Ditto.
(static_profile_templ_cmp): Ditto.
(sort_templ_hashes_cmp): Ditto.
(order_templ_hashes): Ditto.
(locality_dc_template_p): Ditto.
(populate_templ_info): Ditto.
(create_locality_info): Call populate_templ_info.
(partition_callchain): Call callee_templ_cmp.
(locality_determine_static_order): Populate and sort templ_hash_map.
(locality_partition_and_clone): Handle lto_locality_heuristics.
(lc_execute): Initialize templ_hash_map.
* params.opt: New param.
2026-01-20 Prachi Godbole <pgodbole@nvidia.com>
* ipa-locality-cloning.cc (struct locality_callee_info): New struct.
(struct locality_info): Ditto.
(loc_infos): Ditto.
(get_locality_info): New function.
(sort_all_callees_default): Ditto.
(callee_default_cmp): Ditto.
(populate_callee_locality_info): Ditto.
(populate_caller_locality_info): Ditto.
(create_locality_info): Ditto.
(adjust_recursive_callees): Access node_to_clone by reference.
(inline_clones): Access node_to_clone and clone_to_node by reference.
(clone_node_as_needed): Ditto.
(accumulate_incoming_edge_frequency): Remove function.
(clone_node_p): New function.
(partition_callchain): Refactor the function.
(is_entry_node_p): Call local_p ().
(locality_determine_ipa_order): Call create_locality_info ().
(locality_determine_static_order): Ditto.
(locality_partition_and_clone): Update call to partition_callchain ()
according prototype.
(lc_execute): Allocate and free node_to_ch_info, node_to_clone,
clone_to_node.
2026-01-20 Richard Biener <rguenther@suse.de>
PR middle-end/123697
* gimple-fold.cc (gimple_fold_partial_load_store): Use an
empty CTOR for a zero else value in .MASK_LOAD_LANES.
2026-01-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/123729
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Set
SSA_NAME_OCCURS_IN_ABNORMAL_PHI if the reduction flows
across an abnomal edge.
2026-01-20 Richard Biener <rguenther@suse.de>
* tree-phinodes.h (phi_arg_index_from_use): Use gphi *.
(phi_arg_edge_from_use): New helper composing
phi_arg_index_from_use and gimple_phi_arg_edge.
2026-01-19 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR rtl-optimization/121787
* config/riscv/riscv-vsetvl.cc (pre_vsetvl): Adjust call to
loop_optimizer_init to avoid making CFG changes.
2026-01-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sol2.opt.urls: Regenerate.
* config/darwin.opt.urls: Likewise.
* config/dragonfly.opt.urls: Likewise.
* config/freebsd.opt.urls: Likewise.
* config/gnu-user.opt.urls: Likewise.
* config/hpux11.opt.urls: Likewise.
* config/i386/cygwin.opt.urls: Likewise.
* config/mingw/mingw.opt.urls: Likewise.
* config/netbsd.opt.urls: Likewise.
* config/openbsd.opt.urls: Likewise.
* config/rs6000/aix64.opt.urls: Likewise.
* config/rtems.opt.urls: Likewise.
2026-01-19 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sol2.h (CPP_SUBTARGET_SPEC): Remove.
* config/sol2.opt (pthread): Ignore.
(pthreads): Likewise.
* config/i386/sol2.h (CPP_SPEC): Remove.
(SUBTARGET_CPU_EXTRA_SPECS): Remove cpp_subtarget.
* doc/invoke.texi (Solaris 2 Options, pthread): Remove.
2026-01-19 Jeff Law <jeffrey.law@oss.qualcomm.com>
Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/113666
* fold-const-call.cc (fold_const_vec_extract): New function.
(fold_const_call, case CFN_VEC_EXTRACT): Call it.
* match.pd (IFN_VEC_EXTRACT): Handle extraction from a uniform
vector.
2026-01-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/123061
PR tree-optimization/123636
* tree-ssa-loop-im.cc (fill_always_executed_in_1): Change
outer-to-inner to inner-to-outer iteration. Update inner
loop state only when always executed in an immediately
nested loop.
2026-01-19 Tobias Burnus <tburnus@baylibre.com>
* doc/install.texi (GCN): gfx9-4-generic requires LLVM 20.
2026-01-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/123602
* tree-ssa-pre.cc (find_or_generate_expression): Do not
generate references to abnormal SSA names.
2026-01-19 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config.gcc: Deprecate -m31.
* doc/invoke.texi: Deprecate -m31.
2026-01-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123656
* tree-vect-generic.cc (expand_vector_mult): Fix up alg_sub_factor
handling. Fix up formatting in alg_add_t_m2 handling.
2026-01-19 Richard Biener <rguenther@suse.de>
PR target/123603
* config/i386/i386.opt (-param=ix86-vect-compare-costs=): Add.
* config/i386/i386.cc (ix86_autovectorize_vector_modes): Honor it.
* doc/invoke.texi (ix86-vect-compare-costs): Document.
2026-01-19 Lulu Cheng <chenglulu@loongson.cn>
PR target/117575
* config/loongarch/lasx.md: Modify the range of operand1.
2026-01-18 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123645
* tree-ssa-phiopt.cc (cond_removal_in_builtin_zero_pattern): Rewrite
the canonicalization of the args code based on e1/e2 being edges into
the join block.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
* config/darwin.opt.urls: Regenerated.
* config/dragonfly.opt.urls: Regenerated.
* config/freebsd.opt.urls: Regenerated.
* config/gnu-user.opt.urls: Regenerated.
* config/hpux11.opt.urls: Regenerated.
* config/i386/cygwin.opt.urls: Regenerated.
* config/i386/i386.opt.urls: Regenerated.
* config/mingw/mingw.opt.urls: Regenerated.
* config/nds32/nds32.opt.urls: Regenerated.
* config/netbsd.opt.urls: Regenerated.
* config/nvptx/nvptx.opt.urls: Regenerated.
* config/openbsd.opt.urls: Regenerated.
* config/pru/pru.opt.urls: Regenerated.
* config/riscv/riscv.opt.urls: Regenerated.
* config/rl78/rl78.opt.urls: Regenerated.
* config/rs6000/aix64.opt.urls: Regenerated.
* config/rs6000/rs6000.opt.urls: Regenerated.
* config/rs6000/sysv4.opt.urls: Regenerated.
* config/rtems.opt.urls: Regenerated.
* config/rx/rx.opt.urls: Regenerated.
* config/s390/s390.opt.urls: Regenerated.
* config/s390/tpf.opt.urls: Regenerated.
* config/sh/sh.opt.urls: Regenerated.
* config/sol2.opt.urls: Regenerated.
* config/sparc/sparc.opt.urls: Regenerated.
* config/v850/v850.opt.urls: Regenerated.
* config/vax/vax.opt.urls: Regenerated.
* config/vxworks.opt.urls: Regenerated.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/nds32/nds32.opt: Tidy documentation strings.
(mbig-endian, mlittle-endian): Remove "Undocumented" flag since
these are, in fact, documented.
* doc/invoke.texi (Option Summary) <NDS32 Options>: Document
-EB, -EL, -mabi, -mfloat-abi, -malways-align, -malign-functions,
-mfp-as-gp, -mext-dsp, -mext-fpu-fma, -mext-fpu-sp, -mext-fpu-dp,
-misr-vector-size, -misr-secure, -mcpu, -mconfig-fpu,
-mconfig-mul, -mconfig-register-ports, -mrelax-hint,
-msched-prolog-epilog, -mno-ret-in-naked-func, -malways-save-lp,
-munaligned-access, and -minline-asm-r15.
(NDS32 Options): Likewise.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/xtensa/uclinux.opt (elf2flt, elf2flt=): Mark as Undocumented.
* config/xtensa/xtensa.opt (mlra): Likewise.
* doc/invoke.texi (Option Summary) <Xtensa Options>: Remove
redundant negative forms plus obsolete -mfused-madd option.
(Xtensa Options): Likewise undocument -mfused-madd. List
negative form of -mforce-no-pic.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/i386/i386.opt (malign-functions): Mark undocumented/unused
option as Undocumented.
(malign-jumps): Likewise.
(malign-loops): Likewise.
(mbranch-cost, mforce-drap): Mark undocumented options likely
intended for developer use only as Undocumented.
(mstv): Correct sense of option in doc string.
(mavx512cd): Remove extra "and" from doc string.
(mavx512dq): Likewise.
(mavx512bw): Likewise.
(mavx512vl): Likewise.
(mavx512ifma): Likewise.
(mavx512bvmi): Likewise.
* doc/invoke.texi (Options Summary) <x86 Options>: Add
missing options. Correct whitespace and re-wrap long lines.
Remove -mthreads which is now classed as a MinGW option.
(Cygwin and MinGW Options): Replace existing documentation of
-mthreads with the more detailed text moved from x86 Options.
(x86 Options): Move introductory text about ISA extensions before
the individual options instead of after. Document them all
individually instead of as a group, and move immediately after
-march/-mtune documentation. Rewrap long lines. Document
interaction between SSE and AVX with -mfpmath=sse. Move -masm
documentation farther down instead of grouped with options
affecting floating-point behavior. Add missing @opindex
entries. Rewrite the -mdaz-ftz documentation. Document
-mstack-arg-probe. Copy-editing. Document -mstv. Remove
obsolete warning about -mskip-rax-setup in very old GCC versions.
Rewrite the -mapx-inline-asm-use-gpr32 documentation.
Document -mgather and -mscatter. Split -miamcu documentation
from -m32/-m64/etc. Rewrite -munroll-only-small-loops documentation.
Document -mdispatch-scheduler.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/invoke.texi (Option Summary) <VxWorks Options>: Add -mvthreads.
(VxWorks Options): Likewise.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/vms/vms.opt (map): Mark as Undocumented.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/visium/visium.opt (menable-trampolines): Mark Undocumented.
* doc/invoke.texi (Options Summary) <Visium Options>: Remove
redundant -mno- option.
(Visium Options): Copy-editing to put in active voice and add markup.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/vax/elf.opt (mno-asm-pic): Mark as Undocumented.
* doc/invoke.texi (Option Summary) <VAX Options>: Add
-mvaxc-alignment and -mqmath.
(VAX Options): Likewise.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/v850/v850.opt: Copy-edit documentation strings.
(mdebug): Make Undocumented.
(mno-strict-align): Add RejectNegative.
(mUS-bit-set): Make Undocumented.
* doc/invoke.texi (Option Summary) <V850 Options>: Remove
redundant -mno- forms from list. Add missing entries.
(V850 Options): Add @opindex for negative forms. Combine
entries for -mapp-regs and -mno-app-regs. Document -msmall-sld,
-mno-strict-align, and -mjump-tables-in-data-section.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/invoke.texi (Option Summary) <SPARC Options>: Remove
redundant -mno- forms from the list. Add -mptr32 and -mptr64.
(SPARC Options): Document -mptr32 and -mptr64.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* doc/invoke.texi (Option Summary) <Solaris 2 Options>:
Remove redundant negative option forms from list. List both
-pthread and -pthreads.
(Solaris 2 Options): Index and list the negative forms here.
Combine the two @table environments. Document both -pthread
and -pthreads.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/sh/sh.opt (mhitachi, mpadstruct): Mark obsolete options
as Undocumented.
* doc/invoke.texi (Option Summary) <SH Options>: Add missing
entries for -m4-* and other options. Remove redundant -mno- entries
and obsolete options. Add missing options -mfdpic, -mlra.
(SH Options): Combine entries for -mrenesas and -mno-renesas.
Index and list -mno- forms for other options that have them.
Remove documentation for obsolete options -mpadstruct and
-mfused-madd. Add documentation for -mlra. Copy-edit and wrap long
lines throughout the section.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/s390/s390.opt (mbranch-cost): Mark as Undocumented.
* config/s390/tpf.opt (mtpf-trace-hook-prologue-check=): Likewise.
(mtpf-trace-hook-prologue-target=): Likewise.
(mtpf-trace-hook-epilogue-check=): Likewise.
(mtpf-trace-hook-epilogue-target=): Likewise.
* doc/invoke.texi (Option Summary) <S/390 and zSeries Options>:
Remove redundant -mno- entries and add missing options. Make
entries with arguments match the syntax in the main documentation.
(S/390 and zSeries Options): Light copy-editing. Wrap overly-long
lines. Add missing @opindex entries. Add documention for
-mmain, -mno-pic-data-is-text-relative, -mindirect-branch,
-mindirect-branch-jump, -mindirect-branch-call,
-mfunction-return, -mfunction-return-mem, -mfunction-return-reg,
-mindirect-branch-table, -mfentry, -mrecord-mcount, -mnop-mcount,
-mpreserve-args, and -munaligned-symbols.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/rx/rx.opt (mgcc-abi, mrx-abi): Mark as Undocumented.
* doc/invoke.texi (Option Summary) <RX Options>: Remove redundant
entries for -mno-forms, correct name of -msmall-data-limit option,
add -mlra, clean up formatting.
(RX Options): Minor copy-editing, add -mlra.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
* config/rs6000/darwin.opt (Waltivec-long-deprecated): Mark as
Undocumented.
(faltivec, ffix-and-continue, findirect-data): Likewise.
* config/rs6000/rs6000.opt (mvrsave): Likewise.
* config/rs6000/sysv4.opt (mno-toc, mtoc, mno-traceback): Likewise.
(mshlib, mnewlib): Likewise.
* doc/invoke.texi (Option Summary) <RS/6000 and PowerPC Options>:
Document only one form of each option. Add missing options.
Correct whitespace.
(RS/6000 and PowerPC Options): Separately document -mpowerpc-gpopt,
-mpowerpc-gfxopt, -mpowerpc64, -mmfcrf, -mpopcntb, -mpopcntd,
-mfprnd, -mcmpb, and -mhard-dfp and move their documentation after
-mcpu=. Remove documentation for -mtoc which is unimplemented.
Add missing @opindex entries. Minor copy-editing and whitespace
fixes.
2026-01-17 Sandra Loosemore <sloosemore@baylibre.com>
PR other/122243
PR target/71340
* doc/invoke.texi (Option Summary) <RL78 Options>: Remove
never-implemented -m64bit-doubles and -m32bit-doubles options.
Add missing entries for -mrelax, -mes0, -mmul=rl78, -mcpu=rl78,
and -mrl78.
(RL78 Options): Likewise. Add missing @opindex entries.
Light copy-editing.
2026-01-17 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123513
* tree.cc (valid_new_delete_pair_p): If new_name[3] or delete_name[3]
is 'I', return false with *pcertain set to false rather than true.
2026-01-16 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* hierarchical_discriminator.cc (init_copyid_allocator): Walks the function
body to find existing max copyids per location.
(record_existing_copyid): New.
2026-01-16 Alice Carlotti <alice.carlotti@arm.com>
PR target/123460
* config.gcc: Accept hyphens in aarch64 --with-arch extensions.
2026-01-16 David Malcolm <dmalcolm@redhat.com>
PR analyzer/123145
* timevar.def (TV_ANALYZER_SUPERGRAPH): Rename to...
(TV_ANALYZER_SUPERGRAPH_CREATION): ...this.
(TV_ANALYZER_SUPERGRAPH_FIXUP_LOCATIONS): New.
(TV_ANALYZER_SUPERGRAPH_SIMPLIFY): New.
(TV_ANALYZER_SUPERGRAPH_SORTING): New.
2026-01-16 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/123092
* lra-constraints.cc (lra_constraints): Push insn on processing
stack after equivalence substitution.
2026-01-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR pch/110746
* config/host-freebsd.cc: New file.
* config.host <*-*-freebsd*>: Use it.
* config/x-freebsd: New file.
2026-01-16 Martin Jambor <mjambor@suse.cz>
PR ipa/123412
* ipa-cp.cc (devirtualization_time_bonus): Do add the indirect
edge frequency at least once even for targets which cannot be
inlined.
2026-01-16 Jakub Jelinek <jakub@redhat.com>
PR target/123607
* config/i386/i386.md (movhf_mask): Change constraint on
match_operand 2's second alternative from 0C to 0.
2026-01-16 Lulu Cheng <chenglulu@loongson.cn>
PR target/123521
* config/loongarch/loongarch.cc
(loongarch_expand_vector_init_same): Fixed a bug in the
vector initialization section..
2026-01-16 David Guillen Fandos <david@davidgf.net>
* config/mips/mips.h (ISA_HAS_FMIN_FMAX): Add R5900;
note that, R5900 is not IEEE754 fully compatiable.
2026-01-15 Marek Polacek <polacek@redhat.com>
Jakub Jelinek <jakub@redhat.com>
PR c++/120775
PR c++/123081
PR c++/122634
* attribs.cc (attribute_value_equal): Return false if either attribute
is ATTR_UNIQUE_VALUE_P.
(merge_attributes): Handle lists with ATTR_UNIQUE_VALUE_P values.
* doc/invoke.texi: Document -freflection.
* dwarf2out.cc (is_base_type) <case default>: Check
TREE_CODE >= LAST_AND_UNUSED_TREE_CODE instead of is_cxx_auto.
(gen_type_die_with_usage): For TREE_CODE >= LAST_AND_UNUSED_TREE_CODE
trees use use DW_TAG_unspecified_type.
* tree-core.h (struct tree_base): Update a comment.
* tree.h (ATTR_UNIQUE_VALUE_P): Define.
(BINFO_BASE_ACCESSES): Update the comment.
2026-01-15 Peter Damianov <peter0x44@disroot.org>
PR driver/123504
* config/i386/cygming.h (EXTRA_DEFAULT_COMPILERS): Comment out
.res spec to allow COFF files with .res extension to pass
through to the linker.
* config/aarch64/cygming.h (EXTRA_DEFAULT_COMPILERS): Likewise.
2026-01-15 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* ira-lives.cc (ira_implicitly_set_insn_hard_regs): Honor hard
register constraints.
* ira.cc (ira_setup_alts): Ditto.
2026-01-15 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* doc/extend.texi: Document current limitations of hard register
constraints.
* stmt.cc (parse_output_constraint): Reject multiple hard
register constraints or a combination of hard register
constraints and regular register constraints in one alternative.
(parse_input_constraint): Ditto.
2026-01-15 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-simd.md: Add comment.
* config/aarch64/aarch64-sme.md: Likewise.
* config/aarch64/aarch64-sve-builtins-base.def: Likewise.
* config/aarch64/aarch64-sve-builtins-sme.def: Likewise.
* config/aarch64/aarch64-sve-builtins-sve2.def: Likewise.
* config/aarch64/aarch64-sve-builtins.def: Likewise.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/aarch64.md: Likewise.
2026-01-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sparc/sparc.h (TARGET_SUN_TLS): Remove.
* config/sparc/sol2.h (TARGET_SUN_TLS): Likewise.
* config/sparc/sparc.cc (TARGET_ASM_OUTPUT_DWARF_DTPREL): Guard
with HAVE_GNU_AS.
(sparc_tls_got): Guard with !HAVE_GNU_AS.
(sparc_legitimize_tls_address): Likewise.
* config/sparc/sparc.md ("tls_delay_slot"): Likewise.
("@tie_add<P:mode>"): Likewise.
2026-01-15 Jakub Jelinek <jakub@redhat.com>
PR debug/121045
* tree-pretty-print.h (dump_location): Add new dump_flags_t
argument defaulted to TDF_NONE.
* tree-pretty-print.cc (dump_location): Add flags argument. Don't
print discriminator if TDF_COMPARE_DEBUG bit is set in flags.
(dump_block_node, dump_generic_node): Pass through flags to
dump_location.
* gimple-pretty-print.cc (dump_gimple_phi, pp_gimple_stmt_1,
dump_implicit_edges): Likewise.
(gimple_dump_bb_as_sarif_properties): Pass dump_flags to
dump_location.
* print-rtl.cc (rtx_writer::print_rtx_operand_code_L): If dump_flags
has TDF_COMPARE_DEBUG bit set, don't print discriminators.
2026-01-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/i386/sol2.h [!HAVE_GNU_AS] (ASM_CPU32_DEFAULT_SPEC): Use -m32.
(ASM_CPU64_DEFAULT_SPEC): Use -m64.
2026-01-15 Josef Melcr <josef.melcr@suse.com>
PR ipa/122852
* cgraph.cc (cgraph_node::verify_node): Verify that callback
edges are unreachable when the carrying edge is unreachable.
* ipa-fnsummary.cc (redirect_to_unreachable): Redirect callback
edges to unreachable when redirecting the carrying edge.
2026-01-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_cv_as_sparc_ua_pcrel): Remove.
(gcc_cv_as_sparc_ua_pcrel_hidden): Likewise.
* configure: Regenerate.
* config.in: Regenerate.
* config/sparc/sparc.h (ASM_PREFERRED_EH_DATA_FORMAT): Remove
!HAVE_AS_SPARC_UA_PCREL, !HAVE_AS_SPARC_UA_PCREL_HIDDEN support.
* config/sparc/sol2.h (ASM_PREFERRED_EH_DATA_FORMAT): Remove.
* config/sparc/sparc.cc (TARGET_ASM_OUTPUT_DWARF_DTPREL): Remove
HAVE_AS_SPARC_UA_PCREL guard.
2026-01-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sparc/sparc.h (TARGET_TLS): Define as HAVE_AS_TLS.
Update comment.
(TARGET_SUN_TLS): Define as 0.
(TARGET_GNU_TLS): Remove.
* config/sparc/freebsd.h (TARGET_SUN_TLS): Remove.
(TARGET_GNU_TLS): Remove.
* config/sparc/linux.h: Likewise.
* config/sparc/linux64.h: Likewise.
* config/sparc/sol2.h (TARGET_SUN_TLS): Redefine as 1.
Guard with HAVE_AS_TLS && !HAVE_GNU_AS.
(TARGET_GNU_TLS): Remove.
* config/sparc/sparc.cc (TARGET_ASM_OUTPUT_DWARF_DTPREL): Use
!TARGET_SUN_TLS in guard.
with !TARGET_SUN_TLS only.
* config/sparc/sparc.md ("tls_delay_slot"): Guard with
!TARGET_SUN_TLS.
2026-01-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR target/38118
* config/sparc/sol2.h (ASM_OUTPUT_ALIGNED_COMMON): Remove.
2026-01-15 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* cfgloopmanip.cc (duplicate_loop_body_to_header_edge): Assign
hierarchical discriminators for loop unrolling.
* cfgloopmanip.h (DLTHE_RECORD_HIERARCHICAL_DISCRIMINATOR): New flag.
* tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely): Pass flag
to enable hierarchical discriminator assignment.
(try_peel_loop): Likewise.
2026-01-15 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* gimple-loop-versioning.cc (loop_versioning::version_loop): Assign
copyid discriminators to distinguish different loop versions.
2026-01-15 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* tree-vect-loop-manip.cc (vect_loop_versioning): Assign copyid
discriminators for vectorized and scalar loop versions.
* tree-vect-loop.cc (vect_transform_loop): Assign copyid
discriminators for vectorized and scalar loop versions.
2026-01-15 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* Makefile.in: Add hierarchical_discriminator.o to OBJS.
* hierarchical_discriminator.cc: New file.
* hierarchical_discriminator.h: New file.
* function.h (copyid_alloc): New.
* input.cc (location_with_discriminator_components): New function.
(get_discriminator_components_from_loc): Likewise.
* input.h (DISCR_BASE_BITS): New constant.
(DISCR_MULTIPLICITY_BITS): Likewise.
(DISCR_COPYID_BITS): Likewise.
(DISCR_UNUSED_BITS): Likewise.
(DISCR_BASE_MASK): Likewise.
(DISCR_MULTIPLICITY_MASK): Likewise.
(DISCR_COPYID_MASK): Likewise.
(DISCR_BASE_SHIFT): Likewise.
(DISCR_MULTIPLICITY_SHIFT): Likewise.
(DISCR_COPYID_SHIFT): Likewise.
(DISCR_BASE_MAX): Likewise.
(DISCR_MULTIPLICITY_MAX): Likewise.
(DISCR_COPYID_MAX): Likewise.
(location_with_discriminator_components): New function declaration.
(get_discriminator_components_from_loc): Likewise.
2026-01-15 DengJianbo <dengjianbo@loongson.cn>
* config/loongarch/loongarch.md: Remove condition in template
movdi_symbolic_off64.
2026-01-14 Peter Bergner <bergner@tenstorrent.com>
PR target/123092
* config/riscv/constraints.md (ZD): Disable when xmipscbop is disabled.
2026-01-14 Martin Jambor <mjambor@suse.cz>
PR ipa/123542
* ipa-cp.cc (ipa_value_from_jfunc): Always use
ipacp_value_safe_for_type. Bail out if parm_type is NULL.
2026-01-14 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/121240
* config/aarch64/aarch64.md (mov<mode>): Expand FP immediates early.
* config/aarch64/aarch64.cc (aarch64_select_rtx_section): Force
immediates <= 8 bytes to constdata.
(aarch64_rtx_costs): Increase cost of CONST_DOUBLE loaded from memory.
2026-01-14 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/114528
* config/aarch64/aarch64.cc (aarch64_check_mov_add_imm12):
New function to check and emit MOV+ADD/SUB immediates.
(aarch64_internal_mov_immediate): Add support for MOV+ADD/SUB
immediates.
2026-01-14 Tejas Belagod <tejas.belagod@arm.com>
PR middle-end/123392
* cfgexpand.cc (expand_debug_expr): Handle variable-length initializer
for CONSTRUCTOR.
2026-01-14 Jakub Jelinek <jakub@redhat.com>
PR middle-end/123115
* defaults.h (EH_RETURN_DATA_REGNO): Add void (N) to the macro
definition inside of a comma expression before INVALID_REGNUM.
2026-01-14 Jakub Jelinek <jakub@redhat.com>
PR target/120250
* combine.cc (recog_for_combine): Don't try to put SET_SRC
into a constant pool if SET_DEST is pc_rtx.
2026-01-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/123190
* tree-vectorizer.h (vect_load_store_data): Add n_loads member.
* tree-vect-stmts.cc (get_load_store_type): Record the
number of required loads for permuted loads.
(vectorizable_load): Make use of this when costing loads
for VMAT_CONTIGUOUS[_REVERSE].
2026-01-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/123190
* tree-vect-loop.cc (vect_analyze_loop_costing): Allow
vectorizing loops with a single scalar iteration iff the
vectorization factor is 1.
2026-01-14 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/123544
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case AND>: Don't canonicalize (subreg (lshiftrt (x cnt)) low) into
(lshiftrt (subreg x low) cnt) if the SUBREG is paradoxical.
2026-01-14 Prathamesh Kulkarni <prathameshk@nvidia.com>
* auto-profile.cc: (string_table::filenames): New method.
(function_instance::timestamp_): New member.
(function_instance::timestamp): New accessor for timestamp_ member.
(function_instance::set_timestamp): New function.
(function_instance::prop_timestamp): Likewise.
(function_instance::prop_timestamp_1): Likewise.
(function_instance::function_instance): Initialize timestamp_ to 0.
(function_instance::read_function_instance): Adjust prototype by
replacing head_count with toplevel param with default value true, and
stream in head_count and timestamp values from gcov file.
(autofdo::timestamp_info_map): New std::map.
(autofdo_source_profile::get_function_instance_by_decl): New argument
filename with default value NULL.
(autofdo_source_profile::read): Populate timestamp_info_map and
propagate timestamp to inlined instances from toplevel function.
(afdo_annotate_cfg): Assign node->tp_first_run based on
timestamp_info_map and bail out of annotation if
param_auto_profile_reorder_only is enabled.
* params.opt: New param auto-profile-reorder-only.
2026-01-14 Lili Cui <lili.cui@intel.com>
* config/i386/x86-tune.def (X86_TUNE_ALIGN_TIGHT_LOOPS):
disable tight loop alignment for m_CORE_ATOM.
2026-01-14 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
* match.pd: remove 'fold_overflow_warning' references.
* tree.h (TYPE_OVERFLOW_UNDEFINED): remove note telling
that we must use warn_strict_overflow for every optimization
based on TYPE_OVERFLOW_UNDEFINED.
2026-01-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* match.pd (`(T1)(a bit_op (T2)b)`): Remove redundant
type checks.
2026-01-13 Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>
PR tree-optimization/123109
* fold-const.cc (fold_binary_loc): Remove (X >> C) NE/EQ 0 -> X LT/GE 0
folding.
* match.pd (`(X >> C) NE/EQ 0 -> X LT/GE 0`): New pattern.
2026-01-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/119402
* match.pd (`(a*zero_one_valued_p) & b`): New pattern.
2026-01-13 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/123312
* ifcvt.cc (noce_try_cond_zero_arith): Rename to ...
(noce_try_cond_arith): This. For AND try `cmp ? a : -1`
also to see which one cost less.
(noce_process_if_block): Handle the rename.
2026-01-13 Jonathan Yong <10walls@gmail.com>
* config/i386/winnt-utf8.manifest: enable longPathAware.
2026-01-13 Jonathan Yong <10walls@gmail.com>
PR driver/108865
* config/i386/winnt-utf8.manifest: correct XML tags
2026-01-13 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR tree-optimization/123530
* match.pd (reassociating xor to enable rotations): Verify constants
fit into a uhwi before trying to extract them as a uhwi.
2026-01-13 Richard Biener <rguenther@suse.de>
PR middle-end/123573
* fold-const.cc (fold_vec_perm): Actually check, not assert,
that input and output vector element numbers agree.
* match.pd (vec_perm @0 @1 @2): Make sure element numbers
are the same when folding to an input vector and wrap that
inside a VIEW_CONVERT_EXPR.
2026-01-13 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123525
* tree-ssa-forwprop.cc (simplify_vector_constructor): Use
converted source type for conversion bit field ref.
2026-01-13 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123301
* tree-if-conv.cc (convert_scalar_cond_reduction):
Disallow vector types.
2026-01-13 Robin Dapp <rdapp@oss.qualcomm.com>
PR rtl-optimization/123501
PR rtl-optimization/123444
* rtlanal.cc (nonzero_bits1): Use operand mode instead of
operation mode.
2026-01-13 Jakub Jelinek <jakub@redhat.com>
PR libstdc++/123396
* configure.ac (gcc_cv_ld_use_as_needed_ldscript): New test.
(USE_LD_AS_NEEDED_LDSCRIPT): New AC_DEFINE.
* gcc.cc (LINK_LIBATOMIC_SPEC): Use "-latomic_asneeded" instead
of LD_AS_NEEDED_OPTION " -latomic " LD_NO_AS_NEEDED_OPTION
if USE_LD_AS_NEEDED_LDSCRIPT is defined.
(init_gcc_specs): Use "-lgcc_s_asneeded" instead of
LD_AS_NEEDED_OPTION " -lgcc_s " LD_NO_AS_NEEDED_OPTION
if USE_LD_AS_NEEDED_LDSCRIPT is defined.
* config.in: Regenerate.
* configure: Regenerate.
2026-01-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/123539
* tree-vect-loop.cc (vect_create_epilog_for_reduction):
Use the compute vectype to pun down to smaller or element
size for by-element reductions.
2026-01-13 Kito Cheng <kito.cheng@sifive.com>
* tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
build_bitint_type for BITINT_TYPE when maxsizei exceeds
MAX_FIXED_MODE_SIZE.
2026-01-13 Kito Cheng <kito.cheng@sifive.com>
PR target/117581
* config/riscv/riscv.cc (riscv_bitint_type_info): New function.
(TARGET_C_BITINT_TYPE_INFO): Define.
2026-01-13 liuhongt <hongtao.liu@intel.com>
PR target/123484
* config/i386/mmx.md (divv4hf3): Add TARGET_MMX_WITH_SSE to
the condition.
(cmlav4hf4): Ditto.
(cmla_conjv4hf4): Ditto.
(cmulv4hf3): Ditto.
(cmul_conjv4hf3): Ditto.
2026-01-12 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/122845
PR tree-optimization/122843
* match.pd (`(T1)(a bit_op (T2)b)`): Also
simplify if T1 is the same type as b and T2 is wider
type than T1.
2026-01-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/123528
* tree-vect-patterns.cc (vect_recog_bool_pattern): Restore
INTEGRAL_TYPE_P check but also allow SCALAR_FLOAT_TYPE_P.
2026-01-12 Martin Jambor <mjambor@suse.cz>
PR ipa/123543
* ipa-cp.cc (propagate_bits_across_jump_function): Fix test for
recipient_only_p.
2026-01-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/122830
PR tree-optimization/122824
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Generalize
aggregate copy handling when no variable offsets are
involved.
2026-01-12 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Only tentatively
accumulate extra_off when tentatively consuming components
during aggregate copy handling.
2026-01-12 Richard Biener <rguenther@suse.de>
PR middle-end/123175
* match.pd (vec_perm @0 @1 @2): Fixup for inputs having a
different number of elements than the result.
* tree-vect-generic.cc (lower_vec_perm): Likewise.
2026-01-12 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/123523
* simplify-rtx.cc (simplify_const_binary_operation): Use
DImode for VOIDmode shift and truncation counts if int_mode
is narrower than HOST_BITS_PER_WIDE_INT rather than
word_mode if int_mode it is narrower than BITS_PER_WORD.
2026-01-12 Dhruv Chawla <dhruvc@nvidia.com>
* auto-profile.cc (autofdo_source_profile::offline_unrealized_inlines):
Add missing check for in_map.
2026-01-11 Michal Jires <mjires@suse.cz>
* asm-toplevel.cc (mark_fragile_ref_by_asm):
Add marked_local to handle symbol as local.
(ipa_asm_heuristics): New.
(class pass_ipa_asm): New.
(make_pass_ipa_asm_lgen): New.
(make_pass_ipa_asm_wpa): New.
* common.opt: New flto-toplevel-asm-heuristics.
* passes.def: New asm passes.
* timevar.def (TV_IPA_LTO_ASM): New.
* tree-pass.h (make_pass_ipa_asm_lgen): New.
(make_pass_ipa_asm_wpa): New.
2026-01-11 Michal Jires <mjires@suse.cz>
* asm-toplevel.cc (mark_fragile_ref_by_asm): New.
(struct constraint_data): New.
(walk_through_constraints): Handle .local definitions.
(analyze_toplevel_extended_asm): Propagate constraint_data.
2026-01-11 Michal Jires <mjires@suse.cz>
* cgraph.h: Add must_remain_in_tu_*.
* cgraphclones.cc (cgraph_node::create_clone): Propagate
must_remain_in_tu_body.
* cif-code.def (MUST_REMAIN_IN_TU): New.
* ipa-icf.cc (sem_function::equals_wpa): Check
must_remain_in_tu_*
(sem_variable::equals_wpa): Likewise.
* ipa-inline-transform.cc (inline_call): Propagate
must_remain_in_tu_body.
* ipa-inline.cc (can_inline_edge_p): Check
must_remain_in_tu_body.
* lto-cgraph.cc (lto_output_node): Output must_remain_in_tu_*
(lto_output_varpool_node): Likewise.
(input_overwrite_node): Input must_remain_in_tu_*.
(input_varpool_node): Likewise.
* tree.cc (decl_address_ip_invariant_p): Check
must_remain_in_tu_name.
* varpool.cc (varpool_node::ctor_useable_for_folding_p): Check
must_remain_in_tu_body.
2026-01-11 Michal Jires <mjires@suse.cz>
* lto-cgraph.cc (compute_ltrans_boundary): Add symbols
referenced from asm_nodes.
* lto-streamer-out.cc (lto_output): Move adding asm_nodes
to...
* passes.cc (ipa_write_summaries): ...here.
2026-01-11 Michal Jires <mjires@suse.cz>
* ipa-free-lang-data.cc (find_decls_types_in_asm): New.
(free_lang_data_in_cgraph): Use find_decls_types_in_asm.
* lto-cgraph.cc (input_cgraph_1): Move asm to..
(input_toplevel_asms): ..here.
* lto-streamer-in.cc (lto_input_toplevel_asms):
Allow extended asm.
* lto-streamer-out.cc (lto_output_toplevel_asms):
Allow extended asm.
(lto_output_toplevel_asms): Allow ASM_EXPR.
* lto-streamer.h (input_toplevel_asms): New.
2026-01-11 Michal Jires <mjires@suse.cz>
PR ipa/122458
* Makefile.in: Add new file.
* cgraph.h (analyze_toplevel_extended_asm): New.
* cgraphunit.cc (symbol_table::finalize_compilation_unit):
Call analyze_toplevel_extended_asm.
* asm-toplevel.cc: New file.
2026-01-11 Michal Jires <mjires@suse.cz>
* cgraph.cc (cgraph_node_cannot_be_local_p_1): Check ref_by_asm.
(cgraph_node::verify_node): Likewise.
* cgraph.h (cgraph_node::only_called_directly_or_aliased_p):
Likewise.
(cgraph_node::can_remove_if_no_direct_calls_and_refs_p):
Likewise.
(varpool_node::can_remove_if_no_refs_p): Likewise.
(varpool_node::all_refs_explicit_p): Likewise.
* cgraphunit.cc (symtab_node::needed_p): Likewise.
(analyze_functions): Likewise.
* gimple-ssa-pta-constraints.cc (refered_from_nonlocal_fn):
Likewise.
(refered_from_nonlocal_var): Likewise.
(ipa_create_global_variable_infos): Likewise.
* ipa-comdats.cc (ipa_comdats): Likewise.
* ipa-visibility.cc (cgraph_externally_visible_p): Likewise.
(varpool_node::externally_visible_p): Likewise.
* ipa.cc (symbol_table::remove_unreachable_nodes): Likewise.
* lto-cgraph.cc (lto_output_node): Output ref_by_asm.
(lto_output_varpool_node): Likewise.
(input_overwrite_node): Input ref_by_asm.
(input_varpool_node): Likewise.
* symtab.cc (address_matters_1): Check ref_by_asm.
2026-01-11 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_rtx_costs) <POST_INC>: Handle POST_INC
as ZERO_EXTEND and SIGN_EXTEND, i.e. as an operator without cost.
2026-01-10 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/mcore/mcore.h (ASM_OUT_ADDR_DIFF_ELT): Remove.
2026-01-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-modes.def (FLOAT_MODE): Add HF mode.
(VECTOR_MODE): Add V{1,2,4,8,16}HF modes.
* config/s390/s390.cc (s390_scalar_mode_supported_p): For 64-bit
targets z10 and newer support HF mode.
(s390_vector_mode_supported_p): Add HF mode.
(s390_register_move_cost): Keep HF mode operands in registers.
(s390_legitimate_constant_p): Support zero constant.
(s390_secondary_reload): For GPR to FPR moves a secondary reload
register is required.
(s390_secondary_memory_needed): GPR<->FPR moves don't require
secondary memory.
(s390_libgcc_floating_mode_supported_p): For 64-bit targets z10
and newer support HF mode.
(s390_hard_regno_mode_ok): Allow HF mode for FPRs and VRs.
(s390_function_arg_float): Consider HF mode, too.
(s390_excess_precision): For EXCESS_PRECISION_TYPE_FLOAT16
return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16.
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
* config/s390/s390.md (movhf): Define.
(reload_half_gprtofpr_z10): Define.
(signbithf2): Define.
* config/s390/vector.md: Add new vector modes to various
iterators.
2026-01-10 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123417
* tree-cfgcleanup.cc (maybe_remove_forwarder_block): Always
protect latches.
2026-01-10 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123431
* gimple-range-op.cc (gimple_range_op_handler::maybe_builtin_call):
Punt if type-generic builtins with a single argument don't have
exactly one argument. For returns_arg punt if call doesn't have
at least one argument.
2026-01-09 Robin Dapp <rdapp@oss.qualcomm.com>
PR tree-optimization/123414
* tree-ssa-forwprop.cc (simplify_vector_constructor):
Use ssizetype as mask type.
2026-01-09 Jakub Jelinek <jakub@redhat.com>
* config/loongarch/genopts/gen-evolution.awk: Update
copyright year.
(copyright_header): Separate parts of Copyright word
with " " so that it doesn't get matched by update-copyright.py.
(gen_full_header, gen_full_source, gen_full_def): Include
2026 year in the ranges.
2026-01-09 David Malcolm <dmalcolm@redhat.com>
* channels.h (gcc::topics::analyzer_events::subscriber): New
forward decl.
(compiler_channels::analyzer_events_channel): New field.
* doc/plugins.texi (PLUGIN_ANALYZER_INIT): Delete.
* plugin.cc (register_callback): Delete PLUGIN_ANALYZER_INIT.
(invoke_plugin_callbacks_full): Likewise.
* plugin.def (PLUGIN_ANALYZER_INIT): Delete this event.
2026-01-09 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS): Add tree-diagnostic-cfg.o.
(OBJS-libcommon): Add custom-sarif-properties/cfg.o,
diagnostics/digraphs-to-dot.o, and
diagnostics/digraphs-to-dot-from-cfg.o.
* cfghooks.cc: Define INCLUDE_VECTOR. Add includes of
"diagnostics/sarif-sink.h" and "custom-sarif-properties/cfg.h".
(dump_bb_as_sarif_properties): New.
* cfghooks.h (diagnostics::sarif_builder): New forward decl.
(json::object): New forward decl.
(cfg_hooks::dump_bb_as_sarif_properties): New callback field.
(dump_bb_as_sarif_properties): New decl.
* cfgrtl.cc (rtl_cfg_hooks): Populate the new callback
field with rtl_dump_bb_as_sarif_properties.
(cfg_layout_rtl_cfg_hooks): Likewise.
* custom-sarif-properties/cfg.cc: New file.
* custom-sarif-properties/cfg.h: New file.
* diagnostics/digraphs-to-dot-from-cfg.cc: New file, partly
adapted from gcc/graph.cc.
* diagnostics/digraphs-to-dot.cc: New file.
* diagnostics/digraphs-to-dot.h: New file, based on material in...
* diagnostics/digraphs.cc: Include
"diagnostics/digraphs-to-dot.h".
(class conversion_to_dot): Rework and move to above.
(make_dot_graph_from_diagnostic_graph): Likewise.
(make_dot_node_from_digraph_node): Likewise.
(make_dot_edge_from_digraph_edge): Likewise.
(conversion_to_dot::get_dot_id_for_node): Likewise.
(conversion_to_dot::has_edges_p): Likewise.
(digraph::make_dot_graph): Use to_dot::converter::make and invoke
the result to make the dot graph.
* diagnostics/digraphs.h (digraph:get_all_nodes): New accessor.
* diagnostics/html-sink.cc
(html_builder::m_per_logical_loc_graphs): New field.
(html_builder::add_graph_for_logical_loc): New.
(html_sink::report_digraph_for_logical_location): New.
* diagnostics/sarif-sink.cc (sarif_array_of_unique::get_element):
New.
(sarif_builder::report_digraph_for_logical_location): New.
(sarif_sink::report_digraph_for_logical_location): New.
* diagnostics/sink.h: Include "diagnostics/logical-locations.h".
(sink::report_digraph_for_logical_location): New vfunc.
* diagnostics/text-sink.h
(text_sink::report_digraph_for_logical_location): New.
* doc/invoke.texi (fdiagnostics-add-output): Clarify wording.
Distinguish between scheme-specific vs GCC-specific keys, and add
"cfgs" as the first example of the latter.
* gimple-pretty-print.cc: Include "cfghooks.h", "json.h", and
"custom-sarif-properties/cfg.h".
(gimple_dump_bb_as_sarif_properties): New.
* gimple-pretty-print.h (diagnostics::sarif_builder): New forward
decl.
(json::object): Likewise.
(gimple_dump_bb_as_sarif_properties): New.
* graphviz.cc (get_compass_pt_from_string): New
* graphviz.h (get_compass_pt_from_string): New decl.
* libsarifreplay.cc (sarif_replayer::handle_graph_object): Fix
overlong line.
* opts-common.cc: Define INCLUDE_VECTOR.
* opts-diagnostic.cc: Define INCLUDE_LIST. Include
"diagnostics/sarif-sink.h", "tree-diagnostic-sink-extensions.h",
"opts-diagnostic.h", and "pub-sub.h".
(class gcc_extra_keys): New class.
(opt_spec_context::opt_spec_context): Add "client_keys" param and
pass to dc_spec_context.
(handle_gcc_specific_keys): New.
(try_to_make_sink): New.
(gcc_extension_factory::singleton): New.
(handle_OPT_fdiagnostics_add_output_): Rework to use
try_to_make_sink.
(handle_OPT_fdiagnostics_set_output_): Likewise.
* opts-diagnostic.h: Include "diagnostics/sink.h".
(class gcc_extension_factory): New.
* opts.cc: Define INCLUDE_LIST.
* print-rtl.cc: Include "dumpfile.h", "cfghooks.h", "json.h", and
"custom-sarif-properties/cfg.h".
(rtl_dump_bb_as_sarif_properties): New.
* print-rtl.h (diagnostics::sarif_builder): New forward decl.
(json::object): Likewise.
(rtl_dump_bb_as_sarif_properties): New decl.
* tree-cfg.cc (gimple_cfg_hooks): Use
gimple_dump_bb_as_sarif_properties for new callback field.
* tree-diagnostic-cfg.cc: New file, based on material in graph.cc.
* tree-diagnostic-sink-extensions.h: New file.
* tree-diagnostic.cc: Define INCLUDE_LIST. Include
"tree-diagnostic-sink-extensions.h".
(compiler_ext_factory): New.
(tree_diagnostics_defaults): Set gcc_extension_factory::singleton
to be compiler_ext_factory.
2026-01-09 David Malcolm <dmalcolm@redhat.com>
* channels.h: New file.
* context.cc: Define INCLUDE_LIST. Include "channels.h".
(gcc::context::context): Create m_channels.
(gcc::context::~context): Delete it.
* context.h (struct compiler_channels): New forward decl.
(gcc::context::get_channels): New accessor.
(gcc::context::m_channels): New field.
* passes.cc: Define INCLUDE_LIST. Include "topics/pass-events.h"
and "channels.h".
(execute_one_pass): If the global context's pass_events_channel
has subscribers, publish before_pass and after_pass events to it.
* topics/pass-events.h: New file.
2026-01-09 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon): Add pub-sub.o.
* pub-sub.cc: New file.
* pub-sub.h: New file.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::pub_sub_cc_tests.
* selftest.h (selftest::pub_sub_cc_tests): New decl.
2026-01-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR target/123457
* config/aarch64/aarch64-sve-builtins.cc (struct registered_function_hasher):
Change base class to ggc_ptr_hash.
(initial_indexes): Mark with GTY.
(function_table): Likewise.
(handle_arm_sve_h): Allocate function_table from ggc instead of heap.
2026-01-09 Jakub Jelinek <jakub@redhat.com>
* doc/invoke.texi (-x): Add c++-system-module, objc-cpp-output,
objc++-cpp-output, adascil, adawhy, modula-2, modula-2-cpp-output,
rust, algol68 and lto as further possible option arguments.
2026-01-09 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/123121
* lra-remat.cc (bad_for_rematerialization_p): Consider div/mod ops.
(operand_to_remat): Exclude rematerialization of insns with
multiple sets.
2026-01-09 Peter Bergner <bergner@tenstorrent.com>
PR target/123492
* config/riscv/riscv-cores.def (RISCV_CORE)<tt-ascalon-d8>: Add missing
extensions via use of rva23s64 profile and adding zkr, smaia, smmpm,
smnpm, smrnmi, smstateen, ssaia, ssstrict, svadu.
2026-01-09 Martin Jambor <mjambor@suse.cz>
* ipa-cp.h (class ipcp_bits_lattice): New members set_recipient_only,
recipient_only_p and m_recipient_only.
(class ipcp_vr_lattice): Likewise.
(ipcp_vr_lattice::init): Initialize also m_recipient_only.
* ipa-cp.cc (ipcp_bits_lattice::print): Adjust printting to also
print the new flag.
(ipcp_vr_lattice::print): Likewise.
(ipcp_vr_lattice::set_recipient_only): New function.
(ipcp_bits_lattice::set_recipient_only): Likewise.
(set_all_contains_variable): New parameter MAKE_SIMPLE_RECIPIENTS, set
bits and vr lattices to recibient only insted to bottom when it is
true.
(initialize_node_lattices): Pass true to the second parameter of
set_all_contains_variable.
(propagate_bits_across_jump_function): Treat recipient_only source
lattices like bottom.
(propagate_vr_across_jump_function): Likewise.
(ipcp_store_vr_results): Skip non-local nodes.
2026-01-09 Martin Jambor <mjambor@suse.cz>
* ipa-cp.cc (good_cloning_opportunity_p): Dump a message when
bailing out early too.
(find_more_scalar_values_for_callers_subset): Rename to
find_scalar_values_for_callers_subset, collect constants regardless of
what is already in the vector. Remove dumping.
(find_more_contexts_for_caller_subset): Rename to
find_contexts_for_caller_subset, collect contexts regardless of what
is already in the vector. Remove dumping.
(find_aggregate_values_for_callers_subset): Rename to
find_aggregate_values_for_callers_subset_gc, implement using new
functions.
(find_aggregate_values_for_callers_subset_1): New function.
(find_aggregate_values_for_callers_subset): Likewise.
(copy_known_vectors_add_val): Removed.
(dump_reestimation_message): New function.
(decide_about_value): Remove formal parameter avals, compute it
independently, and use it to estimate local cloning effects.
(struct cloning_opportunity_ranking): New type.
(compare_cloning_opportunities): New function.
(cloning_opportunity_ranking_evaluation): Likewise.
(decide_whether_version_node): Pre-sort candidates for cloning before
really evaluating them. Calculate context independent values only
when considering versioning for all contexts.
(ipcp_val_agg_replacement_ok_p): Renamed to
ipcp_val_replacement_ok_p, check also non-aggregate values.
2026-01-09 Alexandre Oliva <oliva@gnu.org>
PR target/119430
* config/arm/arm.cc (arm_function_ok_for_sibcall): Disable
sibcalls for long-calls that use all call-clobbered
general-purpose registers, including the static chain.
2026-01-09 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (print_operand): Align %cN with %N.
* config/s390/s390.md: Remove comment.
2026-01-09 Filip Kastl <fkastl@suse.cz>
PR c/123212
* opts.cc: Enable -fbit-tests and -fjump-tables at -Og.
2026-01-09 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64-builtins.cc
(aarch64_expand_pragma_builtin): Add case for FMMLA.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Add new __ARM_FEATURE_X macros.
* config/aarch64/aarch64-simd-pragma-builtins.def
(vmmlaq_f16_mf8): New intrinsic.
(vmmlaq_f32_mf8): Likewise.
* config/aarch64/aarch64-simd.md
(@aarch64_<insn><VDQ_HSF_FMMLA:mode>): New instruction.
* config/aarch64/aarch64-sve-builtins-base.cc: Update mmla_impl
for new instructions.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(struct mmla_def): Add support for the new widening forms.
* config/aarch64/aarch64-sve-builtins-sve2.def (svmmla) Add new
intrinsics.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_cvt_narrow_s):
Fix comment.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve2_<sve_fp_op><SVE_FULL_HSF_FMMLA:mode><VNx16QI_ONLY:mode>): New instruction.
(@aarch64_sve2_<sve_fp_op><VNx4SF_ONLY:mode><VNx8HF_ONLY:mode>): Likewise.
* config/aarch64/aarch64.h (TARGET_F8F32MM): New macro.
(TARGET_F8F16MM): Likewise.
(TARGET_SVE_F16F32MM): Likewise.
* config/aarch64/iterators.md (insn): Add fmmla entry.
(VDQ_HSF_FMMLA): New iterator.
(SVE_FULL_HSF_FMMLA): Likewise.
2026-01-09 Christophe Lyon <christophe.lyon@linaro.org>
* config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Remove
TARGET_HAVE_MVE condition.
(class arm_target_switcher): New.
(arm_init_mve_builtins): Remove calls to
arm_init_simd_builtin_types and
arm_init_simd_builtin_scalar_types. Switch to MVE isa flags.
(arm_init_neon_builtins): Remove calls to
arm_init_simd_builtin_types and
arm_init_simd_builtin_scalar_types.
(arm_need_mve_mode_regs): New.
(arm_need_neon_mode_regs): New.
(arm_target_switcher::arm_target_switcher): New.
(arm_target_switcher::~arm_target_switcher): New.
(arm_init_builtins): Call arm_init_simd_builtin_scalar_types and
arm_init_simd_builtin_types. Always call arm_init_mve_builtins
and arm_init_neon_builtins.
2026-01-09 Jakub Jelinek <jakub@redhat.com>
PR target/123489
* config/i386/i386-builtin.def (__builtin_ia32_cvttsd2sis64_round,
__builtin_ia32_cvttsd2usis64_round, __builtin_ia32_cvttss2sis64_round,
__builtin_ia32_cvttss2usis64_round): Require OPTION_MASK_ISA_64BIT.
2026-01-09 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR rtl-optimization/123491
* ifcvt.cc (noce_try_cond_zero_arith): Reject non-scalar
integer modes for the inner mode of the subreg.
2026-01-09 Shreya Munnangi <smunnangi1@ventanamicro.com>
Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/121778
* match.pd: Add pattern to recognize rotate with one or more
bits flipped via xor.
* config/sh/sh.md (*rotcl); New variant which handles the output
we get after the match.pd change above.
2026-01-09 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/andes-23-series.md: Clamp reservations to 7c.
* config/riscv/andes-25-series.md: Likewise.
* config/riscv/andes-45-series.md: Likewise.
* config/riscv/generic.md: Likewise.
* config/riscv/mips-p8700.md: Likewise.
* config/riscv/sifive-7.md: Likewise.
* config/riscv/spacemit-x60.md: Likewise.
2026-01-09 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
PR gcov-profile/123019
* auto-profile.cc (auto_profile): Call execute_fixup_cfg.
2026-01-09 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
PR ipa/123383
* cgraph.cc (cgraph_edge::get_next_speculative_id): Check
lto_stmt_uid in get_next_speculative_id.
2026-01-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/111817
* stmt.cc (parse_input_constraint): For matching construct, goto
before the loop without changing j instead of break. Remove comment
about that problem.
2026-01-08 Robin Dapp <rdapp@ventanamicro.com>
PR target/122846
* config/riscv/riscv-opts.h (enum rvv_max_lmul_enum): Add
RVV_CONV_DYNAMIC.
(TARGET_MAX_LMUL): Ditto.
* config/riscv/riscv-string.cc (use_vector_stringop_p): Use
LMUL1 for RVV_CONV_DYNAMIC.
(expand_rawmemchr): Ditto.
(expand_strcmp): Ditto.
(check_vectorise_memory_operation): Ditto.
* config/riscv/riscv-vector-costs.cc (get_smallest_mode):
New function.
(compute_lmul_from_conversion_ratio): Calculate LMUL from
largest/smallest type.
(costs::has_unexpected_spills_p): Split.
(costs::compute_live_ranges_and_lmul): Compute smallest type and
call new function.
(costs::cleanup_live_range_data): New function.
(costs::compute_conversion_dynamic_lmul): New function.
(costs::record_potential_unexpected_spills): Use new function.
(costs::better_main_loop_than_p): Allow appropriate LMUL.
* config/riscv/riscv-vector-costs.h: Declare.
* config/riscv/riscv.opt: New option
-mrvv-max-lmul=conv-dynamic.
2026-01-08 Qing Zhao <qing.zhao@oracle.com>
* doc/extend.texi: Update doc to support pointers inside structures.
2026-01-08 Olivier Hainque <hainque@adacore.com>
Alexandre Oliva <oliva@adacore.com>
* config.gcc [x86_64-*-*]: Match *abi32 target, default to m32
abi. Accept 32 or m32 for --with-abi.
2026-01-08 Jonathan Wakely <jwakely@redhat.com>
* doc/invoke.texi (C++ Dialect Options): Fix typo in
documentation of -flang-info-module-cmi.
2026-01-08 Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
* Makefile.in: Add with_multi_buildlist for multilib
configuration control. Pass an additional argument to
genmultilib indicating whether --with-multi-buildlist is set
(true or false). Use with_multi_buildlist to filter
multilib directories in fixinc_list.
* configure: Regenerate.
* configure.ac: Restrict the installed fixedincludes multilibs.
* configure.tgt: New file.
* doc/install.texi: Add --with-multi-buildlist configure option
for multilib filtering.
* genmultilib: Document the new eleventh argument indicating
whether --with-multi-buildlist configure option is set (true or
false). Update argument parsing to include this flag before
enable_multilib. Modify reuse rule validation:
- Keep the original error for reuse of nonexistent multilibs
when --with-multi-buildlist is not used.
- Suppress the error only when the new configure option is
active, allowing reuse rules to reference multilibs that are
intentionally excluded from the build.
2026-01-08 Tomas Glozar <tglozar@gmail.com>
* config/ia64/ia64.cc (MAX_VECT_LEN): Set to 16 from 8.
2026-01-08 Robin Dapp <rdapp.gcc@gmail.com>
PR target/123268
* gimple-match-exports.cc (convert_conditional_op): Check if
orig_op->type and type of else value match.
2026-01-08 Richard Sandiford <rdsandiford@googlemail.com>
Richard Biener <rguenther@suse.de>
PR tree-optimization/122793
* tree-vect-slp.cc (vect_add_slp_permutation): Document the existing
identity_offset parameter. Handle identities that take from the
second input rather than the first.
2026-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/123310
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Properly
test against unknown offset.
2026-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/123298
* tree-ssa-alias.h (get_continuation_for_phi): Take a gphi *,
add is_backedge hook argument.
(walk_non_aliased_vuses): Add is_backedge hook argument.
* tree-ssa-alias.cc (maybe_skip_until): Adjust.
(get_continuation_for_phi): Use new hook to classify an
edge into the PHI as backedge.
(walk_non_aliased_vuses): Adjust.
* gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children):
Likewise.
* ipa-prop.cc (determine_known_aggregate_parts): Likewise.
* tree-ssa-scopedtables.cc (avail_exprs_stack::lookup_avail_expr):
Likewise.
* tree-ssa-pre.cc (translate_vuse_through_block): Likewise.
* tree-ssa-sccvn.cc (vn_bb_to_rpo): Make BB to RPO order
mapping accessible from new hook.
(do_rpo_vn_1): Likewise.
(vn_is_backedge): New hook to classify edge.
(vn_reference_lookup_pieces): Adjust.
(vn_reference_lookup): Likewise.
2026-01-08 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_shift): Improve missing
optab or optab support messages.
(vectorizable_operation): Likewise.
2026-01-08 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc (s390_logical_operator_ok_p): Test for
volatile memory.
(s390_mem_constraint): Remove volatile condition.
* config/s390/s390.md (*andc_split_<mode>): Test for volatile
memory.
2026-01-08 Richard Biener <rguenther@suse.de>
PR middle-end/123107
* fold-const.cc (fold_binary_loc): Guard (v >> CST) == { 0, 0.. }
to v < { 0, 0.. } folding.
2026-01-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
PR tree-optimization/123382
* tree-if-conv.cc: Reject VEC_PERM_EXPR for factoring
if it is the mask and they are constant.
2026-01-08 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* cse.cc (cse_find_path): Change follow_jumps to bool.
2026-01-07 Tomas Glozar <tglozar@gmail.com>
PR target/121535
* config/ia64/ia64.cc (TARGET_ZERO_CALL_USED_REGS): Override
function with target-specific one.
(struct gcc_target): Move to end of file.
(ia64_zero_call_used_regs): Add target-specific function.
2026-01-07 Xinhui Yang <cyan@cyano.uk>
* config.gcc: limit -lunwind usage by testing if the system
libunwind is being used.
2026-01-07 Xi Ruoyao <xry111@xry111.site>
PR target/123320
* config/loongarch/loongarch.md (<optab><mode>3): Only expand
using psuedos when can_create_pseudo_p ().
(addsi3): Likewise.
2026-01-07 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/123300
* gimple-range-gori.cc (gori_map::exports_and_deps): New.
* gimple-range-gori.h (exports_and_deps): New prototype.
(FOR_EACH_GORI_EXPORT_AND_DEP_NAME): New macro.
* tree-vrp.cc (remove_unreachable:remove_unreachable): Initialize
m_tmp bitmap.
(remove_unreachable:~remove_unreachable): Dispose of m_tmp bitmap.
(remove_unreachable:fully_replaceable): Move from static function
and check reachability of exports and dependencies.
2026-01-07 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/123319
* value-range.cc (irange::intersect): If there is a bitmask, snap
subranges after creating them.
2026-01-07 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/102486
* match.pd (`popcount (X & -X) -> -X != 0`): New pattern.
2026-01-07 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119291
PR rtl-optimization/121773
* combine.cc (try_combine): Check that SET_DEST (setN) is neither
modified_between_p nor reg_used_between_p instead of just not
reg_used_between_p or pc_rtx.
2026-01-07 Richard Earnshaw <rearnsha@arm.com>
PR target/123390
* config/arm/arm.cc (arm_gen_constant): Fix types of HWI literals.
(arm_const_double_prefer_rsbs_rsc): Likewise.
2026-01-07 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.cc (aarch64_parse_fmv_features): Add parsing
for priority arguments.
(aarch64_process_target_version_attr): Update call to
aarch64_parse_fmv_features.
(get_feature_mask_for_version): Update call to
aarch64_parse_fmv_features.
(aarch64_compare_version_priority): Add logic to order by priority if present.
(aarch64_functions_b_resolvable_from_a): Update call to
aarch64_parse_fmv_features.
(aarch64_mangle_decl_assembler_name): Update call to
aarch64_parse_fmv_features.
(dispatch_function_versions): Add logic to sort by priority.
(aarch64_same_function_versions): Add diagnostic if invalid use of
priority syntax.
(aarch64_merge_decl_attributes): Add logic to make suer priority
arguments are preserved.
(aarch64_check_target_clone_version): Update call to
aarch64_parse_fmv_features.
2026-01-07 Alfie Richards <alfie.richards@arm.com>
* target.def (TARGET_OPTION_SAME_FUNCTION_VERSIONS): Update
documentation.
* tree.cc (disjoint_version_decls): Change for new NULL parameter
to same_function_versions.
(diagnose_versioned_decls): Update to pass diagnostic location to
same_function_versions.
* doc/tm.texi: Regenerate.
* config/aarch64/aarch64.cc (aarch64_same_function_versions):
Update hook impl for new arguments.
* config/riscv/riscv.cc (riscv_same_function_versions): Update
hook impl for new arguments.
* config/loongarch/loongarch.cc
(loongarch_same_function_versions): Likewise
* hooks.cc (hook_stringslice_stringslice_unreachable): Changed
to...
(hook_stringslice_consttree_stringslice_consttree_unreachable):
...this and add extra arguments.
* hooks.h (hook_stringslice_stringslice_unreachable): Changed
to...
(hook_stringslice_consttree_stringslice_consttree_unreachable):
and add extra arguments.
2026-01-07 Martin Jambor <mjambor@suse.cz>
* params.opt (param_ipa_cp_sweeps): New.
* doc/invoke.texi (ipa-cp-sweeps): New.
* ipa-cp.cc (max_number_sweeps): New.
(get_max_overall_size): New parameter cur_sweep, use it and the total
number of sweeps from the NODE to calculate the result too.
(ipcp_propagate_stage): Get the maximum number of sweeps specified in
the corresponding parameter of any possibly affected node.
(good_cloning_opportunity_p): Add parameter cur_sweep, adjust the
threshold according to it.
(decide_about_value): New parameter cur_sweep, pass it to
get_max_overall_size and to good_cloning_opportunity_p.
(decide_whether_version_node): New parameter cur_sweep, pass it to
decide_about_value and get_max_overall_size. Make sure the node is
not dead.
(ipcp_decision_stage): Make multiple sweeps over the call-graph.
2026-01-07 Martin Jambor <mjambor@suse.cz>
* ipa-prop.h (ipa_node_params): Remove member do_clone_for_all_contexts.
(ipa_node_params::ipa_node_params): Do not initialize
do_clone_for_all_contexts.
* ipa-cp.cc (gather_context_independent_values): Remove parameter
calculate_aggs, calculate them always.
(estimate_local_effects): Move the decision whether to clone for
all context...
(decide_whether_version_node): ...here. Fix dumps.
(decide_about_value): Adjust alignment in dumps.
2026-01-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/123315
* tree-vect-loop.cc (vect_analyze_loop_2): Reset
LOOP_VINFO_USING_DECREMENTING_IV_P before retrying.
2026-01-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/123221
* tree-vect-loop.cc (vectorizable_reduction): When we did not
find the non-conversion reduction operation, bail.
2026-01-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/123316
* tree-vect-loop.cc (vectorizable_reduction): Detect missing
PHI patterns for bools.
2026-01-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
PR debug/123259
* toplev.cc (process_options): Guard CTF non-C warning by
-Wcomplain-wrong-lang.
* doc/invoke.texi (Warning Options, -Wno-complain-wrong-lang):
Document effect on -gctf/-gsctf.
2026-01-07 Siddhesh Poyarekar <siddhesh@gotplt.org>
PR tree-optimization/123374
* gimple-ssa-warn-access.cc (pass_waccess::set_pass_param): Add
a second parameter.
(pass_waccess::check_call): Skip access checks for waccess2.
(pass_waccess::execute): Drop initialization of
M_CHECK_DANGLING_P.
* passes.def: Adjust.
2026-01-06 Sebastian Huber <sebastian.huber@embedded-brains.de>
* tree-profile.cc (tree_profiling): Do not use atomic operations
if they are not available. Try to use at least partial atomic
updates as a fallback.
2026-01-06 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h (EPILOGUE_USES): New macro definition.
* config/xtensa/xtensa.md (return):
Remove '(use (reg:SI A0_REG))' from the template description, and
reload_completed from the condition.
(sibcall_epilogue): Remove emitting '(use (reg:SI A0_REG))'.
2026-01-06 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* tree-if-conv.cc (ifcvt_can_predicate): Add check for
normal builtins.
2026-01-06 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): New builtin flag.
(aarch64_init_pcdphint_builtins): New builtin function.
(aarch64_expand_pldir_builtin): Expander for new intrinsic.
(aarch64_general_expand_builtin): Call new expander.
* config/aarch64/aarch64.md
(aarch64_pldir): New pattern for instrinsic.
* config/aarch64/arm_acle.h
(__attribute__): New call to builtin.
(__pldir): Likewise.
2026-01-06 Richard Ball <Richard.Ball@arm.com>
* config/aarch64/aarch64-builtins.cc
(enum aarch64_builtins): Add new flags.
(aarch64_init_pcdphint_builtins): Create new Builtin functions.
(aarch64_general_init_builtins): Call init for PCDPHINT.
(aarch64_expand_stshh_builtin): Expander for new intrinsic.
(aarch64_general_expand_builtin): Call new expander.
* config/aarch64/aarch64-c.cc
(aarch64_update_cpp_builtins): New feature.
* config/aarch64/aarch64.h (TARGET_PCDPHINT): Likewise.
* config/aarch64/arm_acle.h
(__atomic_store_with_stshh): Generic to call builtins.
* config/aarch64/atomics.md
(@aarch64_atomic_store_stshh<mode>): New pattern for intrinsic.
* config/aarch64/iterators.md: New UNSPEC.
2026-01-06 Eric Botcazou <ebotcazou@adacore.com>
PR target/121192
* expr.cc (store_constructor) <VECTOR_TYPE>: Disable the special
trick for uniform boolean vectors with integer modes and single-bit
mask entries on big-endian platforms.
2026-01-06 Eric Botcazou <ebotcazou@adacore.com>
* doc/install.texi (Prerequisites): Remove reference to Ada in
conjunction with GCC 9.5 and adjust its GCC version requirement.
2026-01-06 Jakub Jelinek <jakub@redhat.com>
Marco Falke <falke.marco@gmail.com>
PR tree-optimization/123351
* tree-object-size.cc (object_sizes_set_temp): Separate calls to
make_ssa_name to ensure deterministic execution order.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* tree-vect-stmts.cc (vectorizable_call): Handle trapping math.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* tree-if-conv.cc (ifcvt_can_predicate): Support gimple_call_builtin_p.
(if_convertible_stmt_p, predicate_rhs_code,
predicate_statements): Likewise.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* match.pd: Add COND_FMA to COND_FMS rewrite rules.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* doc/md.texi: Document them
* internal-fn.cc (FOR_EACH_COND_FN_PAIR, internal_fn_else_index): Add
SQRT, CEIL, FLOOR, ROUND and RINT.
* internal-fn.def (IFN_COND_SQRT, IFN_COND_CEIL, IFN_COND_FLOOR,
IFN_COND_ROUND, IFN_COND_RINT, IFN_COND_LEN_SQRT, IFN_COND_LEN_CEIL,
IFN_COND_LEN_FLOOR, IFN_COND_LEN_ROUND, IFN_COND_LEN_RINT): New.
* optabs.def (cond_rint_optab, cond_sqrt_optab, cond_round_optab,
cond_ceil_optab, cond_floor_optab, cond_len_rint_optab,
cond_len_sqrt_optab, cond_len_round_optab, cond_len_ceil_optab,
cond_len_floor_optab): New.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/122103
* gimple.cc (gimple_could_trap_p_1): Handle __builtin_ calls.
2026-01-05 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv-string.cc (expand_block_move): Restore using
inlined memcpy/memmove for unknown counts if the param hasn't been
specified.
(expand_vec_setmem): Similarly for memset.
2026-01-05 Pan Li <pan2.li@intel.com>
PR target/123317
* config/riscv/autovec-opt.md: Take zero_extend for
both the vwaddu and vwsubu wx pattern.
2026-01-05 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sme.md
(aarch64_sme_write_zt): Add TARGET_STREAMING requirement.
(aarch64_sme_lut_zt): Ditto.
2026-01-05 Alice Carlotti <alice.carlotti@arm.com>
* doc/invoke.texi: Fix incorrect function name.
2026-01-05 Pan Li <pan2.li@intel.com>
* tree-vect-slp.cc (vec_slp_has_scalar_use): Adjust the
depth_limit from 2 to 3.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR target/121290
* config/aarch64/aarch64.cc (aarch64_possible_by_lane_insn_p): New.
(aarch64_vector_costs): Add m_num_dup_stmts and m_num_total_stmts.
(aarch64_vector_costs::add_stmt_cost): Use them.
(adjust_body_cost): Likewise.
2026-01-05 Tamar Christina <tamar.christina@arm.com>
PR target/123017
* config/aarch64/aarch64-json-schema.h: Add br_mispredict_factor.
* config/aarch64/aarch64-json-tunings-parser-generated.inc
(parse_branch_costs): Add br_mispredict_factor.
* config/aarch64/aarch64-json-tunings-printer-generated.inc
(serialize_branch_costs): Add br_mispredict_factor.
* config/aarch64/aarch64-protos.h (struct cpu_branch_cost): Add
br_mispredict_factor.
* config/aarch64/aarch64.cc (aarch64_max_noce_ifcvt_seq_cost,
aarch64_noce_conversion_profitable_p,
TARGET_MAX_NOCE_IFCVT_SEQ_COST,
TARGET_NOCE_CONVERSION_PROFITABLE_P): New.
* config/aarch64/tuning_models/generic.h (generic_branch_cost): Add
br_mispredict_factor.
* config/aarch64/tuning_models/generic_armv8_a.h: Remove
generic_armv8_a_branch_cost and use generic_branch_cost.
2026-01-04 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* configure: Regenerate.
2026-01-04 Jeff Law <jeffrey.law@oss.qualcomm.com>
* config/riscv/riscv.cc (riscv_conditional_register_usage): Revert
patch that made VXRM a global register.
2026-01-04 Keith Packard <keithp@keithp.com>
* config.gcc: Add clause for picolibc.
* config/picolibc-spec.h: New file.
* config/picolibc.opt: Likewise.
* config/picolibc.opt.urls: Likewise.
* configure.ac: Add support for --with-picolibc.
* configure: Rebuilt.
* doc/invoke.texi: Document picolibc options.
* doc/tm.texi.in (LIBC_CPP_SPEC): Document.
(LIBC_LINK_SPEC): Similarly.
* doc/tm.texi: Rebuilt.
* gcc.cc (LIBC_CPP_SPEC): Provide default definition.
(LIBC_LINK_SPEC): Likewise.
(cpp_spec): Include LIBC_CPP_SPEC.
(link_spec): Similarly for LIBC_LINK_SPEC.
2026-01-04 Jeff Law <jeffrey.law@oss.qualcomm.com>
* doc/contrib.texi: Add Kazumoto & Oleg.
2026-01-04 Richard Braun <rbraun@sceen.net>
* config/c6x/c6x-sched.md.in (mpydp_m_N__CROSS_,
mpyspdp_m_N__CROSS_, mpysp2dp_m_N__CROSS_): Update reservations.
* config/c6x/c6x-sched.md: Regenerated.
* config/c6x/c6x.md (m1dp, m1spdp, m2dp, m2spdp): New CPU units.
2026-01-04 Kalvis Duckmanton <kalvisd@gmail.com>
* config/host-netbsd.cc (netbsd_gt_pch_use_address): Support PCH
loading at addresses other than its preferred address.
* config/host-openbsd.cc (openbsd_gt_pch_use_address): Likewise.
2026-01-04 Daniel Barboza <daniel.barboza@oss.qualcomm.com>
PR tree-optimization/122608
* match.pd (`(c ? a : b) op d -> c ? (a op d) : (b op d)`): New
pattern.
(`d op (c ? a : b) -> c ? (d op a) : (d op b)`): Likewise
2026-01-04 Jeff Law <jeffrey.law@oss.qualcomm.com>
PR target/123010
* simplify-rtx.cc (simplify_binary_operation_1, case ASHIFT): Simplify
case where a left shift of the sign extracted field can be turned into
a sign extension of a left shift.
2026-01-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/123372
* tree-ssa-math-opts.cc
(build_saturation_binary_arith_call_and_replace): Pass type of op_0
rather than type of lhs as second argument to
direct_internal_fn_supported_p.
2026-01-02 Iain Sandoe <iain@sandoe.co.uk>
* config/aarch64/aarch64-sve-builtins-shapes.cc
(INCLUDE_ALGORITHM): Define.
2026-01-01 Kugan Vivekanandarajah <kvivekananda@nvidia.com>
* cgraph.cc (cgraph_edge::get_next_speculative_id): New.
* cgraph.h (cgraph_edge::get_next_speculative_id): New.
* ipa-devirt.cc (ipa_devirt): Use get_next_speculative_id
in make_speculative.
2026-01-01 Jakub Jelinek <jakub@redhat.com>
* gcc.cc (process_command): Update copyright notice dates.
* gcov-dump.cc (print_version): Ditto.
* gcov.cc (print_version): Ditto.
* gcov-tool.cc (print_version): Ditto.
* gengtype.cc (create_file): Ditto.
* doc/cpp.texi: Bump @copying's copyright year.
* doc/cppinternals.texi: Ditto.
* doc/gcc.texi: Ditto.
* doc/gccint.texi: Ditto.
* doc/gcov.texi: Ditto.
* doc/install.texi: Ditto.
* doc/invoke.texi: Ditto.
Copyright (C) 2026 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.