commit 03f3365742a9341992f0c8fc751e2d143e49f95d
author Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Tue Sep 27 17:26:08 2022 +0800
committer Kito Cheng <kito.cheng@sifive.com> Thu Sep 29 01:32:14 2022 +0800
tree 1670a26a897374dbadad0cd6c18eac5cbf9488a8
parent 5d7be27bf7ef63c770a591f69845c4245522cd76

RISC-V: Add ABI-defined RVV types.

gcc/ChangeLog:

	* config.gcc: Add riscv-vector-builtins.o.
	* config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV builtin function.
	* config/riscv/riscv-protos.h (riscv_v_ext_enabled_vector_mode_p): New function.
	* config/riscv/riscv.cc (ENTRY): New macro.
	(riscv_v_ext_enabled_vector_mode_p): New function.
	(riscv_mangle_type): Add RVV mangle.
	(riscv_vector_mode_supported_p): Adjust RVV machine mode.
	(riscv_verify_type_context): Add context check for RVV.
	(riscv_vector_alignment): Add RVV alignment target hook support.
	(TARGET_VECTOR_MODE_SUPPORTED_P): New target hook support.
	(TARGET_VERIFY_TYPE_CONTEXT): Ditto.
	(TARGET_VECTOR_ALIGNMENT): Ditto.
	* config/riscv/t-riscv: Add riscv-vector-builtins.o
	* config/riscv/riscv-vector-builtins.cc: New file.
	* config/riscv/riscv-vector-builtins.def: New file.
	* config/riscv/riscv-vector-builtins.h: New file.
	* config/riscv/riscv-vector-switch.def: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/abi-1.c: New test.
	* gcc.target/riscv/rvv/base/abi-2.c: New test.
	* gcc.target/riscv/rvv/base/abi-3.c: New test.
	* gcc.target/riscv/rvv/base/abi-4.c: New test.
	* gcc.target/riscv/rvv/base/abi-5.c: New test.
	* gcc.target/riscv/rvv/base/abi-6.c: New test.
	* gcc.target/riscv/rvv/base/abi-7.c: New test.
	* gcc.target/riscv/rvv/rvv.exp: New test.