commit 1750c038f9d0e0e6d1ad977e7b9f69ae7cb67455
author Victor Do Nascimento <victor.donascimento@arm.com> Mon Oct 23 15:39:41 2023 +0100
committer Victor Do Nascimento <victor.donascimento@arm.com> Thu Dec 07 03:14:18 2023 +0000
tree 5d598186adde6cf76b1f3115dbcf88987269914c
parent df193bda748c9c3f1e23cc2c4a636db578239001

aarch64: rcpc3: Add relevant iterators to handle Neon intrinsics

The LDAP1 and STL1 Neon ACLE intrinsics, operating on 64-bit data
values, operate on single-lane (Vt.1D) or twin-lane (Vt.2D) SIMD
register configurations, either in the DI or DF modes.  This leads to
the need for a mode iterator accounting for the V1DI, V1DF, V2DI and
V2DF modes.

This patch therefore introduces the new V12DIF mode iterator with
which to generate functions operating on signed 64-bit integer and
float values and V12DIUP for generating the unsigned and
polynomial-type counterparts.  Along with this, we modify the
associated mode attributes accordingly in order to allow for the
implementation of the relevant backend patterns for the intrinsics.

gcc/ChangeLog:

	* config/aarch64/iterators.md (V12DIF): New.
	(V12DUP): Likewise.
	(VEL): Add support for all V12DIF-associated modes.
	(Vetype): Add support for V1DI and V1DF.
	(Vel): Likewise.