middle-end: Use conservative store semantics for MEM_NOTRAP [PR127185]

set_mem_attributes derives MEM_NOTRAP from tree_could_trap_p.  That
predicate describes a load.  A store to readonly or otherwise unwritable
memory can therefore be marked as nontrapping.  RTL exception analysis can
then omit an edge for a store that can raise a non-call exception.

For example, the asm output in the test was marked nontrapping:

  (set (mem/u/c:SI (...) [ output+0 ]) ...)

Use store trap semantics for it instead:

  (set (mem/u:SI (...) [ output+0 ]) ...)

Add MAY_STORE_P to the memory attribute setters and use lhs_could_trap_p
when it is true.  Default MAY_STORE_P to true so that an unclassified
caller cannot create an unsafe nontrapping claim.

EXPAND_NORMAL is the only expand modifier that guarantees that a memory
reference describes a load.  Treat the other modifiers conservatively.
This includes EXPAND_STACK_PARM and the direction-neutral EXPAND_MEMORY.
Recompute MEM_NOTRAP on copied declaration RTL so that a normal load keeps
the nontrapping form:

  (mem/u/c:SI (...) [ output+0 ])

This can lose MEM_NOTRAP precision for loads expanded with a
direction-neutral modifier.  Later patches restore that precision for
get_memory_rtx, memory-only inline-assembly inputs, partial loads, and STRUB
watermark loads.

Bootstrapped and tested on aarch64-unknown-linux-gnu.  Tested on
x86_64-pc-linux-gnu.

	PR middle-end/127185

gcc/ChangeLog:

	* emit-rtl.cc (set_mem_attributes_minus_bitpos): Add MAY_STORE_P.
	Use lhs_could_trap_p when it is true.
	(set_mem_attributes): Add MAY_STORE_P and pass it through.
	* emit-rtl.h (set_mem_attributes): Add MAY_STORE_P with a
	conservative default.
	(set_mem_attributes_minus_bitpos): Likewise.
	* expr.cc (expand_assignment): Mark the destination as a store.
	(expand_expr_real_1): Treat only EXPAND_NORMAL as a known load.
	Set MEM_NOTRAP from the access direction.

gcc/testsuite/ChangeLog:

	* g++.dg/eh/noncall-store-2.C: New test.
	* g++.dg/opt/mem-notrap-store-asm.C: New test.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>