ARM: Fix -mpure-code for v6m When running the testsuite with -fdisable-rtl-fwprop2 and -mpure-code for cortex-m0, I noticed that some testcases were failing because we still generate "ldr rX, .LCY", which is what we want to avoid with -mpure-code. This is latent since a recent improvement in fwprop (PR88833). In this patch I change the thumb1_movsi_insn pattern so that it emits the desired instruction sequence when arm_disable_literal_pool is set. To achieve that, I introduce a new required_for_purecode attribute to enable the corresponding alternative in thumb1_movsi_insn and take the actual instruction sequence length into account. gcc/ChangeLog: 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org> Backport from mainline 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/arm.md (required_for_purecode): New attribute. (enabled): Handle required_for_purecode. * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to work with -mpure-code.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4de9e50..c8dd6d0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog
@@ -1,6 +1,16 @@ 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org> Backport from mainline + 2020-02-25 Christophe Lyon <christophe.lyon@linaro.org> + + * config/arm/arm.md (required_for_purecode): New attribute. + (enabled): Handle required_for_purecode. + * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to + work with -mpure-code. + +2020-02-25 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline 2019-12-17 Christophe Lyon <christophe.lyon@linaro.org> * config/arm/arm-protos.h (thumb1_gen_const_int): Add new prototype.
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index ae58217..efa2d31 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md
@@ -94,6 +94,11 @@ ; an IT block in their expansion which is not a short IT. (define_attr "enabled_for_short_it" "no,yes" (const_string "yes")) +; Mark an instruction sequence as the required way of loading a +; constant when -mpure-code is enabled (which implies +; arm_disable_literal_pool) +(define_attr "required_for_purecode" "no,yes" (const_string "no")) + ;; Operand number of an input operand that is shifted. Zero if the ;; given instruction does not shift one of its input operands. (define_attr "shift" "" (const_int 0)) @@ -237,6 +242,10 @@ (match_test "arm_restrict_it")) (const_string "no") + (and (eq_attr "required_for_purecode" "yes") + (not (match_test "arm_disable_literal_pool"))) + (const_string "no") + (eq_attr "arch_enabled" "no") (const_string "no")] (const_string "yes")))
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 15bf3f0..041e2db 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md
@@ -691,8 +691,8 @@ ) (define_insn "*thumb1_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, m,*l*h*k") - (match_operand:SI 1 "general_operand" "l, I,j,J,K,>,l,mi,l,*l*h*k"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,r,l,l,l,>,l, l, m,*l*h*k") + (match_operand:SI 1 "general_operand" "l, I,j,J,K,>,l,i, mi,l,*l*h*k"))] "TARGET_THUMB1 && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" @@ -704,14 +704,16 @@ # ldmia\\t%1, {%0} stmia\\t%0, {%1} + movs\\t%0, #:upper8_15:%1; lsls\\t%0, #8; adds\\t%0, #:upper0_7:%1; lsls\\t%0, #8; adds\\t%0, #:lower8_15:%1; lsls\\t%0, #8; adds\\t%0, #:lower0_7:%1 ldr\\t%0, %1 str\\t%1, %0 mov\\t%0, %1" - [(set_attr "length" "2,2,4,4,4,2,2,2,2,2") - (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load_4,store_4,load_4,store_4,mov_reg") - (set_attr "pool_range" "*,*,*,*,*,*,*,1018,*,*") - (set_attr "arch" "t1,t1,v8mb,t1,t1,t1,t1,t1,t1,t1") - (set_attr "conds" "set,clob,nocond,*,*,nocond,nocond,nocond,nocond,nocond")]) + [(set_attr "length" "2,2,4,4,4,2,2,14,2,2,2") + (set_attr "type" "mov_reg,mov_imm,mov_imm,multiple,multiple,load_4,store_4,alu_sreg,load_4,store_4,mov_reg") + (set_attr "pool_range" "*,*,*,*,*,*,*, *,1018,*,*") + (set_attr "arch" "t1,t1,v8mb,t1,t1,t1,t1,t1,t1,t1,t1") + (set_attr "required_for_purecode" "no,no,no,no,no,no,no,yes,no,no,no") + (set_attr "conds" "set,clob,nocond,*,*,nocond,nocond,nocond,nocond,nocond,nocond")]) ; Split the load of 64-bit constant into two loads for high and low 32-bit parts respectively ; to see if we can load them in fewer instructions or fewer cycles.