commit 826c22dff6455ba324fea120be27c2be638f0b96
author liuhongt <hongtao.liu@intel.com> Fri Nov 18 16:08:08 2022 +0800
committer liuhongt <hongtao.liu@intel.com> Tue Nov 22 12:49:53 2022 +0800
tree 0f12e325dec0ebb86c99c40cd3f6c1eaeeced48a
parent b20a3854c9f2923ac02c26385dac0c68f4df1e66

Some tidy up for RA related hooks.

1. We also need to guard size of TO to be
less than TARGET_SSE2 ? 2 : 4 in ix86_can_change_mode_class.
2. Merge VALID_AVX512FP16_SCALAR_MODE plus BFmode
into VALID_AVX512F_SCALAR_MODE since we've support 16-bit data move
above SSE2, so no need for the condition of AVX512FP16 for those evex
sse registers.
3. Allocate DI/HImode to sse register for SSE2 above just like
SImode since we've supported 16-bit data move between sse and gpr
above SSE2, this will help RA to handle cases like (subreg:HI (reg:V8HI)
0) or else RA will spill it. This enable optimization for
pices-memset-{3,37,39}.c

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_can_change_mode_class): Also guard
	size of TO.
	(ix86_hard_regno_mode_ok): Remove VALID_AVX512FP16_SCALAR_MODE
	* config/i386/i386.h (VALID_AVX512FP16_SCALAR_MODE): Merged to
	..
	(VALID_AVX512F_SCALAR_MODE): .. this, also add HImode.
	(VALID_SSE_REG_MODE): Add DI/HImode.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pieces-memset-3.c: Remove xfail.
	* gcc.target/i386/pieces-memset-37.c: Remove xfail.
	* gcc.target/i386/pieces-memset-39.c: Remove xfail.