gnu /
gcc /
ac74b3f82b339569b34dc9d1330c2faf74a1c82a RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
by splitting it into a zero-extraction (bext) and an xori. This both
avoids burning a register on a temporary and generates a sequence that
clearly captures 'extract bit, then invert bit'.
This change improves the previously generated
srl a0,a0,a1
not a0,a0
andi a0,a0,1
into
bext a0,a0,a1
xori a0,a0,1
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add split covering
"(a & (1 << BIT_NO)) ? 0 : 1".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
3 files changed
