| commit | b5d0cfab39608ff1f010a571122d6105b6e0e91e | [log] [tgz] |
|---|---|---|
| author | Vineet Gupta <vineetg@rivosinc.com> | Fri Jul 04 12:33:09 2025 -0700 |
| committer | Jeff Law <jlaw@ventanamicro.com> | Mon Jul 14 06:41:49 2025 -0600 |
| tree | 9dd16e97186635eb2612a831be72d9ab78240952 | |
| parent | e7d4593d6932c3d16e3cdc837538403859edb52f [diff] |
RISC-V: prefetch: const offset needs to have 5 bits zero, not 4 Spotted this by chance as I saw a similar fixup in comment. From comments, I think this is needed, but I've not hit any issues due to this. gcc/ChangeLog: * config/riscv/predicates.md (prefetch_operand): mack 5 bits. Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> (cherry picked from commit b960201091fcab631a34a8c8d5b30e9f297dfbe5)