aarch64: Some fixes for SVE INDEX constants

When using SVE INDEX to load an Advanced SIMD vector, we need to
take account of the different element ordering for big-endian
targets.  For example, when big-endian targets store the V4SI
constant { 0, 1, 2, 3 } in registers, 0 becomes the most
significant element, whereas INDEX always operates from the
least significant element.  A big-endian target would therefore
load V4SI { 0, 1, 2, 3 } using:

    INDEX Z0.S, #3, #-1

rather than little-endian's:

    INDEX Z0.S, #0, #1

While there, I noticed that we would only check the first vector
in a multi-vector SVE constant, which would trigger an ICE if the
other vectors turned out to be invalid.  This is pretty difficult to
trigger at the moment, since we only allow single-register modes to be
used as frontend & middle-end vector modes, but it can be seen using
the RTL frontend.

gcc/
	* config/aarch64/aarch64.cc (aarch64_sve_index_series_p): New
	function, split out from...
	(aarch64_simd_valid_imm): ...here.  Account for the different
	SVE and Advanced SIMD element orders on big-endian targets.
	Check each vector in a structure mode.

gcc/testsuite/
	* gcc.dg/rtl/aarch64/vec-series-1.c: New test.
	* gcc.dg/rtl/aarch64/vec-series-2.c: Likewise.
	* gcc.target/aarch64/sve/acle/general/dupq_2.c: Fix expected
	output for this big-endian test.
	* gcc.target/aarch64/sve/acle/general/dupq_4.c: Likewise.
	* gcc.target/aarch64/sve/vec_init_3.c: Restrict to little-endian
	targets and add more tests.
	* gcc.target/aarch64/sve/vec_init_4.c: New big-endian version
	of vec_init_3.c.

(cherry picked from commit 41c446389446a357172883389e36fd10c882ce6d)